LECTURE SUPPLEMENT #06
Basic Circuit Cells of Analog
MOSFET Technology
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–7581 [USC Fax]
johnc@usc.edu
PRELUDE:
In this set of notes, we study the low frequency properties of the basic circuit cells that
underpin active analog integrated circuits realized in MOSFET technology. At this
introductory level, our study is limited to linear amplifiers for which the fundamentally
important properties are input to output (I/O) gain, input resistance, and output
resistance. In the course of our investigations, we shall learn to appreciate more fully
the practical utility of such fundamental circuit and system concepts as Thévenin’s theorem, Norton’s theorem, and the mathematical ohmmeter method of determining circuit
resistance levels. We shall even introduce the reader to basic feedback principles, as applied to linear active networks. Fundamentally, we shall learn that the insightful
exploitation of these and other basic concepts allows us to contrive and efficiently
analyze relatively complex analog network topologies that derive from meaningful
interconnections of basic circuit cells.
May 2009/January 2011
Lecture Supplement #06
Canonic Analog MOS Cells
J. Choma
6.1.0. INTRODUCTION
The preponderance of linear amplification networks realized in either n-channel or pchannel MOSFET technologies are comprised of interconnections of only three basic, or canonic, circuit cells. These cells are the common source amplifier, the common drain amplifier,
which is also known as the source follower, and the common gate amplifier. In a common
source configuration, the input signal that is to be amplified or otherwise processed is applied
with respect to circuit ground at the gate terminal, while the output response to this applied signal is extracted at the drain terminal of the utilized MOS transistor. The common source stage
features extremely high input resistance and is therefore suitable for input signal application in
the form of a voltage source characterized by low to moderately large values of source resistance. It delivers a moderately high to very high output resistance, thereby implying that the signal response to an applied excitation is best extracted as a current. It follows that the common
source stage is comfortable as a transconductance amplifier in the sense that its effective I/O
transconductance, which is the ratio of the output signal current to the input signal voltage, is
nominally independent of both signal source and terminating load resistances. In other words, its
effective transconductance is achievable over broad ranges of signal source and load resistance
values. The fact that the common source amplifier is optimally suited as a transconductance signal processor does not mean that it cannot function as a voltage amplifier. It simply means that
the observed voltage gain, which is the ratio of output signal voltage to input signal voltage, is
dependent on the terminating load resistance. This dependence on load resistance limits the utility of the common source unit as a general purpose voltage amplifier. Yet another important feature of the common source amplifier is I/O phase inversion. In particular, the output voltage signal response is 180° out of phase with the applied input signal, which means that as the input
signal rises with time, the output voltage signal decreases with time and vice versa.
In a common drain amplifier, or source follower, the input signal is applied as a voltage
with respect to ground at the gate terminal of the incorporated MOSFET. The resultant output
response is a signal voltage developed at the source terminal. The source follower functions as a
voltage buffer in that its input resistance is extremely large, while its output resistance is low to
moderately low. Although an ideal voltage buffer supplies unity I/O voltage gain, the MOS
technology source follower delivers a gain that is always less than one. To its advantage, this
voltage gain is nominally insensitive to source and load resistance values. The I/O gain can be
markedly less than one if the gate aspect ratio and/or the quiescent drain current are too small.
As is the case with an ideal voltage buffer, the source follower offers no I/O phase inversion.
This is to say that the source voltage signal “follows” the gate in that as the signal at the gate
rises, so does the source terminal response to this signal and vice versa. Because of the less than
unity voltage gain afforded by the source follower, it is rarely used as a standalone stage in an
electronic system. Instead, and as we shall demonstrate, the source follower is traditionally inserted between the output port of a common source amplifier and a terminating load whose
impedance is relatively small.
The input port of a common gate amplifier is formed by circuit ground and the source
terminal of the utilized MOS device, while its output port is the drain terminal. Because the
common gate amplifier features a relatively small input resistance and typically, a very large output resistance, the input signal is generally applied as a current, and the output response is
logically extracted as a signal current. The I/O current gain presents no phase inversion to the
network in which the stage is embedded and is always less than, but generally very close to, one.
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Canonic Analog MOS Cells
J. Choma
In effect, the common gate amplifier is the dual of the source follower. Recall that the source
follower establishes very high input resistance, moderately low output resistance, and a voltage
gain that can be made to approach one. On the other hand, the common gate configuration
boasts moderately low input resistance, very high output resistance, and a signal current gain that
tends toward unity. Because of these complementary properties, the common gate amplifier can
be thought of as a current buffer. Like the source follower, the common gate amplifier most
commonly appears in conjunction with a common source amplifier in electronic systems for
which the incorporated common source stage is asked to supply substantial I/O transconductance
to a relatively high resistance load.
Table (1) summarizes the foregoing contentions by itemizing the basic low frequency
characteristics of the three fundamental circuit cells that are indigenous to analog MOSFET
technology. It is notable that interconnections of these three canonic topologies or simple variants thereof comprise better than 90% of the analog MOS circuits that might be encountered in
commercial, military, or space system applications. Because these three cells comprise the
foundation of analog MOS networks, an insightful understanding of their static and dynamic
operation is an indispensable design aid.
Amplifier
Input
Resistance
Output
Resistance
I/O Phase
Inversion
Application
Common
Source
Very High
Moderately High
To High
Yes
Common
Drain
Common
Gate
Very High
Low To
Moderately Low
Very High
No
Voltage
Amplifier;
Transconductor
Voltage
Buffer
Current
Buffer
Table (1).
Low To
Moderately Low
No
Summary of performance characteristics for the three basic circuit cells of analog MOSFET
technology.
6.2.0. COMMON SOURCE AMPLIFIER
Figure (6.1a) depicts the simplified schematic diagram of a common source amplifier
realized with a single n-channel MOSFET, or NMOS. Figure (6.1b) is the p-channel, or PMOS,
counterpart to the NMOS common source unit. In the discussion that follows, we shall focus on
only the NMOS circuit in the hope that the discourse provided motivates the reader to pursue
similar investigations on the PMOS circuit. Such investigations will confirm that for low to
moderately high signal frequencies, the gain, input resistance, output resistance, and related other
performance metrics for the PMOS stage mirror their respective expressions deduced below for
the NMOS topology.
We see in Figure (6.1a) that the simple form of the common source amplifier utilizes
two circuit resistances, Rl and Rss. A third resistance, Rs, should not be counted as a circuit element because this resistance represents the internal Thévenin resistance of the signal source, Vs,
which is to be amplified by the analog cell. Resistance Rl, to which we shall refer as the drain
load resistance, influences the biasing of the transistor. It also directly affects the small signal
voltage gain that the MOSFET is capable of delivering. Resistance Rss, which is known as a
source degeneration resistance, also influences biasing and gain. The circuit can be realized
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with Rss = 0; that is, the source terminal of the transistor is connected directly to circuit ground.
But in the configuration depicted in Figure (6.1a), nonzero Rss serves to reduce the sensitivity of
the voltage gain to certain transistor parameters whose precise numerical values are difficult to
predict accurately because of their somewhat nebulous physical nature and the routine
manufacturing tolerances pervasive of semiconductor or circuit processing. Among the prices
paid for this desirable performance desensitization with respect to ill-controlled transistor
parameters is a reduction (hence, “degeneration”) of the effective forward transconductance provided by the transistor. The electrical noise performance of the common source stage also suffers somewhat from the incorporation of a source degeneration resistance.
+Vdd
+Vdd
Rl
Ros
Id
Rs
Rss
Vo
Rs
Vi
+
+
Vs
Vi
Vs
−
+
−
Ris
+
Rss
Vgg
Id
Ris
Vo
Rl
Vgg
−
Ros
−
(a).
(b).
Figure (6.1). (a). Simplified schematic diagram of a common source amplifier realized with an n-channel
transistor. (b). The p-channel counterpart to the n-channel common source amplifier in (a).
Two sources of constant voltage, Vdd and Vgg, are deployed in Figure (6.1a) to bias the
transistor, in its saturation regime. In practice, it is likely that only one such source is used in
that Vgg can be forged as a voltage division of Vdd, which is invariably a voltage that is larger
than Vgg. If the amplifier undergoing study is an internal stage of a multistage configuration, it is
also possible that Vgg can derive as the static output voltage of the preceding stage that drives the
subject amplifier. In another words, it may be possible to use the available static voltages of a
predecessor stage to support the requisite biasing of the present stage under consideration without explicitly incorporating a separate constant voltage, Vgg.
The majority of MOS technology transistors used in continuous time, high performance
analog cells are biased in their saturation regimes. Accordingly, we can assert that the principle
purpose of static voltages Vdd and Vgg is to assure that the indicated transistor operates in saturation for all anticipated values of the signal source voltage, Vs, which we presume has zero average value. Alternatively, if a nonzero average value of Vs prevails, we can easily absorb this
static component of the signal into the constant voltage, Vgg, in that the latter appears in series
with the signal source.
In order for transistor saturation to prevail, two conditions must be satisfied. First, the
gate-source voltage, say Vgs, of the transistor in Figure (6.1a) must exceed the transistor threshold
potential, Vhn. If Vgs ≤ Vhn, no significant drain current, Id, flows, and the transistor is effectively
cutoff. Second, the drain-source voltage, Vds, must remain at least as large as the drain saturation
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voltage, which is nominally (Vgs − Vhn), for all expected values of the signal source voltage, Vs.
In view of the indicated input port voltage, Vi, the fact that zero gate current flows at low signal
frequencies (which renders the source terminal and drain currents identical), and the voltage
drop, IdRss, manifested across resistance Rss by nonzero drain current, the gate-source voltage,
Vgs, is merely (Vi − IdRss). But with zero gate current flowing into the transistor, Vi is little more
than the voltage sum, (Vgg + Vs). Thus, the first of the aforementioned biasing requirements requires
(1)
Vgg + Vs > Vhn + I d Rss .
We should underscore that (1) must be satisfied for all values of the signal voltage, Vs. To this
end, we note something that even relatively experienced circuit designers tend to forget. In
particular, the satisfaction of (1) under quiescent operating conditions (Vs = 0 and Id = IdQ),
which entails
(2)
Vgg > Vhn + I dQ Rss ,
comprises only a necessary, but not sufficient, condition for transistor turn on. Sufficiency is
achieved when (1) is satisfied for the most negative of anticipated signal source voltages.
Continuing with the transistor biasing conditions, we observe a drain-source voltage,
Vds, that is the difference between the output port voltage, Vo, and the potential drop, IdRss, across
Rss. Hence,
(3)
Vo − I d Rss ≥ Vgs − Vhn = Vgg + Vs − I d Rss − Vhn .
Since
Vo = Vdd − I d Rl ,
the constraint of (3) can be couched as
Vdd ≥ Vgg + Vs + I d Rl − Vhn ,
(4)
(5)
which defines the minimum permissible power supply voltage, Vdd. As is the case with the
transistor turn on condition expressed by (1), the saturation constraint voiced by (5) must be
satisfied for all values of Vs. It would appear that while maximally negative Vs comprises a
worst-case situation in (1), maximally positive Vs is the worst-case condition implicit to (5). A
double-barreled concern accompanies the large Vs circumstance. First and most obviously, large
Vs transparently increases the right hand side of (5), thereby rendering the inequality more
difficult to satisfy. But in addition, large Vs increases the input port voltage, Vi, in Figure (6.1a),
which in turn increases the gate-source voltage, Vgs, applied to the transistor. But because of the
nominal square law dependence of drain current on gate-source voltage, drain current Id also
increases, potentially at a rapid rate, with Vs and hence, Vgs. We see then that in addition to
increasing the right hand side of (5) as a result of increasing Vs, a larger signal source voltage
also enhances the voltage term, IdRl, on the right hand side of the subject inequality.
6.2.1. SMALL SIGNAL PERFORMANCE
If the conditions stipulated by (1) and (5) are met, the transistor at hand is assured to
operate in its saturation domain. And if the applied signal, Vs, is sufficiently small, the small
signal components of all circuit branch currents and circuit node voltages interrelate to one another in a reasonably linear fashion. We can quantify the degree of achieved linearity through a
definitive nonlinear analysis of the amplifier undergoing investigation. Such an analysis is
deemed outside the scope of these notes. Suffice it for the present to assert that linearity among
signal components of all circuit variables is tacitly presumed when saturation domain operation
is ensured and additionally, when too large a source signal input is precluded.
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To the extent that signal linearity prevails, the pertinent small signal model of the
amplifier in either Figure (6.1a) or Figure (6.1b) is the topology offered in Figure (6.2). The
model is applicable to only low signal frequencies in that gate-source, gate-drain, bulk-drain, and
bulk-source device capacitances are ignored, as are any parasitic energy storage elements that
may be associated with the load or source circuits. The transistor itself is modeled by three circuit elements: two voltage controlled current sources and a simple resistance.
Ris
Ros
Gate
Rs
+
Vs
−
Ids
Drain
+
V1
−
gmV1
λbgmV2
ro
Vos
Rl
Source
−
V2
+
Rss
Ids
Bulk
Figure (6.2). Small signal, low frequency equivalent circuit of either of the common source amplifiers depicted in Figure (6.1).
(1). The controlled source, gmV1, accounts for most of the signal component, Ids, of the net
drain current conducted by the transistor. This signal component of drain current is manifested by a signal voltage, V1, applied between the gate and source transistor terminals, as
is shown in the equivalent circuit. The parameter, gm, in gmV1 is the forward transconductance of the transistor and is a measure of the I/O gain that can be achieved by the transistor deployed in the amplifier. In terms of the transistor gate aspect ratio, (W/L), and the
quiescent (zero signal) drain current, IdQ, gm for the n-channel transistor is given
approximately by
⎛W ⎞
(6)
g m ≈ 2K n ⎜ ⎟ I dQ ,
⎝L⎠
where it is understood that the transconductance coefficient, Kn, which is the product of
channel carrier mobility and oxide capacitance density, is supplanted by coefficient Kp for
the p-channel unit. As is suggested by (6), the gain enhancement resulting from larger
transconductance can be afforded by increases in either the quiescent drain current and/or
the gate aspect ratio. Unfortunately, engineering prices are paid for each of these approaches. In particular, an increase in the quiescent drain current causes an increase in circuit power dissipation, while setting a larger gate aspect ratio incurs larger device
capacitances and a concomitant diminished bandwidth and slower response speed. In
practice, circuit designers often juggle gate aspect ratio and quiescent current level to secure a desired forward transconductance within the boundaries of acceptable power
dissipation and circuit response speed. At realistic biasing currents, gm is typically of the
order of hundreds of micromhos in deep submicron device technologies (channel lengths
under or equal to about 0.18 micron). It can be as large as several millimhos to tens of
millimhos for transistors featuring channel lengths greater than 0.5 micron.
(2). The second of the aforementioned three transistor modeling elements is the controlled
source, λbgmV2, which relates the perturbation of the signal component of the drain current
to the signal component, V2, of net bulk-source voltage. This drain current perturbation is
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caused by the fact that the threshold voltage of a MOSFET is weakly dependent on bulksource potential. The extent of this dependence is typified by the effective bulk
transconductance, λbgm, where λb is a small number that is proportional to the thickness of
the gate oxide layer. Ideally, we wish to have λbgmV2 equal to zero. Typically, wishes
come approximately true in that λb is usually less than 0.05, which implies that for the extreme case of equal gate-source and bulk-source signal voltages, the bulk-induced drain
current component is twenty times smaller than the drain current manifested by tradi
forward transconductance. We note in addition that if the semiconductor manufacturing
process permits a bulk connection to the source, while still preserving nominally zero net
bulk current for all operating conditions, the bulk-source voltage, inclusive of its signal
constituent, V2, is zero. In this happy circumstance, the bulk transconductance current,
λbgmV2, vanishes, not because of tacit neglect of λbgm, but because signal voltage V2 is
clamped to zero.
(3). The final branch element in the circuit level model of the transistor is the drain-source
channel resistance, ro, which is given by
Vλ + VdsQ − VdsatQ
(7)
ro =
.
I dQ
In this relationship, Vλ denotes the channel length modulation voltage, which is directly
proportional to the geometric device channel length, L, VdsQ is the quiescent value of drainsource voltage, VdsatQ represents the Q-point value of the drain saturation voltage, and, of
course, IdQ symbolizes the quiescent value of the drain current conducted by the transistor.
Ideally, we should like to have infinitely large ro, which would mean that the output port
of the equivalent circuit in Figure (6.2) behaves as a shunt interconnection of two idealized
current sources; that is, a load current that is independent of the signal voltage imposed
across the drain-source terminals. To this end, we should interject that typically, Vλ >>
VdsQ − VdsatQ, because to preclude undue power dissipation, we typically select a quiescent
drain-source voltage that is close to VdsatQ, which is the theoretic minimum drain-source
potential that is commensurate with saturation domain operation. It follows that ro is
principally dictated by channel length. Of course, small drain current also boosts the value
of ro but care should be exercised when establishing very small quiescent drain currents
since the forward transconductance in (6) becomes severely compromised.
Continuing with the small signal model postured in Figure (6.2), we note that the battery voltages, Vdd and Vgg, are effectively supplanted by short circuits. In truth, they are replaced
by their small signal voltage values. Specifically, Vdd is substituted by its signal-induced change,
ΔVdd, and similarly, Vgg becomes its signal-induced value, ΔVgg. But since Vdd and Vgg are presumed to be constant voltage sources, their perturbed values, ΔVdd and ΔVgg, are zero, whence
the appearance that the subject two battery voltages become short circuits in the small signal
amplifier model. In other words, since Vdd and Vgg are independent, constant voltages, their
instantaneous values over time are unaffected by the applied input signal, Vs. Exceptions to this
simple modeling scenario occur. For example, if electrical noise appears on the power bus carrying voltage Vdd to the amplifier, Vdd in the small signal model necessarily becomes the analytical
representation of this noise effect; namely, an independent voltage source whose ΔVdd-value
represents the offending noise perturbation. Moreover, if either Vdd or Vgg derive as Thévenin
equivalents of biasing energy sources, these two voltages would appear as their respective
Thévenin impedances in the small signal representation of the entire amplifier. The latter situation often surfaces in conjunction with Vdd in relatively large, mixed signal integrated circuits
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whose analog cells perform signal processing at very high frequencies. In such a case, the relatively long bus line routing germinates parasitic resistive, capacitive, and inductive effects so that
battery Vdd appears as a finite quality factor, complex and frequency-dependent impedance connected from the power end of the drain load resistance (or source degeneration resistance in the
p-channel version of the amplifier) to ground.
Because of the foregoing battery voltage disclosures, the signal source comprised of the
series interconnection of voltage Vs and resistance Rs is connected from the gate, or input terminal, of the common source amplifier to ground. Analogously, the drain load resistance returns
the drain terminal of the transistor to signal ground. Since the bulk terminal of the transistor is
grounded in the n-channel version of the amplifier, the signal component of the bulk-source voltage, V2, is generated from ground to source terminal, which is effectively the voltage across the
resistance, Rss, in the model of Figure (6.2). In the PMPOS amplifier version in Figure (6.2b),
the bulk is returned to the positive bus voltage. We note, however, that because Vdd is presumed
to be a constant voltage, the bulk terminal in the PMOS amplifier is similarly grounded. Finally,
we should observe that voltage V1 is not the signal voltage from gate to ground but rather, it is
the signal component of gate to source voltage, which is likewise delineated in the subject
model.
6.2.2. ANALYTICAL STRATEGY
In principle, loop and/or nodal equilibrium equations can be written for the model of
Figure (6.2) to arrive at an expression for the small signal voltage gain, Av = Vos/Vs. Subsequent
to replacing the drain load resistance, Rl, by a mathematical ohmmeter, a similar set of loop
and/or nodal equations generates an expression for the indicated common source output resistance, Ros. No such ohmmeter game need be played at the input port where the open circuited
nature of the gate renders transparent an infinitely large input resistance, Ris; that is,
Ris = ∞ .
(8)
Rather than engage in an involved circuit analysis, it proves prudent to attempt a more
generalized analytical strategy that can be adapted to analyze variants of the common source
amplifier and even other amplifier topologies. To this end, we know that the equivalent circuit
shown in Figure (6.2) is a linear network. As such, we are encouraged to reacquaint ourselves
with our good buddies, Thévenin and Norton. They taught us, respectively, that any port of a
linear network can be replaced by a voltage source in series with a resistance/impedance or a current source in shunt with the same resistance/impedance. The choice of adopting Thévenin’s or
Norton’s representation of a port is somewhat arbitrary. But an intelligent choice as to output
model structure of the common source amplifier entails observing that the output resistance
delineated in Figure (6.2) is likely to be large. It is certainly going to be larger than the source
degeneration resistance, Rss, since the drain to ground circuit where the output resistance, Ros, is
measured is a series interconnection of the transistor, which is modeled by the three branch elements discussed in the preceding subsection, and resistance Rss. While it is not illegal to use a
Thévenin format, we succumb to Norton’s lobbying to take advantage of this presumably large
output resistance. Accordingly, we shall represent the output port of the model in Figure (6.2) by
the Norton architecture displayed in Figure (6.3a) where we understand that the current, IN, is the
Norton, or short circuit, current that flows through the load if the load is indeed replaced by a
short circuit. Moreover, network linearity allows us to express current IN as a linear function of
any branch or node variable in the model. We elect to write IN as a current that is proportional to
the applied signal voltage, Vs. As Figure (6.3b) indicates,
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Ris
Ros
Ids
Rs
+
Vs
−
+
V1
−
gmV1
−
V2
+
ro
Rl
Rss
Ids
Ids
IN
λbgmV2
Vos
Ros
Ids
Vos
gmeVs
Rl
(a).
Ros
Vos
Rl
(b).
Figure (6.3). (a). Norton equivalent circuit of the output port for the indicated small
signal model of a common source amplifier. (b). The model of (a) with
Norton current IN expressed as a proportionality to the signal voltage, Vs,
applied to the common source configuration.
I N = g meVs ,
(9)
where the introduced parameter, gme, which is clearly the ratio of the Norton (short circuited
load) current to the signal voltage, can be viewed as an effective I/O transconductance of either
amplifier in Figure (6.1). Finally, resistance Ros in the Norton model is the Thévenin, or output,
resistance seen by the load that terminates the output port of the common source amplifier.
Figure (6.4a) is the equivalent circuit appropriate to the calculation of the Norton output
current for the subject amplifier. This circuit is identical to that of Figure (6.2), with the exception that the drain load resistance has been replaced by a short circuit, which forces the drain signal current, Ids, to be identical to the short circuit, or Norton, load current, IN. Since current IN
necessarily flows through the source degeneration resistance, Rss, as well as through the short
circuited load, the model at hand confirms that
V2 = − I N Rss
(10)
.
V1 = Vs + V2 = Vs − Rss I N
By KVL,
(11)
0 = ro ( I N − g mV1 − λb g mV2 ) + Rss I N .
After we substitute (10) into (11) to get rid of the two voltage variables, V1 and V2, we get
g m roVs
IN =
,
Rss + ⎡⎣1 + ( 1 + λb ) g m Rss ⎤⎦ ro
(12)
from which we deduce an effective I/O transconductance, gme, of
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Ids = IN
Rs
+
Vs
−
+
V1
−
gmV1
λbgmV 2
−
V2
+
ro
Rss
IN
(a).
Ix
Rs
+
V1
−
gmV1
λbgmV 2
ro
+
Vx
−
V2
+
Rss
Ix
−
Ix
(b).
Figure (6.4). (a). Model used in the determination of the Norton equivalent load current, IN, for the common source amplifier modeled in Figure (6.2). (b).
The model used to evaluate the output resistance, Ros, presented to the
load by the common source amplifier.
g me =
gm
Rss
1+
+ ( 1 + λb ) g m Rss
ro
⎛ ro
⎞
gm ⎜
⎟
ro + Rss ⎠
gm
⎝
=
≈
,
1 + g m Rss
1 + ( 1 + λb ) g m ( ro Rss )
(13)
where the approximation stems from the tacit presumptions, ro >> Rss and λb << 1.
It is always sensible to check reasonably intricate results for consistency with special
case circumstances that lend themselves to transparent circuit level interpretations. For example,
consider the special case of zero source degeneration; that is, Rss = 0. In this circumstance, (13)
shows an effective transconductance, gme, which is identical to the transistor transconductance,
gm. From Figure (6.2), Rss = 0 forces V2 = 0 which, in turn, constrains the dependent current
course, λbgmV2, to zero. Moreover, with Rss = 0, the gate-source signal voltage, V1, becomes a
gate to ground voltage that is identical to the signal source voltage, Vs. Accordingly, gmV1
equates to gmVs in the model. But with a short circuited load resistance, Rl, and again, Rss = 0, no
current can flow through the device channel resistance, ro, in Figure (6.2). This fact means that
the current conducted by the short circuit imposed across resistance Rl is identical to gmVs, which
indeed verifies an effective transconductance of gm. Equation (13) therefore appears consistent
with the specialized operating circumstance of a zero-valued source degeneration resistance. To
be sure, such consistency does not guarantee the correctness of the equation under investigation,
but an inconsistency with logical circuit level reasoning suggests analytical incorrectness.
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We can now see why resistance Rss is said to “degenerate” the transistor transconductance. Equation (13) clearly confirms gme < gm for Rss > 0. A simplified, but reasonably accurate, estimate of the factor by which transistor transconductance is reduced, or degenerated, by
source degeneration resistance is (1+gmRss), which is manifested in (13) for the generally valid
approximations of ro >> Rss and λb << 1. In particular, ro is a few thousand to a few tens of
thousands of ohms in reasonably biased MOSFETS, and rarely is Rss made larger than the mid
tens of ohms. Excessively large Rss induces considerable electrical noise (random current and
voltage “spikes”) and additionally, large Rss requires correspondingly large power supply voltages to effect proper biasing. As far as the bulk transconductance factor, λb, is concerned, most
modern transistors deliver values of λb that are considerably smaller than one.
In order to determine an expression for the common source output resistance, Ros, resistance Rl in the network of Figure (6.2) is supplanted by our trusty mathematical ohmmeter. The
ohmmeter current, Ix, injected to the output port of the amplifier manifests a voltage response, Vx,
across the port, as illustrated in Figure (6.4b). The model also reflects a null value imposed on
the lone independent energy source, Vs, applied to the circuit in Figure (6.2). We see in this
equivalent circuit that
V1 = V2 = − Rss I x ,
(14)
and by KCL and KVL,
(15)
Vx = ro ( I x − g mV1 − λb g mV2 ) + Rss I x .
The combination of these two relationships readily leads to
V
(16)
Ros = x = Rss + ⎡⎣1 + ( 1 + λb ) g m Rss ⎤⎦ ro .
Ix
We can test this expression by once again resorting to the special and easily understandable case
of Rss = 0, for which (16) collapses to Ros = ro. Because Rss = 0 forces V1 = Vs and V2 = 0 in the
model of Figure (6.2), we see that the output port of the subject model reduces to a dependent
source, gmVs, placed in shunt with the transistor channel resistance ro. Accordingly, we conclude
a Thévenin output resistance of ro, as expected for the resultant output resistance of the common
source network. We note, however, that when Rss > 0, Ros can be substantively larger than ro,
depending on the numerical value of the transconductance-resistance product, gmRss. For gmRss
>> 1 (an approximation that should be carefully tested when a deep submicron transistor is
used), (16) becomes
Ros = Rss + ⎡⎣1 + ( 1 + λb ) g m Rss ⎤⎦ ro ≈ ( 1 + g m ro ) Rss .
(17)
Armed with the short circuit transconductance, gme, and the output resistance, Ros, we
can now represent the somewhat complicated common source equivalent circuit in Figure (6.2)
by the Norton output model provided in Figure (6.5). An obvious advantage of this representation is that the voltage gain, Avs, now follows by mere inspection. Specifically,
⎛ Ros ⎞
V
(18)
Avs = os = − g me ( Ros Rl ) ≈ − g me Rl ⎜
⎟.
+
R
Vs
R
l⎠
⎝ os
We see that this I/O voltage gain, whose magnitude can be assuredly larger than one, is strongly
dependent on the drain load resistance, Rl. This relatively strong gain dependence on Rl is
magnified if, as is commonly the case, the common source output resistance, Ros, is significantly
larger than Rl. We suggest that Ros >> Rl is a common operating circumstance because Rl
necessarily conducts the Q-point drain current of the transistor. Therefore, large Rl necessitates
an undesirably large power supply voltage, Vdd, which must deliver voltage, not only to Rl, but
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also to the transistor drain-source terminals (at which the voltage must exceed the drain saturation level) and the source degeneration resistance. With Ros >> Rl and additionally, ro >> Rss
and λb << 1, (18) combines with (13) to deliver the approximate voltage gain,
Ris
Ros
Ids
Rs
+
Vs
−
+
V1
−
gmV1
λbgmV 2
−
V2
+
ro
Ids
Vos
Rl
gmeVs
Ros
Vos
Rl
Rss
Ids
Figure (6.5). Norton equivalent representation of the output port for the small signal equivalent circuit of the common source amplifier shown in Figure (6.1).
⎛ Ros ⎞
g m Rl
(19)
.
Avs = − g me Rl ⎜
⎟ ≈ −
1 + g m Rss
⎝ Ros + Rl ⎠
In the generally unlikely circumstance that gmRss >> 1, we observe a gain magnitude that is simply the resistance ratio, Rl/Rss. Although such a gain result is an improbable circumstance, it is
laudable in that resistance ratios can be controlled very accurately in monolithic processes,
assuming, of course, that both Rl and Rss are on-chip resistance elements. Accordingly, a highly
predictable and reproducible voltage gain that is nominally independent of parametric transistor
uncertainties is achieved.
The negative sign in the common source gain results of (18) and (19) is indicative of a
180° phase inversion between the applied input signal and the resultant signal voltage response.
This negative sign is more than mere algebraic nuance. It is an important and physically sound
characteristic of a common source amplifier. In an attempt to understand the phase inversion
concept, return to the circuit of Figure (6.1a) and assume that signal voltage Vs is increasing with
time. The increase in Vs elevates the input port voltage, Vi, which in turn translates to an increase
in the gate-source voltage, Vgs, applied to the transistor. To be sure, the resultant increase in the
gate-source voltage is likely to be measurably smaller than the original rise in signal source
voltage, but it tracks nonetheless with Vs to within some positive factor. As Vgs rises, so must the
drain current, Id, if for no other reason than the drain current displays a square law dependence
on the difference between the gate-source voltage and the threshold potential. But as Id
increases, so must the drop across the load resistance, Rl if George Ohm is to be placated.
However, the output voltage, Vo, is little more than (Vdd − RlId). Since voltage Vdd is a constant,
Vo must diminish as Id increases. The scenario in brief is as follows: Vs rises → Vi increases →
Vgs increases → Id increases → whence, Vo falls as Vs rises. Of course, the opposite scenario
continues to deliver phase inversion; that is, a diminishing Vs results in enhanced Vo. Precisely
identical disclosures apply to the PMOS version of the common source amplifier in Figure
(6.1b).
The fact that Ros is typically much larger than is Rl suggests that the common source
amplifier is better suited as a transconductor than it is as a voltage amplifier. The forward
transconductance, say Gmf, of the amplifier is defined as the ratio of the load signal current (Ids in
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this case) to the applied signal voltage, Vs. In Figure (6.5), we apply current divider principles to
obtain,
⎛ Ros ⎞
I
gm
(20)
,
Gmf ds = g me ⎜
⎟ ≈ g me ≈
Vs
1 + g m Rss
⎝ Ros + Rl ⎠
which is essentially independent of the drain load resistance. In other words, the amplifier is
capable of transforming an applied signal voltage to a known and predictable level of output signal current for a broad range of drain load resistances.
6.2.3. VARIATIONS OF THE COMMON SOURCE THEME
The fundamental common source cells depicted in Figure (6.1) are foundational to
practical topological modifications that increase common source practicality and utility in
application specific systems. In the subsections that follow, a few of these variants are explored
from the perspective of increasing the insightful understanding of circuit dynamics that
ultimately forges design expertise.
6.2.3.1. Single Supply Biasing Via Passive Voltage Division
We noted earlier in conjunction with the common source cells in Figure (6.1) that the
voltage source, Vgg, which is required to elevate the transistor gate-source potential to a level
above threshold, can derive from division of the power line voltage, Vdd. Equally significant is
our taking note of the fact that since the gate conducts zero current and signal source Vs has no
average value, voltage Vgg is the static, or Q-point, value of the input port voltage, Vi, in the
subject figure; specifically, ViQ = Vgg. The simplest way of exploiting voltage division to
implement this static input port voltage appears as the R1−R2 divider in the network of Figure
(6.6). One fly in the proverbial ointment that cures the problem of requiring a separate supply is
the need for the so-called coupling capacitance, C, which literally serves to couple the signal
source to the gate of the transistor. If the signal source were to be coupled directly to the
transistor gate, as would be the case if capacitance C replaced by an electrical short circuit, a
potentially serious problem arises. In particular, R1−R2 no longer forms a simple series
connection of resistances because the static current flowing through resistance R1 must be
supplied to both resistance R2 and the signal source circuit comprised of Rs and Vs. To this end,
recall that Vs has no average value, which implies that if ViQ equals Vgg, a static current of Vgg/Rs
flows back to the signal source. This current, which must ultimately be supplied by the power
line, increases the standby power dissipation of the network. It can be an appreciable current
since source resistance Rs can be 50 ohms or even smaller in practical applications. To be sure,
an analytical account of the backflow current can be made when setting R1 and R2 to values that
are appropriate to establishing a static input port voltage of Vgg. But aside from the
aforementioned increased static power dissipation, another problem with direct coupling is that
the majority of practical signal sources, which may be antennas, compact disk players, optical
sensors, and the like, cannot handle significant static currents. Indeed, even a minute flow of
static current often catastrophically damages these types of signal sources. Placing the capacitor
as shown in the figure at hand solves the problem confronting us in that it isolates the signal
source from “DC.” This isolation derives from the fact that at “DC,” the capacitor functions as
an open circuit, which is to say that the flow of static current back to the source is precluded.
With the coupling capacitor in place, ViQ = Vgg requires
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+Vdd
R1
Rs
+
Vs
Rl
Ros
Id
C
Vo
Vi
Ris
−
R2
Rss
Figure (6.6). Simple resistive divider that implements a single
supply version of the common source amplifier in
Figure (6.1a).
⎛ R2 ⎞
(21)
Vgg = ⎜
⎟ Vdd ,
⎝ R1 + R2 ⎠
where use is made of the facts that neither capacitance C nor the transistor gate conducts any
static current. Since the static power, say Pr, consumed by the resistive divider is
Pr =
2
Vdd
,
(22)
R1 + R2
(21) is equivalent to
PR
Vgg = r 2 .
(23)
Vdd
Since the voltage source, Vgg, in the original common source topology supplies no power to the
gate, we naturally target the power level, Pr, to be small −perhaps 10% or even a smaller
percentage of the power supplied by voltage Vdd to the transistor drain circuit. Once a
satisfactory value of Pr is established, the known value of Vdd and the desired value of Vgg yield
resistance R2 from (23), whence resistance R1 by (22) or (21).
While the capacitor laudably isolates the signal source from biasing potentials in the
network, it remains a somewhat problematic element from the perspective of the signal response
of the amplifier. For example, it is obvious that the capacitively coupled common source
amplifier cannot provide gain at zero frequency, where capacitor C becomes an open circuit.
With C behaving as an open circuit, the signal source comprised of signal voltage Vs and
Thévenin resistance Rs is decoupled from the gate of the transistor in Figure (6.6), thereby
rendering a null signal output response at the transistor drain terminal. In other words, the
amplifier is no longer a strictly lowpass configuration capable of gain all the way down to zero
frequency. But at some relevant low, but nonzero, signal frequency, say ωL, the impedance
presented to the circuit by the capacitance becomes sufficiently small so that the capacitance
approximates an electrical short circuit for signals. Once this short circuit is approached, the
amplifier emulates a lowpass response up to a high frequency, say ωH, where the gain begins to
fall with frequency because of transistor capacitances and parasitic energy storage elements
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associated with the various nodes of the circuit. In such an event, the amplifier bandwidth, B,
can be defined as the difference, (ωH − ωL). This declaration assumes tacitly that ωH and ωL are
the radial signal frequencies where the I/O gain magnitude is 3-dB smaller than the gain
magnitude registered at mid band where C closely approximates a short circuit and device and
other parasitic capacitances are negligible. In many applications, ωH >> ωL so that for all intents
and purposes, the 3-dB bandwidth is essentially ωH. For example, audio amplifiers must provide
gain from minimally 20 Hz to 20 KHz, wherein we see that ωL can be set to 2π(20 Hz) and ωH =
2π(20 KHz). On the other hand, cell phones operate in a relatively narrow passband centered
around 1.8 GHz or larger frequency. There is no point whatsoever in designing the front end of
such a system so that it provides gain down to “DC.” Actually, a strictly low pass design in this
and other types of communication networks is disadvantageous from the standpoint that the total
output electrical noise, which contaminates the otherwise “clean” signal response, is nominally
proportional to the implemented bandwidth. Thus, ωL in such systems is likely to be a relatively
large frequency metric.
In order to examine the manner in which the value of capacitance C can be chosen, we
draw the small signal equivalent circuit of the input port of the amplifier in Figure (6.6) as the
structure shown in Figure (6.7a). In this circuit, resistances R1 and R2 appear as parallel branches
from the input port, where the signal voltage is denoted as Vis, to signal ground. In particular, R2
is directly incident with the input gate node and ground while R1 is connected from the input
node to the power line voltage, Vdd, which has zero signal value and is therefore grounded for
signal conditions. Letting
Rs
Rs
C
Vis
Vis
+
+
Vs
R1
Vs
R2
−
Rp
−
(a).
(b).
Figure (6.7). (a). Small signal model of the input port for the capacitively coupled common source
amplifier in Figure (6.6). (b). The circuit of (a) at signal frequencies for which the
capacitance behaves as a short circuit. Resistance Rp is the parallel interconnection
of resistances R1 and R2.
R p R1 R2
(24)
denote the parallel combination of resistances R1 and R2, we get
Rp
jωR p C
Vis
=
=
,
Vs
R p + Rs + 1 jωC
1 + jω R p + Rs C
(
(25)
)
whose magnitude, which we wish to examine from a frequency response perspective, is
ωR p C
Vis
=
.
2
Vs
1 + ⎡ω R p + Rs C ⎤
⎣
⎦
2
We observe that if [ω(Rp + Rs)C] >> 1 at a signal frequency of ω = ωL,
(
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Rp
Vis
≈
Vs
R p + Rs
J. Choma
(27)
for all ω ≥ ωL. This is to say that the input circuit shown in Figure (6.7a) behaves as does the
simple divider in Figure (6.7b), which is tantamount to replacing capacitance C in the former
circuit by a short circuit. To be sure, the coupling effected by capacitance C is imperfect in the
sense that we do “lose” a fraction of the applied input signal, Vs. But to the extent that resistance
Rp is substantially larger than the signal source resistance Rs, the divider in (27) tends toward
unity.
The only remaining coupling task is the stipulation of the required capacitance value.
Since we require
(
)
⎡ ωL R p + Rs C ⎤
⎣
⎦
(
)
2
>> 1 ,
(28)
ωL R p + Rs C ≥ 10 ≈ 3.2 ,
(29)
whence
3.2
1
C ≥
≈
.
(30)
ωL R p + Rs
2 f L R p + Rs
We note that in effect, the product of the lowest radial frequency of interest, ωL, and the time
constant, (Rp + Rs)C, associated with capacitance C must be at least as large as the square root of
ten. Capacitances that are significantly larger than the right hand side of the last relationship,
which more easily satisfy the requisite inequality, should be avoided because of their physical
size, cost, and in extreme cases, relatively poor reliability.
(
)
(
)
Because of the resistive load imposed at the gate terminal of the capacitively coupled
common source amplifier in Figure (6.6), a few of the small signal performance metrics deduced
for the basic stage shown in Figure (6.1a), are changed slightly. For example, the input
resistance, Ris, is no longer infinitely large but instead, it is now
Ris = R1 R2 ≡ R p .
(31)
for ω > ωL. Moreover, the signal voltage developed at the input port is not Vs and is now Vis, per
(27), for ω > ωL. Thus, the effective transconductance and small signal voltage gain in (13) and
(18), respectively, become somewhat attenuated by the voltage divider action inspired between
resistance Rp and signal source resistance Rs. In particular,
⎛ ro ⎞ ⎛ R p ⎞
gm ⎜
⎟
⎟⎜
⎛
⎞ ⎛ Rp ⎞
gm
⎝ ro + Rss ⎠ ⎜⎝ R p + Rs ⎟⎠
(32)
g me =
≈ ⎜
⎟
⎟ ⎜⎜
⎟
1
g
R
R
R
+
+
1 + ( 1 + λb ) g m ( ro Rss )
m ss ⎠ ⎝ p
s⎠
⎝
and
⎛ Ros ⎞ ⎛ R p ⎞
⎛ gm Rl ⎞ ⎛ R p ⎞
Avs = − g me Rl ⎜
(33)
⎟ ≈ −⎜
⎟.
⎟ ⎜⎜
⎟ ⎜⎜
⎟
⎟
R
+
R
R
+
R
1
+
g
R
R
+
R
l ⎠⎝ p
s⎠
m ss ⎠ ⎝ p
s⎠
⎝ os
⎝
The output resistance, Ros in (16), is unchanged by the resistive biasing divider at the amplifier
input port.
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6.2.3.2. Single Supply Biasing Via Active Voltage Division
The most appreciated types of design creativity are those that take the form of practical
circuit level solutions to problems perceived in extant topologies. In the case of the input resistive divider used to forge an input port biasing potential, ViQ, of Vgg, a potential shortfall is that
the need for very low power dissipation in the resistive biasing branch manifests very large resistances, R1 and R2. Additionally, large R1 and R2 are required to achieve a large parallel equivalent resistance, Rp, if significant attenuation of the mid band effective transconductance and voltage gain is to be avoided. Unfortunately, large on-chip resistances are difficult to fabricate
accurately and to layout without incurring high frequency performance degradation incurred by
energy parasitics implicit to these resistive elements. A possible solution is the modified common source stage in Figure (6.8) in which resistance R1 in Figure (6.6) is supplanted by a transistor, M1, while resistance R2 is replaced by transistor M2. In effect, the passive divider formed of
resistances R1 and R2 is replaced by an active voltage divider formed of transistors M1 and M2.
Transistors M1 and M2 are identical to the transistor, M, embedded in the common source amplifier, but neither of their gate aspect ratios, say η1 and η2, respectively, need be the same as the
gate aspect ratio implicit to transistor M.
+Vdd
M1
R1
Rs
+
Vs
−
C
Rl
IR
Ros
Id
Vo
M
Vi
R2
Ris
M2
Rss
Figure (6.8). Common source amplifier of Figure (6.6) with passive
resistive divider formed of resistances R1 and R2 replaced
by an active divider formed of transistors M1 and M2.
We note that both M1 and M2 in Figure (6.6) are connected as effective diodes, which
is to say that the gate and drain terminals of each of the two inserted transistors are connected
together. There are two immediate ramifications of this diode-type connection. First, both M1
and M2 are guaranteed to operate in their saturation domains, regardless of the current levels
they conduct, because each device has a drain-source voltage that is necessarily identical to its
corresponding gate-source voltage. This voltage equality forces M1 and M2 to support precisely
zero gate-drain voltage, Vgd, and since Vgd = 0 certainly assures Vgd smaller than threshold potential, the source to drain channels of M1 and M2 exude pinchoff and therefore operate in
saturation. The second ramification is that since the gate and drain are connected together, the
nominally three terminal transistor element (the bulk terminals are simply grounded to inhibit
any current conduction in the bulk) functions as an effective two terminal device, as does a
conventional PN junction diode. This state of affairs means that when either M1 or M2 is
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modeled by its linear, small signal, low frequency equivalent circuit, either device behaves as a
memoryless, two terminal, and linear branch element. But two terminal, linear, memoryless
behavior defines a classic linear resistance. In other words, M1 in Figure (6.8) emulates the
functionality of resistance R1 in Figure (6.6) and analogously, M2 behaves electrically in a fashion similar to that of a passive resistance, R2.
Before examining the nature of the small signal resistances presented to the circuit by
the diode-connected transistors, let us see how transistors M1 and M2 interact to establish the
desired Q-point value of input port voltage Vi, which is ViQ = Vgg. The Q-point value, say IRQ,
of the indicated current, IR, in the diagram flows through the drains of both transistors M1 and
M2. Since these devices are in saturation,
2
2
K
K
I RQ = n η1 Vdd − ViQ − Vhn = n η2 ViQ − Vhn ,
(34)
2
2
where channel length modulation is deemed insignificant because the drain-source voltages of
each transistor are limited to their respective gate-source potentials. Additionally, we recall that
η1 and η2 respectively symbolize the gate aspect ratios of transistors M1 and M2. Choosing
these ratios small obviously leads to low-level current conduction of M1 and M2 and hence, low
power dissipation in the input biasing subcircuit. We can easily solve (34) for voltage ViQ to get
⎛
⎛ 1 − η1 η2 ⎞
η1 η2 ⎞
ViQ = ⎜
Vdd + ⎜
V ,
(35)
⎟
⎜1+ η η ⎟
⎜ 1 + η η ⎟⎟ hn
1
2
1
2
⎝
⎠
⎝
⎠
which clearly suggests that the requisite value of Q-point voltage ViQ can derive from the power
line voltage, Vdd, through proper selection of the ratio, η1/η2, of device gate aspect ratios. We
note that if η1 = η2, voltage ViQ is rendered independent of the threshold potential, Vhn, which is
advantageous in light of at least a small degree of uncertainty that pervades the threshold voltage
parameter for a MOSFET. Moreover, ViQ is simply Vdd/2 when η1 = η2, which is reasonable in
light of the fact that identical gate aspect ratios imply a simple voltage divider formed of a series
interconnection of two identical transistors operated effectively as identical two terminal resistances.
(
)
(
)
In order to determine the effective resistance, R1, presented to the amplifier by transistor M1 in Figure (6.8), the M1 subcircuit is redrawn for convenience in Figure (6.9a). The traditional low frequency small signal model of this subcircuit appears in Figure (6.9b), where the
desired effective resistance, R1, is the ratio, Vx/Ix, of the introduced mathematical ohmmeter variables. But we note in Figure (6.9b) that the gate-source signal voltage, V1 is identical to the
negative of the ohmmeter voltage, Vx; ditto for the bulk-source signal voltage, V2. It follows that
the model in Figure (6.9b) is electrically identical to that of Figure (6.9c) where the directions of
the two dependent sources in Figure (6.9b) have been reversed to reflect the constraint of V1 = V2
= −Vx. But in the resultant configuration of Figure (6.9c), we see that the ohmmeter voltage, Vx,
appears directly across, and in associated polarity convention with, the voltage controlled current
source, gm1Vx. This state of affairs means that the subject dependent current source is equivalent
to a branch conductance of gm1 or equivalently, a branch resistance of 1/gm1. The same argument
applies to the dependent source, λb1gm1V2, which is seen to reflect a branch resistance of 1/λb1gm1.
Our clever observations serve to collapse the model in Figure (6.9c) to the simple three branch
circuit in Figure (6.9d) for which we see, by inspection that
V
1
ro1
1
(36)
R1 = x =
=
≈
,
Ix
(1 ro1 ) + (1 + λb1 ) gm1 1 + (1 + λb1 ) gm1ro1 gm1
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J. Choma
+
V1
−
M1
R1
gm1V1
Vx
Ix
−
(b).
gm1Vx
1
λb1gm1
1
gm1
ro1
λb1gm1Vx
+
−
V2
+
ro1
+
−
V2
+
(a).
+
V1
−
λb1gm1V2
Vx
ro1
+
Ix
R1
Vx
Ix
−
−
(d).
(c).
Figure (6.9). (a). The use of diode-connected transistor M1 in the amplifier of Figure (6.8) to emulate
a nominally linear, two terminal resistance of value R1. (b). Low frequency, small signal model appropriate to determining the effective resistance presented by transistor M1
between its source terminal and signal ground. (c). Equivalent representation of the
small signal model in (b). (d). Circuit level implication of the small signal model in (c)
as the shunt interconnection of three resistances.
where the approximation reflects the reasonable presumptions that λb1 << 1 and gm1ro1 >> 1.
With a small Q-point current, IRQ, conducted by transistor M1 to sustain low biasing power
dissipation, transconductance gm1, which is proportional to the square root of IRQ is correspondingly small, whence the desired target of a relatively large R1 is ostensibly achieved.
The situation surrounding transistor M2 is entirely analogous to that of M1. Actually, it
is even a somewhat simpler scenario in that since both the bulk and the source terminals of
transistor M2 are grounded, the signal component of the bulk-source voltage of M2 is necessarily
zero. This means that the bulk transconductance generator, λb2gm2V2, which theoretically appears
in the small signal model of M2 is zero, whence resistance R2 is simply
1
ro2
1
(37)
R2 =
=
≈
.
(1 ro2 ) + gm2 1 + gm2 ro2 gm2
6.2.3.3. Diode-Connected Degeneration And Load
The diode-connected transistor strategy invoked on the input port biasing problem can
be applied to the source degeneration resistance, Rss, and the load resistance, Rl, as suggested in
Figure (6.10). In this diagram, which displays only the simplified, battery-driven input port biasing, the source degeneration resistance in the amplifier of Figure (6.1a) is realized by the diodeconnected transistor Ms, which has a gate aspect ratio of ηs. Similarly, load resistance Rl is
effectively synthesized by transistor Ml, whose gate aspect ratio can be taken as ηl. Appealing to
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the resistance results that are disclosed in the preceding subsection of material, we understand
that in the amplifier under present consideration,
+Vdd
Ml
Rl
Rs
+
Id
Vi
M
−
Vgg
Rout
Rss
Vs
+
Vo
Ros
Ris
Ms
−
Figure (6.10). The amplifier in Figure (6.1) with the source degeneration
resistance, Rss, replaced by transistor Ms and the drain load
resistance, Rl, supplanted by transistor Ml.
ros
1
≈
g ms ros
g ms
(38)
.
rol
1
=
≈
1 + ( 1 + λbl ) g ml rol
g ml
Accordingly, the resultant effective transconductance and voltage gain metrics derive directly
from (13) and (18) into which we need only to substitute the foregoing expressions for Rss and Rl.
The pertinent results are
⎛ gms ro ⎞
gm ⎜
⎟
1 + gms ro ⎠
gm
⎝
gme =
≈
(39)
gm
1 + λb ) gm ro
(
1
+
1+
gms
1 + gms ro
1
=
(1 ros ) + gms 1 +
1
Rl =
(1 rol ) + (1 + λbl ) gml
Rss =
and
⎛
1 ⎞
g m ⎜ Ros
⎟
⎡
⎤
gml ⎠
Vos
rol
⎝
Avs =
= − gme ⎢ Ros
,
(40)
⎥ ≈ −
g
Vs
1 + (1 + λbl ) g ml rol ⎦⎥
⎣⎢
1+ m
gms
where by (16) and (38), the output resistance, Ros, seen looking into the drain of transistor M in
Figure (6.10) is now given by
⎡
⎛
⎞⎤
ros
ros
gm ro
+ ⎢1 + ( 1 + λb ) gm ⎜
.
Ros =
(41)
⎟ ⎥ ro ≈
1 + g ms ros ⎣
gms
⎝ 1 + gms ros ⎠ ⎦
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It is interesting to examine the gain expression in (40) from the perspective that the
output resistance, Ros, is, by (41), likely to be appreciably larger than the inverse of the
transconductance, gml, presented to the drain of transistor M by the diode-connected load device,
transistor Ml. With Ros >> (1/gml), (40) reduces to the approximate form,
gm
V
gml
Avs = os ≈ −
.
(42)
g
Vs
1+ m
g ms
But we note that the quiescent drain current, IdQ, flowing in the so-called driver transistor, M, is
identical to the Q-point drain current conducted by both transistors Ms and Ml. Since all transistors are fabricated on the same monolithic chip, all such devices have identical transconductance
coefficients, Kn. Indeed, the three transistors in the schematic diagram of Figure (6.10) differ to
first order only with respect to their gate aspect ratios, which are chosen by the circuit designer.
Remembering, therefore, that transistors Ms and Ml have gate aspect ratios of ηs and ηl, respectively, and taking η as the gate aspect ratio of transistor M, (6) gives the pertinent device forward
transconductances as
g ms ≈
2K n ηs I dQ
g ml ≈
2K n ηl I dQ
gm ≈
2K n η I dQ
(43)
.
We resultantly see that the ratio of any two of these transistor transconductances is simply the
square root ratio of their corresponding gate aspect ratios. It follows that (42) can be written as
η
gm
ηl
V
g ml
(44)
Avs = os ≈ −
≈ −
.
gm
Vs
η
1+
1+
g ms
ηs
This result is interesting in that gate aspect ratios, and particularly ratios of gate aspect ratios, can
be controlled very accurately during the chip fabrication process. Accordingly, the gain of the
amplifier at hand is rendered very predictable and arguably even very reliable since performance
predictability usually begets operational stability and reliability. We should also note that the
voltage gain in (44) is obviously smaller than the square root ratio of driver to load gate aspect
ratios because of the deployment of source degeneration in the form of transistor Ms. Since a
prime motivation underlying the use of source degeneration is the reduction of performance
sensitivity to ill-defined and ill-controlled transistor parameters, this degeneration in the circuit
of Figure (6.10) is superfluous overkill. If the source terminal of transistor M were grounded by
implementing Rss = 0 in Figure (6.1a), the effect is, by (38), an infinitely large gms, as is projected by the modified amplifier of Figure (6.11). It follows that the resultant small signal voltage gain at low to moderate signal frequencies is
V
g
η
(45)
Avs = os ≈ − m ≈ −
.
Vs
g ml
ηl
which obviously still exudes numerical predictability.
Yet another aspect of the amplifiers in both Figures (10) and (11) is the apparent fact
that with the drain load resistance emulated actively by a diode-connected transistor, the load
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actually driven by the amplifier is not connected in series with the drain circuit of transistor M.
Instead, the load is external to the amplifier and is connected, perhaps with capacitive coupling,
from the drain node of transistor M to ground. To this end, the amplifiers in either of the two
aforementioned figures are decent voltage amplifiers because the output resistance, Rout, seen
looking back toward the drain node of transistor M can be relatively small. This resistance is the
parallel combination of the resistance seen south of the drain node and that seen north of the
load; specifically,
+Vdd
Ml
Rl
Rs
+
Id
Vi
M
Vo
Ros
Rout
Vs
−
+
Vgg
Ris
−
Figure (6.11). The amplifier of Figure (6.10) operated without source
degeneration.
1
,
(46)
gml
where use is made of an earlier observation that Ros in (41) is large and Rl in (38) is approximately the inverse of the forward transconductance associated with the load transistor. To the
extent that the gate aspect ratio of the load device is large, and/or at least a moderate amount of
drain current is allowed to flow through transistor Ml, gml is relatively large, whence a the
reasonably small output resistance that befits a practical voltage amplifier.
Rout = Ros Rl ≈
6.2.3.4. CMOS Amplifier
Yet another variant of the canonic common source amplifier is the complementary
MOSFET, or CMOS structure displayed in Figure (6.12a). This form of the common source
configuration finds widespread utility in applications, such as operational amplifiers, which require very high open loop (meaning prior to the incorporation of feedback) voltage gains. It is
termed a complementary MOSFET stage because of the use of both an n-channel device (transistor Mn in the figure) and a p-channel transistor (Mp). No source degeneration is invoked since
resistances inserted in the source lead of the n-channel driver compromise the available voltage
gain of the stage, and the primary purpose of CMOS signal processing is the delivery of very
high voltage gain. We note that the gate terminal of the PMOS transistor is connected to a
presumably constant biasing voltage, Vbias, which means that the gate of transistor Mp in Figure
(6.12a) lies at signal ground. Both the source and bulk terminals of Mp are likewise signal
grounded through the constant power bus voltage, Vdd. We accordingly recognize that for small,
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low frequency signals, transistor Mp effectively functions as a straightforward resistive load imposed on the drain of transistor Mn. In effect, transistor Mp functions as an active equivalent to
the drain load resistance, Rl, used in the amplifier of Figure (6.1a). The value generated for Rl is
the channel resistance, rop, of transistor Mp, which is very large.
+Vdd
Vbias
Mp
Rl
Vo
Id
Rs
Vi
+
Mn
Ros
Rl
Mp Gate
Vs
−
+
Vgg
Ris
−
(a).
Mp Drain
+
Va = 0
−
Mp Source
−
Vb = 0
+
Mp Bulk
gmpVa
λbpgmpVb
rop
(b).
Figure (6.12). (a). CMOS common source amplifier. The amplifier utilizes a p-channel transistor to
synthesize the drain load resistance imposed on the n-channel transistor. (b). Low frequency, small signal model of transistor Mp in the circuit of (a).
The last contention in the preceding paragraph is easily verified through a casual
inspection of the pertinent small signal model for Mp, which is offered as Figure (6.12b). We
should take special note of the fact that the model for the p-channel transistor is identical to the
model used to analyze the small signal performance of n-channel devices. Since the signal
component, Va, of the gate-source voltage applied to Mp is zero by virtue of the fact that the gate
and source terminals of this transistor are incident with signal ground, gmpVa in this model is
zero. Similarly, the bulk transconductance generator, λbpgmpVb is zero because bulk-source signal voltage Vb is forced to zero through signal grounding of both the bulk and source terminals.
Resultantly, only the channel resistance, rop, remains in the low frequency small signal model.
This channel resistance is upwards of several thousand to even several tens of thousands of
ohms. Such a large resistance value for the passive drain load in Figure (6.1a) is impractical because of biasing constraints. For example, if Rl = 10 KΩ, a mere 1 mA of Q-point drain current
conducted by the n-channel device mandates a power line voltage, Vdd, in excess of 10 volts in
that Vdd must supply energy to both the load resistance, Rl, and the n-channel transistor. But in
the active PMOS load realization of Figure (6.12a), the voltage drop across transistor Mp need
only be slightly larger than the drain saturation voltage, which for small geometry transistors, is
typically of the order of less than a volt. In effect, the CMOS amplifier gives us our cake, in the
form of a very large load resistance, while providing that good chocolate icing as well through
the need of only a relatively small power line voltage.
A stipulation of the voltage gain provided by the CMOS amplifier involves little more
than a reexamination of (13), (16), and (18), which collectively define various common source
performance metrics in generalized terms. For example, since the source degeneration
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resistance, Rss, is zero in the network of Figure (6.12a), (13) confirms an effective forward
transconductance that is identical to the transconductance, gmn, of the n-channel driver in the basic CMOS stage. Additionally, (16) shows that the low frequency resistance seen looking into
the drain of a common source amplifier exploiting no source degeneration is simply the channel
resistance, ron of the n-channel driver; that is, Ros = ron. Then, from (18), the low frequency,
small signal voltage gain, Avs, of the CMOS stage follows as
V
(47)
Avs = os = − g mn ron rop .
Vs
where we have made use of the fact that the effective load resistance imposed on the drain of the
n-channel driver is rop.
(
)
Variations of the basic CMOS gain stage abound. One commonly used example of an
alternative CMOS common source network is the amplifier appearing in Figure (6.13). In this
configuration, we note that both the source signal and the gate biasing voltage are commonly applied to the gate terminals of both the p-channel device and the n-channel transistor. The common connection of the signal source to both gates means that the resultant output signal response
effectively reflects a superposition of the small signal dynamics associated with two common
source amplifiers. In particular, we have an n-channel common source amplifier loaded in an
active p-channel load combined with a p-channel common source amplifier terminated at its
drain in an active n-channel load. An analytical confirmation of this viewpoint is left as an
exercise for the reader, who should be able to show that the resultant small signal gain of the
subject network is
+Vdd
Mp
Rl
Vi
Vo
Id
Rs
+
Ris
Ros
Mn
Vs
−
+
Vgg
−
Figure (6.13). A commonly exploited variation
of the basic CMOS common
source amplifier in Figure (6.12a).
(
)(
)
Vos
(48)
= − g mn + g mp ron rop ,
Vs
which clearly suggests that the stage in Figure (6.13) is capable of a potentially significantly larger gain magnitude than is the basic CMOS cell we investigated earlier.
Avs =
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age, which is VoQ, is at least as large as its applied gate-source voltage, which is Vgg, less an nchannel threshold potential, Vhn; that is,
(49)
VoQ ≥ Vgg − Vhn .
In order for the p-channel transistor to be in saturation
Vdd − VoQ ≥ Vdd − Vgg − Vhp ,
(50)
where Vhp represents the threshold voltage of transistor Mp. We note that (50) equates to the
constraint,
(51)
VoQ ≤ Vgg + Vhp .
A comparison of (51) with (49) underscores the necessity of sustaining a Q-point voltage at the
output port that lies in the somewhat narrow range between one n-channel threshold voltage
below Vgg and one p-channel threshold voltage above Vgg. This range of allowable Q-point voltage essentially brackets the maximum permissible dynamic range, or “swing,” of the output signal response, Vos.
Setting the output Q-point voltage reliably and predictably to an appropriate value that
satisfies both (49) and (51) is a not a trivial design task. The problem stems from the fact that to
the extent that channel length modulation phenomena are negligible, the p-channel transistor acts
as an ideal source-drain current source that is placed in series with an ideal drain-source current
sink emulated by the n-channel transistor. Specifically, for the p-channel transistor,
⎛ Kp ⎞
2
,
I dQ = ⎜
(52)
⎟ η p Vdd − Vgg − Vhp
⎝ 2 ⎠
while for the n-channel device,
2
⎛K ⎞
,
I dQ = ⎜ n ⎟ ηn Vgg − Vhn
(53)
⎝ 2 ⎠
where ηp and ηn stipulate the gate aspect ratios of transistor Mp and transistor Mn, respectively.
We observe that these two relationships are independent of the quiescent output voltage, VoQ,
which means that equating these two expressions fails to define a value of VoQ. Precisely the
same problem pervades the basic CMOS cell of Figure (6.12a). The problem at hand is akin to
the classic insoluble problem that is abstracted in Figure (6.14). In this problem, the neophyte
circuits student is asked to attempt the determination of the voltage, VoQ, across an ideal current
source (IdQ) that is placed in series with a second current source, necessarily having the same current value of IdQ, both of which are driven by a known voltage source, Vdd. Before the student
striving to solve the problem contemplates something rash, we remind him or her that since the
current conducted by an ideal current source (or sink) is independent of the voltage developed
across the terminals of the source or sink, the problem assigned cannot be solved.
(
(
)
)
It is one thing to pull a nasty trick of an unsuspecting circuits student. It is quite another thing to circumvent the problem pragmatically with circuit hardware. To this end, a strategy involving the use of common mode feedback is typically exploited. In this design approach,
a replica of the CMOS stage is incorporated as a means of monitoring a linear proportionality of
the desired Q-point output voltage. This measured voltage is compared to a reference voltage,
whose value is usually the desired Q-point output voltage. The response to the difference between monitored and reference voltages is appropriately fed back to the CMOS stage to achieve
the desired static output. We shall leave the detailed discussion of common mode feedback to
another time.
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+Vdd
IdQ
Drain Current of
p-Channel Transistor
VoQ
Drain Current of
n-Channel Transistor
IdQ
Figure (6.14). Illustration of the output voltage biasing
problem in the CMOS amplifiers of either Figure (6.13) or Figure (6.12a)
6.3.0. COMMON DRAIN AMPLIFIER
The simplified schematic diagram of an NMOS common drain amplifier, which is also
known as a source follower is drawn in Figure (6.15a). Its PMOS counterpart appears as Figure
(6.15b). In the source follower, we see that the input signal is applied to the gate terminal of the
utilized transistor, while the output response, which is traditionally a signal voltage, is extracted
at the source terminal. As in the common source amplifier, the power line voltage, Vdd, and the
gate biasing voltage, Vgg, are selected to ensure that the transistor operates in its saturation domain for all anticipated amplitudes of the signal voltage, Vs. But unlike the common source
stage, the source follower is rarely postured as a standalone amplifier. Instead, it is commonly
used in conjunction with a common source amplifier that is called upon to deliver gain to a
strongly capacitive load or more generally, a low impedance load termination. As such, the
source follower serves as a buffer inserted between the output port of a common source amplifier
and the load. In such a buffering application, voltage Vgg commonly derives from the output Qpoint voltage of the predecessor common source amplifier.
The contention is that the source follower functions as a voltage buffer inserted between the output port of a predecessor stage of amplification and a presumably low impedance
load that the preceding stage is prevailed upon to drive. Recall that an ideal voltage buffer boasts
unity I/O voltage gain, infinitely large input impedance, and zero output impedance. As such,
there is the inference that the MOSFET source follower boasts at least near unity voltage gain,
very large input impedance, and very low output impedance. An inspection of either schematic
diagram in Figure (6.15) confirms that for low to moderately high frequencies, the input resistance, Rid, is infinitely large, since the input port is incident with the gate terminal of the utilized
transistor. We might hazard a guess that the output resistance, Rod, is low at low signal frequencies, since the output port is formed by the source terminal of the transistor and signal ground.
We proffer this contention in light of our earlier work with diode-connected transistors, which
presented a small resistance of approximately 1/gm at its source terminal. If a relatively small
output resistance prevails for the source follower, it makes sense to represent the follower output
port by a Thévenin equivalent circuit.
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+Vdd
Rl
+Vdd
Rs
+
Vs
+
−
Vo
Rid
+
Vi
Vs
Rod
−
Vgg
Rs
Vi
Vo
Rod
Rl
Vgg
−
+
Rid
−
(a).
(b).
Figure (6.15). (a). Simplified schematic diagram of a common drain amplifier realized with an n-channel
transistor. (b). The p-channel counterpart to the source follower in (a).
6.3.1. SMALL SIGNAL ANALYSIS
With the load resistance, Rl, removed, as befits a Thévenin equivalent circuit, the low
frequency, small signal model of either of the two source followers diagrammed in Figure (6.15)
appears as the network in Figure (6.16). For clarity, the transistor gate, drain, source, and bulk
nodes have been labeled by the boldface letters, G, D, S, and B, respectively. With the load open
circuited, the response established at the source terminal is not the signal component, Vos, of the
net output voltage, Vo, but instead, it is the signal level Thévenin, or open circuit, output voltage,
Vot. The Thévenin resistance established at the source port is indeed the output resistance, Rod, in
which we are interested. We can succumb to the crank and grind circuit analysis strategy to deduce expressions for Vot and Rod. Or we can be a bit more creative and reduce the model in question to a simplified topological structure that inspires an insightful understanding of the dynamics that underpin the Thévenin voltage and output resistance. Guess which approach we shall
adopt.
Rid
G
Rs
+
Vs
−
+
V1
−
D
gmV1
−
V2
+
λbgmV2
ro
Vot
S
Rod
B
Figure (6.16). Low frequency, small signal model of either of the source followers appearing in Figure (6.15).
We begin by observing in Figure (6.16) that the gate-source signal voltage, V1, is the
signal voltage difference, (Vs − Vot). Our unbelievable astuteness resultantly postures
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g mV1 = g mVs − g mVot ,
(54)
which implies that the controlled current, gmV1, flowing from the drain terminal of the transistor
to the source terminal, where voltage Vot is sustained, can be viewed as the shunt interconnection
of two controlled currents. One of these currents is gmVs, which flows from drain to source in the
same direction as does the original gmV1, while, because of the minus sign in (54), the other
current, gmVot, is directed from source to drain, opposite to the flow of gmV1. These observations
are portrayed schematically as step 1 in the modeling diagram of Figure (6.17a). But since voltage Vot appears directly across, and in associated reference polarity with, the controlled current,
gmVot, current gmVot can be supplanted, as suggested in step 2 of Figure (6.17a), by a simple
branch whose resistance value is 1/gm. We note that the current flowing though this resistive
branch is indeed gmVot, identical to the current value of the controlled source it replaces. In step
3 of Figure (6.17a) we simply redraw the outcome of the preceding modeling step to depict the
source terminal at the top of the structure and open circuit voltage Vot, established with respect to
signal ground, to which the drain terminal is incident, at the source terminal.
1
D
2
D
gmV1
gmVs
3
D
gmV ot
Vot
1
gm
gmVs
S
S
gmVs
S
Vot
Vot
S
1
gm
D
Vot
(a).
1
D
2
D
λbgmV 2
S
λbgmVot
S
S
Vot
Vot
3
S
Vot
1
λbgm
λbgmVot
D
D
Vot
(b).
Vot
S
gmV s
1
λbgm
1
gm
D
ro
Rod
(c).
Figure (6.17). (a). Replacement of the voltage controlled current source, gmV1, in the model
of Figure (6.16) by a controlled source, gmVs shunted by a branch resistance
of value 1/gm. (b). Replacement of the controlled source, λbgmV2, in the
source follower model of Figure (6.15) by a branch resistance of value
1/λbgm. (c). Simplified model for the open circuited output port of the source
follower whose equivalent circuit appears in Figure (6.15).
Returning to Figure (6.16), we see that the bulk-source signal voltage, V2, is precisely
the negative of voltage Vot. Thus, the λbgmV2 source, whose current flows from drain to source,
is equivalent to a current, λbgmVot, directed from source to drain, as illustrated in step 1 of Figure
(6.17b). Step 2 in this diagram is a trivial redraw of the result of step 1, wherein we see that voltage Vot appears directly across the subject generator. Step 3 therefore follows naturally in that
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the λbgmVot generator in the outcome of step 2 can be represented electrically as a branch resistance of 1/λbgm.
We can conflate the foregoing two disclosures with the output port of the general model
given in Figure (6.16) to arrive at the Thévenin representation of the follower output port given
in Figure (6.17c). This diagram straightforwardly depicts the output resistance, Rod, as the parallel combination of the three resistances, 1/gm, 1/λbgm, and ro; namely,
ro
Rod =
.
(55)
1 + ( 1 + λb ) g m ro
As we suspected, this resistance approaches 1/gm, but only if λb << 1 and gmro >> 1. The constraint entailing the bulk transconductance factor, λb, is reasonable for most properly biased
MOSFETs. The second requirement, gmro >> 1 is somewhat problematic for deep submicron
devices, which deliver arguably anemic forward transconductances and drain-source channel
resistances for routine gate aspect ratios and reasonable biasing. In view of (55), the Thévenin
voltage gain, Atd = Vot/Vs, projected by the simple model in Figure (6.17c) is
V
g m ro
(56)
Atd = ot = g m Rod =
,
Vs
1 + ( 1 + λb ) g m ro
which is clearly less than one. We do see, however, that Atd approaches unity for the same constraints that validate the approximation, Rod ≈ 1/gm. The foregoing two results directly enable the
equivalent circuit shown in Figure (6.18), which represents the terminated output port of the
source follower operated at relatively low signal frequencies. This structure highlights a terminated voltage gain, Avd = Vos/Vs, of
⎡
⎤⎛
⎛
⎞
⎞
V
Rl
g m ro
Rl
Avd = os = Atd ⎜
(57)
⎥⎜
⎟.
⎟ = ⎢
Vs
⎝ Rl + Rod ⎠
⎣ 1 + ( 1 + λb ) g m ro ⎦ ⎝ Rl + Rod ⎠
Rod
Vos
+
AtdVs
Rl
−
Figure (6.18). The terminated output port model,
which exploits Thévenin’s theorem,
for either source follower depicted
in Figure (6.15).
which remains less than one and is indeed smaller than the Thévenin voltage gain, Atd. If the
terminating load resistance, Rl is appreciably larger than the follower output resistance, Rod,
which fundamentally mandates gmRl >> 1, Avd approaches its open circuit value, which can be
near unity as discussed earlier. Note further that no phase inversion prevails between the input
and output ports of the source follower. Engineering credence is lent to the latter observation by
returning to either amplifier in Figure (6.15). In the NMOS circuit of Figure (6.15a), for example, we observe that an increase in the source signal voltage, Vs, manifests an increase in the
gate-source signal voltage, which in turn spawns an increase in the drain current conducted by
the transistor. Since the drain current is necessarily dumped into the load resistance, Rl, across
which the signal voltage response, Vos is extracted, we confirm that Vos rises with increasing Vs
(and vice versa). The lack of phase inversion, together with an I/O gain that can approach one, is
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ostensibly the reason that the common drain amplifier is often termed a source follower; that is,
the “source follows the gate” in the sense of producing an output voltage response that virtually
mirrors the signal applied at the gate input port. It nonetheless bears underscoring that when
realized in deep submicron MOS technology, the relatively anemic nature of both the forward
transconductance and the drain-source channel resistance rarely allows a voltage gain that is larger than around 850 mV/volt. Moreover, the output resistance for these configurations is hardly
near zero and is typically in the high tens to hundreds of ohms.
6.3.2. SOURCE FOLLOWER WITH ACTIVE LOAD
In order to achieve a terminated voltage gain that approaches its open circuit value in a
source follower, a sufficiently large load resistance, Rl is clearly required. Unfortunately, too
large of a load resistance in either of the common drain units shown in Figure (6.15) requires a
commensurately large power line voltage, Vdd, which must supply voltage to both the load
resistance and the transistor. One way of achieving large effective Rl without requiring a
significant increase in the power line voltage is to replace the passive load resistance, Rl, by an
active load that functions as an approximate ideal current source or sink. An NMOS example of
such a variation to the basic follower is provided in Figure (6.19), where the load resistance in
the original schematic diagram is replaced by transistor Ml. We see that the gate of this
introduced device is biased by constant voltage, thereby resulting in null gate-source signal
voltage. For this zero gate-source signal voltage and the connection of both the bulk and source
transistor terminals to ground, the small signal model of transistor Ml consists solely of its
channel resistance, say rol, which can be substantial for appropriate choices of gate aspect ratio
and quiescent current. In other words, Ml approximates a constant current generator that
provides a current path to ground for the source current conducted by the follower transistor, M.
We say that Ml behaves as a current sink in that it returns the current of transistor M to ground.
As such, its function is similar to the active load transistor Mp in the CMOS amplifier of Figure
(6.12), except that Mp therein sources current (meaning it supplies current) to the common
source transistor, Mn. The resultant terminated voltage gain of the actively loaded source
follower derives directly from (57), subject to the proviso that resistance Rl in that expression is
replaced by the channel resistance, rol, of transistor Ml.
+Vdd
Rs
+
Vs
−
+
Vgg
M
Vi
Rod
Rid
Vbias
Ml
Vo
−
Figure (6.19). The NMOS source follower of Figure
(6.15a) with the passive load resistance,
Rl, replaced by an active, current sinking load comprised of transistor Ml.
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6.3.3. BUFFERED COMMON SOURCE AMPLIFIER
A meaningful example of a source follower buffering application initiates with a
reconsideration of the actively loaded common source amplifier shown in Figure (6.12a). This
amplifier is redrawn in Figure (6.20a), subject to the incorporation of a capacitive load, Cl, across
the output port. The subject load capacitance can represent the input impedance of a succeeding
common source amplifier, or it can represent the input port capacitance of a data converter,
signal processor, or some other form of dominantly capacitive load that the base amplifier
comprised of transistors Mn and Mp is compelled to drive. The fundamental problem with this
CMOS amplifier, aside from the biasing issues discussed earlier, is that the 3-dB bandwidth of
the stage at hand is limited by the substantial output resistance, Rout1, which faces capacitance Cl.
This output resistance is the parallel combination of the channel resistances, ron and rop, of the
NMOS and PMOS transistors, respectively. As a result, the bandwidth, say B1 of the stage is,
assuming that no capacitances within the models of the transistors are significant at frequency
B1,
1
1
(58)
B1 =
=
,
Rout1Cl
ron rop Cl
(
)
which is potentially deficient in light of the fact that both ron and rop are reasonably large
resistances. At frequencies lying below the 3-dB bandwidth and thus, for frequencies within the
passband of the amplifier, Cl emulates an open circuit. Resultantly, the amplifier in Figure
(6.20a) reduces to the topological form of the network in Figure (6.12a). This means that the low
frequency gain of the amplifier at hand remains given by
V
(59)
Avs = os = − g mn ron rop ,
Vs
where model parameter gmn is recalled as the forward transconductance of the n-channel
transistor that serves as the driving amplifier in Figure (6.20a). It follows that the gainbandwidth product, GBPs, of the topology under current scrutiny is
(60)
GBPs = Avs B1 = g mn Cl .
(
)
For a fixed load capacitance, we see that the gain bandwidth product, which we should like to
have as large as possible so that we might achieve a large magnitude of passband gain and a
large bandwidth, is controlled exclusively by the transconductance of the driver. We remember
that the transconductance can be increased through increases in the transistor gate aspect ratio
and/or increases in the Q-point drain current. But large gate aspect ratios run the risk of
magnifying transistor capacitances to levels that challenge the presumption of a clearly dominant
load capacitance and thus potentially compromise the accuracy of the 3-dB bandwidth
relationship in (58). On the other hand, large quiescent drain currents imply possibly
unacceptably large circuit power dissipation.
In order to understand how the buffer introduced in Figure (6.20b) addresses the
challenge of a desirably large circuit gain-bandwidth product, we note that the load capacitance
is now incident with the output port of the source follower formed by transistor M and its source
lead load, transistor Ml. Since channel resistance rol is the resistance presented to this output port
by Ml and Rod, as given by (55), is the resistance seen looking into the source of transistor M, the
time constant associated with load capacitance Cl, is simply the product of Cl and the parallel
combination of resistances rol and Rod. Assuming that Cl remains the dominant capacitance in
the circuit, this means that the revised 3-dB bandwidth, B2, is
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+Vdd
Vbias
Mp
rop
Rout1
Vo
Id
Rs
Vi
+
ron
Mn
Cl
Vs
−
Ris
+
Vgg
−
(a).
+Vdd
Vbias
Mp
rop
Id
Rs
Vi
+
Rout1
Vi
ron
Rod
Mn
Vo
Vs
rol
−
+
Vgg
M
Ris
Vbias
Ml
Cl
−
(b).
Figure (6.20). (a). Common source CMOS amplifier of Figure (6.12a) with capacitive load appended. (b). Common source amplifier of (a) with source follower buffer inserted
between the output port of the common source unit and the capacitive load.
B2 =
g
1
1
≈
≈ m ,
( rol Rod ) Cl Rod Cl Cl
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where we have tacitly presumed large channel resistances in both transistors and negligible body
effect in the source follower device, M, whose forward transconductance is symbolized herewith
as gm. Under these approximate operating conditions, the small signal gain, Vos/Vis, in the
buffered amplifier of Figure (6.20b) is, by (57), very close to unity, which means that the overall
gain, Vos/Vs, within the passband remains the same as stipulated by (59); namely, Avs. This
assertion follows from our observation that the output signal voltage, Vis, developed at the drain
of transistor Mn in Figure (6.20b) is essentially an open circuit voltage in that Vis is applied to the
gate terminal of transistor M. But signal voltage Vos in Figure (6.20a), to which (59) pertains, is
also an open circuit voltage in that the load capacitance in this schematic diagram behaves as an
open circuit within the passband of the amplifier. Consequently, the buffered gain-bandwidth
product, say GBPb, is
⎛g ⎞
(62)
GBPb ≈ Avs B2 ≈ g mn ron rop ⎜ m ⎟ ≈ ⎡ g m ron rop ⎤ GBPs .
⎣
⎦
⎝ Cl ⎠
(
)
(
)
Obviously, the buffered gain-bandwidth product exceeds its non-buffered counterpart if
gm(ron||rop) > 1. For routine source follower biasing currents, the satisfaction of this inequality is
all but guaranteed if for no other reason than resistances ron and rop, which remain unaffected by
source follower biasing, are reasonably large.
6.4.0. COMMON GATE AMPLIFIER
The last of the three analog canonic cells of MOSFET technology is the common gate
amplifier for which signal is applied at the source terminal and response is extracted at the drain
terminal. We have already witnessed through our work with diode-connected transistors and the
source follower that the resistance established at the source terminal of a MOSFET is relatively
low and indeed, is of the order of an inverse transconductance. We have also seen that the resistance established at the drain terminal of a MOS technology amplifier is at least as large as the
channel resistance of the utilized device. It is therefore logical (but not completely necessary) to
posture the signal applied to the input port of a common gate unit as a current source and thence
to extract the response associated with this input signal as itself a current. For these reasons, we
choose to depict the NMOS common gate amplifier as the topology in Figure (6.21a), where,
unlike the common source and common drain cases, the input signal is represented as a Norton
equivalent circuit comprised of signal current Is and source resistance Rs. Because of this Norton
representation, it is fair to presume that resistance Rs is large. The output response to current Is is
the signal component, say Ios, of the net output current, Io, flowing through the load resistance, Rl
and, of course, through the drain of the transistor, whose gate is biased at a constant voltage,
Vbias. The constant, or static, current, IQ, together with the power line voltage, Vdd, and the gate
biasing voltage, Vbias, biases the transistor in its saturation regime. The low frequency, small signal equivalent circuit of the amplifier before us appears in Figure (6.21b). For clarity, we have
delineated the gate, drain, source, and bulk terminals of the transistor model. Additionally, we
have noted that the signal current, Ios, conducted by the load resistance and the drain of the
transistor is necessarily identical to the transistor source current because zero current flows
through the gate at low signal frequencies.
6.4.1. SMALL SIGNAL METRICS
We commence our analysis of the common gate amplifier with an investigation of the
input resistance, Rig, seen by the applied signal source. To this end, the model in Figure (6.22a)
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+Vdd
Rl
Rog
Io
G
Rog
+
V1
−
Vbias
Is
gmV1
−
V2
+
Rig
IQ
D
ro
λbgmV 2
Rl
S
Rig
Ios
Is
Rs
Ios
Rs
B
(b).
(a).
Figure (6.21). (a). Basic schematic diagram of a common gate amplifier driven by an input current signal.
The output response is taken as the signal component of current Io. (b). Low frequency, small
signal equivalent circuit of the amplifier in (a).
allows us to evaluate Rig as the voltage to current ratio, Vx/Ix, of our mathematical ohmmeter,
which we apply as current Ix directed from signal ground to the transistor source terminal. The
subject model, which is offered as Figure (6.22a), derives directly from Figure (6.21b), which
confirms the voltage identity, V1 ≡ V2 ≡ −Vx. Due account is made of this voltage constraint by
adding the currents of the two voltage controlled current sources and flipping their directional
flow. From Figure (6.22a), Kirchhoff infers
D
ro
(1+λb)gmVx
Ix − (1+λb )gmVx
Rig
Ix
S
+
Vx
−
Rl
Ios
S
Ix
Is
B
Rs
Rig
B
(a).
(b).
Figure (6.22). (a). Low frequency, small signal model used in the evaluation of the input
resistance, Rig, of the common gate amplifier in Figure (6.20a). (b).
Representation of the input port of the common gate configuration.
Vx = ro ⎡⎣ I x − ( 1 + λb ) g mVx ⎤⎦ + Rl I x ,
from which we deduce immediately that the input resistance is
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Vx
ro + Rl
.
=
(64)
Ix
1 + ( 1 + λb ) g m ro
Three important observations surface from this resistance relationship. First, we note that for a
large channel resistance, ro, and negligible bulk-induced threshold voltage modulation (λb ≈ 0),
Rig ≈ 1/gm. This approximate result mirrors expectations since the input port of a common gate
amplifier is formed with respect to ground at the device source terminal where we have previously observed a nominal resistance of an inverse forward transconductance. Second, we see
that for the special case of Rl = 0, Rig is identical to Rod, the output resistance of a source follower, as per (55). Once again, we draw engineering comfort from this conclusion in that the
output port of a source follower, which inherently has zero resistance in the drain terminal of the
transistor deployed in the follower, is, like the input port of the common gate amplifier, formed
by the device source terminal and signal ground. Finally, since the signal current, Ios, conducted
by the resistive load imposed on the common gate unit also flows through the device source
terminal where we have deduced a port resistance of Rig, we are motivated to represent the
amplifier input port by the simple structure in Figure (6.22b). The resultant current gain, say Aig,
now derives straightforwardly as
I
Rs
Rs
g m Rs
Aig os =
,
=
≈
(65)
ro + Rl
Is
Rs + Rig
1 + g m Rs
Rs +
1 + ( 1 + λb ) g m ro
Rig =
where the indicated approximation once again invokes the presumptions of large channel resistance and negligible body effect.
In (65), we witness a common gate current gain that displays no phase inversion and a
magnitude that is always less than one. The absence of phase inversion between the input and
output currents supports the small signal dynamics implied by the model in Figure (6.21b). In
particular, the current response, Ios, conducted by the load resistance necessarily flows into the
drain terminal of the transistor and then out of the source terminal, which is the indicated directional flow of the signal source current, Is. We also notice that Aig tends toward unity if Rs >>
Rig, whose satisfaction likely bodes no significant challenge in that Rig is a reasonably small
resistance. In fact, if Rs is infinitely large, Aig is precisely one, which is gratifying in light of the
fact that zero signal current in the gate lead of the transistor clearly forces an identity between
the drain and source terminal signal currents. A final important observation is that to the extent
that ro is large and λb is small in (65), the current gain, Aig, is roughly invariant with the load
resistance. This fact suggests that the common gate amplifier is characterized by a very large
output resistance, Rog, as compared to the drain load resistance, Rl.
The foregoing contention as regards output resistance can be confirmed through use of
the basic common gate model in Figure (6.21b). To this end, the subject model is redrawn in
Figure (6.23a), where the terminating load resistance, Rl, has been supplanted by our proverbial
mathematical ohmmeter, the signal source, Is, is set to zero, and use is once again made of the
fact that the gate-source and bulk-source signal voltages, V1 and V2, respectively, are identical.
Moreover, since the ohmmeter signal current, Ix, enters the drain terminal of the transistor and
exits its source terminal, V1 ≡ V2 ≡ −RsIx. Thus, the two controlled generators, gmV1 and λbgmV2,
can be replaced by a single controlled source of value (1+λb)gmRsIx, the direction of which is
opposite to either of the two original current generators. These manipulations are reflected by
the model in Figure (6.23a). By inspection, we conclude an output resistance, Rog, of
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Rog
D
(1+λb)gm RsIx
S
Ix
Ix + (1+λb )gm Rs Ix
ro
+
Vx
−
Ix
D
AngIs
Rs
B
IN
Ios
Rog
Rl
B
(b).
(a).
Figure (6.23). (a). Low frequency, small signal model used to investigate the output
resistance, Rog, of the common gate amplifier in Figure (6.20a). (b). Norton
representation of the output port of the common gate configuration.
Vx
= Rs + ⎡⎣1 + ( 1 + λb ) g m Rs ⎤⎦ ro ≈ (1 + gm ro ) Rs .
(66)
Ix
Since the resistance, Rs, of the signal source applied to the common gate amplifier is invariably
large for most practical applications of the amplifier in question, (66) assures a very large output
resistance, Rog.
Rog =
With resistance Rog well-defined and analytically determined to be large, it may be prudent to wrap up this phase of our electronic amplifier discussion by formulating the Norton
equivalent representation of the common gate output port. We need only determine the Norton,
or short circuit output current, IN. Since (65) effectively defines the generalized common gate
current gain in terms of any load termination, Rl, we readily arrive at the Norton current gain,
Ang, by simply setting the load resistance to zero in (65). Accordingly,
I
Rs
g m Rs
(67)
Ang N = Aig
=
≈
≈ Aig .
Rl =0
ro
+
g
R
Is
1
m
s
Rs +
1 + ( 1 + λb ) g m ro
Because gmro is generally a large number and λb is almost always significantly smaller than one,
it is interesting that the Norton gain closely approximates the actual common gate current gain.
The resultant Norton model of the output port is the network shown in Figure (6.23b), which
postures a terminated common gate amplifier current gain of
⎛ Rog ⎞
I
Aig os = Ang ⎜
⎟
⎜ Rog + Rl ⎟
Is
⎝
⎠
⎡
⎤
⎢
⎥ ⎡ R + ⎡1 + ( 1 + λ ) g R ⎤ r ⎤
Rs
s
b m s⎦ o
⎣
⎥⎢
= ⎢
⎥ .
r
⎢R +
⎥ ⎢⎣ Rs + ⎣⎡1 + (1 + λb ) gm Rs ⎦⎤ ro + Rl ⎥⎦
o
⎢ s 1 + (1 + λb ) g m ro ⎥
⎣
⎦
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While it may not be immediately apparent, this expression, upon recall of (64), predicts identically the same gain as does the more compact gain form in (65). That which is immediately
evident is that both factors on the far right hand side of (68) are less than one, whence a terminated current gain, Aig, that always satisfies the inequality, Aig < 1.
6.4.2. COMMON SOURCE-COMMON GATE CASCODE
While the common gate amplifier can function as a standalone amplification cell, it is
more commonly used in conjunction with a common source amplifier to improve certain
performance metrics of the latter. A typically exploited application is the common source-common gate cascode for which a basic, but nonetheless practical, schematic diagram is provided in
Figure (6.24a). A source degeneration resistance, Rss, is included in this schematic diagram in
the interests of analytical generality, but its utilization is optional and dependent on the intended
application of the stage, the available standby voltage and power budgets, and other factors that
the design engineer must scrutinize. Figure (6.24b) redraws the network in Figure (6.24a) as a
signal schematic diagram, which is to say that all constant voltages, which are used exclusively
for biasing purposes, are replaced by short circuits that are returned to signal ground. Additionally, all branch and node variables are replaced by their small signal values. Most notably, the
net drain current Id becomes small signal drain current Ids, while the net output voltage, Vo, becomes its implicit signal component, Vos, in the signal schematic diagram. These actions reflect
the fact that the static voltages applied to the original circuit and which have been reduced to
zero in the signal schematic diagram, give rise to only quiescent branch current and node voltage
components, assuming that the biasing is judiciously implemented to achieve relatively high network linearity. Without such reasonable linearity, the superposition concepts effectively applied
to evaluate the static and small signal responses of the amplifier are invalid. Finally, the output
port of the source-degenerated common source amplifier formed of transistor M1, which drives
the input port of the common gate unit comprised of M2, has been supplanted by its Norton
equivalent circuit. To the latter end, we have relied on Figure (6.5), where by (13), the effective
forward transconductance, gme, of the common source cell is
⎛ ro1 ⎞
gm1 ⎜
⎟
ro1 + Rss ⎠
gm1
⎝
≈
.
(69)
gme =
1 + gm1Rss
1 + ( 1 + λb1 ) gm1 ( ro1 Rss )
In this expression, we understand that parameter gm1 represents the forward transconductance of
transistor M1, alone, at the operating point prescribed for M1. Of course, parameter λb1 represents the bulk transconductance factor of transistor M1. Moreover, resistance Ros in the Norton
model invoked in Figure (6.24b) is, by (16),
Ros = Rss + ⎡⎣1 + ( 1 + λb1 ) gm1Rss ⎤⎦ ro1 ≈ (1 + gm1Rss ) ro1 .
(70)
When we study the diagram in Figure (6.24b), it is important that we draw the proper
comparisons with the basic common gate amplifier in Figure (6.21a). In particular, the signal
current applied to the common gate amplifier in Figure (6.21a), which is generically symbolized
as Is, is now seen to be the current, gmeVs applied to the common gate input port of the cascode in
Figure (6.24b). Moreover, the generalized signal source resistance in Figure (6.21a) is now Ros,
the output resistance of the common source amplifier whose output port is coupled directly to the
common gate unit under present consideration. These circuit level interpretations, when viewed
in the context of the Norton common gate output port model developed in Figure (6.23b), allow
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the Norton embodiment for the output port of the cascode amplifier in the form of the structure
delivered in Figure (6.24c). In the latter diagram, the indicated Norton gain, is, using (67),
Rl
+Vdd
Vos
Ids
Rl
Rog
Vo
Id
M2
Rog
Ids
Rig
M2
Vbias
Id
Rs
+
Vi
gmeVs
Rig
Ros
M1
(b).
Ids
Vs
−
+
Ros
Ris
Ang gme Vs
Rss
Vgg
Rog
Vos
Rl
−
(c).
(a).
Figure (6.24). (a). Basic schematic diagram of a common source-common gate cascode amplifier. (b). Small signal schematic diagram of the amplifier in (a). The small signal
model of the output port for the common source amplifier formed of transistor M1
is represented by its Norton equivalent circuit. (c). Small signal Norton equivalent circuit of the output port formed of signal ground and the drain terminal of
the common gate transistor, M2.
Ang =
Ros
≈
g m2 Ros
≈ 1,
1 + g m2 Ros
(71)
ro2
Ros +
1 + ( 1 + λb2 ) g m2 ro2
where we have replaced source resistance Rs in (67) by the effective source resistance, Ros, seen
by the common gate device in Figure (6.24a). We have additionally taken the liberty of
presuming the plausible circumstance that gm2Rss >> 1 in (71).
Continuing with the Norton output port depiction in Figure (6.24c), shunt resistance Rog
derives directly from (66); namely,
Rog = Ros + ⎡⎣1 + ( 1 + λb2 ) g m2 Ros ⎤⎦ ro2 ≈ (1 + gm2 ro2 ) Ros .
(72)
This output resistance is formidably large in that it multiplies Ros, which is a resistance greater,
−and potentially significantly greater− than ro1, the channel resistance of the common source
transistor, M1, by a potentially large number, (1 + gm2ro2). As a result, we surmise a load resistance, Rl, which is significantly smaller than Rog, and we conclude a signal output voltage, Vos, in
Figure (6.24c) of
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)
Vos = − Ang g me Rog Rl Vs ≈ − gme RlVs .
(73)
It follows that the I/O voltage gain, Avc, of the common source-common gate cascode amplifier is
V
gm1Rl
Avc = os = − Ang gme Rog Rl ≈ − gme Rl ≈ −
.
(74)
Vs
1 + gm1Rss
(
)
Although the foregoing investigations systematically exploit straightforward circuit
analysis procedures, it may prove instructive and even insightful to execute an approximate study
predicated on the simplifying assumptions of infinitely large channel resistances and null bulk
transconductance factors. To begin, the signal voltage, Vs, applied to the amplifier in Figure
(6.24a) does not appear directly across the gate-source terminals of transistor M1 because of the
source degeneration resistance, Rss. Accordingly, the signal current, Ids, conducted by the drain
of M1 is not gm1Vs (which it would if Rss = 0) but is instead degraded by the factor, (1+gm1Rss).
In other words,
gm1Vs
I ds ≈
.
(75)
1 + gm1Rss
To the extent that channel resistances are large, the signal current given by (75) rolls through the
source and drain terminals of transistor M2 in Figure (6.24a) and ultimately through the
terminating load resistance, Rl. The signal voltage response, Vos, therefore follows as
g RV
Vos = − Rl I ds ≈ − m1 l s ,
(76)
1 + gm1Rss
whence the approximate voltage gain result in (74) is transparently confirmed.
A comparison of the cascode gain result in (74) with the gain disclosure in (18), which
applies to both of the single transistor common source amplifiers depicted in Figure (6.1),
suggests that the two voltage gains are virtually identical. Indeed, the two gains are identical if
the utilized transistors boast very large channel resistances and negligible bulk transconductance
factors. This gain observation logically begets questions as to what purposes are served by
merging the common gate cell with the common source amplifier into the cascode topology of
Figure (6.24b). The truth is that no gain advantages accrue from the cascode configuration. In a
sense, a penalty arguably accrues with the deployment of a common gate amplifier in conjunction with a common source amplifier in that in the cascode configuration, standby power dissipation must be supplied to two transistors as opposed to only one in the common source cell.
While the gain of the common source and common source-common gate cascode structures are virtually identical, the output resistance, as seen by the terminating load resistance, Rl,
is greatly enhanced by the insertion of the cascode stage. Indeed, (72) suggests that the factor by
which the cascode topology increases the traditional common source output resistance is
approximately given by
Rog
(77)
≈ 1 + g m2 ro2 .
Ros
This factor can be quite large, particularly if transistor M2 has a large gate aspect ratio and/or the
quiescent drain current conducted by both M2 and M1 in Figure (6.24a) is relatively low. High
output resistance is an important performance metric in the design of transconductance amplifiers, which ideally have infinitely large output resistances. In turn, transconductance cells are vital active components of a class of high performance filters known as operational transconductance-capacitance (OTA-C) filters[1]-[2]. Transconductance cells also comprise the foundation of
a class of impedance converters known as gyrators, which have the ability of transforming a
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capacitive load termination into an effective input port inductance. Such an impedance
transformation is laudable because of the challenges implicit to realizing passive inductors on
integrated circuit chips. With gyrators, tuned circuits comprised only of resistances and
capacitances can be forged to realize fixed frequency and voltage controlled oscillators, tuned
bandpass filters, and even broadband lowpass amplifiers[3]-[7].
6.4.2.1. Miller Capacitance
Another potential advantage of the cascode topology lies in the arena of circuit
broadbanding, which is the task of increasing the 3-dB bandwidth of an amplifier to a desired
target value without significantly affecting the gain afforded by the amplifier at low to moderate
signal frequencies. The bandwidth of a circuit is fundamentally related to the inverse sum of the
time constants associated with the energy storage elements implicit to the circuit topology and
the models of the active devices embedded therein. While numerous design challenges and issues accompany the bandwidth enhancement problem, it is generally true that progressively
smaller network time constants engender correspondingly larger bandwidths. The common gate
cascode attacks but one of the time constants evidenced in a common source amplifier; namely
the time constant associated with the gate-drain capacitance, Cgd, of the common source, or driving, transistor.
In order to gain an appreciation of the effect that a cascode has on 3-dB bandwidth, we
return to the basic amplifier schematic of Figure (6.1a) and explicitly incorporate the gate-drain
capacitance as depicted by the partially dashed external branch capacitance in Figure (6.25a).
The corresponding small signal model is offered in Figure (6.25b), where because of our present
explicit focus on gate-drain capacitance, the gate-source, bulk-source, and bulk-drain capacitances of the transistor are not shown. It should be clearly understood that we are not implying
herewith that these latter three capacitances insignificantly affect the observable circuit bandwidth. Instead, we are focusing only on the gate-drain capacitance whose effects are ostensibly
mitigated by the incorporation of a cascode stage in tandem with the subject common source
amplifier.
Before diving into the appropriate sea of mathematical analysis, we should note in
Figure (6.25b) that the gate-drain capacitance, Cgd, can be expected to conduct a high frequency
signal current, Igd, which must be supplied by the source of signal excitation. In the steady state,
this capacitive current can be large, as might be expected at very high frequencies, since in terms
of the voltage variables delineated in Figure (6.25b),
I gd = jωC gd (Vi − Vos ) .
(78)
In addition to the direct proportionality of capacitive current Igd on radial frequency ω, we can
postulate a potentially significant voltage difference, (Vi − Vos), which can further increase the
magnitude of the current conducted by capacitance Cgd. This postulate derives from the fact that
a common source amplifier is typically designed for significantly larger than unity I/O voltage
gain. Moreover, a common source amplifier exhibits 180° of I/O phase inversion, at least at low
to moderately high signal frequencies. Consequently, and to crude first order, Vos is proportional
to input port voltage Vi by some negative, gain-related constant, say (−K), whence
I gd = jωC gd (Vi − Vos ) = jωC gd ( 1 + K )Vi ,
(79)
which is certainly sizeable for a large gain magnitude, K. Because the current predicted by either
of the preceding two relationships is necessarily supplied by the signal source, a fraction of the
Thévenin signal voltage, Vs, is lost as a high frequency voltage drop across the internal source
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resistance, Rs. This signal voltage loss spells a diminished input port signal, Vi, which in turn
proportionately decreases the magnitude of the output voltage response, Vos. If the stage at hand
exhibits voltage gain, as is commonly the case, the magnitude of Vos decreases at a faster rate
than that of Vi and hence, gain is degraded at the high signal frequencies that spawn a measurable
gate-drain capacitive current. As we learned earlier, a measure of this gain degradation is the 3dB bandwidth, which is the signal frequency at which the magnitude response has degraded by 3
decibels with respect to the gain manifested at low to moderate signal frequencies where the currents conducted by all circuit capacitances are negligible.
+Vdd
Rl
Cgd
Vo
Igd
Rs
+
Id
Vi
Vs
−
+
Vgg
Rss
−
(a).
Vi
Rs
+
Igd
Cgd
Ids
+
V1
−
gmV1
Vs
Vos
Rl
Rss
−
(b).
Figure (6.25). (a). Common source amplifier of Figure (6.1a) with
due consideration given to the gate-drain capacitance,
Cgd, implicit to the utilized transistor. (b). Small signal
schematic diagram of the amplifier in (a). The only
capacitance addressed by the model is the gate-drain
capacitance of the transistor in (a).
As inferred earlier, bandwidth is inversely related to the time constants associated with
the energy storage elements. In order to compute the time constant of capacitance Cgd in Figure
(6.25b), we must first evaluate the resistance, say Rgd, faced by Cgd. To this end, we apply our
mathematical ohmmeter between the gate and drain terminals, where Cgd is incident, as we
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demonstrate in Figure (6.26a). Note in this model that the signal source, Vs, is set to zero, which
is appropriate for the computation of resistance Rgd as the ohmmeter voltage to current ratio,
Vx/Ix. The model in question stipulates
Ix
Vi
+
V1
−
Rs
+
Vx
Ix+gmV1
−
gmV1
Rl
Rss
Ix
gmV 1
(a).
Vi
Rs
Cm
+
Vos
+
V1
−
gmV1
Vs
Rl
Cgd
Rss
−
(b).
Figure (6.26). (a). Circuit model for computing the resistance faced by
capacitance Cgd in the equivalent circuit of Figure (6.25b).
(b). Alternative equivalent circuit for the model in Figure
(6.25b). The structure predicts the same low frequency
voltage gain predicted by the original model, and the sum
of the time constants associated with capacitances Cm and
Cgd is identical to the time constant established by capacitance Cgd alone in the former model.
Vx = Rs I x + Rl ( I x + g mV1 )
.
V1 = Rs I x − g m RssV1
Upon combining the two relationships in (80), we find that
⎛
V
g m Rl ⎞
Rgd = x = Rl + ⎜ 1 +
⎟ Rs ,
+
Ix
1
g
R
m
ss
⎝
⎠
(80)
(81)
thereby yielding a time constant, τgd, associated with capacitance Cgd of the form,
τ gd = Rgd C gd = Rl C gd + Rs Cm
(82)
where
⎛
g m Rl
Cm = ⎜ 1 +
1 + g m Rss
⎝
⎞
⎟ C gd .
⎠
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Equation (82) suggests the alternative high frequency model appearing in Figure (6.26b). This
alternative structure is equivalent to that of Figure (6.25a) in only two senses. First, both models
predict the same voltage gain at low signal frequencies where the effects of capacitance Cgd can
be ignored. Second, the sum of the two time constants (one due to Cgd and one due to Cm)
evoked by Figure (6.26b) is identical to the time constant, τgd, predicted by Figure (6.25a). However, it should be underscored that the latter model is not strictly correct in a physical sense in
that it predicts two finite frequency poles (one due to each of the two capacitors) and no finite
frequency zeros. In contrast, the model in Figure (6.25a) establishes a single finite frequency
pole and, as detailed analyses reveal, a finite frequency zero lying in the right half plane.
The most notable aspect of (82) and (83) is that the gate-drain capacitance forges a time
constant component, RsCm, which can be interpreted as an effective capacitance, Cm, placed
directly in shunt with the input port to the common source amplifier. It therefore directly imposes a high frequency load on the signal source that is not evident at low to moderately high
signal frequencies. From (83), this high frequency load can be substantial because capacitance
Cm can significantly exceed the original gate-drain capacitance. Indeed, (19) reveals that the
factor by which Cm exceeds Cgd is intimately related to the magnitude of common source voltage
gain. In particular, for large channel resistance and negligible bulk transconductance,
⎛
g m Rl ⎞
(84)
Cm = ⎜ 1 +
⎟ C gd ≈ ( 1 + Avs ) C gd .
1 + g m Rss ⎠
⎝
Capacitance Cm is often referenced in the literature as the Miller capacitance, and the approximate multiplication of Cgd by one plus the common source gain magnitude, is traditionally
termed the Miller multiplication factor. Pardon the pun, but it may be natural to refer to the time
constant, τgd, in (82) as the “Miller time” constant. It is interesting to note that a progressively
larger magnitude of circuit gain results in a larger Miller capacitance and resultantly, a larger circuit time constant that can degrade the bandwidth of the network. This observation is important
because generally, high gain and large bandwidth are difficult to achieve simultaneously without
appropriate design heroics.
If we now turn our attention to the basic form of the common source-common gate cascode amplifier in Figure (6.24a), we see that the effective load resistance imposed on the drain of
the common source transistor, M1, is no longer the actual load resistance, Rl. Instead, it is Rig,
the input resistance to the common gate cell formed of transistor M2. This means that the Miller
capacitance, say Cmc, evidenced implicitly at the input port of the cascode amplifier in Figure
(6.24a) is given by
g m Rig ⎞
⎛
Cmc = ⎜ 1 +
(85)
⎟ C gd ,
+
1
g
R
m
ss
⎝
⎠
where gm and Cgd respectively denote the forward transconductance and gate-drain capacitance
of transistor M1. Recalling (64),
ro2 + Rl
1
Rig =
≈
.
(86)
1 + ( 1 + λb2 ) g m2 ro2
g m2
The indicated approximation reflects the reasonable presumptions that the channel resistance, ro2,
of M2 is much larger than the actual load resistance, Rl, and the bulk transconductance factor,
λb2, of M2 is negligibly small. Accordingly,
⎛
⎞
g g
(87)
Cmc ≈ ⎜ 1 + m m2 ⎟ C gd .
1 + g m Rss ⎠
⎝
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To the extent that
1
Rig ≈
< Rl ,
(88)
g m2
we observe that the cascode version of the Miller capacitance, Cmc, is smaller than the basic common source Miller capacitance, Cm. This is to say that the gate-drain capacitance in the cascode
configuration establishes a smaller time constant, and hence a diminished high frequency load on
the input signal source, than does the gate-drain capacitance of the basic common source amplifier. In a word, the cascode addendum to the common source amplifier ostensibly improves the
3-dB bandwidth of the common source amplifier.
Before telephoning home to arrange a party in celebration of the foregoing discovery,
we should warn of the need for guarded optimism. The first issue inherently underpinning design caution is that in a common source amplifier, the gate-drain capacitance may not establish a
dominant part, or even a comparable part, of the net sum of time constants established by the
amplifier. For minimal geometry transistors processed in a self-aligning gate technology, which
ideally reduces the gate-drain capacitance to nearly zero, it is arguably likely that the gate-drain
capacitance does not establish time constant dominance or significance. A common source
amplifier implicitly has gate-source, bulk-source, and bulk-drain capacitances. Moreover, the
amplifier circuit itself may be plagued by parasitic nodal capacitances associated with the layout
and packaging of the amplifier cell, and/or the amplifier may be called upon to drive a strongly
capacitive (or even inductive) external load termination. Any one or more of these energy storage elements may give rise to time constants that are respectively many-fold larger than the time
constant attributed to the gate-drain capacitance. In such a circumstance, a cascode-related decrease in the Miller time constant may result in no observable improvement in the measured 3dB bandwidth of the compensated amplifier.
The foregoing plausible dilemma is exacerbated by the fact that the deployment of a
common gate cascode does not eliminate the gate-drain capacitive time constant. To the extent
that (88) is valid, it merely diminishes said time constant. But in the process of such time constant attenuation, a second transistor, M2, replete with its own gate-drain, gate-source, bulk
source, and bulk-drain capacitances, adds time constants to those that already prevail in the simple common source amplifier. Therefore, the question that naturally arises is whether the time
constant reduction afforded by the common gate cascode is larger or smaller than the additional
time constants added to those that already prevail in the simple form of the amplifier. If such
reduction is larger, the bandwidth can be expected to grow larger. Otherwise, the bandwidth
may actually be smaller than that observed prior to incorporation of the cascode unit. Whether
we win or lose by the cascode compensation is strongly dependent on the size of the utilized
transistors, the biasing invoked on these devices, and the intended system application of the final
form amplifier.
6.4.2.2. Folded Cascode
The folded cascode, which is depicted in Figure (6.27), uses an n-channel common
source amplifier (M1), a p-channel common gate stage (M2), and a p-channel current source
(M3) to achieve nominally the performance characteristics that are indigenous to the traditional
common source-common gate cascode amplifier shown in Figure (6.24a). It offers two advantages over its conventional counterpart. The first is that the biasing current, say Id2Q, which flows
through the p-channel common gate stage and which is set by the indicated biasing potential,
Vbias1, need not be the same as the standby current, Id1Q, conducted by the common source
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transistor, M1. Among other things, this means that the forward transconductance, gm2, of
transistor M2 can be increased with respect to the forward transconductance, gm1, of M1 through
biasing means alone, without risking the potentially deleterious bandwidth consequences associated with increasing the gate aspect ratio of M2. Increased gm2 is desirable in that it results in a
decreased input resistance to the common gate amplifier, thereby making this amplifier behave
as a better emulation of an ideal current buffer. Of course, if M1 conducts Id1Q and M2 conducts
Id2Q at the quiescent operating point of the circuit, the biasing voltage, Vbias2, which is applied to
the gate of the current source transistor, M3, must be adjusted so that the standby current flowing
through M3 is the quiescent current sum, (Id1Q + Id2Q). We should also understand that the three
indicated static voltages, Vdd, Vbias1, and Vbias2, must be selected to ensure the saturation domain
operation of all three active devices in the subject circuit.
+Vdd
Vbias2
M3
Rig
Id1
Rs
+
Vi
Ros
M2
Id2
Vs
−
+
Vgg
Vbias1
M1
Rog
Vo
Ris
Rss
−
Rl
Figure (6.27). Schematic diagram of a folded common source-common
gate cascode amplifier.
A second advantage of the folded cascode is that the static output voltage, VoQ, in the
circuit of Figure (6.27) is rendered less vulnerable to variations in the power line voltage, Vdd,
than is the corresponding static output voltage of the traditional cascode. In particular, VoQ in
Figure (6.27) is merely Id2QRl. To the extent that channel length modulation in both M2 and M3
is minimal, this voltage is independent of the source-drain Q-point voltages of M3 and M2, and is
therefore nominally insensitive to the power line voltage, Vdd. Depending on the system into
which the folded cascode is embedded, there may even be an additional advantage precipitated
by the fact that the static output voltage of Id2QRl in Figure (6.27) lies closer to system ground
than does the static output voltage, (Vdd − IdQRl), evidenced in the network of Figure (6.24a).
We shall commence our small signal investigation of the folded cascode by first adopting the simplifying approximations that all transistors in the network of Figure (6.27) have infinitely large channel resistances and negligibly small bulk transconductances. Accordingly and in
light of the source degeneration resistance, Rss, the signal current, I1s, conducted by M1 is
g m1Vs
(89)
I d1s =
.
1 + g m1 Rss
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Since the source-gate voltage applied to transistor M3 is the constant, (Vdd−Vbias2), its drain current is signal invariant, at least to the extent that our presumption of infinite channel resistance is
reasonable. This means that zero signal current flows through M3, and in turn, signal current Id1s
must be supplied exclusively by transistor M2. With reference to the subject schematic diagram,
g m1Vs
(90)
I d2s = − I d1s = −
= − g meVs ,
1 + g m1 Rss
where we have exploited (69). It follows that the signal output voltage, Vos, is
g RV
(91)
Vos = I d2s Rl = − m1 l s = − g me RlVs ,
1 + g m1 Rss
from which we readily uncover a small signal voltage gain of
Vos
g m1 Rl
(92)
= −
= − g me Rl .
Vs
1 + g m1 Rss
We note by (74) that this voltage gain is identical to the approximate voltage gain, Avc, of the
traditional common source-common gate cascode, thereby lending credence to a previous
declaration that the folded cascode performs similarly to the traditional cascode.
Rig
Id1s
M2
gmeVs
Ros
ro3
Id2s
Rog
Vos
Rl
Figure (6.28). Small signal schematic diagram of the folded cascode
amplifier in Figure (6.27). The output port of transistor M1 is modeled by its Norton equivalent, which includes the shunting resistance effect of the channel
resistance, ro3, of transistor M3.
For the purists among the readership, we can execute a more definitive small signal
analysis of the folded configuration by relying once again on our trusted friend, Norton. To this
end, we can replace the circuit lying to the left of the source terminal of transistor M2 in Figure
(6.27) by its Norton equivalent. If we appeal to Figure (6.24b) we have most of this circuit
equivalence at hand, the only difference being that transistor M3 in Figure (6.27) imposes an
additional load comprised of its channel resistance, ro3, on the source terminal of the present pchannel cascode device. This load is indeed a simple channel resistance because both the bulk
and source terminals of M3 are connected together at the power line, thereby posturing no bulk
transconductance phenomena. Accordingly, the pertinent small signal schematic diagram is the
structure shown in Figure (6.28), where relevant currents and node voltages have been replaced
by their signal components. In this structure, the effective transconductance, gme, which is manifested by the M1 common source driver, remains given by (69). Moreover, the resistance, Ros,
which is now paralleled by resistance ro3, is still defined by (70), while resistance Rig, which
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represents the input resistance at the source terminal of the grounded gate transistor, M2, remains
stipulated by (64). On the other hand, resistance Rog, which is the cascode output resistance
facing the drain load resistance of Rl, is, recalling (72),
Rog = Ros ro3 + ⎡⎣1 + ( 1 + λb2 ) g m2 ( Ros ro3 ) ⎤⎦ ro2 ≈ ( 1 + g m2 ro2 ) ( Ros ro3 ) . (93)
Armed with this slightly modified resistance and the foregoing observations, the voltage gain of
the folded common source-common gate cascode amplifier derives directly from (74), with the
understanding that the Norton current gain, Ang, in (71) is now given by
g m2 ( Ros ro3 )
Ros ro3
Ang =
≈
≈ 1,
(94)
ro2
1
+
g
R
r
(
)
m2
os
o3
Ros ro3 +
1 + ( 1 + λb2 ) g m2 ro2
From a simplistic, but nonetheless accurate, perspective, we can state that all of the small signal
metrics deduced in the course of analyzing the conventional common source-common gate cascode configuration remain applicable to its folded counterpart if resistance Ros in the former
expressions is replaced by the slightly reduced resistance value, (Ros||ro3).
6.4.2.3. Regulated Cascode
+Vdd
Rl
R
Vo
Id
Ror
M2
V3
M3
V2
Rir
Id
Rs
+
Vi
Ros
M1
Vs
−
+
Vgg
Ris
Rss
−
Figure (6.29). Schematic diagram of a regulated common
source-common gate cascode amplifier.
In yet another variation of the basic common source-common gate cascode amplifier,
the regulated common source-common gate cascode amplifier depicted in Figure (6.29) deploys
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a common source transistor, M3, to establish local feedback from the source terminal to the gate
terminal of the common gate device, M2. The circuit cell comprised of transistors M2 and M3
and the resistances, R and Rl, is often referred to in the literature as a regulated common gate
amplifier. As is the case in the standard, or effectively unregulated, common source-common
gate amplifier of Figure (6.24a), transistor M1 is the common source input, or driver, amplifier to
which signal is applied in the form of a voltage source. We shall learn that the forward
transconductance of the feedback transistor, M3, has a dramatic effect on the effective load resistance, Rir, which also represents the input resistance to the regulated common gate topology,
driven by the common source input stage. Transistor M3 also influences strongly the output
resistance, Ror of the regulated cascode and combined with its affect on resistance Rir, M3 renders
the regulated common gate stage an excellent approximation of an ideal, unity gain, current
amplifier.
Prior to formulating the small signal model of the regulated cascode, it proves expedient to observe that transistor M3 in Figure (6.29) functions as a simple common source amplifier.
The external load imposed on the drain of M3 is solely resistance R since the gate of transistor
M2 conducts no signal current at low to moderate signal frequencies. Accordingly, the ratio,
V3s/V2s, of the signal components of the indicated voltages, V3 and V2, is predicated on the
expression in (18). In particular,
V
Avf − 3s = gm3 ( ro3 R ) ≈ gm3 R ,
(95)
V2s
Ror
Ids
V3s
Vos
+
ro2
gm2Va
λb2gm2Vb
ro3||R
Va
Rl
−
V2s
−
Ids
Rir
−
Vb
Ros
AvfV2s
gmeVs
+
+
Figure (6.30). Low frequency, small signal model of the regulated cascode
configuration in Figure (6.29). The output port of the common source
subcircuit formed of transistor M1 and resistance Rss is represented as
a Norton equivalent circuit.
where we have elected to write gain parameter Avf as a positive number. Recalling (13) and (16),
we have additionally capitalized on the facts that M3 utilizes no source degeneration and,
because both the bulk and source terminals of this transistor are resultantly grounded, it evokes
no bulk-induced threshold modulation, or body effect. Consequently, the small signal model of
interest can be couched in the form of the architecture displayed in Figure (6.30). In the interest
of academic completeness, we have included the Thévenin resistance, (ro3||R), associated with
the dependent voltage source, (−AvfV2s), that drives the gate of feedback transistor M3. Of
course, this resistance is inconsequential at the low to even moderately high signal frequencies
for which no observable gate current flows. Recalling the modeling developments that precipiMing Hsieh Department of Electrical Engineering
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tated Figure (6.5), we have proceeded to represent the output port of the source-degenerated
common source transistor, M1, in the regulated cascode network by its Norton equivalent circuit.
It should therefore be understood that transconductance gme and shunt resistance Ros in this
Norton model are given respectively by (13) and (16), respectively. Upon adapting these two
expressions to the amplifier under present consideration, we have
⎛ ro1 ⎞
gm1 ⎜
⎟
ro1 + Rss ⎠
gm1
⎝
≈
,
(96)
gme =
1 + gm1Rss
1 + ( 1 + λb1 ) gm1 ( ro1 Rss )
and
Ros = Rss + ⎡⎣1 + ( 1 + λb1 ) gm1Rss ⎤⎦ ro1 ≈ (1 + gm1Rss ) ro1 .
(97)
We begin our investigation by determining the input resistance, Rir, seen looking into
the input port of the regulated cascode structure. To this end, the pertinent model is given in
Figure (6.31a), where we see that
ro3||R
V2s
−
AvfV2s
+
Va
−
V3s
gm2Va
−
Vx
ro2
Rl
Ix+gm2Va+λb2gm2Vb
Rir
Ix
+
Vb
+
λb2gm2Vb
−
Ix
+
(a).
Ror
ro3||R
V2s
−
AvfV2s
+
Va
−
Ix
V3s
gm2Va
ro2
Ix−gm2Va−λb2gm2Vb
−
Ix
Vb
+
λb2gm2Vb
Vx
Ros
+
−
Ix
+
(b).
Figure (6.31). (a). Small signal model used to evaluate the low frequency input
resistance, Rir, of the regulated common gate amplifier. (b). Small
signal model used to compute the low frequency output resistance,
Ror, of the regulated common gate amplifier.
V2s = − Vb = Vx ,
Va = − Avf V2s − V2s = − Avf + 1 Vx ,
(
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and
(100)
Vx = ro2 ( I x + g m2Va + λb2 g m2Vb ) + Rl I x .
If we insert (98) and (99) into (100), we arrive at our resistance expression goal. Specifically,
V
ro2 + Rl
1
1
(101)
Rir = x =
≈
≈
,
Ix
(1 + gm3 R ) gm2
1 + 1 + λb2 + Avf g m2 ro2
1 + Avf g m2
(
)
(
)
where the indicated approximations reflect the presumptions of large channel resistances and, for
transistor M2, small bulk transconductance. We remember that the input resistance of the classic
form of a common gate amplifier is nominally 1/gm2. The result at hand suggests an input resistance for the regulated common gate amplifier that is significantly smaller than 1/gm2. In particular, we see that the effect of the feedback common source amplifier comprised of transistor M3
and resistance R is to multiply the transconductance, gm2 of the common gate transistor, M2, by a
factor of one plus the voltage gain magnitude afforded by the M3-R subcircuit. The reduction in
this input resistance value can be understood qualitatively by noting in Figure (6.29) that squirting a mathematical ohmmeter current, Ix, into the source terminal of transistor M2 supports an
increase in the signal voltage, V2s, which is also the ohmmeter voltage, Vx, established at this
source node. But the gate of the common source transistor, M3, is also connected to the M2
source terminal, whence an increase in V2s results in the establishment of a signal voltage, V3s, at
the drain of M3. This voltage response is a phase inverted and amplified version of V2s. In other
words, the indicated signal voltage, V3s, developed at the drain node of transistor M3 is larger in
magnitude than is signal voltage V2s, and in relationship to a positive signal voltage, V2s, it is a
negative voltage signal response. Since the drain of M3 is connected to the gate of M2, and the
voltage at the source of M2, where ohmmeter current Ix is originally applied, follows the gate, the
resultant signal voltage response at the ohmmeter site counteracts the original rise in voltage
caused there by current Ix. Consequently, the Vx/Ix ratio is small, which is indeed indicative of a
small input resistance level.
Figure (6.32b) offers the low frequency, small signal model pertinent to the evaluation
of the output resistance, Ror, seen by the drain load resistance, Rl, imposed on the regulated common source-common gate cascode amplifier of Figure (6.29). An analysis similar to the one executed to discern the input resistance, Rir, seen by the common source driver reveals
V
Ror = x = ro2 + ⎡1 + 1 + λb2 + Avf gm2 ro2 ⎤ Ros ≈ (1 + gm3 R )( g m2 ro2 ) Ros .
(102)
⎣
⎦
I
x
(
)
As in the case of the expression for Rir in (101), we see that the effect of the feedback common
source amplifier comprised of transistor M3 and resistance R is to multiply the forward
transconductance of the common gate transistor by a factor of one plus the magnitude of the voltage gain projected by said feedback amplifier. Because of this multiplicative effect, resistance
Ror is likely to be huge (likely into the meg-ohm range) even for deep submicron transistors that
offer only relatively anemic channel resistances.
Since the output resistance of the regulated cascode is very large, it makes sense to
model the output port of the amplifier by a Norton equivalent circuit, as is suggested by Figure
(6.32a), where signal current Ins is the Norton, or short circuit output port current. And in light of
the fact that the regulated amplifier is driven by a voltage signal, Vs, the Norton current generator
for the output port is reasonably cast into the form of a voltage controlled current source whose
Norton transconductance, say Gnr, is simply the ratio of Norton signal current Ins to input signal
voltage Vs. The resultant Norton equivalent circuit is symbolically portrayed in Figure (6.32b).
In Figure (6.32a), we observe
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V2s
−
+
Va
−
J. Choma
Ins
V3s
gm2Va
−
λb2gm2Vb
ro2
Ins
Vb
AvfV2s
gmeVs
+
Ros
+
(a).
Ins
Vos
Ror
GnrVs
Rl
(b).
Figure (6.32). (a). Small signal model used to evaluate the low frequency, short
circuit current, Ins, evidenced at the output port of the regulated
common gate amplifier. (b). The Norton equivalent circuit for the
output port of the regulated cascode configuration.
0 = ro2 ( I ns − g m2Va − λb2 g m2Vb ) − Vb ,
where
Va = − Avf V2s − V2s =
( Avf + 1)Vb ,
(103)
(104)
and
(105)
Vb = − Ros ( I ns − g meVs ) ,
The substitution of the last two relationships into (103) leads to a Norton output port
transconductance of
I
gme
gme
≈
Gnr ns =
. (106)
ro2
1
Vs
+
1
1+
⎡1 + 1 + λb2 + Avf gm2 ro2 ⎤ Ros
(1 + gm3 R )( gm2 Ros )
⎣
⎦
As witnessed for both the input and the output resistances, the multiplicative impact on
transconductance gm2 by the feedback common source amplifier is evident even for the Norton
output port transconductance. However, the effect of this multiplication factor on the observable
transconductance of the input stage common source driver is minimal because (1+gm3R)(gm2Ros)
is likely to be much larger than one. It therefore follows from (106) that
g me
(107)
Gnr ≈
≈ g me ,
1
1+
(1 + gm3 R )( gm2 Ros )
which is to say that the regulated common gate amplifier comprised of transistors M2 and M3
and resistance R in Figure (6.29) delivers essentially unity I/O current gain. In view of this fact,
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the very low input resistance, and its very high output resistance, the regulated common gate
stage can be proffered as an excellent approximation of an ideal current buffer.
6.5.0. WILSON CURRENT AMPLIFIER
Of the three standard cells of analog MOSFET technology –the common source amplifier, the source follower, the common gate amplifier– that we have studied now, only the common gate unit functions as a current amplifier in at least the senses that it provides a relatively
low input resistance and a very large output resistance. Unfortunately, the actual current gain
afforded by the traditional common gate topology is at most one and in practice is slightly less
than one owing to the presence of a finite signal source resistance.
The Wilson amplifier, whose basic schematic diagram is given in Figure (6.33), improves on the current signal processing capability of a common gate stage by offering an I/O current gain that can be rendered a highly predictable and greater than unity value. In the subject
diagram, transistors M1, M2, and M3 operate in their stereotypical saturation modes and are
similar devices, save for designable differences in their respective gate aspect ratios. In particular, while the gate aspect ratio of transistor M3 is generally selected as the same as that of M2,
the gate aspect ratio of transistor M2 is chosen to be a factor of η larger than that of transistor
M1. Note then from (6) that if I2Q is the quiescent drain current flowing through M2 and if I1Q
symbolizes the standby drain current of transistor M1, the forward transconductances, gm1 and
gm2, of M1 and M2, respectively, are
+Vdd
Io
Rl
Row
Riw
M3
V1
I1
IQ + Is
Rs
I2
M1
V2
I2
M2
Figure (6.33). Basic schematic diagram of the Wilson current amplifier. The
output response to the input excitation to the amplifier, which
consists of a quiescent current, IQ, and a signal current component, Is, is the indicated current Io, which itself is the
superposition of a Q-point current, IoQ, and a signal response, Ios.
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g m2 ≈
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⎛W ⎞
2K n ⎜ 1 ⎟ I1Q
⎝ L1 ⎠
⎛W ⎞
2K n ⎜ 2 ⎟ I 2Q
⎝ L2 ⎠
J. Choma
(108)
.
It follows that
g m2
=
g m1
⎛ W2 ⎞
⎜
⎟ I 2Q
⎝ L2 ⎠
=
⎛ W1 ⎞
⎜
⎟ I1Q
⎝ L1 ⎠
⎛ I 2Q
η⎜
⎜ I1Q
⎝
⎞
⎟ ,
⎟
⎠
(109)
where we have made use of the stipulation that the gate aspect ratio, W2/L2, of transistor M2 is ηtimes larger than W1/L1, the gate aspect ratio of transistor M1. But transistors M1 and M2 form
what is known as a current mirror. Specifically, we note that the gate-source voltages of M1 and
M2 are identical, which means that to the extent that channel length modulation phenomena are
negligible in both devices and/or the difference of the quiescent drain-source voltages, V1Q and
V2Q, and the respective drain saturation voltages of the two transistors are not significantly different,
2
K ⎛W ⎞
I1Q ≈ n ⎜ 1 ⎟ Vgs1Q − Vh
2 ⎝ L1 ⎠
(110)
,
2
K n ⎛ W2 ⎞
I 2Q ≈
⎜
⎟ Vgs2Q − Vh
2 ⎝ L2 ⎠
(
)
(
)
where Vh represents the threshold potential of the MOSFETs. Since the quiescent gate-source
voltage, Vgs1Q, applied to transistor M1 is the same as Vgs2Q, the Q-point gate-source voltage
delivered to M2, and since (W2/L2) = η(W3/L3),
I 2Q
=η .
(111)
I1Q
Although this relationship is couched expressly in terms of quiescent currents, it applies equally
well to instantaneous and signal component currents flowing through transistors M2 and M3
since the square law expressions in (111) apply to static, as well as to signals at low through
moderately high signal frequencies. In a word, the static, signal components, and net instantaneous currents conducted by M1 and M2 are geometrically scaled mirror images of one another.
The immediate impact of this disclosure is that it reduces (109) to
⎛ I 2Q ⎞
η⎜
(112)
⎟ = η ,
⎜ I1Q ⎟
⎝
⎠
which is to say that just as the M1 and M2 transistor currents scale by a factor of η, the forward
transconductances of these devices also scale by the same geometric factor. It is worthwhile
interjecting that because parameter η represents a ratio of a ratio of geometric dimensions, the
numerical value of η is highly predictable and accurately controllable in conventional monolithic
processes.
g m2
=
g m1
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There is another, even more important, aspect to (111). In particular, we observe in
Figure (6.33) that the net input current, (IQ + Is), is the drain current, I1, conducted by transistor
M1 if the effective source resistance, Rs, is much larger than the indicated input resistance, Riw.
But with I1 = (IQ + Is), the current, I2, conducted by M2 is, by (111), I2 = ηI1 = η(IQ + Is). In
turn, current I2 rolls through transistor M3 so that the output current, Io, is Io = I2 = η(IQ + Is).
We conclude, subject to the proviso that Rs >> Riw, that the approximate current gain, say Aiw, of
the Wilson amplifier is
I
ηI s
(113)
Aiw = os ≈
= η .
Is
Is
which suggests that the current gain of the Wilson stage is determined almost exclusively by a
ratio of transistor gate aspect ratios. Although the realization of a predictable current gain that
can be greater than one is a laudable characteristic of the Wilson architecture, its downside is that
the standby, or Q-point, current conducted by transistors M2 and M3 is likewise a factor of η larger than the quiescent current flowing in transistor M1. Thus, we are forced to temper a desire
for a large current gain with a concern over proportionately large standby power dissipation.
In arriving to (113), we tacitly presume an input resistance that is significantly smaller
than the signal source resistance. A first blush inspection of the circuit in Figure (6.33)
seemingly contradicts this presumption because it would appear that the input resistance is the
parallel combination of the ostensibly large resistances presented to the signal source by the
drain of M1 and the gate of M3. This tacit observation is incomplete and indeed, it is flat out
wrong! Consider our infamous ohmmeter, which we can use to squirt a current into the input
port where the drain of M1 and the gate of M3 are incident. This current raises the input port
voltage, V1, which in turn increases (likely to a lesser extent) the voltage, V2, at the source terminal of M3, since the source of a MOSFET follows the voltage established at its gate. We see that
the source of M3 is pinned to the gate of M1, which fundamentally operates as a common source
amplifier. Because a common source stage exudes voltage gain with phase inversion, the effect
of a rising gate voltage is a potentially substantial decrease in the signal voltage, V1, established
at the drain node. To be sure, M1 is a common source unit. Even more significantly, it is a common source amplifier that functions as a feedback element in the Wilson configuration. This is
to say that M1 feeds back to the input node an amplified and phase inverted version of the signal
generated at its gate. The signal voltage fed back to the drain of M1 opposes the original increase in voltage at this input node that is spawned by our mathematical ohmmeter current. We
therefore contend that the voltage to current ratio at the drain of M1, which in fact is the input
resistance, Riw, is smaller than the voltage to current ratio caused solely by the ohmmeter current.
The implication herewith −to be sure, without rigorous proof− is that the input resistance is
small.
The feedback manifested by transistor M1 can also be used to explain a potentially
large output resistance, Row, in Figure (6.33). To this end, let us now imagine our ohmmeter
squirting a current into the drain of transistor M3. This current flows out of the source of M3 and
into the diode-connected transistor, M2, thereby increasing the signal voltage, V2, at the M1 gate
to which transistor M2 is incident. Because of the common source nature of M1, the rise in voltage V2 results in a decrease in the voltage at the gate of M3 to which the drain of M1 is incident.
Since M3 operates as a common source amplifier, the decrease in M3 gate voltage produces an
amplified signal voltage at the drain of M3, to which our ohmmeter is attached. Thus, the response to the original ohmmeter-induced increase of the signal voltage at the output node is a
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further increase in output node voltage, which, for a fixed level of ohmmeter current, suggests a
potentially large output resistance.
6.5.1. SMALL SIGNAL PERFORMANCE
By virtue of the preceding discourse, we suspect that the Wilson amplifier of Figure
(6.33) is characterized by a small input resistance, Riw, and a large output resistance, Row, which
suggests the propriety of a Norton equivalent small signal model for the Wilson output port. At a
minimum, a detailed small signal analysis is appropriate if for no other reason than to lend
analytical credence to the largely qualitative disclosures postured in the preceding subsection of
material. To this end, we shall begin by developing a tractable model for the feedback current
mirror comprised of transistors M1 and M2. We shall then use this model in conjunction with
the small signal equivalent circuit for transistor M3 to execute a thorough small signal performance investigation of the entire Wilson topology.
6.5.1.1. Feedback Current Mirror
Figure (6.34a) highlights, for the case of small signal operating conditions, the feedback current mirror subcircuit embedded within the Wilson amplifier. Figure (6.34b), represents
this current mirror by its low frequency, small signal equivalent circuit. In the course of
formulating this model, we note that voltage V2s, which is the signal potential established across
diode-connected transistor M2, is also the signal voltage appearing across the gate-source terminals of transistor M1. We have additionally exploited the fact that no bulk transconductance effects prevail in either transistor M1 or M2 since the bulk and source terminals of both of these
devices are grounded, thereby assuring zero bulk-source signal potential. Because transistor M2
is configured as a diode-connected transistor, we have replaced it by a simple two-terminal resistance, rm2, which derives from earlier considerations that precipitate (36). In particular and in
light of the absence of bulk transconductance phenomena,
ro2
1
1
(114)
rm2 = ro2
=
≈
,
g m2
1 + g m2 ro2
g m2
where, of course, ro2 and gm2 respectively denote the drain-source channel resistance and forward
transconductance of transistor M2. The indicated approximation reflects the reasonable assumption that gm2ro2 >> 1. The model in Figure (6.34c) is electrically identical to that of Figure
(6.34b) in that the drain-source signal voltage developed across M2 relates to the signal current,
I2s, conducted by M2 as
V2s = rm2 I 2s .
(115)
It follows that the dependent current source, gm1V2s, in Figure (6.34b) is expressible as
g m1V2s = g m1 rm2 I 2s = f w I 2s ,
(116)
where
g m1ro2
g
1
(117)
f w g m1 rm2 =
≈ m1 =
,
1 + g m2 ro2
g m2
η
and (114) and (112) have been recalled. Armed with Figure (6.34c), the complete low frequency, small signal model of the Wilson current amplifier is the structure appearing in Figure
(6.35). In the latter equivalent circuit, we have made use of the fact that the signal current, I2s, is
identical to the output current, Ios, which flows through the terminating load resistance, Rl. Thus,
the current controlled current source, fwI2s, in Figure (6.34c) is replaced by fwIos, which obviously
reflects a dependent current that is directly proportional to the output signal current.
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+Vdd
Io
Rl
Row
Riw
M3
V1
I1
IQ + Is
V2s
I1s
I2
M1
Rs
V1s
I2s
M1
V2
I2
M2
M2
(a).
V1s
I1s
I2s
gm1V2s
ro1
V2s
V1s
I1s
I2s
rm2
ro1
fwI2s
(b).
V2s
rm2
(c).
Figure (6.34). (a). Wilson amplifier with the current mirror subcircuit comprised of transistors M1
and M2 extracted for small signal analysis purposes. (b). The low frequency, small
signal model of the current mirror subcircuit. (c). Equivalent model of the network
in (b) with the voltage controlled current source, gm2V2s, replaced by a current controlled source, fwI2s.
Row
Ios
Riw
V1s
Is
gm3Va
I1s
Rs
λb3gm3Vb
+ Va −
ro1
fwIos
ro3
Rl
− Vb +
+
rm2
V2s
−
I2s
Figure (6.35). Low frequency, small signal equivalent circuit of the Wilson current amplifier shown in
Figure (6.33). The model makes use of the current mirror representation in Figure (6.34b).
The parameter, fw, is a critical metric that, as we shall shortly demonstrate, dramatically
influences the current gain, input resistance, and output resistance (as well as several other
performance barometers) of the Wilson configuration. It is referred to as the global feedback
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factor of the Wilson current amplifier in that it measures the amount of signal current that is fed
back to the input port, where input signal current Is is applied, from the output port 1 . We note in
Figure (6.35) that in the presence of this feedback generator, the net signal current exciting the
input port of the subject amplifier is the current difference,
ΔIi = I s − f w I os .
(118)
which in the jargon of feedback amplifiers is often termed the input current error. If this input
current error were to be magically forced to zero by the Wilson circuit, (118) implies
I os
1
;
=
(119)
I s ΔI =0
fw
i
that is, the current gain becomes merely the inverse of the feedback factor. By (117), this inverse
feedback factor is the ratio, η, of the gate aspect ratio of transistor M2 to that of M1, which we
previously demonstrated, per (113), as the approximate current gain of the Wilson amplifier. We
are therefore moved to proffer that minimizing the input current error to zero in a Wilson
amplifier is foundational to a current gain that is locked to a supremely predictable ratio of gate
aspect ratios.
6.5.1.2. Wilson Amplifier Analysis – An Introduction To Feedback
Let us begin to quantify the small signal characteristics of the Wilson current amplifier
by returning to the model in Figure (6.35) to write
V1s = ( Rs ro1 )( I s − f w I os ) ,
(120)
V2s = rm2 I 2s = rm2 I os ,
(121)
and
Va = V1s − V2s = ( Rs ro1 ) I s − ⎡⎣ f w ( Rs ro1 ) + rm2 ⎤⎦ I os .
(122)
Moreover,
R I + V2s
,
I os = gm3Va + λb3 gm3Vb − l os
(123)
ro3
where the bulk-source signal voltage, Vb, applied to transistor M3 is related to signal voltage V2s
and output signal current Ios through
Vb = − V2s = − rm2 I os .
(124)
If (122) and (124) are inserted into (123), we arrive at a Wilson amplifier current gain, Aiw, of
g m3 ( Rs ro1 )
I
(125)
Aiw = os =
.
Rl + rm2
Is
+ (1 + λb3 ) g m3 rm2 + f w g m3 ( Rs ro1 )
1+
ro3
An equation that is as algebraically sloppy as (125) is either useless for design or is an eager
candidate for a design-oriented, insightful interpretation. Let us assume the latter if for no other
reason than Mr. Wilson knew what he was doing when he forged his current amplifier topology.
Consider first the special case of no feedback; that is, fw = 0. From (117), fw = 0
materializes if resistance rm2 in (114) is zero or if the transconductance, gm1, of transistor M1 is
1
The term, “global,” is used in conjunction with the phrase, “feedback factor,” to denote that the feedback path
proceeds directly from the output port of the amplifier to the input port; in other words, “global” encompasses the
entire amplifier from output port to input port. In contrast, “local feedback” commonly refers to feedback executed
between internal amplifier nodes, one of which is neither the output port node nor the input port node.
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null. Since rm2 represents the small signal resistance of the diode-connected transistor, M2, it is
impractical to presume rm2 can be zero, for such a constraint mandates the silliness of either an
M2 channel resistance of zero or an M2 transconductance that is infinitely large. Thus, the only
recourse supportive of the zero feedback condition is gm1 = 0, which is tantamount to zero drain
current flowing in transistor M1. In turn, if M1 conducts no drain current, it effectively behaves
as an open circuit, which is to say that the feedback precipitated by transistor M1 from the source
terminal of M3 to the gate of M3 is disabled. In the lexicon of the feedback literature, this zero
feedback state is referred to as the open loop condition. We may therefore assert with engineering traction that the open loop gain, say Aow, of the Wilson amplifier is
g m3 ( Rs ro1 )
I
(126)
Aow = Aiw f =0 = os
=
.
Rl + rm2
w
I s f =0
+ (1 + λb3 ) g m3rm2
1+
w
ro3
which is certainly larger than the actual current gain, Aiw. Parameter Aow is literally the low frequency, small signal gain of the Wilson unit if transistor M1 is either removed from the circuit or
is erroneously biased in cutoff.
An appreciation of the utility of the open loop gain metric is sparked by an algebraic
reconsideration of (125), from which we deduce the considerably simpler gain expression,
I
Aow
Aiw = os =
.
(127)
Is
1 + f w Aow
This transfer function result is typified by the classic system level block diagram shown in
Figure (6.36). In this abstraction, we observe that the two signal currents, Is and fwIos, applied to
the indicated algebraic summer are precisely the two anti-phase currents that activate the input
port of the amplifier model in Figure (6.35). It therefore follows that the summing operation in
Figure (6.35) is a mathematical representation of the input port node in the amplifier small signal
equivalent circuit. We observe further that the response of the summer in the block diagram before us is precisely the input current error defined by (118). This error current activates the open
loop gain block to produce an output current response, Ios, of
Is
+
Σ
ΔIi
Aow
Ios
−
fw Ios
fw
Figure (6.36). System level block diagram model of the Wilson
current amplifier. The transfer function parameter, Aow is the open loop, or zero feedback, small
signal current gain of the amplifier in Figure
(6.33), where it is understood that “zero feedback”
connotes fw = 0, which is equivalent to open
circuiting the drain of transistor M1.
I os = Aow ( ΔI i ) .
(128)
If we determine the current ratio, Ios/Is, from the expression that results when (118) is substituted
into (128), we reassuringly find that this ratio is identical to that postured by (127). In other
words, the block diagram in Figure (6.36) mirrors the circuit level analyses that produce the
algebraic gain result in (127).
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The block diagram representation in Figure (6.36) provides us with a mathematical picture that proves useful in developing an engineering interpretation of the nomenclature commonly invoked in the study of feedback networks. For example, (127) clearly demonstrates an
amplifier gain that is identical to the metric, Aow, if parameter fw is null. Referring to Aow as an
open loop gain is now seen as making intuitive sense in that forcing fw to zero is tantamount to
breaking, or opening, the signal processing loop forged by gain blocks Aow and fw between the
input current error, ΔIi, and the fed back current, fwIos, of the feedback (fw) block. Because a loop
is indeed formed by the open loop block and the feedback block in Figure (6.36), it makes sense
to call the product, fwAow, the loop gain, say Tw, of the Wilson amplifier. With
Tw f w Aow ,
(129)
(127) becomes expressible as
I
Aow
Aow
Aiw = os =
=
.
(130)
Is
1 + f w Aow
1 + Tw
And since the loop in question is effectively closed when neither the feedback factor, fw, nor the
open loop gain, Aow, are zero, the current gain, Aiw, which we have thus far referenced as the
mundane phrase, “actual current gain,” is more commonly and more meaningfully labeled the
closed loop gain of the current amplifier.
The loop gain of a feedback network is a critically important measure of feedback
amplifier quality. For example, if high frequency phenomena are addressed in the model utilized
to characterize the performance of the amplifier undergoing investigation, the loop gain establishes the frequency domain locations of closed loop pole and zero locations in terms of the critical frequencies of the open loop gain function. As such, it determines the overall quality of the
closed loop frequency and transient step responses, and it additionally quantifies the degree of
stability of the considered network[8]. These and other important issues are a trifle beyond the
scope of this document. We shall therefore be at least temporarily content to examine the effect
that the loop gain, Tw, has on the input current error response, ΔIi, to the applied signal current
excitation, Is. To this end, we observe from (118) and (127) that
ΔI i
I − f w I os
f w Aow
1
1
.
= s
= 1−
=
=
(131)
Is
Is
1 + f w Aow
1 + f w Aow
1 + Tw
This outcome suggests that for a given input excitation, the input current error is diminished for a
large loop gain. Indeed, ΔIi approaches zero in the limit as loop gain Tw tends toward infinity.
Recall that (119) portends a closed loop gain of inverse fw if indeed, the input current error is
“magically forced to zero.” In truth, we learn that magic is in short supply in a practical Wilson
amplifier in that its input current error can never be made to disappear. But we now see that this
error current can be rendered small if the adopted circuit design strategy focuses on achieving a
large loop gain. For the large loop gain circumstance, we observe in (130) that since large Tw,
implies fwAow >> 1, Aiw collapses to Aiw ≈ 1/fw, which happily agrees with our earlier disclosures
surrounding (118).
It is only natural to investigate if a large loop gain is practicable in a Wilson current
amplifier. Since the loop gain, Tw, is the product of the feedback factor, fw, and the open loop
gain, Aow, a large loop gain mandates a very large open loop gain. This logic derives from our
understanding that in light of a closed loop gain that is approximately 1/fw, fw is necessarily
smaller than one if we are to achieve a closed loop gain greater than one. If we do not achieve
greater than one gain, we might just as well abandon our Wilson topology in favor of a
considerably simpler common gate standard cell. In (126), the body effect factor, λb3, for
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transistor M3 is invariably much smaller than one. Moreover, for reasonable values of the
terminating load resistance, Rl, we can expect the M3 channel resistance, ro3, to be significantly
larger than the resistance sum, (Rl + rm2). Accordingly,
g m3 ( Rs ro1 )
(132)
Aow ≈
.
1 + g m3 rm2
In this approximate relationship, rm2, which is given by (114) is likely comparable to the inverse
of the transistor M3 transconductance, gm3, especially if transistors M3 and M2 have nominally
the same gate aspect ratios. Thus, it may prove unreasonable to force gm3rm2 << 1, thereby
rendering an attempt to increase Aow through increases in parameter gm3 potentially
counterproductive. We conclude that a very large Aow can be realized only if the source resistance, Rs, is large and the channel resistance, ro1 of transistor M1 is likewise large. A large
source resistance is likely since the Wilson stage is best driven by a current signal. On the other
hand, large ro1 can be accomplished, at some risk of circuit bandwidth deterioration, by laying
out transistor M1 as a relatively long channel device. Additionally, ro1 can be made large if the
drain biasing current through M1 is chosen to be small. Caution must accompany the latter design tack in that a small M1 bias current also reduces its transconductance, gm1. Recalling (117),
a small gm1, in turn, may reduce the feedback factor to a level where the corresponding loop gain,
fwAow, is anemic. We conclude that a large loop gain in the Wilson current amplifier is possible
only if a large signal source resistance prevails and a large M1 channel resistance can be
achieved without incurring undue compromises in other performance metrics indigenous to the
Wilson stage.
6.5.1.3. Norton Output Port Model
The Norton equivalent circuit for the output port of the Wilson amplifier adopts the
traditional topological form depicted in Figure (6.37). In this representation, Row denotes the output resistance seen by the load resistance, Rl, while Anw is the short circuit, or Norton, small signal current gain. Specifically, Anw is the closed loop current gain under the condition of a short
circuited load resistance; that is, Rl = 0. Appealing to (125)
Ios
Row
Anw Is
Rl
Figure (6.37). Norton equivalent, low frequency, small signal
representation of the output port of the Wilson
amplifier in Figure (6.33).
g m3 ( Rs ro1 )
I
(133)
Anw = Aiw R =0 = os
=
,
rm2
l
I s R =0
+ g m3 ⎡⎣( 1 + λb3 ) rm2 + f w ( Rs ro1 )⎤⎦
1+
l
ro3
where we have exploited the fact that the feedback factor, fw, in (117) is independent of load
resistance Rl. A careful comparison of this result with (125) allows expressing the closed loop
current gain, Aiw, in the form
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I os
=
Is
1+
J. Choma
Anw
Rl
.
(134)
{1 + gm3 ⎡⎣(1 + λb3 ) rm2 + f w ( Rs ro1 )⎤⎦}ro3 + rm2
But the Norton model in Figure (6.37) projects a closed loop current gain of
⎛ Row ⎞
I
Anw
Aiw = os = Anw ⎜
.
(135)
⎟ =
R
Is
R
R
+
l
l⎠
⎝ ow
1+
Row
Upon comparing the denominators on the far right hand sides of each of the preceding two
expressions, we are led to conclude that the output resistance of the Wilson current amplifier is
Row = 1 + g m3 ⎡⎣( 1 + λb3 ) rm2 + f w ( Rs ro1 )⎤⎦ ro3 + rm2 ,
(136)
{
}
which is larger −potentially significantly larger− than the channel resistance, ro3, of transistor
M3. For a large signal source resistance, Rs, and a large M1 channel resistance, ro1,
Row = 1 + g m3 ⎡⎣(1 + λb3 ) rm2 + f w ( Rs ro1 )⎤⎦ ro3 + rm2 ≈ f w ( g m3 ro3 ) ( Rs ro1 ) .
(137)
{
}
We observe that a large closed loop current gain, which is roughly 1/fw, tempers the otherwise
large output resistance that is proportional to the product of two numerically large factors: the
parallel combination of the signal source resistance (Rs) and the M1 channel resistance (ro1), and
the product of M3 transconductance and M3 channel resistance.
6.5.1.4. Input Resistance
In order to evaluate the input port resistance, Riw, presented by the Wilson amplifier to
the signal source, we once again play ohmmeter. As is implied by the equivalent circuit in
Figure (6.38), this input resistance is simply the voltage to current ratio, Vx/Ix. But rather than
execute yet another detailed circuit analysis, we observe that the subject voltage to current ratio
is identical to the ratio, V1s/Is, in Figure (6.35), subject to proviso that source resistance Rs be set
to infinity. We therefore have from (120),
Ios
Riw
Vx
Ix
gm3Va
I1s
λb3gm3Vb
+ Va −
ro1
Rl
− Vb +
+
fwIos
ro3
rm2
V2s
−
I2s
Figure (6.38). Equivalent circuit for computing the input resistance, Riw, of the Wilson current mirror.
⎛
⎞
V1s
I
⎟ ro1 .
= ⎜ 1 − f w os
(138)
⎜
I s R =∞
I s R =∞ ⎟
s
s
⎝
⎠
Using (125) under the infinitely large source resistance constraint, (138) can be shown to be
Riw =
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Rl + rm2
⎡
⎤
+ (1 + λb3 ) gm3 rm2 ⎥
⎢1+
ro3
Riw = ro1 ⎢
⎥,
(139)
f w gm3
⎢
⎥
⎢⎣
⎥⎦
which reflects the clarion fact that the input resistance is the parallel combination of channel
resistance ro1 and the effective resistance established across the input port by the controlled feedback source, fwIos. Despite the fact that this feedback generator is a current source, it does not
emulate an infinitely large resistance because as the signal source current, Is, increases, so does
the output current Ios (in direct proportion to Is). Because feedback factor fw is a positive number,
this increase in Ios imposes an additional current load on input current Is, thereby reducing the
effective resistance seen by Is. For large channel resistances in transistors M1 and M3 and
negligible bulk-induced threshold modulation in M3, (139) reduces to
Rl + rm2
⎡
⎤
+ (1 + λb3 ) gm3rm2 ⎥
⎢1+
ro3
1 ⎛
1 ⎞
Riw = ro1 ⎢
⎥ ≈
(140)
⎟.
⎜ rm2 +
f w g m3
fw ⎝
g m3 ⎠
⎢
⎥
⎢⎣
⎥⎦
Since rm2 is the small signal resistance associated with diode-connected transistor M2 and
transconductance gm3 can be relatively large for appropriately chosen bias current and gate aspect
ratio in transistor M3, Riw is seen as being the reasonably small input resistance for which we
strive in the design of a current amplifier. But just as I/O current gain (roughly 1/fw) compromises the desirably large output resistance of the Wilson structure, we see that large current gain
elevates the input resistance.
6.5.2. WILSON CASCODE
The Wilson cascode amplifier, whose basic schematic diagram appears in Figure
(6.39a), utilizes a p-channel common source transistor, M4, in conjunction with the Wilson current amplifier studied in the preceding subsection of material to achieve a transconductance
amplifier boasting high frequency signal processing capabilities. Transistor M4 is shown with its
source lying at signal ground but in other embodiments, source degeneration can be deployed to
reduce the sensitivity of I/O gain with respect to the forward transconductance, gm4, of M4. The
Wilson cascode boasts a significant advantage over its conventional common source-common
gate counterpart. In particular, the common gate subcircuitry in the common source-common
gate cascode can provide a current gain that can only approach one from the left while the
Wilson subcircuit in the present cascode can be designed for greater than unity current gain.
Among other things, this means that if the Wilson cascode were to be used as a voltage amplifier, the load resistance, Rl, can be decreased by a factor of the Wilson closed loop current gain
while still netting the same I/O voltage gain provided by the conventional cascode. The load
resistance reduction is laudable from a bandwidth perspective. A reduced load resistance decreases the net output resistance established at the drain node of transistor M3, thereby reducing
the time constant contribution to overall 3-dB bandwidth of output port capacitance, which includes the M3 bulk-drain capacitance, external load capacitance, and any other parasitic
capacitances that materialize at the amplifier output port. In other words, the Wilson cascode
can boast a gain bandwidth product that is larger than that afforded by its traditional common
source-common gate counterpart. As in the conventional cascode, Miller multiplication of the
gate-drain capacitance of the common source driver is held to a minimum by the low input resisMing Hsieh Department of Electrical Engineering
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tance of the Miller structure. In Figure (6.39a), we see that this Wilson input resistance, Riw,
which remains analytically defined by (140), serves as the effective drain load driven by common source transistor M4.
+Vdd
Io
Rl
Rs
+
Vs
−
Vgg
+
Riw
M4
IQ − gm4Vs
V1
I1
Vo
Rowc
M3
Ios
gmwcVs
I2
M1
Rowc
Vos
Rl
V2
I2
−
M2
(a).
(b).
Figure (6.39). (a). Schematic diagram of the Wilson cascode amplifier. The amplifier uses a pchannel common source amplifier (M4) in conjunction with a Wilson current
amplifier. (b). Low frequency, small signal, Norton equivalent circuit of the output
port for the amplifier in (a).
We can expedite the low frequency, small signal analysis of the Wilson cascode by
merely drawing comparisons between Figure (6.39a) and the fundamental Wilson current amplifier to which Figure (6.34a) is focused. To begin, we notice that the input quiescent current, IQ,
supplied to transistor M1 in Figure (6.34a) is now manifested as the quiescent drain current of
transistor M4 in Figure (6.39a). This current must be implemented in such a way as to assure
saturation of M4, which requires
(141)
Vdd − V1Q ≥ Vdd − Vgg − Vh4
or equivalently,
(142)
Vgg ≥ V1Q − Vh4 .
In the preceding two expressions, Vh4 denotes the threshold voltage of transistor M4, and V1Q is
the standby voltage developed at the gate terminal of transistor M3, which forms the input port of
the Wilson current amplifier. Second and in the absence of source degeneration in M4, the
Norton signal current flowing in the drain of M4 is simply gm4Vs, where Vs signifies the applied
input voltage signal. In concert with our adopted practice of displaying a drain signal current in
PMOS, as well as in NMOS, as flowing from drain to source and proportional to gate-source (not
source-gate) signal voltage, this current is indicated in Figure (6.39a) as a negative entity flowing
out of the M4 drain and thence into the Wilson input port. This notation implies that the signal
current, Is, applied to the Wilson topology in Figure (6.34a) becomes the current, Is = −gm4Vs, in
Figure (6.39a). A final important stipulation we assert before proceeding to the analysis of the
cascode structure before us is that the signal source resistance, Rs, in Figure (6.34a) is formed as
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the output resistance of the M4 common source circuit in Figure (6.39a). This output resistance,
which effectively functions as the signal source resistance seen by transistor M3, is simply the
channel resistance, ro4, of transistor M4.
Because the output resistance, denoted here as Rowc (for output resistance of Wilson
cascode), seen by the terminating load resistance, Rl, is large, we are motivated to represent the
low frequency, small signal characteristics of the output port of the Wilson cascode by a Norton
equivalent circuit. And since the input signal is a voltage (Vs), we represent the obligatory
dependent generator in this Norton output structure as a voltage-controlled current source,
gmwcVs, as shown in Figure (6.39b). The transconductance, gmwc, associated with this dependent
generator, which represents the effective forward transconductance of the Wilson cascode, can
be discerned directly from (133), which defines the Norton, or short circuit, current gain of the
Wilson current amplifier. In that expression, we set Is = −gm4Vs and Rs = ro4 to obtain
g m4 g m3 ( ro4 ro1 )
I
(143)
= −
g mwc os
.
rm2
Vs R =0
+ g m3 ⎡⎣(1 + λb3 ) rm2 + f w ( ro4 ro1 )⎤⎦
1+
l
ro3
With the traditional approximations invoked, this result crunches down to the simpler result,
gm4 gm3 ( ro4 ro1 )
I
g
gmwc os
≈ −
≈ − m4 ,
(144)
Vs R =0
fw
1 + f w g m3 ( ro4 ro1 )
l
where in the second of the indicated two approximations, we presume tacitly that in light of
expectedly large channel resistances, ro1 and ro4, fwgm4(ro4||ro1) >> 1. Recall that 1/fw approximates the closed loop current gain of the Wilson current amplifier. Accordingly, the second
approximation in the last relationship supports a previous allegation about a greater than unity
current gain in the Wilson cascode in that the overall transconductance is roughly the
transconductance of the common source driver amplified by the subject closed loop Wilson current gain.
In the interest of clarity, the negative signs on the right hand sides of (143) and (144)
derive from the algebraic fact that the signal current driving the Wilson current amplifier in
Figure (6.39a) is −gm4Vs. From an engineering perspective, these negative signs indicate phase
inversion between the applied signal source, Vs, and the signal component, Ios, of net output
current. In particular, as Vs increases with time, the source to gate voltage evidenced on transistor M4 diminishes, whence the net drain current conducted by M4 decreases. But if the drain
current flowing through M4 decreases, so does the net voltage, V1, applied to the gate of transistor M3. Since M3 functions as a common source unit, it displays I/O phase inversion, which is to
say that a decrease in V1 applied to its gate manifests an increase in the net output voltage, Vo. In
turn, increased Vo gives rise to a diminished net output current, Io, since Io flows through a resistance, Rl, which is connected between a constant voltage (Vdd) power line and the output port that
supports voltage Vo.
The output resistance, Rowc in Figure (6.39b), can be deduced straightforwardly from
(137). In that expression, we need only supplant resistance Rs by channel resistance ro4. To wit,
Rowc = 1 + g m3 ⎡⎣(1 + λb3 ) rm2 + f w ( ro4 ro1 ) ⎤⎦ ro3 + rm2 ≈ f w ( gm3ro3 ) ( ro4 ro1 ) . (145)
{
}
To the extent that ro4 is larger than the signal source resistance, Rs, appearing in Figure (6.39a),
we expect resistance Rowc to be slightly larger than the output resistance, Row, of the basic Wilson
current amplifier.
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The only outstanding issue is the voltage gain, say Avwc, of the Wilson cascode. By
inspection of Figure (6.39b), this gain is
V
Avwc = os = − g mwc ( Rowc R1 ) .
(146)
Vs
Because gmwc in (143) and (144) is negative, voltage gain Avwc is positive. In other words, no
phase inversion prevails between the voltage signal, Vs, applied to the Wilson cascode and its
small signal voltage response, Vos. The load resistance, Rl, is invariably much smaller than the
output resistance, Rowc. This contention and (144) reduce the voltage gain result to
V
g R
Avwc = os = − gmwc ( Rowc R1 ) ≈ m4 l .
(147)
Vs
fw
Large I/O voltage gain is certainly possible for the Wilson cascode network. But we note that
the approximate voltage gain is directly proportional to load resistance Rl, which is indicative of
a high amplifier output resistance and the resultant fact that the amplifier in question is better
suited as a transconductor than it is as a voltage amplifier.
6.6.0. BALANCED DIFFERENTIAL AMPLIFIER
The balanced differential amplifier, which is abstracted at a fundamentally system level
in Figure (6.40), is not an additional standard cell of analog circuit technology. Rather, it is an
interconnection of a matched pair of analog cells and thus, the balanced differential circuit is often cleverly referenced as a balanced differential pair. The pair of cells embedded within a balanced differential architecture allow for the application of two distinct input signals −one of
which might be zero−, and the generation of multiple output responses. In the subject diagram,
the applied inputs are delineated as the voltage sources, Vs1 and Vs2, but current source inputs are
also permitted. The output responses can be taken as currents or voltages anywhere in the system. In this exercise, we shall initially focus on output voltage responses. To this end, the three
immediate outputs of interest are the single ended voltages, Vo1 and Vo2, and the indicated
differential voltage, Vdo. By a single ended voltage is meant a voltage measured at a circuit node
with respect to signal ground. In effect, all of the output voltages addressed in our preceding
discussions are single ended voltages. In contrast, the indicated differential voltage is not referred to signal ground and, in attempt to keep Gustav Kirchhoff happy, it is merely the difference between the single ended output voltages, Vo1 and Vo2; that is,
Vdo = Vo1 − Vo2 .
(148)
The diagram of Figure (6.40) clearly incorporates two amplifiers. Each of these
amplifiers can be a common source unit, a common drain cell, a common gate structure, any of
the other more intricate topologies dealt with in preceding sections of material, or any other
configuration innovated by the circuit designer. The amplifiers need not be realized in MOS
technology. They can be implemented with bipolar junction transistors, a mixture of MOS and
bipolar devices (commonly referred to in the literature is BiCMOS technology), or with III-V
compound devices (e.g. gallium arsenide, indium phosphide, etc.). The pivotally important key
to a balanced differential system is that whatever topology and whatever device technology is
exploited for the individual amplifiers, they must be identical, which is to say that they must be
mirror images of one another. Although biasing is not explicitly shown in the differential network at hand, this identity mandate subsumes identical biasing of each amplifier. With identical
topological structures that are biased identically for presumably linear signal processing
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purposes, we satisfy the necessary conditions underpinning each amplifier exhibiting the same
performance characteristics. Sufficiency complements necessity with respect to the realization
of matched amplifier performance traits when we additionally require that the input and output
ports of both amplifiers be terminated by the same signal source resistances (Rs) and the same
single ended loads, Rl, respectively. Moreover, the resistances, Rgg, in the third amplifier terminal, which is normally the signal ground lead of the amplifier when it is utilized in a single ended
architecture (e.g. the source terminal in a common source amplifier) must be matched. The same
statement applies to any input port biasing resistances, Rb, which may be required. Identical
topologies that are identically biased and input and output ports that are terminated in identical
impedances guarantee that the two amplifiers deliver equivalent I/O gains, identical I/O resistances or impedances, the same 3-dB bandwidths, identical transient responses, and in general,
correspondingly identical metrics that serve to define the performance characteristics of the
individual amplifiers.
Input Node:
Amplifier #1
Vi1
Ib1
Rs
+
Rb
−
Input Node:
Amplifier #2
Rs
Ib2
Vi2
+
Ill
Rgg
Ib1+Ib2
Vs1
Output Node:
Amplifier #1
Vo1
I1
Rb
Vb
Io1
Amplifier
#1
Rl
I1+I2
Vk
Rbb
Rgg
Rll
Vdo
Rkk
Vl
Rll
I2
Amplifier
#2
−
Vo2
Output Node:
Amplifier #2
Io2
Rl
+
Vs2
−
Figure (6.40). System level portrayal of a balanced differential amplifier. Amplifiers #1 and #2
are identical active networks that are biased identically for linear signal
processing purposes. Because no biasing subcircuits are delineated, all indicated
voltage and current variables represent only signal components thereof.
Before proceeding with our analytical investigation of the balanced differential amplifier, it is interesting to point out while differential technology has existed for decades, the
technology did not rise to prominence until the advent of the modern monolithic age[9]. Prior to
the integrated circuit revolution, the circuit designer had no option but to realize differential
topologies with discrete, off the shelf components. The inherent problem plaguing discrete
components is that matching of presumably like devices and circuit elements is a daunting challenge. This challenge can be mitigated through time-consuming, and therefore costly, individual
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component testing and selection or through circuit design heroics that may compromise system
performance and integrity. The matching challenge is far from superficial. For example, threshold voltages of same type discrete component MOSFETs can differ by tens of percent, and
transconductance coefficients (Kn) can be at variance by many tens of percent. To be sure, we
can offset these effects, perhaps by implementing the two resistive branch elements, Rgg, as judiciously adjusted, non-equivalent resistances. But such a tack invariably engenders increased
power dissipation, increased noise levels, diminished system reproducibility, and other issues.
Even simple, non-precision resistors rated for the same resistance values have their resistance
values stipulated to within error tolerances of at least ±10%. It follows that the likelihood of
straightforwardly realizing two identical resistances, yet alone two identical amplifiers, with discrete, off-the-shelf components, is virtually nil. But when implemented in an integrated circuit,
matching among like circuit devices and components, though still strictly imperfect, comes au
gratis. Indeed, implicit mismatches between two similar components laid out in close proximity
to one another on an integrated circuit chip are virtually imperceptible.
One caveat to the matching attribute of integrated circuits must be flagged when one of
the two input signals, say Vs2, applied to the balanced amplifier is zero. In this case, the source
resistance, Rs, associated with the nonzero input signal voltage, Vs1, is the internal resistance of
the source, which may be an antenna, a CD player, or the output resistance of a preceding stage
of amplification. With Vs2 nonexistent, the terminating resistance, Rs, at the input port of the second amplifier, must be implemented as a two terminal resistor that is physically constructed on
chip. In this circumstance, component matching between the two Rs resistances is problematic,
particular since the internal resistance associated with an actual signal source is generally neither
precisely known nor strictly independent of signal source voltage and current levels. The problem at hand is not severe in MOS technology realizations that feature either a common source or
a source follower amplifier input stage for which input port biasing resistances (Rb = ∞) are not
essential. In these embodiments, the gate of the input stage, which comprises the input port of
each amplifier, conducts no current, at least at low to moderately high signal frequencies. As a
result, no signal voltage is established across either resistance, Rs, which is to say that resistances
Rs and their unavoidable mismatches are inconsequential.
6.6.1. DIFFERENTIAL AND COMMON MODE SIGNALS
Because the amplifiers utilized in the differential system of Figure (6.40) are biased to
support linear signal processing of sufficiently small input signals, we can exploit classic
superposition theory to formulate general expressions that link the single ended output voltages,
Vo1 and Vo2, to voltages Vs1 and Vs2. In particular,
Vo1 = A11Vs1 + A12Vs2
(149)
,
Vo2 = A21Vs1 + A22Vs2
where the Aij are suitable gain constants that are independent of all signal voltages and signal
currents observed in the differential network. We note that parameter A11 is the voltage gain,
Vo1/Vs1, under the condition of Vs2 = 0, while A22 denotes the gain, Vo2/Vs2, with Vs1 = 0. In other
words, A11 is the voltage transfer function of Amplifier #1 with Amplifier #2 serving as a kind of
dummy load on #1 in that no input signal is externally applied to its input port. Similarly, A22 is
the gain of Amplifier #2 when Amplifier #1 functions as the dummy load imposed on #2. But
since the two amplifiers in question are matched and the balanced network at hand is necessarily
electrically symmetrical, the subject two voltage gains are identical. Accordingly, we can assert
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A11 ≡ A22 Ai .
(150)
We can offer precisely the same stipulation as regards gain parameters A12 and A21; that is,
A12 ≡ A21 A f .
(151)
This stipulation merely asserts that in a balanced differential pair, the sensitivity of output Vo1 to
input Vs2 (with Vs1 = 0) is the same as the sensitivity of Vo2 to Vs1 (with Vs2 = 0). In other words,
the cross-correlated voltage gains of the two amplifiers are identical in a balanced differential
architecture. The preceding two results allow us to simplify (149) to the form
Vo1 = Ai Vs1 + A f Vs2
(152)
,
Vo2 = A f Vs1 + Ai Vs2
where we witness the need of only two voltage gain metrics, Ai and Af, to relate the single ended
output signal voltages to the single ended input voltages applied to the balanced differential system.
In the process of analyzing the differential network of Figure (6.40), we shall find it
profitable to introduce the concepts of differential and common mode voltage and current signals. To this end, let the differential mode input signal, say Vdi, be defined as the difference between the two applied input signal voltages; namely,
Vdi Vs1 − Vs2 ,
(153)
where we note an unmistakable algebraic similarity to the differential output voltage, Vdo, in
(148). The common mode input signal, Vci, is
V + Vs2
,
Vci s1
(154)
2
which represents little more than the average of the two inputs. If we simultaneously solve (153)
and (154) for voltages Vs1 and Vs2, we get
V
Vs1 = Vci + di
2
.
(155)
Vdi
Vs2 = Vci −
2
Our ninth grade mathematics teachers would be proud of our algebraic acumen. Teacher pride
notwithstanding, the design-oriented interpretations and implications of (155) are vital to earning
an insightful understanding of both the operation and utility of a balanced differential amplifier.
First, we see that the system in Figure (6.40) can be diagrammed as the circuit in Figure
(6.41), where input signals Vs1 and Vs2 have been replaced by the superposition of differential
and common mode input voltages documented in (155). The latter illustration highlights the fact
that the common mode input signal is a constituent of both Vs1 and Vs2 that serves to activate the
input ports of both of the matched amplifiers. As such, Vci might be indicative of electrical noise
radiated by lighting fixtures, nearby electrical appliances, or proximately located electronics that
is picked up in like fashion by both of the amplifier input ports. Of course, the feasibility of both
input ports witnessing precisely the same unwanted electrical interference assumes that these
ports are physically laid out on chip with minimal geometrical separation. The common mode
input can also reflect fluctuations in biasing applied commonly to both input ports. Such
fluctuations might be incurred by electrical noise coupled to the biasing line from which the input port biasing level is derived, temperature-induced changes in device or circuit parameters,
routine battery degradation, and the like. As long as these network parasitic effects induce small
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changes in the common mode input voltage level, the differential system continues to respond
linearly to common mode signal fluctuations, which is an underlying requirement of (152).
Input Node:
Amplifier #1
Vi1
Ib1
Rs
−
Vi2
Rs
Rbb
Rgg
Rll
Vdo
Rkk
Vl
Rll
I2
Amplifier
#2
Vo2
−
Output Node:
Amplifier #2
Io2
Rl
−
+
Vci
+
Vdi
2
Rl
I1+I2
Vk
Ib2
Input Node:
Amplifier #2
Ill
Rgg
Ib1+Ib2
Rb
+
−
Vdi
2
+
Output Node:
Amplifier #1
Vo1
I1
Rb
Vb
Io1
Amplifier
#1
Figure (6.41). Alternative representation of the balanced differential architecture in Figure (6.40).
A laudable design goal inspired by these arguments is a differential network that in fact
does not respond to Vci and is therefore impervious to common mode parasitic phenomena. A
clue that we might be able to achieve, or at least to approximate, this design outcome is offered
by (155) and Figure (6.41) in that the differential input signal, Vdi = (Vs1 − Vs2), is independent of
the common mode input. It indeed stands to reason that if a signal, parasitic or otherwise, is
applied simultaneously (or “commonly”) to both of the amplifier inputs, the difference signal
between these two input port voltages automatically cancels the common mode excitation. Thus,
if the balanced differential network can be designed in such a way as to respond only to differential inputs, the output responses of the system are divorced of any ramifications attributed to
common mode input excitation.
A second implication of the differential and common mode concepts is that the
superposition equations in (152) can be rewritten as
⎛ Ai − A f ⎞
Vo1 = Ai + A f Vci + ⎜
⎟ Vdi
2 ⎠
⎝
;
(156)
⎛ Ai − A f ⎞
Vo2 = Ai + A f Vci − ⎜
⎟ Vdi
2 ⎠
⎝
(
)
(
)
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that is, the single ended output responses, Vo1 and Vo2, are individually a superposition of
differential and common mode input excitations. This discovery is hardly anything to write
home about since the outputs are inherently a superposition of the effects of Vs1 and Vs2, and Vs1
and Vs2, in turn, are linear functions of Vdi and Vci. But (156) conveniently serves to define three
traditionally adopted performance metrics of a balanced differential amplifier. The first of these
is the differential voltage gain, say Ad, which is the ratio of the differential output voltage to the
differential input voltage under the condition of a common mode input voltage constrained to
zero. Recalling (148),
V
V − Vo2
(157)
Ad do
= o1
= Ai − A f .
Vdi V =0
Vdi
V =0
ci
ci
In the course of formulating (157), we observe that the differential output response of a balanced
differential pair is invariant with common mode input excitation, which is to say that there is no
common mode signal component to the differential output voltage response. If we accept our
view of a common mode input as reflecting undesirable electrical phenomena, this independence
of differential output voltage to common mode input voltage is commendable. The downside,
however, is that since Vdo is not a single ended voltage response, it is impossible to maintain a
common signal ground between input signals and differential output response. This shortfall is
troublesome in most electronic systems, but it can be circumvented through the incorporation of
a differential to single ended converter, which we shall address later.
The second important performance metric is the common mode voltage gain, Ac, which
is the ratio of the common mode output voltage to the common mode input voltage when the
differential input signal is held at zero. A null differential input signal requires Vs1 = Vs2 and
therefore equal signal excitations applied to both of the amplifier input ports. Borrowing from
(154), the common mode output voltage, Vco, is defined as
V + Vo2
.
Vco o1
(158)
2
This definition and (156) combine to evolve
V
= Ai + A f .
(159)
Ac co
Vci V =0
di
In the idealized situation of a zero common mode response, we see that gain parameter Af must
be the negative of gain parameter Ai, which, by (157) gives a differential voltage gain of Ad = 2Ai
or equivalently, (−2Af).
The final metric of interest is the common mode rejection ratio, ρ, which is simply the
ratio of differential mode to common mode gains. From (157) and (159),
Ai − A f
A
ρ d =
.
(160)
Ac
Ai + A f
The common mode rejection ratio, as its name implies, is a measure of the ability of a differential network to reject, or at least substantively attenuate, the network responses to common mode
input signals. Since Ac is zero for complete rejection of applied common mode signals, the
idealized value of the common mode rejection ratio is ρ = ∞.
Equations (157), (159), and (160) can be used to express the output responses in (156)
in the form,
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A ⎛
2V ⎞
⎛A ⎞
Vo1 = AcVci + ⎜ d ⎟ Vdi = d ⎜ 1 + ci ⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
(161)
.
⎛
⎞
A
2V
⎞
d 1−
ci V
⎜
⎟ di
⎟ Vdi = −
2 ⎝
ρVdi ⎠
⎠
We have already seen, as is confirmed by the foregoing result, that the differential output response in a balanced differential network is divorced of a common mode signal component. But
interestingly, we now gather that
A ⎛
2V ⎞
⎛A ⎞
⎛A ⎞
Vo1 = AcVci + ⎜ d ⎟ Vdi = d ⎜ 1 + ci ⎟Vdi ≈ ⎜ d ⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
⎝ 2 ⎠
(162)
,
Ad ⎛
2Vci ⎞
⎛ Ad ⎞
⎛ Ad ⎞
Vo2 = AcVci − ⎜
⎜1 −
⎟Vdi ≈ − ⎜
⎟ Vdi = −
⎟Vdi
2 ⎝
ρVdi ⎠
⎝ 2 ⎠
⎝ 2 ⎠
which is approximately independent of the common mode input signal, provided that
⎛V ⎞
ρ ⎜ di ⎟ >> Vci ,
(163)
⎝ 2 ⎠
where absolute value signs are adopted to allow for the possibility that Vdi, Vci, and/or ρ may be
negative in a particular application. In short, the individual single ended output responses show
no significant common mode deterioration if either the common mode rejection ratio is large
and/or the common mode input signal is not especially large. For this special, yet practical, case,
we note that the magnitude of the single ended to differential input voltage gains, Vo1/Vdi and
Vo2/Vdi, are identical and equal to one-half of the differential gain of the of the entire differential
amplifier. Moreover, the individual single ended output responses are 180° out of phase with
one another, which gives the circuit designer flexibility over choosing Vo1 or Vo2 as the preferred
single ended output response.
⎛A
Vo2 = AcVci − ⎜ d
⎝ 2
Although we have focused herewith on only the output voltage responses of the balanced differential amplifier under consideration, the general form of the results disclosed is
applicable to any voltage or current variable in the network. A synopsis of this general form is
Circuit Variable = Common Mode Component
(164)
± Half Differential Mode Component ,
where it is understood that the plus (+) sign applies when the circuit variable of interest is associated with that part of the network that is driven by +Vdi/2, and the minus (−) sign applies to that
part of the system that is driven by −Vdi/2. For example, consider currents I1 and I2 in Figure
(6.41), where I1 flows out of Amplifier #1, which is excited at its input port by a signal voltage
whose differential component is +Vdi/2. On the other hand, current I2 flows out of Amplifier #2,
whose input differential signal is −Vdi/2. We note in accord with the defining nature of common
mode signals, that both amplifiers are excited by a common mode signal component, Vci. Letting
subscript “d” designate differential mode response and subscript “c” denote common mode response, we use (164) to write for currents I1 and I2,
I
I1 = I c1 + d 1
2
(165)
.
Id 1
I 2 = I c1 −
2
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Because of circuit linearity, we understand that current Ic1 is linearly related to the common
mode input voltage, Vci, while differential current Id1 is directly proportional to the differential
input excitation, Vdi. Although currents I1 and I2 have different values because of the phase
inversion ascribed to their differential components, both currents share the same common mode
ingredient and the same magnitude of differential component. This observation synergizes with
our perception of a balanced amplifier. Its propriety can be confirmed qualitatively by mentally
applying superposition theory to the network in Figure (6.41). To wit, if Vdi is set to zero,
thereby constraining the differential components of all circuit variables to zero, voltage Vci is the
only voltage applied to the input ports of each amplifier. But because each amplifier and its
terminations are identical in all electrical respects, a current of I1 = Ic1 generated by Vci applied to
Amplifier #1 must mirror the common mode component of current I2 spawned by Vci, which is
simultaneously applied to Amplifier #2. With Vci set to zero, the common mode components of
all network variables are vanquished, and +Vdi/2 is applied to Amplifier #1, while the negative of
this voltage excites the input port of Amplifier #2. Once again, linearity allows us to state that if
+Vdi/2 causes a current of Id1/2 to flow in the third lead of Amplifier #1, the corresponding lead
of Amplifier #2 necessarily conducts a current of −Id1/2. Yes, a negative differential current is
plausible for we must remember that all of these currents represent only signal components of
corresponding net currents.
A problem with the foregoing heuristic arguments occurs with respect to the voltages,
Vb, Vk, and Vl, which are established at circuit nodes lying on the electrical centroid of the network. In other words, are the differential components of these centroid variables associated with
+Vdi/2 or with −Vdi/2? There are two ways to address this dilemma, which we will exemplify
with voltage Vk. The first way entails blindly writing
V
Vk = Vck + dk
2
(166)
.
Vdk
Vk = Vck −
2
Clearly, (166) makes engineering sense only if the presumed differential part, Vdk, of voltage Vk
is zero. This postulate infers that Vk contains no differential component and therefore only a
common mode component, Vck. Our argument is reasonable in that if the indicated +Vdi/2 incurs
a rise in voltage Vk, the corresponding −Vdi/2 applied to the second amplifier causes a decrease in
Vk by precisely the same amount as the observed initial increase. Hence, no net change is manifested in voltage Vk if only a differential input signal is applied to the overall configuration.
The situation just described is reminiscent of the seesaws we enjoyed with our best
childhood friend. Upon mounting the seesaw, a push downward by our friend sitting at one end
of the seesaw is matched by our swinging upward by precisely the same amount as the initial
downward travel at the other end, and vice versa. Accordingly, there is “differential swing” in
that the motion downward (upward) at one end of the equipment is mirrored at the other end of
the seesaw by upward (downward) displacement. But despite the amount of “differential
swing,” the fulcrum of the seesaw, which is effectively the centroid of the equipment, moves neither upward nor downward. In other words, there is no differential displacement change at the
seesaw centroid. In effect, the fulcrum is grounded, thereby allowing us to measure the amount
of displacement at either end of the seesaw with respect to the fulcrum.
An alternative way of addressing the problem at hand is to compute voltage Vk in terms
of the currents, I1 and I2, disclosed in (165). We glimpse in Figure (6.41) that the current flowing
through resistance Rkk, which returns to ground the circuit node at which voltage Vk is estabMing Hsieh Department of Electrical Engineering
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lished, is (I1 + I2). But from (165), we see that (I1 + I2) has only a common mode constituent
(actually twice the common mode current indigenous to either current I1 or current I2). If there is
no differential current implicit to (I1 + I2), there can be, if Ohm is to be placated, no differential
part to voltage Vk, which appears directly across resistance Rkk.
6.6.2. HALF CIRCUIT ANALYSES
The straightforward way to assess the small signal performance of the differential pair
diagrammed in Figures (40) and (41) entails chasing the solutions to the Kirchhoff equations
written subsequent to replacing each amplifier by its appropriate small signal model. This tack
can prove formidable, particularly if the individual amplifiers are complex architectures.
Unfortunately, formidable analyses invariably foster complicated, if not intractable, disclosures
that inhibit an insightful understanding of circuit operation. A better analytical approach is
predicated on exploiting the architectural symmetry inherent in a balanced differential network.
6.6.2.1. Differential Mode Half Circuit
With superposition in mind, consider first the case of zero common mode input voltage,
which fosters zero common mode components to all network branch currents and node voltages.
As indicated in Figure (6.42a), voltage Vo1 sits at +Vdo/2, Vo2 = −Vdo/2, and Vi1 = −Vi2 = +Vd1/2,
where Vd1 is the voltage difference, Vd1 = (Vi1 − Vi2). For reasons articulated in the preceding
subsection, voltage Vk in Figure (6.41), which can assume only a common mode stature, is remanded to zero when, in fact, the common mode input signal is null. In effect, the node at which
voltage Vk is established acts as a virtual signal ground when the only prevailing input signal is
differential in nature. Voltage Vb in the same diagram is analogous to Vk, and the node that supports this voltage, like the node supporting voltage Vk, also lies at signal ground potential. Let us
now examine voltage Vl. An inspection of the current, Ill, conducted by the series interconnection of the two resistances labeled Rll reveals
Vdo
− Vl
Vdo
2
I ll =
=
,
(167)
2Rll
Rll
which immediately confirms Vl = 0. Like the nodes at which voltages Vk and Vb are sustained,
the junction supporting voltage Vl with respect to ground is a virtual signal ground. These
revelations allow us to replace, for exclusively differential input excitation, the entire differential
architecture in Figure (6.41) by the half circuit offered in Figure (6.42b). Either the top half or
the bottom half of the circuit can form the basis of this differential mode half circuit. We have
chosen the top half. If we had opted for the bottom half, the only changes would be an input signal of −Vdi/2 and a resultant output response of −Vdo/2.
In the half circuit in Figure (6.42b), the I/O voltage gain, which is the ratio of output
signal voltage Vdo/2 to applied input signal voltage Vdi/2, is equal to the differential voltage gain,
Ad, defined by (157) of the balanced differential amplifier shown in Figure (6.40). We
enthusiastically note that this gain metric is obtainable through consideration of only one-half of
the original balanced network. The analytical simplifications that ensue from an investigation of
only a compressed architecture are likely to be enhanced further in that there is a distinct
possibility that Amplifier #1 in Figure (6.42b) is a familiar or otherwise recognizable architecture. For example, Amplifier #1 may be one of the networks we have already studied in depth,
or it could be a combination of two or more of these previously investigated active networks. In
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this event, an evaluation of the differential gain amounts to little more than adapting previously
derived results to the half circuit model at hand.
Vd1 /2
Rs
Vdi
2
Id1 /2
Rb
Rgg
0
Rb
−
Vdi
2
Ill
Rl
0
Vk = 0
Rbb
Rgg
−Idb /2
Rs
+
Idb /2
Vb = 0
+
Vdo /2
Amplifier
#1
Vdo
Rkk
Vl = 0
Rll
−Id1 /2
−Vdo /2
Amplifier
#2
−Vd1 /2
Rll
−
Rl
−
+
(a).
Rdi /2
Rdo /2
Vd1 /2
Rs
Vdi
2
+
Amplifier
#1
Vdo /2
Idb /2
Id1 /2
Rb
Rgg
Rl
Rll
−
(b).
Figure (6.42). (a). The balanced differential architecture of Figure (6.41) under the condition of
null common mode input excitation. (b). The differential mode half circuit model of
the network in (a).
The foregoing gain assertions apply equally well to the input and output resistances, but
we must exercise care when interpreting these resistance results. To wit, the input resistance
seen by the signal source in the differential mode half circuit model is delineated as Rdi/2 in
Figure (6.42b). Parameter Rdi symbolizes the differential mode input resistance, which is to say
that it is the net effective resistance seen by the net differential input voltage, Vdi, under the
condition of zero source resistance; that is, Rs = 0. In other words, Rdi is the input resistance
referenced to the two amplifier input nodes that support voltages Vi1 and Vi2 in Figure (6.41).
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But since the network in Figure (6.42b) is only one-half of the original balanced configuration,
wherein all centroid nodes are returned to signal ground, the input resistance actually evaluated
in the subject half circuit diagram is literally one-half of the true differential input resistance of
the entire amplifier. An analogous situation applies to the differential mode output resistance,
Rdo, where in the present case, we have elected to include resistances Rl and Rll in the calculation.
The schematic diagram in Figure (6.42b) correctly shows that a resistance evaluation pursued at
the output port of the half circuit results in one-half of the actual differential output resistance of
the original circuit.
6.6.2.2. Common Mode Half Circuit
Having studied the balanced differential amplifier for the differential mode case in
which the common mode input signal, Vci, is held to zero, let us now turn to the common mode
situation for which the input differential signal, Vdi, is set to zero. The electrical conditions
corresponding to exclusively common mode signal excitation are highlighted in Figure (6.43a),
where all branch currents and node voltages assume their common mode values. The
corresponding common mode half circuit appears in Figure (6.43b). Several differences become
apparent when we compare this model to its differential mode counterpart in Figure (6.42b). We
can begin to underscore these differences by first examining the common mode voltage, Vcb,
which is developed at the node to which the two resistances of value Rb and the resistance, Rbb,
are incident. Unlike the differential value, Vdb, of voltage established at the subject circuit node
when the common mode signal is set to zero, voltage Vcb is not zero in that it must support the
flow of current through Rbb. This current is twice the common mode current, Icb, conducted by
each of the two resistances, Rb, whence Vcb = 2IcbRbb. The common mode half circuit, which we
arbitrarily choose to construct from the top half of the network in Figure (6.43a), must be faithful
to the current conducted by resistance Rb, as well as to the voltage, Vcb. Since a current of (2Icb)
rattling through a resistance of Rbb develops the same voltage that does a current of Icb conducted
by an effective resistance of (2Rbb), we place a resistance of (2Rbb) in series with the resistance,
Rb, which we have noted in Figure (6.43a) as conducting a current of Icb. An entirely analogous
situation is pervasive of resistances Rk and Rkk, whence (2Rkk) appears in series with Rk in the
common mode half circuit. Resistances Rll in Figure (6.43a) are not embedded in Figure (6.43b)
for the simple reason that neither Rll conducts any current. This null value of current is caused
by the fact that the voltages appearing with respect to signal ground at both of the single ended
amplifier output ports are identical and, in fact, equal to the common mode voltage response, Vco.
It follows that the differential voltage generated between these two ports, and which appears
across the series interconnection of the two circuit resistances, Rll, is zero, which reflects the zero
differential signal input state to which attention is presently focused. If no current flows through
a branch, no electrical purpose is served by the branch, and it can therefore be trashed.
We now see that the voltage gain, Vco/Vci, of the common mode half circuit in Figure
(6.43b) is precisely the common mode voltage gain, Ac, of the entire balanced differential amplifier. As in the case of the differential voltage gain, which derives as the voltage gain of the
differential mode half circuit, this gain can usually be evaluated either by inspection or with the
minimal amount of analysis fostered by our experiences with previously encountered similar circuit cells. The input resistance of the common mode half circuit is denoted as Rci and is termed
the common mode input resistance. It represents the net resistance with respect to signal ground
established at both of the two amplifier input port nodes, where signal voltages Vi1 and Vi2
respectively appear in the system of Figure (6.40). Similarly, the common mode output resistance, Rco, of the balanced differential network is identical to the output resistance witnessed in
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the common mode half circuit. It is the resistance with respect to signal ground at either of the
two output port nodes of the original balanced network.
Vc1
Icb
Rs
Ill = 0
Rgg
2Icb
Vcb
+
Ic1
Rb
Rl
2Ic1
Vck
Rbb
Rb
Rll
0
Rkk
Rgg
Icb
Rll
Ic1
−
Vco
Amplifier
#2
Vc1
Rs
Vco
Amplifier
#1
−
Vci
+
Rl
(a).
Rci
Rco
Vc1
Rs
Icb
+
Vci
−
Amplifier
#1
Ic1
Rb
Vcb
Vco
Rgg
Rl
Vck
2Rbb
2Rkk
(b).
Figure (6.43). (a). The balanced differential architecture of Figure (6.41) under the condition of
null differential mode input excitation. (b). The common mode half circuit model of
the network in (a).
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6.6.2.3. Utility Of The Half Circuit Models
In the interest of clarity, it is worthwhile placing the analytical issues deriving from the
half circuit models of a balanced differential pair into perspective. Let us start with I/O gain
issues. The differential gain, Ad, which is quite literally the voltage transfer function of the
differential mode half circuit in Figure (6.42b), is the ratio of the differential output voltage to
the difference between the two applied signals in the balanced pair of Figure (6.40).
Specifically,
V
V − Vo2
Ad = do = o1
,
(168)
Vdi
Vs1 − Vs2
where we understand that all stipulated voltages are small signal components divorced of any
biasing levels. In contrast, the common mode gain, Ac, which derives as the voltage transfer
function, Vco/Vci, of the common mode half circuit in Figure (6.43b), is
Vo1 + Vo2
Vco
V + Vo2
2
(169)
Ac =
=
= o1
.
Vs1 + Vs2
Vci
Vs1 + Vs2
2
At least four single ended gain relationships may be of at least tacit interest to the
circuit designer. The first of these is the ratio of the single ended voltage, Vo1, in Figure (6.40) to
the applied input signal, Vs1, under the condition that input signal Vs2 is held fast at zero. Using
(153), (154), and (161),
Vdo
AcVs1 AdVs1
+
+
V
co
Vo1
A + Ac
2
2
2
=
=
= d
≡ A11 ,
(170)
Vs1 V =0
Vs1
Vs1
2
s2
Vs2 =0
where we introduced constant A11 in the superposition relationship of (149). Because of the
balanced nature of the differential amplifier undergoing scrutiny, this gain can be shown to be
the same as the ratio of the second of the two available single ended output voltages, Vo2, to the
second applied input signal, Vs2, under the constraint of Vs1 = 0. In short,
Vo2
V
A + Ac
(171)
≡ o1
= d
≡ A22 ≡ A11 ≡ Ai ,
Vs2 V =0
Vs1 V =0
2
s1
s2
The voltage gain from the second input signal to the first single ended output, for the case of Vs1
= 0, is
V
AcVs2 Ad ( −Vs2 )
Vco + do
+
Vo1
A − Ac
2
2
2
=
=
= − d
≡ A12 .
(172)
Vs2 V =0
Vs2
Vs2
2
s1
Vs1 =0
Finally, the voltage gain from the first input signal to the second single ended output with Vs2 = 0
is the same as the gain just disclosed. In other words, the balanced nature of the amplifier at
hand delivers
Vo2
V
A − Ac
≡ o1
=− d
≡ A21 ≡ A12 ≡ A f .
(173)
Vs1 V =0
Vs2 V =0
2
s2
s1
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We observe that if |Ac| << |Ad|, which reflects the requirement of a large common mode
rejection ratio, ρ, all of the gains in (170) through (173) are nominally independent of the
network common mode gain and given quite simply as ±Ad/2.
Rdi
Input Node:
Amplifier #1
Rxi
Vi1
Rdo
Input Node:
Amplifier #2
Vi2
Rci
Output Node:
Amplifier #1
Rci
Rxo
Vo1
Vo2
Rco
(a).
Output Node:
Amplifier #2
Rco
(b).
Figure (6.44). (a). Conceptual circuit model for the input ports of the balanced differential amplifier in
Figure (6.40). (b). Conceptual circuit model for the output ports of the balanced differential amplifier in Figure (6.40).
The interpretation of the differential mode and common mode input and output
resistances is facilitated by the conceptual port models advanced in Figure (6.44)[10]. We begin
with the input port model shown in Figure (6.44a). There is little to argue about the fact that the
common mode input resistance, Rci, terminates each input port of the balanced differential
amplifier to ground. However, a potential argument surfaces concerning the resistance, Rxi,
which is shown connecting together the subject two input ports. It seems almost natural to view
this resistance as the differential input resistance. Ostensibly natural inclinations can be
fallacious, and the present case support this prophecy. In particular, we must remember that Rdi
represents the net resistance established differentially across the two amplifier input ports. As
such, we recognize that Rdi must make due account of the port loading effected by the two
common mode input resistances, Rci. Accordingly, we must select resistance Rxi in such a
manner that the net resistance seen between input ports 1 and 2 is the differential input
resistance, Rdi, computed from the differential mode half circuit. In particular,
Rdi = Rxi ( 2Rci ) ,
(174)
which we can solve for Rxi to deliver
2Rci Rdi
Rxi =
.
(175)
2Rci − Rdi
As expected, large Rci, which implies minimal common mode loading of the amplifier input
ports, promotes Rxi ≈ Rdi. The situation at the output ports, which is abstracted in Figure (6.44b),
is the same as that just considered for the input ports. Thus, we offer without analytical fanfare,
2Rco Rdo
Rxo =
.
(176)
2Rco − Rdo
In order to demonstrate the utility of the port resistance models, let us suppose that the
balanced differential pair of Figure (6.40) is operated with signal voltage Vs2 equal to zero and
that we wish to determine the input resistance, say Rin, seen by the signal applied to input port 1.
The applicable circuit crutch is the resistive network of Figure (6.45a), where we have
terminated input port 2 to ground in the physical resistance, Rs, which, of course, must be
matched in theory to the internal resistance associated with signal source Vs1. By inspection of
the subject model, we see that
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⎡ 2Rci Rdi
⎤
Rin = Rci ⎡⎣ Rxi + ( Rci Rs )⎤⎦ = Rci ⎢
+ ( Rci Rs ) ⎥ .
(177)
⎣ 2Rci − Rdi
⎦
We note that this input resistance is dependent on resistance Rs. But once again, this particular
Rs is not the source resistance associated with the first signal voltage, Vs1. Instead, it is the port 2
physical resistance required to match both of the input ports of the differential configuration.
Input Node:
Amplifier #1
Input Node:
Amplifier #2
Rxi
Vi1
Vi2
Rci
Rci
Output Node:
Amplifier #1
Rxo
Vo1
Rs
Vo2
Rco
Rco
Rout
Rin
(a).
Output Node:
Amplifier #2
Rout
(b).
Figure (6.45). (a). Model used to evaluate the input resistance, Rin, seen at port 1 of the balanced
differential amplifier in Figure (6.40) under the condition that signal source Vs2 is zero.
(b). Model used to compute the output resistance, Rout, at either output port of the balanced differential amplifier in Figure (6.40).
Figure (6.45b) is the model pertinent to computing the output port resistance, Rout,
which, because of amplifier symmetry, is identical for both output ports. By inspection of this
model and with (176) in mind, we find that the output resistance is
⎡ 2Rco Rdo
⎤
+ Rco ⎥
Rout = Rco [ Rxo + Rco ] = Rco ⎢
⎣ 2Rco − Rdo
⎦
(178)
⎡⎛ 2Rco + Rdo ⎞
⎤
= Rco ⎢⎜
⎟ Rco ⎥ .
−
2R
R
do ⎠
⎣⎝ co
⎦
Equation (178) in general projects a net output resistance that is larger than Rco/2 for given
common mode and differential mode output resistances. We see, however, that Rout ≡ Rco if Rdo
= 2Rco, which, by (176), is tantamount to an infinitely large output port coupling resistance, Rxo.
6.6.3. BALANCED DIFFERENTIAL PAIR CIRCUIT ANALYSIS
Because balanced differential circuit technology does not generally advance new analog circuit cells, its circuit level analysis relies largely on an awareness of the properties,
characteristics, and models of commonly encountered single ended circuit structures. Balanced
amplifier analysis therefore presents few challenges, save possibly for the fact that the differential and common mode performance metrics associated with balanced circuit architectures must
be clearly understood, properly interpreted, and judiciously applied to the relevant problems
placed before us. This caveat renders prudent a consideration of a specific example of a balanced differential amplifier and to that end, we shall examine the somewhat imposing structure
offered in Figure (6.46). For this amplifier, we wish to determine expressions for the low frequency, single ended, small signal voltage gain, Av = Vo2s/Vs, the input resistance, Rin, seen by the
signal source comprised of the series interconnection of Thévenin signal voltage Vs and Thévenin
source resistance Rs, and the output resistance, Rout. Although we can assuredly determine these
and other amplifier metrics accurately by considering the effects of all device channel resistances, device bulk transconductances, and other second order circuit and layout phenomena, we
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shall adopt herewith a simplified analytical strategy that is premised on several operating
presumptions and stipulations.
+Vdd
Rl
M3
Vo1
R
Rl
M7
Vy1
M4
Vo2
Vy2
M2
Vbias1
M3a
M2a
Rout
M4a
C1
C1
M8
M1
M1a
C2
Rs
Rin
Rb
Rss
Rss
Rb
Rs
M5
+
Vs
−
Rkk
M6
Figure (6.46). An example of a balanced differential pair. Although not explicitly shown, the bulk
terminals of all transistors are connected to circuit ground, which in this case is the minimum static potential of the circuit. The low frequency, small signal analysis of the
amplifier is carried out in the text for the simplifying approximations of very large device
channel resistances and negligible bulk transconductances in all transistors.
(1). We shall assume that all transistors are biased in their saturation regimes and have very
large drain-source channel resistances and negligibly small bulk-induced transconductances. It follows that the low frequency, small signal model of every transistor consists
merely of a voltage controlled current source, gmV, directed from drain terminal to source
terminal, where gm is, of course, the forward transconductance of a device, and V symbolizes the gate to source signal voltage imposed on the considered transistor. While this
simplified analytical procedure may be distasteful to the analytical purist, it is justifiable
from a design-oriented perspective. In particular, acceptable or desirable responses deduced from analyses predicated on simplified approximations can be viewed as a necessary condition that underpins a successful design venture. Stated bluntly, a circuit that
does not evoke proper I/O functionality under simplified −perhaps almost idealized−
conditions has little, if any, hope for functionality with realistic device models and due
consideration given to all circuit and system parasitics. To be sure, performance estimates
derived under approximate operating circumstances constitute only design necessity, sans
design sufficiency, which can only be promoted by definitive manual and computer-based
analyses and in more extreme cases, prototype testing.
(2). Implicit to the device modeling assumption voiced in the preceding paragraph is the
presumption that the signal frequencies implicit to signal source Vs are not so high as to require a consideration of transistor capacitances (gate-source capacitance, bulk-drain
capacitance, gate-drain capacitance, etc.).
(3). The circuit capacitances, C1 and C2, are chosen to behave as short circuited branch elements for all radial signal frequencies above a proscribed minimum, say ωl. Thus, while
we shall be cavalier by referring to the amplifier as a lowpass amplifier, in truth, the netMing Hsieh Department of Electrical Engineering
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work operates acceptably only for frequencies above ωl. Our cavalier stance is tolerable if
the 3-dB bandwidth is significantly larger than frequency ωl.
(4). We are told that the amplifier is a balanced configuration. This balance requires that
transistor Mi be geometrically and electrically matched to transistor Mia for i = 1, 2, 3, 4.
Note that transistor Mj or Mja need not be respectively matched to transistor Mi or Mia in
order for operational balance to be effected. Thus, for example, while transistors M2 and
M2a must be identical, inclusive of gate aspect ratios, transistors M1 and M1a, which must
be a matched pair, need not have the same gate aspect ratios as do M2 and M2a.
6.6.3.1. Casual Circuit Inspection
Viewing any comparatively intricate circuit diagram for the first time can be an imposing ordeal for even the more venerable of circuit design engineers. This taxing experience is all
too often exacerbated by an inclination to initiate mathematical analysis without an adequate
appreciation of the design targets of the circuit at hand and without a meaningful strategy that
encourages streamlined analytical procedures that ultimately produce response disclosures
couched in mathematically meaningful and insightful forms. An impressively precise and definitive analysis that illuminates no results that are transparently applicable to circuit design is arguably a moot accomplishment in the electronic systems and circuits discipline. But approximate
disclosures whose sources of error are clearly understood and understandable are priceless assets
when we profit from them in the course of successfully navigating a design challenge. We therefore argue that the best first step to conducting a meaningful analysis of a practical circuit is to
put the pencil and paper down and to turn away from the computer. Instead, let us begin by carefully studying the circuit schematic provided us −albeit in only qualitative or visceral senses− to
ascertain the functionality of the various active and passive circuit components embedded in the
network. If we execute this type of investigation with care and without violating any of the
fundamental precepts of circuit analysis, we just might deduce first order, but sufficiently accurate, response results that can form an engineering basis for more definitive manual and computer-assisted follow-up circuit analyses from which an optimal design realization can ultimately
be contrived. Practicing this analytical tack for a variety of circuit structures has long-term benefits in that it increases our intuitive abilities to gauge circuit dynamics and in the process, our design skills are ultimately honed.
Let us return to the circuit schematic diagram in Figure (6.46) to deduce the basic
functionality and purposes of the various components therein.
(1). We know that a balanced differential amplifier exploits two amplifiers whose architectures, biasing, I/O terminations, and other electrical characteristics at circuit nodes and
within circuit branches are matched. We see that one of the requisite amplifiers in the balanced configuration of Figure (6.46) is forged by transistors M1, M2, M3, and M4. The
other amplifier, which is necessarily matched to the first, is formed of transistors M1a,
M2a, M3a, and M4a.
(2). We recognize transistors M1 and M1a as common source amplifiers in that signal is applied to the gate terminal of M1 with the understanding that a signal of zero value is likewise applied to the gate of transistor M1a. Moreover, the outputs of these transistors are
extracted at their drain terminals. The common source amplifiers at hand are source
degenerated via resistances Rss. We recall from our earlier travels that this source
degeneration resistance desensitizes amplifier gain with respect to the forward
transconductances of its embedded active elements. Resistance Rkk, is required to provide
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a current path to ground for the source currents conducted by transistors M1 and M1a.
Without Rkk, the source current of one of these two transistors would be constrained to be
the negative of the net source current of the other transistor, which is clearly an impossible
situation.
(3). The drain current outputs of the M1-M1a pair are applied to common gate transistors M2
and M2a, ostensibly for the purpose of mitigating Miller multiplication of the gate-drain
capacitances of transistors M1 and M1a. We note that the gates of M2 and M2a are
grounded, via capacitance C2, for all signal frequencies of immediate interest, leaving only
their source terminals as input ports and their drains as output ports. The gates of these
two common gate transistors are biased by the power line active divider comprised of diode-connected transistors M7 and M6. It is notable that neither of these latter two devices
plays a role in the small signal performance of the amplifier. In particular, transistor M8 is
shorted directly to ground through capacitance C2. Recall that C2, like all other indicated
circuit capacitances, is chosen to emulate a short circuit for frequencies of interest,
presumably under both differential and common mode circumstances. On the other hand,
the gate and drain terminals of transistor M7 lie at signal ground, assuming that the power
line is driven by an essentially ideal voltage source, Vdd. Moreover, the source terminal of
M7 is returned to ground via capacitance C2. It follows that for small signals, M7 is connected between ground and ground; this is, it is short circuited to ground.
(4). A similar divider −this one formed of transistors M5 and M6− powers up the gate terminals of the common source transistors, M1 and M1a. Because no static current is conducted by transistor gates and no static current flow through the coupling capacitances, C1,
is possible, no static current flows through the bias resistances Rb. Accordingly, the static
voltage developed at the source terminal of transistor M5 in the divider topology is the
static voltage manifested at the gates of transistors M1 and M1a. Unlike transistors M7
and M8, M5 and M6 are not bypassed to ground and therefore, they do influence the small
signal performance of the entire amplifier.
(5). The load imposed on the common source-common gate cascode formed of transistor pairs
M1-M1a and M2-M2a consists of the interconnection of the single ended resistances, Rl,
and the differential resistance, R. The voltages, Vy1 and Vy2, developed across this
terminating load structure are coupled to the amplifier output ports through the balanced
source follower comprised of the transistor pair, M3-M3a. We see that each of these two
source follower transistors is terminated in active loads formed of the matched transistor
pair, M4-M4a. Because only a constant bias voltage, Vbias1, is applied to the gates of the
latter two devices, no gate-source signal voltage prevails for either M4 or M4a. As a result, the gmV dependent sources in the small signal models of M4 and M4a are zero,
thereby leaving, in view of the presumption of negligible body effect, only drain-source
channel resistances in these models. Since all device channel resistances are presumed
very large, the small signal models of M4 and M4a reduce to effective open circuits at
their respective drain sites. This state of affairs is indicative of the fact that M4 and M4a
conduct only constant currents that necessarily have no signal-induced change and therefore, zero small signal current value. In short, M4 and M4a behave as open circuits for the
signals applied to the differential amplifier.
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Rl
M3
Rl
R
Vy1s
Vo1s
J. Choma
M3a
Vy2s
M2
M2a
Vo2s
Rout
Rin
M1
Rs
Rb
M1a
Rss
Rss
Rb
Rs
1
gm5
+
Vs
−
Rkk
1
gm6
Figure (6.47). The signal schematic equivalent of the balanced differential amplifier shown in
Figure (6.46).
The foregoing observations encourage us to simplify the given schematic diagram expressly for the purpose of small signal analysis. The specific simplification that supports efficient small signal analysis is the so-called signal schematic diagram provided in Figure (6.47).
This diagram crops all biasing issues from the schematic picture, which is the reason that the Vdd
power line is now shown as a signal short circuit. More formally, the battery voltage, Vdd, has
been replaced by its small signal value, which is zero, if Vdd emulates a constant voltage source.
With the line voltage removed, all variables in the circuit assume their respective small signal
values. Thus, voltage Vy1 in Figure (6.46) becomes Vy1s in Figure (6.47), voltage Vo1 is supplanted by Vo1s, and so forth, where as usual the subscript, “s,” is understood to identify a small
signal value of a branch current or a node voltage variable. Because of the signal short circuit
natures of Vdd and capacitance C2, transistors M7 and M8 in Figure (6.46) do not appear in the
signal schematic version of the amplifier because these devices are shorted for the signal
frequencies of interest. In concert with the discussion above, transistors M4 and M4a in Figure
(6.46) become open circuits in Figure (6.47). Since transistors M5 and M6 are diode-connected
two terminal branch elements, these transistors are replaced by their small signal resistance values, which, in consideration of the approximations invoked, are 1/gm5 and 1/gm6, respectively.
Finally, capacitances C1 are replaced by short circuits on the presumption that we are currently
focused on the signal processing characteristics of the differential amplifier for frequencies
above the lowest frequency of interest.
Before turning to the actual analysis of the circuit in Figure (6.47), we should also note
that since the source follower transistors, M3 and M3a, are terminated in open circuits, their
individual voltage gains are unity because of the assumptions of large channel resistances and
negligible bulk transconductances. This fact follows immediately from the disclosures in Sections (3.1) and (3.2). Consequently, Vy1s = Vo1s and Vy2s = Vo2s. More definitively,
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V
A V
Vo1s = Vco + do = AcvVci + dv di = V y1s
2
2
,
(179)
Vdo
AdvVdi
Vo2s = Vco −
= AcvVci −
= V y2s
2
2
where Adv denotes the differential mode voltage gain of the balanced amplifier, and Acv is its
common mode voltage gain. From (153) and (154), the differential input voltage, Vdi, applied to
the balanced pair is
Vdi = Vs ,
(180)
while the corresponding common mode input signal voltage, Vci, is
V
Vci = s .
(181)
2
It follows by (179) that the desired overall voltage gain, Av, of the network undergoing
investigation is
V
A − Acv
Av = o2s = − dv
.
(182)
Vs
2
which underscores our need to evaluate the differential and common mode gains in order to
determine the overall single ended voltage gain of the balanced differential amplifier.
6.6.3.2. Circuit Analysis
We shall rely on the pertinent half circuit models that we conceptually developed in
Section (6.2) to evaluate the differential mode and common mode voltage gains of the circuit
before us. Figure (6.48a) delineates the differential mode half circuit model of the simplified
amplifier depicted in Figure (6.47). In concert with our earlier discussions, the circuit node to
which resistance Rkk is connected, the node to which the resistances, 1/gm5 and 1/gm6, are incident, and the mid point of resistance R are grounded. Since the half model in question applies
only to differential mode, all circuit node voltages, as well as all branch currents, are divorced of
common mode components and indeed have only half amplitude differential mode signal components. Indeed, the input signal applied to the half circuit is now Vdi/2. At the output port, we
have made use of the fact that the source follower transistor, M3, delivers unity gain, whence its
output signal voltage, Vdo/2, is identical to the signal voltage that prevails at its gate terminal.
We observe further that the indicated input resistance is Rdi/2; that is, it is one-half of
the differential input resistance of the entire balanced amplifier. Since the gate of transistor M1
conducts no current at low to moderately high signal frequencies, a casual inspection produces
Rdi
= Rb .
(183)
2
Recalling our work with source followers, the indicated half differential output resistance, Rdo/2,
is simply the resistance presented by transistor M3 at its source terminal. Within the framework
of our approximations, this resistance is 1/gm3. Specifically,
Rdo
1
=
.
(184)
2
gm3
We now turn to the calculation of the differential voltage gain, Adv. In Figure (6.48a),
the signal voltage, Vdii/2, established at the gate of transistor M1 is simply a voltage divider function of the input signal, Vdi/2. This is to say that
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Rl
Rl
M3
Vdo /2
R/2
M3
Vco
Vdo /2
M2
Rci
M2
Vdi
2
Ic1
Vcii
Rdi /2
Vdii /2
M1
Id1 /2
M1
Rs
Rb
+
Ic1
Rco
Id1 /2
Rdo /2
Rs
Vco
Rss
Id1 /2
−
+
Vci
−
Rb
Rss
Ic1
2
gm5+gm6
2Rkk
(b).
(a).
Figure (6.48). (a). Differential mode half circuit schematic diagram of the balanced differential amplifier in
Figure (6.46). (b). Common mode half circuit schematic diagram of the balanced differential pair in Figure (6.46).
⎛ Rb ⎞ Vdi
Vdii
k V
= ⎜
= b1 di ,
⎟
2
2
⎝ Rb + Rs ⎠ 2
(185)
where
Rb
(186)
Rb + Rs
is the pertinent input port divider function. Because signal voltage Vdii/2 is established at the gate
of transistor M1, whose source is degenerated by resistance Rss, the signal drain current of M1 is,
recalling (13),
⎛
⎞ kb1Vdi
I d1s
g m1
(187)
= ⎜
.
⎟
2
⎝ 1 + g m1 Rss ⎠ 2
As is indicated in the diagram of Figure (6.48a), this current rolls through common gate device
M2 and thence through the load resistance, which is comprised of the shunt interconnection of
resistances Rl and R/2. It follows that the half differential output voltage, Vdo/2, is
⎛
⎞⎛
Vdo
I
g m1
⎛
R⎞
R ⎞ kb1Vdi
(188)
= − d1s ⎜ Rl
= −⎜
,
⎟ ⎜ Rl
⎟
2
2 ⎝
2⎠
2 ⎟⎠ 2
⎝ 1 + g m1 Rss ⎠ ⎝
whence a low frequency, small signal, differential mode voltage gain, Adv, of
⎛ k g
⎞⎛
V
R⎞
.
Adv = do
= − ⎜ b1 m1 ⎟ ⎜ Rl
(189)
2 ⎟⎠
Vdi V =0
⎝ 1 + g m1 Rss ⎠ ⎝
kb1 =
ci
We should be clear about the fact that the proviso, Vci = 0, which is appended as a subscript to
this voltage gain equation, is automatically satisfied in the differential mode half circuit of Figure
(6.48a). In particular, Figure (6.48a) applies exclusively to differential mode excitation, which
means that the common mode component, Vci, of the applied signal source is constrained to zero.
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As expected, we see in (189) that the source degeneration resistance, Rss, reduces the differential
gain sensitivity to transistor transconductance gm1. Of course, the price paid for this reduced
sensitivity is reduced gain. We also notice that since the divider constant, kb1, is obviously less
than one, kb1 contributes to gain magnitude degradation. Such degradation is kept minimal if the
biasing resistance, Rb, in (186) is selected to be significantly larger than signal source resistance
Rs.
Figure (6.48b) is the common mode half circuit equivalent for the subject balanced
differential amplifier. In this model, the signal source is the common mode input voltage, Vci,
and all node voltage and branch currents, inclusive of the output voltage variables, assume their
respective common mode signal values. No differential mode voltage or current components
prevail in this model because the differential part, Vdi, of the applied input signal is set to zero.
Three topological differences prevail between the common mode half circuit and its differential
mode brethren. First, the node to which resistances Rb, 1/gm5, and 1/gm6 are incident in Figure
(6.47) is not grounded for common mode excitation. Since an amplifier operated with common
mode input has common mode signal voltage applied to both input ports of a balanced pair, the
current conducted by the resistance whose conductance sum is (gm5 + gm6) is necessarily twice
the signal current that flows through either resistance Rb. Thus, the common mode model places
a resistance of 2/(gm5 + gm6) in series with biasing resistance Rb, as shown in Figure (6.48b). For
the second topological difference, the argument just invoked applies equally well to resistance
Rkk in Figure (6.47), whence we place a resistance of 2Rkk in series with the source degeneration
element, Rss. Finally, resistance R/2 no longer shunts the drain load resistance, Rl. In Figure
(6.47) we witness R as connected between the two output ports. Since both of these output nodes
support the same common mode signal response, Vco, no current flow through R can be supported, which allows resistance R to be removed from the circuit.
By inspection of the common mode half circuit in Figure (6.48b), the indicated common mode input resistance, Rci, is
R
2
2
(190)
Rci = Rb +
= di +
,
g m5 + g m6
2
g m5 + g m6
where we have appealed to (183). The effective input resistance, Rin, can now be determined
through a direct substitution of (190) and (183) into (177). This substitution exercise is a task
best left to the reader. But for the generally practical case of a large biasing resistance, Rb, which
satisfies the constraint,
(191)
( gm5 + g m6 ) Rb >> 2 ,
it is simple to confirm
Rin ≈ Rb .
(192)
which supports our intuitive view of the input port in the amplifier of Figure (6.47). In particular, if either transconductance gm5 and/or transconductance gm6 is large, which supports the
requirement projected by (191), resistance Rb comprises a resistive branch connection from the
input port to ground.
An inspection of the output port in Figure (6.48b) reveals a common mode output resistance, Rco, of
R
1
(193)
Rco =
= do ,
g m3
2
where (184) is exploited. Using (178), (193) and (184) deliver a net output resistance, Rout, of
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Rout = Rco =
J. Choma
1
.
(194)
g m3
This result is self-evident in that in Figure (6.47), the M3a gate, which conducts essentially no
signal current, isolates transistor M3a from the rest of the circuit, leaving only the resistance,
1/gm3, seen looking into the source of M3a as the observable output resistance.
The only major task remaining is the derivation of the common mode gain of the
differential network. In Figure (6.48b), the common mode signal voltage, Vcii, developed at the
gate of transistor M1 is
2
⎛
⎞
⎜ Rb + g + g
⎟
m5
m6
⎜
⎟ Vci = kb2Vci ,
(195)
Vcii =
2
⎜R +
⎟
+
R
s⎟
⎜ b g +g
m5
m6
⎝
⎠
where
2
Rb +
2 + ( g m5 + g m6 ) Rb
gm5 + gm6
(196)
kb2 =
.
=
2
2
g
g
R
R
+
+
+
(
)(
)
m5
m6
b
s
Rb +
+ Rs
gm5 + gm6
Noting now an effective source degeneration resistance of (Rss + 2Rkk), the common mode signal
drain current, Ic1s, conducted by transistor M1 follows as
⎡
⎤
g m1
I c1s = ⎢
(197)
⎥ kb2Vci .
⎣ 1 + g m1 ( Rss + 2Rkk ) ⎦
This current flows through common gate transistor M2 and load resistance Rl so that the common
mode signal output voltage, Vco, is
⎡
⎤
g m1 Rl
Vco = − I c1s Rl = − ⎢
(198)
⎥ kb2Vci .
⎣ 1 + g m1 ( Rss + 2Rkk ) ⎦
Clearly, the common mode voltage gain, Acv, is
V
kb2 g m1 Rl
Acv = co
= −
.
(199)
Vci V = 0
1 + g m1 ( Rss + 2 Rkk )
di
The low frequency, small signal, single ended voltage gain, Vo2s/Vs, of the balanced network in Figure (6.46) can now be determined simply by plugging (199) and (189) into (182).
The delineation of the resultant “exact” gain expression is left as an exercise for the reader. But
we can formulate a useful approximate gain relationship by observing that if the biasing
resistance, Rb, satisfies (191), the divider constant, kb2, in (196) closely approximates kb1 in (196).
If in addition to satisfying (191), Rl is implemented as a resistance that is significantly smaller
than R/2, which is likely owing to circuit biasing constraints, the resultant (approximate) single
ended voltage gain, Adv, is
⎤
⎛ k g R ⎞⎡
V
g m1 Rkk
Adv = o2s ≈ ⎜ b1 m1 l ⎟ ⎢
(200)
⎥ .
Vs
⎝ 1 + g m1 Rss ⎠ ⎣ 1 + g m1 ( Rss + 2Rkk ) ⎦
We note that because of resistance Rkk and to the extent that Rl << R/2, the approximate single
ended gain is slightly less than one-half the magnitude of the differential gain of the circuit.
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The design-oriented issues surrounding resistance Rkk, whose only purpose in the network of Figure (6.46), is to route the source currents of transistors M1 and M1a to ground, deserve further exploration. We note in (199), for example, that large Rkk, engenders a small
common mode gain, which we earlier hypothesized as a desirable design target. Recall that a
small common mode gain is tantamount to an appreciable rejection of common mode inputs,
which is especially laudable when such inputs are manifested by undesirable parasitic signals or
other electrical phenomena. We are therefore led to believe in light of the fact that the differential mode gain is independent of Rkk, that the common mode rejection ratio is rendered large if
indeed Rkk is large. We can easily confirm this contention by combining (189) and (199) with
(160) to arrive at a common mode rejection ratio, ρ, of
⎛ k ⎞⎛ R 2 ⎞⎛
A
2g m1 Rkk ⎞
(201)
ρ = dv = ⎜ b1 ⎟ ⎜
⎟ ⎜1 +
⎟ ,
Acv
1 + g m1 Rss ⎠
⎝ kb2 ⎠ ⎝ Rl + R 2 ⎠ ⎝
which advances rejection as rising linearly with Rkk. Unfortunately, there are practical limits as
to how large Rkk can be in the circuit at hand. Specifically, a large Rkk burdens the supply voltage, Vdd, in that independent of its resistance value, Rkk must conduct the sum of currents flowing
through transistors M1 and M1a. For large Rkk, Georgey O. warns us that the resultant potential
drop across Rkk, which must be supplied by voltage Vdd, is commensurately large.
We can, however, get our proverbial cake (large Rkk) and be allowed to eat it too (no
excessive burden imposed on Vdd), by replacing Rkk with an active current sink, as is suggested in
the modified schematic diagram of Figure (6.49). The active current sink in question is forged
by transistor M9, whose gate-source potential is supplied by a constant, and thus signal invariant,
voltage, Vbias2. Because the gate-source voltage of transistor M9 is constant, no gmV controlled
source prevails in the small signal model of M9. Indeed, said model is comprised solely of a
drain-source channel resistance, say ro9. This means that in (201), resistance Rkk is supplanted by
ro9, which, depending on the channel length selected for M9, can be several tens of thousands of
ohms It follows that the common mode rejection ratio, ρ, can be rendered very large. Indeed, if
we continue our previously established precedent of very large channel resistances in the
modified amplifier of Figure (6.49), ρ tends toward its idealized value of infinity. Intuitive support for this contention derives from a casual re-inspection of the common mode half model in
Figure (6.48b). If in this structure, resistance Rkk, which is presently replaced by ro9, tends toward infinity, the source terminal of transistor M1 is left open circuited, which obviously precludes any signal current flow through M1, M2, and the load termination, Rl. With zero current
conducted by Rl, the common mode output response, Vco, is clamped to zero, whence zero common mode gain and correspondingly infinitely large common mode rejection ratio.
In the preceding paragraph, we suggest that channel resistance ro9 can be rendered
significantly larger than the previously utilized passive resistance, Rkk. For reasonable drain currents, a large channel resistance invariably requires a proportionately large channel length, which
in our minds automatically flags potential frequency response issues. But the frequency response
capabilities of transistor M9 are immaterial since for differential mode, the circuit node to which
the drain of M9 is connected is a virtual ground. And it should be noted from (162) that for the
very large common mode rejection ratio bred by the presumably large channel resistance of M9,
differential operation is the only operational mode of consequence. A final noteworthy point is
that unlike the electrical ramifications of a large passive resistance, Rkk, a large ro9 does not require a large drain to source voltage on M9. To be sure, we require M9 to operate in saturation in
order to achieve large channel resistance. But saturation requires only that the drain-source voltage of transistor M9, which effectively replaces the original potential drop across Rkk, be slightly
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larger than its drain saturation level. This saturation voltage, which is nominally the difference
between voltage Vbias2 and the M9 threshold potential, can be quite small if the gate aspect ratio
of transistor M9 is chosen large.
+Vdd
Rl
M3
Vo1
R
Rl
M7
Vy1
M4
Vo2
Vy2
M2
Vbias1
M3a
M2a
Rout
M4a
C1
C1
M8
M1
M1a
C2
Rs
Rin
Rb
Rss
Rss
Rb
Rs
M5
+
Vs
−
Vbias2
M9
M6
Figure (6.49). Modified version of the balanced differential amplifier in Figure (6.46). In this version,
resistance Rkk in Figure (6.46) is replaced by an active current sink formed by transistor
M9 and its gate source bias voltage, Vbias2.
6.6.4. DIFFERENTIAL TO SINGLE ENDED CONVERTER
In Section (6.1), we pointed out that the differential output response of a balanced
differential amplifier is divorced of a common mode signal component regardless of the magnitude of the common mode rejection ratio of the amplifier. Extracting an amplifier output response in a strictly differential form is therefore appealing from the standpoint of obliterating
common mode responses that result from undesirable electrical phenomena that couple to the
input port of a balanced pair. But in communication circuits and a multitude of other system
applications, the inability of a differential output response to maintain a common ground between amplifier input and output ports is generally an undesirable topological feature. The
differential to single ended converter, or DSEC, addresses this problem by essentially converting
the ungrounded differential output signal of a balanced pair to a single ended output signal. As is
abstracted in Figure (6.50), the ungrounded differential output, AdVdi, of the balanced pair serves
as the input to the DSEC, which processes this input to generate a single ended output response,
Vods, which is proportional to its differential input. The constant of proportionality, Ads, of the
DSEC is effectively its voltage gain, where it is understood that the magnitude of Ads can be one,
less than one, or greater than one. In most cases, we opt for a DSEC gain that is near one in order to discourage the DSEC from significantly deteriorating the 3-dB bandwidth of the balanced
amplifier. In the subject diagram, voltages Vdi and Vci and parameters Ad and Ac have their usual
differential circuit and system technology connotations.
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AcVci+
Balanced
Differential
Amplifier
+
−
−
+
+
AdVdi
−
AdVdi
AcVci −
2
Vods
= Ads AdVdi
Vdi
2
Vci
+
Vdi
2
Rs
AdVdi
2
−
Rs
J. Choma
Figure (6.50). Conceptual illustration of the use of a differential to single ended converter in conjunction with a balanced differential amplifier.
+Vdd
M2a
M2
Cl
Vods
M1
M1a
Rs
AdVdi
2
+
Rs
Vbias
−
−
M3
+
+
Rl
AdVdi
2
VQ+AcVci
−
Figure (6.51). Simplified schematic example of a differential to single ended converter realized in CMOS technology.
Figure (6.51) offers a basic CMOS realization of a differential to single ended converter. Included in the common mode signal generator, AcVci, is a bias voltage, VQ. This standby
voltage prevails at the output ports of the predecessor balanced stage and is exploited to bias
transistors M1 and M1a in the DSEC. All transistors in the DSEC operate in their saturation
domains, M1 and M1a are matched pairs, and likewise, M2-M2a are matched transistors. Although not shown explicitly, the bulk terminals of all n-channel transistors are presumed to be
returned to signal ground, while the bulk terminals of all PMOS devices are connected directly to
the power line voltage, +Vdd. The DSEC input signal voltages, (AcVci+AdVdi/2), which is applied
to the gate of transistor M1, and (AcVci−AdVdi/2), which activates the gate terminal of transistor
M1a, are the single ended Thévenin output signal voltages of the preceding balanced amplifier.
The source resistances, Rs, in Figure (6.51), represent the single ended output port resistances of
the differential driver whose ungrounded differential voltage response is to be converted linearly,
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to a single ended output response. This output response is denoted as the voltage, Vods, which
appears across load resistance Rl. Since the load resistance is capacitively coupled to the DSEC
output port, no static voltage is established across resistance Rl, whence the output response contains only a signal component. We assume that capacitance Cl is chosen large enough to enable
its behavior as a short circuit for all signal frequencies of interest. In the subject figure, this output port is taken at the drain of transistor M2a, which mirrors the current that flows through the
diode-connected device, M2. In turn, the M2-M2a mirror is driven by the current output signals
of M1 and M1a.
Because the load imposed on transistor M1 differs from the load imposed on M1a, the
network in Figure (6.51) is not a balanced configuration. However, if we partition the M1-M1a
pair from the load subcircuit comprised of M2, M2a, and the capacitively coupled load resistance
for the purpose of determining the short circuit signal currents say In1 and In2, we can produce the
balanced configuration in Figure (6.52a). We have removed voltage VQ from this input subcircuit because of our present focus on exclusively small signal short circuit current responses. Because the subcircuit at hand is balanced, currents In1 and In2 are expressible in terms of their
stereotypical common mode and differential components, Icn1 and Idn1, respectively, as
I
I n1 = I cn1 + dn1
2
,
(202)
I dn1
I n2 = I cn1 −
2
where in concert with the differential network theory propounded earlier, Icn1 is understood to be
directly proportional to common mode input signal, Vci, and independent of differential mode
input signal, Vdi. Analogously, current Idn1 is independent of Vci and directly proportional to Vdi.
Figure (6.52b) is the pertinent differential mode half circuit equivalent of the topology
in Figure (6.52a), where we have exploited (202) to symbolize the signal drain current in M1 as
Idn1/2. In this half circuit, the electrical centroid node to which the current sink forged by
transistor M3 is connected is dutifully replaced by a virtual ground. Since M1 in this half circuit
reduces to a simple common source amplifier that is operated without source degeneration, we
know that
I dn1
⎛AV ⎞
= gm1 ⎜ d di ⎟ ,
(203)
2
⎝ 2 ⎠
while the associated Thévenin resistance is the channel resistance, ro1, of transistor M1 (and
M1a). Naturally, gm1 in this expression is the forward transconductance of transistor M1 (and
M1a). The resultant differential mode Norton equivalent circuit of the output port for the structure in Figure (6.52a) appears in Figure (6.52d). We observe the current direction of the signal
current source, Idn1/2 in M1a, is source to drain, as opposed to the conventional drain to source
polarity. This change of current direction is warranted by the fact that for differential mode, the
gate-source signal drive for transistor M1a is −Vdi/2 whereas for transistor M1, it is +Vdi/2.
In contrast, the common mode Norton equivalent circuit of the output port in Figure
(6.52a) is submitted as Figure (6.52e). This model derives from the relevant common mode half
circuit offered in Figure (6.52c). The centroid node to which the drain of transistor M3 in Figure
(6.52a) is incident is no longer the short circuit observed in the differential mode half circuit.
Instead, this node is returned to signal ground through a resistance of twice the M3 channel resistance, ro3. Recall that twice resistance value is germane to this centroid-ground path since both
transistors M1 and M1a conduct common mode signal currents, but only half the M1-M1a
Ming Hsieh Department of Electrical Engineering
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Canonic Analog MOS Cells
J. Choma
subcircuit is drawn in the common mode half circuit topology. In view of the fact that transistor
M1 in Figure (6.52c) is a simple common source amplifier operated with resistive source
degeneration in the amount of 2ro3, we perceive a common mode signal drain current, Icn1, of
In1
In2
M1
Idn1 /2
M1a
M1
Rs
AdVdi
2
Rs
+
Vbias
−
M3
−
+
+
Rs
AdVdi
2
AdVdi
2
+
−
AcVci
−
(a).
(b).
Drain
Of M1
Icn1
Drain
Of M1a
Idn1
2
ro1
Idn1
2
ro1
Icn1
Roc
M1
Rs
+
(d).
AcVci
2ro3
−
Drain
Of M1
Drain
Of M1a
Icn1
(c).
Roc
(e).
Figure (6.52). (a). Circuit used to determine the Norton equivalent output currents of the M1-M1a
differential pair in the differential to single ended converter of Figure (6.51). (b). Differential mode half circuit of the network in (a). (c). Common mode half circuit of the network in
(a). (d). Differential mode Norton equivalent output port circuit for the balanced circuit in
(a). (e). Common mode Norton equivalent output port circuit for the balanced circuit in (a).
⎛
⎞
g m1
I cn1 = ⎜
⎟ AcVci .
+
1
2g
r
m1
o3
⎝
⎠
Ming Hsieh Department of Electrical Engineering
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The Thévenin shunt resistance, which we represent as Roc in Figure (6.52e), derives from (16)
and (17), where in those two relationships, gm is gm1, the transconductance of transistor M1, ro is
ro1, the channel resistance of M1, bulk transconductance parameter λb is λb1, and resistance Rss is
2ro3. Accordingly,
Roc = 2ro3 + ⎡⎣1 + 2 ( 1 + λb1 ) gm1ro3 ⎤⎦ ro1 ≈ 2 ( 1 + gm1ro1 ) ro3 .
(205)
The upshot of these two disclosures is the common mode equivalent circuit postured in Figure
(6.52e).
The small signal performance characteristics of the DSEC in Figure (6.51) can now be
evaluated with the aid of the Norton models just developed for the input transistor pair, M1-M1a.
We shall initiate this evaluation in an intuitive sense by adopting the simplifying approximations
of infinitely large channel resistances in all transistors and zero bulk transconductances in M1
and M1a. With channel resistances presumed infinitely large, ro1 in Figure (6.52d) and Roc in
Figure (6.52e) are infinity. As a result, the differential and common mode Norton models can be
coalesced into a single modeling cell, whence we arrive at the small signal representation shown
in Figure (6.53). In this model, the power supply voltage, Vdd, is set to zero to reflect the attention focused on only small signal circuit characteristics. Additionally, capacitance Cl is replaced
by a short circuit in that its capacitance value is selected to emulate a short circuited branch element for all signal frequencies of interest. By inspection of the subject model, we see that the
current delineated as I2s is
M2
M2a
I2as
Ios
Vods
Ids
I2s
Icn1
Idn1
2
Icn1
Idn1
2
Rl
Figure (6.53). Signal schematic diagram of the differential to single ended
converter postured in Figure (6.51). The driving circuit for
the converter has been replaced by its Norton equivalent
model. The signal schematic diagram exploits the assumptions of infinitely large channel resistances and zero bulk
transconductances in all transistors.
I
I 2s = I cn1 + dn1 .
(206)
2
This current flows through the drain of transistor M2. Since transistors M2 and M2a are matched
devices possessed of identical gate aspect ratios and since the source-gate voltages applied to
these two PMOS devices is the same, current I2as mirrors current I2s; that is,
I
I 2as = I 2s = I cn1 + dn1 .
(207)
2
Now current Ids is
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J. Choma
I
I ds = I cn1 − dn1 .
(208)
2
It follows that the current, Ios, conducted by the load resistance, Rl is
I
I
⎛
⎞ ⎛
⎞
I os = I 2as − I os = ⎜ I cn1 + dn1 ⎟ − ⎜ I cn1 − dn1 ⎟ = I dn1 ,
(209)
2 ⎠ ⎝
2 ⎠
⎝
which is independent of the common mode current component generated in the drain circuits of
transistor M1 and M1a. Since common mode responses are inherently (at least in the idealized
sense of infinitely large channel resistances) absent in the load resistance, we can dispute the
necessity of transistor M3, as opposed to the deployment of a simple resistance connected from
the source terminals of M1-M1a and ground. In particular, (204) confirms that the invariably
large channel resistance, ro3, of transistor M3 substantially attenuates the common mode current
response for a given common mode input voltage signal. But since common mode currents
disappear at the DSEC load, a reasonable resistance supplanting M3 arguably suffices. Continuing with (209), (203) allows us to write
I os = I dn1 = gm1 AdVdi ,
(210)
whence an output signal voltage, Vods, of
(211)
Vods = I os Rl = g m1Rl ( AdVdi ) ,
which confirms a single ended output voltage response that is proportional to the ungrounded
voltage, AdVdi, developed differentially across the output terminals of the predecessor balanced
differential amplifier. Equation (211) suggests, with the help of the diagram in Figure (6.50),
that the apparent single ended output to differential input voltage gain, Ads, of the DSEC is
V
Ads = ods = g m1Rl .
(212)
AdVdi
The foregoing results are, of course, only approximate in light of the extreme
approximations on which they are predicated. In order to investigate the small signal
characteristics of the DSEC more definitively, we shall need to account for finite, but nevertheless large, channel resistances and nonzero bulk transconductances in the transistors, M1 and
M1a. Because the Thévenin resistances of the differential mode and common mode Norton
equivalent circuits for the M1-M1a driver differ, we shall also be forced to exploit superposition
theory with respect to the differential and common mode excitations applied to the DSEC.
To the foregoing end, we begin with differential mode considerations and advance the
small signal model depicted in Figure (6.54a). In this low frequency model, which assumes that
coupling capacitance Cl functions as a short circuit for all signal frequencies of interest, diodeconnected transistor M2 is simply replaced by its effective terminal resistance, which our earlier
work suggests is ro2/(1+gm2ro2). Transistor M2a, which is matched to M1, is modeled in the
traditional fashion by a dependent source, gm2V, in shunt with channel resistance ro2, where we
understand voltage V is the gate-source signal voltage applied to M2a. As it turns out, voltage V
is also the signal voltage dropped as indicated across the effective resistance that represents the
small signal dynamics of diode-connected transistor M2. The signal drive circuit for the drain
terminals of M2 and M2a derives directly from Figure (6.52d). An inspection of the model in at
hand reveals
⎡
⎡
⎤
⎛
⎞ ⎤ AdVdi
I
ro2
ro2
V = − dn1 ⎢ ro1
,
(213)
⎥ = − gm1 ⎢ ro1 ⎜
⎟⎥
2 ⎣
1 + g m2 ro2 ⎦
⎢⎣
⎝ 1 + g m2 ro2 ⎠ ⎥⎦ 2
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−
ro2
1+gm2ro2
+
gm2V
V
J. Choma
ro2
Vodd
M1 Drain
Idn1
2
M1a Drain
ro1
Idn1
2
ro1
gm2V
ro2
Rl
(a).
−
ro2
1+gm2ro2
+
V
Vodc
M1 Drain
Icn1
M1a Drain
Roc
Icn1
Roc
Rl
(b).
Figure (6.54). (a). Small signal model of the differential to single ended converter of Figure (6.51) for differential mode input signal excitation. (b). Small signal model of the differential to single ended
converter for common mode input signal excitation. The
capacitance, Cl, in Figure (6.51) is presumed to emulate a short
circuit for the signal frequencies of immediate interest.
where we have made use of (203). Since resistances Rl, ro1, and ro2 are all connected in parallel
with one another, the output voltage, Vodd, due exclusively to differential mode excitation of the
DSEC must satisfy
Vodd
I
+ gm2V − dn1 = 0 .
(214)
2
Rl ro1 ro2
If we substitute (213) and (203) into this expression, we arrive at
⎧⎪
⎡
⎛
⎞ ⎤ ⎫⎪ AdVdi
ro2
(215)
Vodd = g m1 Rl ro1 ro2 ⎨1 + g m2 ⎢ ro1 ⎜
.
⎟⎥ ⎬
⎢⎣
⎝ 1 + g m2 ro2 ⎠ ⎥⎦ ⎪⎭ 2
⎪⎩
Although this result is algebraically cumbersome, it is amenable to engineering interpretation,
subject to a few reasonable approximations. First, it is likely that load resistance Rl is small
enough to satisfy the inequality, Rl << (ro1||ro2). Second, for reasonably large channel resistances,
⎛
⎞
ro2
1
1
≈
.
ro1 ⎜
(216)
⎟ ≈ ro1
+
1
g
r
g
g
m2 o2 ⎠
m2
m2
⎝
(
)
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Canonic Analog MOS Cells
J. Choma
We can therefore see that the output voltage due solely to differential input signals is given
approximately as
AV
Vodd ≈ gm1Rl ( 1 + 1) d di = gm1Rl ( AdVdi ) ,
(217)
2
which reflects the approximate output voltage relationship deduced as (211).
The common mode small signal model of the DSEC system is essentially the same as
its differential mode partner, save for the fact that the driver circuit is comprised of the model
shown in Figure (6.52e). An analysis similar to the one just undertaken gives for the common
mode component, Vodc, of DSEC output voltage,
⎡ gm1 Rl Roc ro2 ⎤ ⎧⎪
⎫⎪
⎡
⎛
⎞⎤
ro2
⎥ ⎨ gm2 ⎢ Roc ⎜
Vodc = ⎢
(218)
⎟ ⎥ − 1⎬ AcVci ,
⎢⎣ 1 + 2gm1ro3 ⎥⎦ ⎪⎩
⎢⎣
⎝ 1 + gm2 ro2 ⎠ ⎥⎦
⎪⎭
where resistance Roc is recalled from (205). For large channel resistances, which makes Roc very
large,
⎛ R ⎞⎛
⎞
⎛
⎞
1
Rl
(219)
Vodc ≈ − ⎜ l ⎟⎜
⎟ AcVci ≈ − ⎜
⎟ AcVci ,
⎝ 2ro3 ⎠⎝ 1 + g m2 Roc ⎠
⎝ 2g m2 ro3 Roc ⎠
which is invariably a very small voltage, especially if the preceding stage is characterized by a
low common mode voltage gain, Ac. The net output response, which is almost assuredly dominated by the component precipitated by differential input signals, is
⎛
⎞
Rl
(220)
Vods = Vodd + Vodc = g m1Rl ( AdVdi ) − ⎜
⎟ AcVci .
⎝ 2g m2 ro3 Roc ⎠
(
)
6.7.0. REFERENCES
[1].
[2].
[3].
[4].
[5].
[6].
[7].
[8].
[9].
[10].
R. L. Geiger and E. Sánchez-Sinencio, “Active Filter Design Using Operational Transconductance Amplifiers: A Tutorial,” IEEE Circuits and Devices Magazine, pp. 20-32, March 1985.
D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
Inc., 1997, chap. 15.
T. Bakken and J. Choma, “Gyrator-Based Synthesis Of Active On Chip Inductances,” Journal
of Analog Integrated Circuits And Signal Processing, vol. 34, pp. 171-181, March 2003.
R. Duncan, K. Martin, and A. Sedra, “A 1 GHz Quadrature Sinusoidal Oscillator,” Proceedings
of the Custom Integrated Circuits Conference, pp. 91-94, 1995.
Y. Chang, J. Choma, Jr., and J. Wills, “A 900 MHz Active CMOS LNA with Bandpass Filter,”
1999 Southwest Symposium On Mixed-Signal Design, Tucson, Arizona, April 11-13, 1999.
Y. Chang, J. Choma, Jr., and J. Wills, “The Design of CMOS Gigahertz–Band Continuous–
Time Active Lowpass Filters with Q-Enhancement,” 1999 Great Lakes Symposium on VLSI,
Ann Arbor, Michigan, March 4-6, 1999.
Y. H. Cho, S. C. Hong and Y. S. Kwon, “A Novel Active Inductor and Its Application To
Inductance-Controlled Oscillator,” IEEE Transactions on Microwave Theory and Techniques,
vol. 45, pp. 1208-1213, August 1997.
J. Choma and W-K Chen, Feedback Networks: Theory and Circuit Applications. Singapore:
World Scientific Press, 2007, chaps. 4 and 5.
L. J. Giacoletto, Differential Amplifiers. New York: Wiley-Interscience, 1970.
S. A. Witherspoon and J. Choma, Jr., “The Analysis of Balanced Linear Differential Circuits,”
IEEE Transactions on Education, vol. 38, pp. 40-50, February 1995.
Ming Hsieh Department of Electrical Engineering
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