Chapter 5:
“The Processor: Datapath and Control”
Part One, The Single
Cycle Processor
1
The Performance Big Picture
•
•
Execution Time = Insts * CPI * Cycle Time
Processor design (datapath and control) will
determine:
Computer
- Clock cycle time
- Clock cycles per
instruction
Input
Control
Memory
Processor
Datapath
•
Output
Starting today:
- Single cycle processor:
• Advantage: CPI = 1
• Disadvantage: long cycle time
Execute an
entire instruction
2
What parts of MIPS?
•
We’ll cover a subset of MIPS
- Memory instructions
- Arithmetic/Logical (and just a subset of these, but
you should be able to figure out how to add many of
them)
- BEQ and J
- Basic load/store architecture with these steps:
•
•
•
•
•
Read PC and Fetch Inst
Read Registers
Do Operation
Write memory/registers
Repeat
.. but you should be able to extend what we do to handle
more of the instructions
3
The MIPS core subset
•
R-type
31
26
op
6 bits
- add rd, rs, rt
- sub, and, or, slt
•
LD/ST
31
- lw rt, rs, imm
- sw rt, rs, imm
•
BRANCH:
26
op
6 bits
31
26
op
6 bits
- beq rs, rt, imm
21
rs
5 bits
16
rt
5 bits
11
rd
5 bits
6
shamt
5 bits
1. Read registers rs and rt
2. Feed them to ALU
3. Update register file
21
rs
5 bits
0
funct
6 bits
16
rt
5 bits
0
immediate
16 bits
1. Read register rs (and rt for store)
2. Feed rs and immed to ALU
3. Move data between mem and reg
21
rs
5 bits
16
rt
5 bits
0
displacement
16 bits
1. Read registers rs and rt
2. Feed to ALU to compare
3. Add PC to disp; update PC
4
Register Transfer Language (RTL)
•
Is a mechanism for describing the
movement of data between storage
elements
- Gives us a precise way to describe various
actions of our instructions
• May be more than 1 RTL statement per inst
- R[3] <= R[5] + R[7]
- PC <= PC + 4
- R[rd] <= R[rs] + R[rt]
5
The basic design algorithm
(after you have the ISA) – you’ll do
this for your own ISA for 141L
•
Build the datapath on the whiteboard
- one by one,
simulate each instruction
on the current datapath “sketch”:
- make sure it is workable
- if not, modify datapath
•
Design the control logic
- one by one,
simulate each instruction on the current
datapath + control logic:
- make sure it is workable
- if not, modify control or datapath
6
The Instruction Execution Cycle
Instruction
Fetch
Instruction
Decode
Obtain instruction from program storage
Determine required actions and instruction size
Operand
Fetch
Locate and obtain operand data
Execute
Compute result value or status
Result
Store
Deposit results in storage for later use
Next
Instruction
Determine successor instruction
7
The MIPS core subset
•
R-type
31
26
op
6 bits
- add rd, rs, rt
- sub, and, or, slt
•
LD/ST
31
- lw rt, rs, imm
- sw rt, rs, imm
•
BRANCH:
26
op
6 bits
31
26
op
6 bits
- beq rs, rt, imm
21
rs
5 bits
16
rt
5 bits
11
rd
5 bits
6
shamt
5 bits
1. Read registers rs and rt
2. Feed them to ALU
3. Update register file
21
rs
5 bits
0
funct
6 bits
16
rt
5 bits
0
immediate
16 bits
1. Read register rs (and rt for store)
2. Feed rs and immed to ALU
3. Move data between mem and reg
21
rs
5 bits
16
rt
5 bits
0
displacement
16 bits
1. Read registers rs and rt
2. Feed to ALU to compare
3. Add PC to disp; update PC
8
R-Format/ Lw/ Sw/ BEQ
PCSrc
Add
4
RegWrite
Instruction [25–21]
PC
Read
address
Instruction
[31–0]
Instruction
memory
Instruction [20–16]
1
M
u
Instruction [15–11] x
0
RegDst
Instruction [15–0]
Read
register 1
Read
register 2
Read
data 1
Read
Write
data 2
register
Write
Registers
data
16
Sign 32
extend
Shift
left 2
ALU
Add result
1
M
u
x
0
MemWrite
ALUSrc
1
M
u
x
0
ALU
control
Zero
ALU ALU
result
MemtoReg
Address
Write
data
Read
data
Data
memory
1
M
u
x
0
MemRead
Instruction [5–0]
ALUOp
RRR
lw
bne
ALUsrc
1
0
1
ALUop
tbd
tbd
cmp
MemRead MemWrite
0
0
1
0
0
0
MemToReg RegDst RegWrite PCsrc
1
0
0
1
1
1
19
1
X
X
0 “Zero”
•
(Derivation of Datapath and Control on
Blackboard)
10