JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 19, NO. 6, DECEMBER 2010
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An Ultra Compact Integrated Front End for Wireless
Neural Recording Microsystems
Gayatri E. Perlin, Member, IEEE, and Kensall D. Wise, Life Fellow, IEEE
Abstract—The design and performance of an integrated front
end for high-channel-count neural recording microsystems is presented. This front end consists of a 3-D micromachined microelectrode array, realized using a new architecture that allows
simple and rapid microassembly. A 64-site 3-D multiprobe, realized using the new architecture, interfaces with tissue volumes
of less than 0.01 mm3 and has a footprint of 1 mm2 . For amplification, filtering, and buffering of the recorded neural signals,
a custom signal-conditioning circuit provides high gain (60 dB),
low noise (4.8 μVrms ), and low power (50 μW) in an area of
0.098 mm2 . In addition, this circuitry implements bandwidth
tuning, offset compensation, and wireless gain programmability.
This new approach to system integration uses a microfabricated
parylene overlay cable to electrically interconnect the 3-D array
and signal-conditioning circuitry. In vivo results obtained using
this integrated microsystem front end in its most compact form
are presented.
[2009-0238]
Index Terms—Implantable microsystems, microassembly, microsystem integration, neural prostheses.
I. I NTRODUCTION
N
EURAL PROSTHESES, such as deep brain stimulation
(DBS) and cochlear implants, have dramatically improved the quality of life for tens of thousands of individuals
with severe neurological disorders. To date, more than 40 000
people worldwide have benefited from Medtronic’s DBS implants for Parkinson’s disease, essential tremor, and dystonia
[1], and according to the Food and Drug Administration, more
than 188 000 cochlear implants are in use worldwide. The remarkable results in tremor suppression [2] and restored hearing
[3] obtained with current technologies are motivating the development of more advanced implantable prostheses for treating
these and many other debilitating neurological disorders. While
tremor suppression and restoring hearing primarily involve
neural stimulation using externally generated electrical pulses,
other applications also require the ability to monitor intrinsic
Manuscript received October 2, 2009; revised March 17, 2010 and
August 18, 2010; accepted August 30, 2010. Date of publication
November 10, 2010; date of current version November 30, 2010. This work
was supported in part by the Engineering Research Centers Program of the
National Science Foundation under Award EEC-9986866 and in part by a gift
from Ms. P. V. Anderson. Subject Editor C. Liu.
G. E. Perlin is with the Advanced Imaging Technology Group,
Massachusetts Institute of Technology Lincoln Laboratory, Lexington, MA
02420-9108 USA (e-mail: gayatri.perlin@ll.mit.edu).
K. D. Wise is with the Center for Wireless Integrated Microsystems, Department of Electrical Engineering and Computer Science, University of Michigan,
Ann Arbor, MI 48109-2122 USA (e-mail: wise@umich.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JMEMS.2010.2082496
neural activity (recording). For example, in severe epilepsy, a
closed-loop wireless microsystem that continuously monitors
neuronal activity to identify the onset of a seizure might be
realized, and electrical stimulation or in situ drug delivery
could then be used to prevent its spread into a full-blown
seizure. In paralysis, the recorded neural activity that captures
command signals from the motor cortex could be transmitted
around the damaged spinal cord to restore functionality to
the limbs. Wireless recording microsystems are also critical
for fundamental neuroscience to allow neural activity to be
recorded from hundreds of neurons simultaneously in freely
behaving subjects.
Many challenges, both technological and physiological, remain for realizing sophisticated miniature wireless devices (microsystems), both to support fundamental work in neuroscience
aimed at better understanding the brain and its disorders and
to treat their symptoms [4]. Implant size, high channel count,
low power consumption, wireless interface, micropackaging,
biocompatibility, surgical techniques, and control algorithms
are among the challenges yet to be overcome.
This paper presents several advances in microtechnology developed for a wireless neural recording microsystem [5]. A new
electrode configuration for forming 3-D arrays is discussed, and
a custom-designed integrated circuit (IC) for neural-signal conditioning is described. Finally, a new microsystem integration
and packaging technique is presented, and the integrated front
end is demonstrated in vivo.
II. W IRELESS N EURAL R ECORDING M ICROSYSTEMS
A fully implantable wireless neural recording microsystem
consists of four main electronic blocks, as shown in Fig. 1.
Neural signals in the form of extracellular action/field potentials are recorded using penetrating microelectrodes. Actionpotential (i.e., spike) amplitudes typically range from 50 to
500 μV with a bandwidth from 100 Hz to 10 kHz. Field (i.e.,
slow-wave) potentials have amplitudes that range from 1 to
5 mV, with a frequency content from less than 10 Hz to about
100 Hz. Neuroscience and neural prostheses primarily make
use of action potentials, but field potentials are also important
in many applications. Penetrating electrodes can be as simple
as an insulated metal wire or a bundle of such wires that form
a multichannel electrode array. More sophisticated microelectrodes based on silicon IC technology were first developed
in the late 1960s [6], [7]. Following this work, a high-yield
fabrication process was developed, resulting in precise and
reproducible devices in a wide variety of 2-D configurations
[8]. For controlled experiments in neurophysiology and neural
1057-7157/$26.00 © 2010 IEEE
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 19, NO. 6, DECEMBER 2010
Fig. 1. Diagram of the key electronic blocks of an implantable neural recording microsystem.
prostheses, it is now thought necessary to record from hundreds
of channels simultaneously, spanning 3-D tissue volumes [9].
Three-dimensional interfaces formed by microassembling thinfilm planar 2-D arrays have been demonstrated [10]–[12]; however, creating such 3-D arrays has remained a challenge since
these previously reported microassembly approaches remain
tedious. The resulting arrays are relatively large and can be
fragile. The technology for realizing 3-D microelectrode arrays
presented in Section III of this paper results in lower profile
more compact microstructures that facilitate implantation while
being robust and relatively easy to assemble.
The signal-conditioning circuitry in Fig. 1 typically performs
the following functions: 1) selection of particular recording
sites to be monitored from among a larger number of sites on
the probe; 2) amplification of the neural signals from those
sites prior to subsequent processing; 3) bandpass filtering of
the signals consistent with the neural activity to be monitored
(from ≤ 1 Hz to 10 kHz); and 4) (sometimes) multiplexing the
channel outputs to reduce the external lead count of the system
front end. In order to buffer the microvolt signals from leakage
and noise on the output cable and reduce the number of off-chip
input/output connections, monolithic integration of the signalconditioning circuitry on the back end of the microelectrode
array (also referred to as an active probe) is the best longterm solution. Active recording probes have been demonstrated
in MOS technologies [13]–[16] but have typically resulted in
relatively large circuit areas due to the feature sizes used in
academic laboratories. To reduce the height of the implant
above the cortical surface from a few millimeters to less than
1 mm, folding back-end technology has been demonstrated
[17]. However, such structures have still occupied more lateral
surface area than is desirable for high-channel-count wireless
microsystems since that area occludes the view of the cortical
surface and may lead to increased tissue reaction.
Neural recording circuits realized as application-specific ICs
(ASICs) have been of interest in order to utilize the submicrometer features that are available through commercial
foundries [18]–[23]. Section IV of this paper presents a signalconditioning ASIC for an implantable 64-channel wireless
neural recording microsystem [5]. The neural amplifier designed as part of this work offers high gain and robust in vivo
operation. The performance of this amplifier is compared with
previously reported amplifiers that have used a similar architecture [24]–[27].
The first two blocks of Fig. 1 constitute the front end
of a neural recording microsystem. The next two blocks
consist of integrated circuitry for signal processing and wireless telemetry. The signal-processing chip performs analogto-digital conversion, separation of the neural spike activity
from background noise (compressing the data and reducing the
required transmission bandwidth), and forming the digitized
data into packets for transmission. The 64-channel neuralsignal processor used in the present microsystem has two modes
of operation [28]. The scan mode allows parallel detection of
neural spikes on all 64 channels using per-channel programmable biphasic threshold levels. The detected spikes are tagged
with their channel addresses and formed into serial data words
for transmission. If the entire neural signal is of interest, the
monitor mode can be used to sample two channels with an 8-b
resolution, forming them in similar data packets for wireless
transmission to the external world. The final block is the
telemetry chip, which wirelessly couples the power and bidirectional data into and out of the implant. The telemetry chip
designed for this microsystem [29], [30] receives inductively
coupled frequency-shift-keying-modulated clock and command
data carried by an RF signal switching between 4 and 8 MHz.
The received energy is used to generate regulated power for the
implanted microsystem. The recorded neural activity is modulated using on–off keying (OOK) and wirelessly transmitted
out of the implant using an 80–160 MHz OOK-modulated
carrier.
The various components of this microsystem must be physically and electrically integrated in a suitable package for
handling and implantation. Three-dimensional integration techniques using flip-chip bonding [31] or through-wafer interconnect technology [32] are a possibility. However, neural-implant
applications require a very low vertical rise above the cortical
surface to allow the dura covering the brain to be replaced after
surgery and permit the implant to move freely with the brain
and avoid becoming attached to the skull. Laterally placed components can limit the vertical rise but require a relatively large
footprint. Section V of this paper presents a new approach to
microsystem integration that allows components to be densely
spaced.
PERLIN AND WISE: ULTRA COMPACT INTEGRATED FRONT END FOR WIRELESS NEURAL RECORDING MICROSYSTEMS
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Fig. 2. Conceptualization of a two-module architecture for a fully implantable
neural recording microsystem where the implanted electrode array rests on the
cortical surface and is connected by a flexible cable to the electronic package
placed on the skull.
The conceptualization of a fully implantable wireless neural
recording microsystem described earlier is shown in Fig. 2.
In this diagram, the penetrating electrode array is implanted,
resting on the cortical surface, while flexible cables connect
the electronic package placed on the skull, just below the
skin. There are several advantages to this two-module architecture. First, the size requirements of the front end are the
most stringent since it needs to be placed in brain tissue,
while the size of the subcutaneous electronic module can be
more relaxed. Second, by placing the electronic module on
top of the skull, the power needed for wireless transmission
can be greatly reduced. Third, physically separating the highimpedance front-end electrodes from the RF link reduces the
potential for electromagnetic interference in the neural-signal
path, a challenge not insignificant in the stacked flip-chip approaches [31].
III. T HREE -D IMENSIONAL A RRAYS
OF M ICROELECTRODES
The previous approach to the microassembly of 3-D microelectrode arrays [10]–[12] has involved inserting the shanks
of each 2-D planar probe into corresponding holes in a thin
(∼15-μm-thick) silicon platform (formed using a diffused
boron etch stop). Multiple 2-D probes are secured in parallel
on the platform with orthogonally fitted comblike spacers, also
defined by boron diffusion. To form electrical lead transfers
from the probe to the platform, each 2-D probe is designed
with lateral wings carrying electroplated gold lead tabs. Prior
to the insertion of each probe into the platform, the lead tabs
are bent orthogonal to the probe, and once the probe is in
place on the platform, they are ultrasonically bonded to corresponding pads on the platform. These wings typically extend to
several hundred micrometers on each side beyond the shanks,
making the overall device significantly larger than the tissue
area being instrumented. For active probes having few transfer
Fig. 3. Diagram of a new approach to the microassembly of compact 3-D
arrays of neural microelectrodes. (a) Top view of the silicon platform. (b) Cross
section of the platform with an assembled probe. (c) Two views of an assembled
3-D neural-probe array.
leads, the wings are manageable, but for passive probes having
many sites/leads, they are excessively wide. In addition, the
microassembly procedure is tedious and fragile, limiting the
number of such arrays that can be provided to the neuroscience
community.
A. New Three-Dimensional Array Architecture
In the new 3-D array architecture shown in Fig. 3, multishank 2-D probes (with or without monolithically integrated
circuitry) are designed with electroplated gold lead-transfer
tabs that extend off the back end of the structure, eliminating
the lateral wings used in past designs [10]–[12]. The silicon
platform uses a thicker substrate [e.g., the full wafer thickness
(∼ 500 μm)] rather than a thin boron-diffused structure used
in past approaches [10]–[12]. Parallel slots are formed in the
platform with an internal ledge, created by using a two-sided
deep reactive ion etch (DRIE) that countersinks and holds the
back end of each 2-D probe, as shown in Fig. 3(b). Careful
design of the slot width creates a natural stabilization mechanism, preventing the probe back end from wobbling in the slot.
A single slot opening is used rather than perforated holes for
each shank, simplifying fabrication and assembly. The probe
tabs are orthogonally bent onto the surface of the platform
where they are ultrasonically bonded to corresponding pads,
creating a planar array of lead transfers. An important feature
of this architecture is that no elements protrude above the
platform, allowing for high-yield rapid multitab bonding and
other advantages in system integration and device implantation
that will be discussed in later sections.
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This architecture allows for a high degree of flexibility
and control of design parameters. For any given geometric
configuration of recording sites, the appropriate 2-D probes can
be designed and then the platform can be configured to fit the
probes at the appropriate spacing. The size of the platform is
largely determined by the number of shanks, their width, and
their spacing, with very little overhead.
B. Platform Fabrication
To demonstrate this new architecture, a 64-channel 3-D array
using four 16-channel 2-D probes has been designed. Each 2-D
probe includes four shanks, with each shank measuring 4 mm
long, 60 μm wide (including any lateral boron diffusion), and
spaced at a 150-μm pitch. Four recording sites are spaced
100 μm apart along the length of each shank. The total width
of the probe back end is 600 μm, including a 50-μm overhang
beyond the shank on each side to support the probe in the platform. Given this width of the back end, 16 gold electroplated
lead-transfer tabs are formed at a pitch of 40 μm (30-μm lead/
10-μm space). A dielectric extension along the back end of the
probe prevents electrical shorting of the tabs to the boron-doped
substrate of the probe back end. The height of the probe back
end, which determines the frontside slot depth in the platform,
is 300 μm. Although this passive probe (without integrated
circuitry) could be designed with a shorter back end (e.g.,
75 μm, considering the lead fan-out in 3-μm technology),
the taller back end was designed to address the challenges in
platform fabrication. The fabrication of 2-D Michigan microelectrode arrays is a standard process the details of which can
be found elsewhere [33].
The focus here is on the fabrication of the platform given
this 2-D probe design and spacing. The platform fabrication
starts with a double-side-polished 100-mm silicon wafer approximately 500 μm thick. First, silicon dioxide is grown on
the wafer using thermal oxidation at 1100 ◦ C to obtain an oxide
thickness of approximately 1.2 μm. Next, the frontside of the
wafer is metalized with 200 Å of chromium (Cr) and 5000 Å
of gold (Au) and patterned using liftoff to define bonding pads
on the platform. Slot openings and the perimeter of the platform
are defined on the frontside in a single lithography step using
a thick photoresist (∼15 μm) mask. Anisotropic deep reactive
ion etching is used to etch the patterned areas to a depth
corresponding to the height of the probe back end (300 μm
deep in this case). The process wafer is now mounted to a glass
carrier wafer using photoresist. The backside of the process
wafer is then aligned to the frontside and patterned to define the
backside slot and perimeter regions. Again, anisotropic DRIE
is used to etch the patterned regions until the backside etch
reaches the frontside etch (at a depth of 200 μm in this case),
creating a through hole in the slot regions and releasing the
platform from the bulk wafer along its perimeter. Simultaneous etching of the slots and perimeter reduces the fabrication
process to just three lithography steps: bonding-pad patterning,
frontside slot/perimeter etch, and backside slot/perimeter etch
and release. The SEM image in Fig. 4 shows a cross section of
the etched slots. The slot opening was designed to be 25 μm
wide to fit passive probes fabricated in the typical Michigan
Fig. 4. SEM image showing the cross section of DRIE etched slots in the
platform of the 3-D probe array.
probe process. As shown in Fig. 4, the frontside etch depth
is 295 μm, while the remaining wafer thickness was etched
from the backside. The taper toward the bottom of the slot was
calculated to be approximately 2◦ from measurements taken in
the SEM. The key in this process is to ensure that a through
hole is created in the slot region before the device is released
along the perimeter. This can be achieved by designing the two
openings to be equally wide. In this case, a cusp is formed in
the through hole at the point where the backside slot meets
the frontside slot, as shown in the detailed part of Fig. 4.
Although the opening at the meeting point is wide enough to
insert the shanks, this cusp can hinder the insertion of shanks
if design tolerances are too tight. To overcome the formation
of a cusp, the backside perimeter opening can be designed
slightly smaller in width compared with the slot opening. This
allows the backside-slot area to overetch before the perimeter
is released, creating a smoother through hole in the shankpenetration region.
C. Microassembly of Three-Dimensional Arrays
Due to the small dimensions of the devices under consideration, their efficient assembly presents a significant challenge,
which is addressed with a specialized setup. The released platforms, measuring 1 mm × 1 mm × 0.5 mm, must be secured
during the assembly procedure, which includes insertion of
the 2-D probes into the platform followed by tab bonding to
make electrical connections from the probe to the platform. To
secure these platforms, an assembly wafer was micromachined
using a two-mask DRIE process. In the first step, the outline
of the platform was etched approximately 200 μm deep. Then,
a second DRIE etch from the backside of the wafer was used
to produce a single through hole overlapping all slot regions.
The wafer was then diced into approximately 1 cm × 1 cm dies
of silicon (500 μm thick) containing multiple micromachined
mounting regions to form a silicon assembly carrier. Since this
carrier is only 0.5 mm thick, a supporting metal block that
is 5 mm tall was used to clear the shank length (4 mm, in
this work) during assembly. The silicon carrier was secured to
PERLIN AND WISE: ULTRA COMPACT INTEGRATED FRONT END FOR WIRELESS NEURAL RECORDING MICROSYSTEMS
Fig. 5. SEM images of an assembled and bonded probe with 30-μm-wide tabs
(40-μm pitch).
the support block using a silicone elastomer around the edges,
creating an assembly jig. The 3-D array platform was placed
in the corresponding region of the silicon carrier, secured in
place using a dissolvable lacquer (e.g., nail polish or hand
soap) along the perimeter and allowed to harden in place.
Since the silicon carrier is micromachined, multiple platforms
can be assembled simultaneously using this setup. Using this
jig, a three-way micromanipulator with a vacuum pick, and a
stereo microscope, individual 2-D probes were aligned to the
slots in the platform and dropped into place. Following the
insertion of all 2-D probes (four, in this work), a micropipette or
tweezers can be rolled over the surface, simultaneously bending
all tabs onto the bonding pads on the platform. The jig was
then moved to a wire bonder to make electrical connections
using ultrasonic bonding of the gold tabs to the gold bonding
pads. Once bonding and electrical continuity tests have been
completed, the loaded platform can be released in acetone or
water and removed from the jig.
The SEM image of an assembled and bonded probe is shown
in Fig. 5. Each tab here was ultrasonically bonded with a
25-μm bonding tip. The bond quality depends on three main
parameters: the force exerted by the wedge, the power of the
ultrasonic waves, and the duration of the process. A wider
bonding tool with a 60-μm tip was also used to successfully
gang bond two tabs simultaneously, demonstrating the ability
to speed up the assembly process. High-pitch tabs (15 μm)
are also being considered for simultaneous multitab bonding,
enabled with this platform architecture, to make the process
still more efficient. Electrical continuity was verified between
the bonding pads on the platform and the sites on the probe
by placing the shanks into physiological saline and probing
the bonding pad on the platform. Perspective views of a fully
assembled 64-channel 3-D four-probe array having probes on
200-μm centers with 4-mm-long shanks in a platform measuring 1 mm × 1 mm × 0.5 mm are shown on a U.S. penny
and on an index finger in Fig. 6. By themselves, these arrays
are of limited use since bonding individual wire connections to
the platform is impractical. At the minimum, a microfabricated
multilead cable is necessary between the platform and the
outside world, but with passive probes, leakage on that cable
is then a serious concern. Buffering/amplification on the probes
or on/near the platform is critical in order to realize a viable
chronic implant.
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Fig. 6. Photographs of the 64-channel compact 3-D array (platform measures
1 mm × 1 mm with 4-mm-long shanks).
IV. F RONT-E ND S IGNAL -C ONDITIONING C IRCUITRY
A custom-designed IC was implemented to condition the
neural signals recorded by the microelectrode array. This chip
includes 64 parallel channels for the amplification, filtering, and
buffering of the signals and a serial-to-parallel shift register for
programming the amplifier-gain setting using a 6-b command.
Bandwidth tuning is achieved by direct global analog control.
A scalable 0.5-μm CMOS technology was chosen for the chip
(AMI 0.5-μm three-metal two-poly (3M2P) N-well CMOS)
for both the signal-conditioning chip of this work and the
signal processing ASIC [28] so that in future versions, these
circuit blocks could be integrated onto a single chip, reducing
packaging requirements and resulting in a more robust, higher
yield, and smaller system.
The neural recording amplifier on the signal-conditioning
ASIC is designed to provide the following [34]: 1) rejection
of electrode dc polarization arising from the metal–electrolyte
interface (100–500 mV for Au, Pt, Ir) to avoid saturation of the
amplifier; 2) a very low input-equivalent noise (5–10 μVrms
to achieve a minimum SNR of 8 dB using a typical 1–2-MΩ
electrode site); 3) a variable low-frequency cutoff (for
inclusion/rejection of field potentials); 4) a very low power
consumption; and 5) a small die area.
In the past, several techniques have been used to reject dc
offsets at the input of the amplifier. One approach has been
the use of frequency-sensitive feedback networks using an RC
combination at the input to set a low cutoff frequency, where
C is the electrode capacitance (in the range of 50–100 pF
at 100 Hz, and R, in the range of 50–500 MΩ, is realized
using diode/MOS clamps [14], [15], [27], [35]. This technique,
however, is too dependent on electrode impedance to be generally applicable. Capacitive coupling is another technique that
has been used successfully to reject the input dc potentials,
where an integrated capacitor is placed at the input of the
amplifier [24], [25]. More recently, a dc cancellation technique that eliminates the need for area-consuming integrated
capacitors by subtracting the input offset from itself has also
been demonstrated [36]. To achieve low noise, most neural
recording-amplifier designs use large PMOS input devices [24],
[25], [27]. The use of chopper modulation to filter flicker noise
and avoid area-consuming input devices has also been reported
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Fig. 7. Schematic of the programmable-gain neural recording amplifier in open- and closed-loop configurations.
[37]. Variable bandwidth has been implemented by using the
gigaohm resistance provided by biasing feedback transistors in
the subthreshold region [24], [25]. Although this technique has
been successfully demonstrated, it is subject to considerable
variability since this resistance is voltage and threshold dependent. Another approach to variable bandwidth uses a strictly
two-band signal-conditioning method and was presented by
Perelman and Ginosar [38]. Low-power techniques in neural
amplifiers include the use of single-stage open-loop amplifier
designs to achieve submicrowatt power levels [39] and the use
of fully depleted silicon-on-insulator technology [40].
A. Neural Recording-Amplifier Design
The diagram of the neural recording amplifier is shown in
Fig. 7, in open- and closed-loop configurations. A two-stage
architecture is used for the design of the open-loop operational
amplifier, with the first stage being a differential input pair and
the second being a gain stage, as shown in Fig. 7. The input pair
(MP1 and MP2) has been designed using large PMOS transistors to achieve low-noise performance since the gate-referred
equivalent mean-square voltage noise is inversely proportional
to the gate capacitance. A p-channel current source (MP5)
and an n-channel current mirror load (MN3–MN4) are used in
the input stage. The second stage of the operational amplifier
includes an n-channel common-source amplifier (MN9) with
a p-channel current source load (MP8) to achieve maximum
output swing. Miller compensation (Cc ) is used with a nulling
series resistance implemented using PMOS (MP10) and NMOS
(MN11) transistors for stable operation in feedback mode and
to set the high-frequency cutoff. Finally, MP6 and MP7 form
the bias network.
In the closed-loop configuration shown in Fig. 7, the amplifier uses capacitive coupling (C1 ) at the input to reject the dc
potential of the electrode. A second capacitor (C2 ) placed in the
feedback path is used to set the closed-loop gain, given by the
ratio of C1 to C2 . The low-frequency cutoff is determined by
the RC time constant in the feedback path and is given by fl =
1/(2πRf C2 ). A cutoff ranging from below 1 Hz to few hundred
hertz is achievable using very high resistance (in gigaohms). To
achieve this resistance, subthreshold-biased transistors are used
in the feedback path [24], [25]. The low-frequency cutoff can be
varied to allow/reject field potentials by changing the effective
channel resistance of the feedback transistors operated in the
subthreshold-biased region. In Fig. 7, the PMOS feedback
transistors MP20 and MP21 are biased in subthreshold with
external control of their gate voltage to tune the low-frequency
cutoff. Selection of field potentials with signal amplitudes in the
few hundred millivolt range or spike activity in the few hundred
microvolt range requires an amplifier design with adjustable
gain. To achieve gain programmability, the input capacitor
C1 in Fig. 7 has been subdivided into six parallel capacitors.
A 6-b serial to parallel shift register is used to control the
gain by selecting combinations of these capacitors. Five of
the six capacitors are designed to be 10 pF, while the sixth is
5 pF so that, with C2 set to 0.05 pF, gain programming from
100× to 1100× in steps of 100× is achievable. The switches
implemented in this design use complementary-pass transistor
logic, as shown in Fig. 7, with the PMOS transistors having a
W/L ratio of 1.5 μm/0.6 μm and the NMOS transistors having
W/L ratio of 1.2 μm/0.6 μm. Gain programming using the
feedback capacitor C2 could also be considered with a fixed
input capacitance. However, in this case, the low-frequency
cutoff would be gain dependent.
PERLIN AND WISE: ULTRA COMPACT INTEGRATED FRONT END FOR WIRELESS NEURAL RECORDING MICROSYSTEMS
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Fig. 8. Photograph of the 64-channel neural recording front-end ASIC fabricated in the AMI 0.5-μm CMOS foundry process (3.1 mm × 4.8 mm).
The programmable-gain amplifier of this work requires a
layout area of 0.098 mm2 (410 μm × 240 μm) of which only
0.009 mm2 (less than 10%) is taken by the six switches needed
for gain programming. Indeed the input capacitance consumes
the majority of the area (75%) in order to achieve an overall gain
of 1000×. If the total input capacitance were reduced from 55
to 10 pF to save area, a 10-fF feedback capacitance would have
to be used, which is challenging considering process variations
and fringing fields. A two-stage cascaded amplifier design was
also considered, with the first stage providing 100 × (C1 /C2 =
10 pF/0.1 pF) and the second providing 10 × (C1 /C2 =
1 pF/0.1 pF); however, it was found that while a two-stage
cascaded design that achieves 1000× gain saves only 30% in
area compared with the single-stage design, it consumes twice
as much power.
As with any capacitively coupled design, high input impedance is a consideration, particularly when using highimpedance electrodes (> 1 MΩ at 1 kHz). Since the thermal
noise of the electrode is generally proportional to its impedance,
lower impedance electrodes are preferred. The thermal noise of
a 1-MΩ electrode (at 1 kHz) is approximately 13 μVrms over a
10-kHz bandwidth, which is already significant compared with
the 50-μVp−p neural signals, even excluding amplifier noise.
For this amplifier design, the signal attenuation of a 1-MΩ
electrode at 1 kHz is 25% in the highest gain setting. Lower
impedance electrodes experience signal attenuation at an input
of less than 10% at this setting.
Fig. 9. Measured gain spectrum of the tunable-bandwidth amplifier for multiple tuning voltages along with the low-frequency cutoff values. The measured
midband gain is 65.1 dB, and the high-frequency cutoff is 9.1 kHz.
Fig. 10. Measured noise spectrum of the amplifier for different tuning voltages (referred to the input).
B. Front-End ASIC Performance Results
The 64-channel front-end chip, which is shown in Fig. 8,
was fabricated at MOSIS in an AMI 0.5-μm technology and
measures 3.1 mm × 4.8 mm. This chip is shown in Fig. 8.
On this chip, 42% of the area is consumed by the 8 × 8 array
of amplifiers and 34% by their interconnections, including the
fan-out of 64 inputs and outputs to the pads. The pad frame
itself consumes about 19% of the area, and the remaining 5%
Fig. 11. Acute in vivo recordings obtained using the amplifier design of
this work (with V tune = −1.02 V) compared with those processed by a
commercial recording system. Note the inversion when comparing signals from
the two systems.
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JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 19, NO. 6, DECEMBER 2010
Fig. 12. In vivo recordings comparing the output of a commercial system with a fixed bandwidth from 100 Hz to 7 kHz and a gain of 1000× to the output of
the ASIC amplifier (variable low-frequency cutoff, gain of 1000×, and 9-kHz high-frequency cutoff). Note the inversion when comparing signals from the two
systems. Real-time variability of the low-frequency cutoff is demonstrated in vivo. (a) and (b) show gain compression of the spike due to the cutoff frequency
above 100 Hz. (c) Cutoff frequency set to 100 Hz. (e)–(f) show low frequency oscillations below 100 Hz. (a) V tune = −1.1 V. (b) V tune = −1.06 V.
(c) V tune = −1.02 V. (d) V tune = −0.939 V. (e) V tune = −0.829 V. (f) V tune = −0 V.
is dedicated to the 6-b shift register for gain programming and
test structures. Programming of this chip can be done wirelessly
when integrated into the entire system or can be hard wired
when the front end is used independently.
The measured gain spectra of the amplifier are shown in
Fig. 9 for five values of tuning voltage (V tune). The maximum
gain is 65.1 dB, and the high-frequency cutoff is 9.1 kHz. The
low-frequency cutoff can be set to below 10 Hz, as required
for recording field potentials. The input-referred noise spectrum
for three different tuning voltages is shown in Fig. 10. As
expected, when the tuning voltage is adjusted to filter out
the low-frequency components, the noise decreases since the
dominant source is related to 1/f . The total integrated noise
of this amplifier design averages 4.8 μVrms , measured between
10 Hz and 10 kHz across multiple channels and chips. Gain
programmability was verified using a 2-mVp−p sine-wave input
to the amplifier at 1 kHz and a LABVIEW interface to send
clock and data to the chip.
In vivo testing of the front-end ASIC was carried out by
packaging the chip on a custom printed circuit board (PCB)
along with an acute silicon neural recording electrode. The amplifier inputs were connected to additional pins on the PCB to
allow them to be simultaneously monitored using a commercial
multichannel neural recording interface. In vivo spike activity
was obtained using this setup, as shown in Fig. 11 with the
gain of both systems set to 1000×, and the tuning voltage of
the ASIC amplifier was set to reject slow-wave activity. The
top trace is the output of the commercial recording system,
while the bottom trace is the (inverting) output of the amplifier
in this work. The two in vivo recordings are comparable in
terms of gain and spike shape. The ASIC tuning voltage used
here causes a somewhat slower signal rise time, and the highfrequency cutoffs of the two amplifiers are not identical (7-kHz
commercial versus 9-kHz ASIC). Results from tuning the
low-frequency cutoff during the in vivo recording session are
shown in Fig. 12. In Fig. 12(a) and (b), the gain of the ASIC
amplifier is less than 1000× because the low-frequency cutoff
has been set well above 100 Hz. In Fig. 12(c), the tuning voltage
is adjusted to set the frequency cutoff at 100 Hz, resulting
in the spike activity that is comparable in amplitude with the
spikes recorded from the commercial system. Successively,
more positive tuning voltages [see Fig. 12(d)–(f)] result in
cutoff frequencies below 100 Hz, as apparent from the lowfrequency oscillations.
The performance of the integrated amplifiers on this
64-channel front-end signal-conditioning ASIC is summarized
in Table I and compared with similar designs reported by
others. This design uses a more aggressive (0.5-μm) process
technology and balances higher gain with low noise, low input
offset voltage, and a small layout area. In addition, it offers
the ability to digitally program the gain in wireless recording
microsystems.
PERLIN AND WISE: ULTRA COMPACT INTEGRATED FRONT END FOR WIRELESS NEURAL RECORDING MICROSYSTEMS
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TABLE I
COMPARISON OF THE MEASURED PERFORMANCE FOR INTEGRATED NEURAL-RECORDING AMPLIFIERS
WITH SIMILAR ARCHITECTURES DESIGNED IN CMOS
V. M ICROSYSTEM I NTEGRATION
One of the key challenges in realizing fully implantable
microsystems for neural prostheses and neuroscience applications is the integration and packaging of their various components, particularly the electrodes and their interface circuitry.
Approaches based on flip-chip bonding are being pursued
to vertically integrate such components onto commercial
2-D neural-electrode arrays, and suitable packages are in development [31]. However, such microsystems must deal with
the size and metallurgical constraints of flip-chip bonding and
the increased implant height that results from the stacking of
components. A low profile is particularly important to allow
the dura to be replaced over the implant, decoupling it from the
skull and allowing it to float with the brain. Previously reported
integration approaches that embed the components in a silicon
platform achieve a low vertical rise but, usually, at the expense
of a larger lateral area. For example, wire bonding between
the components and platform bonding pads has been used to
integrate a neural recording microsystem [5]; however, the wire
bonds have appreciable height, and, for high-channel-count
systems, the interconnect routing and bonding pads occupy
significant area (48% of the total platform area for the neural
recording microsystem in [5]).
A new approach to microsystem integration results in nearly
zero vertical rise above the platform while simultaneously
minimizing the size overhead in lateral dimensions. This lowprofile microsystem front end is shown in Fig. 13. It consists
of a silicon platform with etched slots for the assembly of
the 3-D microelectrode array and a dry-etched recessed cavity
for the signal-conditioning ASIC. A microfabricated parylene
cable carrying the interconnect lines is separately fabricated and
overlays the components on the platform. Since the platform
surface is planar and contains no interconnect lines, it is not
significantly larger than the combined areas of the probe array
and ASIC. The cable-based interconnect lines run directly on
top of the components and do not consume extra area. The
cable thickness, on the order of few micrometers, is negligible
in terms of the vertical dimension of the microsystem. For very
complex multichannel interconnect routing, multiple cables can
be stacked with negligible penalty in vertical rise. The far end
of the cable is designed to be bonded to a PCB connector or
percutaneous plug to transfer power and signals to and from
the implant. In the full version of the microsystem, which
would include the circuitry for signal processing and telemetry
in addition to the front-end, the cable would connect to the
subcutaneous electronic module, as shown in Fig. 2.
A. Microfabricated Overlay Cable
Parylene-C was selected as the structural material for the
fabrication of the overlay cable due to its compatibility with
low-temperature deposition, compatibility with lithographic
patterning, mechanical flexibility, and biocompatibility [41]–
[46]. Fabrication begins with the deposition and patterning of
the first layer of parylene on a silicon wafer. Approximately
5 μm of parylene was deposited, although the precise thickness
of the film is not critical. At least, a few micrometers should
be deposited since it acts as a structural layer. This layer of
parylene is patterned using thick photoresist and dry etched in
oxygen plasma to define the outline of the cable and tab cutout
regions. Following this patterning, interconnect definition takes
place. For the interconnect metal, a chromium (300 Å), gold
(3500 Å), and chromium (300 Å) stack is deposited and defined using liftoff. A top layer of chromium is used since an
upper layer of parylene will follow and has better adhesion
to chromium than to gold [45]. The next step is to open the
tab regions with lithography and sputter an electroplating seed
layer: Cr (300 Å) and Au (2000 Å). Due to the 5-μm step height
between the wafer and top surface of the parylene, it is critical
that sputtering be used due to its conformal coverage, rather
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Fig. 13. Diagram of the neural recording microsystem front end integrated using the compact 3-D array and overlay-cable approach.
than evaporation. For the same reason, the tab regions and the
interconnect metalization are defined in two steps, rather than
one. After deposition of the seed layer, lithography is used to
open the tab regions for electroplating. The tab regions are
then electroplated with gold to a thickness of 4.5 to 5 μm.
The electroplating resist is stripped in acetone along with liftoff
of the seed layer. The top parylene layer is now deposited
(∼5 μm), patterned, and dry etched in the field and tab regions.
The final step is to release the individual cables from the wafer
in 1 : 1 HF:deionized H2 O.
A released parylene cable is shown in Fig. 14. The freehanging tabs overlaying the IC are 75 μm wide, and the
parylene cutout region is 100 μm on each side, leaving a 12-μm
gap on the three sides of the tab. The tabs overlaying the 3-D
probe array (4 × 16) are 30 μm wide, spaced at 40-μm pitch.
The interconnect traces on the cable are 10 μm wide with a
pitch of 20 μm.
B. Assembly and Bonding
In the assembly of this front end, the probes (four in parallel)
are first inserted into the platform using the brass jig described
earlier and are ultrasonically bonded to the pads, as described
in Section III-C. Next, the chip is separately secured on a
glass slide using a temporary adhesive, while the parylene
overlay cable is aligned and ultrasonically tab bonded to the
chip bonding pads. At this point, the chip/cable connections
are tested for electrical continuity on a probe station. The chip
is then removed from its temporary fixture and moved, along
with the bonded parylene cable, into its cavity in the silicon
platform. To secure the chip, a very small amount of silastic
is placed in the bottom of the cavity and allowed to cure at
room temperature over a period of several hours. At this point,
the cable/chip fixture can be slightly adjusted within the cavity
such that the 3-D array tabs on the cable are aligned with the
bonding pads on the platform. Once alignment is achieved,
the remaining tabs on the cable are ultrasonically bonded to
the 3-D microelectrode array. Finally, the back end of the cable
is wire bonded to a testing PCB, and the completed device is
released from the assembly jig. The final integrated device
is shown in its most compact form on an index finger in
Fig. 15. The overall size is primarily limited by the individual
components, and the thickness of the platform is limited by
Fig. 14. Images of the parylene overlay cable. The tabs overlaying the 3-D
probe array (4 × 16) are 30 μm wide, spaced at 40-μm pitch; the ASIC tabs
are 75 μm wide with a 12-μm gap on three sides. The interconnect traces on
the cable are 10 μm wide and spaced at 20-μm pitch.
PERLIN AND WISE: ULTRA COMPACT INTEGRATED FRONT END FOR WIRELESS NEURAL RECORDING MICROSYSTEMS
1419
Fig. 15. Microsystem for implantable neural recording. A silicon package
carrying 3-D microelectrode arrays integrated with a signal-conditioning ASIC
using a parylene cable is shown on an index finger.
Fig. 17. (a) Acoustically stimulated neural activity and (b) spontaneous neural
activity, obtained from the inferior colliculus of a guinea pig on multiple
channels of the integrated front end.
Fig. 16. Close up of the implanted front end resting on the cortical surface of
a guinea pig.
the ASIC. Its planar surface provides ease of handling and
implantation.
VI. IN VIVO R ESULTS
The integrated front end was implanted into a guinea pig
auditory cortex and used to successfully record discriminable
neural activity. The implanted front end is shown in Fig. 16.
In this experiment, the tail end of the parylene cable was connected to a custom PCB to transfer power to the front-end ASIC
and recorded signals from the ASIC to an oscilloscope. In this
work, the package was handled with tweezers and implanted
manually. Precise placement using a stereotaxic manipulator
would be readily possible due to the planar architecture of
this package. Mounting to a manipulator would also allow
for the vertical movement of the shanks in a given region to
obtain optimal recording depth. Fig. 16 shows the front-end
package resting on the cortex following complete insertion of
the shanks. The recorded neural activity using this setup is
shown in Fig. 17. In Fig. 17(a), two different channels from
the implanted front end are shown in response to an acousticnoise burst (an 80-dB log upsweep from 500 Hz to 16 kHz with
a duration of 164 ms). Spontaneous neural activity was also
recorded on multiple channels of the integrated front end, as
shown in Fig. 17(b).
VII. C ONCLUSION
This paper has presented an ultracompact fully implantable
microsystem front end for neural recording. The integrated
front end includes a new architecture for 3-D microelectrode arrays and a robust widely applicable signal-conditioning ASIC.
A new integration approach using a microfabricated parylene
cable and ultrasonic tab bonding is used to electrically interface
the microelectrodes with the ASIC. This integration approach
was validated in vivo by recording neural signals using passive
probes connected to the ASIC, while the power and data transfer to and from the chip were carried out by the parylene cable.
The realized device achieves a compact low-profile package,
limited in size only by the various components themselves. The
device also has a planar surface, which facilitates handling and
implantation.
In future versions, a similar approach could be used to realize
a complete two-module implantable microsystem, as shown in
Fig. 2. The second (satellite) platform would accommodate the
signal processing and wireless electronics. An extended overlay
cable would then be used for the integration of the satellite
platform with the platform holding the electrodes. The entire
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implant assembly, except for the electrode sites, should be
encapsulated with a biocompatible material, such as parylene.
ACKNOWLEDGMENT
The authors would like to thank B. Casey for his assistance
with assembly and J. Wiler of the Kresge Hearing Research
Institute at the University of Michigan for his assistance with
the in vivo experiments.
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Gayatri E. Perlin (S’04–M’09) received the B.S.E.
and M.S.E. degrees in electrical engineering, and
the Ph.D. degree developing MEMS technology for
implantable microsystems from the University of
Michigan, Ann Arbor, in 2001, 2003, and 2008,
respectively.
Currently, she is a Member of the Technical Staff, Advanced Imaging Technology Group,
Massachusetts Institute of Technology Lincoln Laboratory, Lexington. Her research interests include
developing micro- and nanotechnology; realization
of microsystems for bioscience, prosthetics, and medical diagnostics, as well
as physical/chemical sensors and microfluidics; and translation of research in
MEMS to product/industry.
1421
Kensall D. Wise (S’61–M’69–SM’83–F’86–LF’07)
received the B.S.E.E. degree with highest distinction
from Purdue University, West Lafayette, IN, in 1963,
and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in
1964 and 1969, respectively.
From 1963 to 1965 and from 1972 to 1974, he
was a Member of Technical Staff, Bell Telephone
Laboratories, where his work focused on the exploratory development of integrated electronics for
use in telephone communications. From 1965 to
1972, he was a Research Assistant and then a Research Associate and
Lecturer in the Department of Electrical Engineering, Stanford University,
working on the development of micromachined solid-state sensors. Since
1974, he has been with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, where he is currently the
J. Reid and Polly Anderson Professor of Manufacturing Technology, Director
of the Engineering Research Center for Wireless Integrated MicroSystems, and
Director of the Lurie Nanofabrication Facility. His present research focuses
on the development of integrated microsystems for health care, environmental
monitoring, and defense applications.
Dr. Wise organized and served as the first Chairman of the Technical
Subcommittee on Solid-State Sensors of the IEEE Electron Devices Society
(EDS). He was General Chairman of the 1984 IEEE Solid-State Sensor
Conference, served as IEEE-EDS National Lecturer (1986), and was Technical Program Chairman (1985) and General Chairman (1997) of the IEEE
International Conference on Solid-State Sensors, Actuators, and Microsystems.
He was the recipient of the Paul Rappaport Award from the EDS (1990), the
Distinguished Faculty Achievement Award from the University of Michigan
(1995), the Columbus Prize from the Christopher Columbus Fellowship Foundation (1996), the SRC Aristotle Award (1997), and the 1999 IEEE SolidState Circuits Field Award. In 2002, he was named the William Gould Dow
Distinguished University Professor at the University of Michigan. He held the
2007 Henry Russel Lectureship at the University of Michican. He is a Fellow of
the American Institute for Medical and Biological Engineering, and a member
of the U.S. National Academy of Engineering.