Application Specific Intelligent Power Modules - A Novel Approach to
System Integration in Low Power Drives
Eric R. Motto - Powerex Inc., Youngwood, Pennsylvania, USA
ABSTRACT
Abstract - This paper reviews the system requirements and key technologies driving the
development of highly integrated Application Specific Intelligent Power Modules (ASIPMs). New
ASIPMs with power circuit topologies, control functions and packaging optimized to meet the
performance, cost and size requirements of specific small motor control applications will be
presented.
I. INTRODUCTION
When used with an inverter, three phase AC motors are smaller, more efficient and more reliable
than the universal AC and brush type DC motors that are commonly used in light industrial and consumer
applications. In order to realize these advantages, the cost of the inverter must be offset by energy savings,
improved performance, and increased reliability. The widespread use of inverters in heavy industrial and
precision motion control applications is evidence that these advantages are being realized. On the other
hand, the use of inverters with small AC motors (100W - 2.2kW) is often limited by the cost and complexity
of the inverter. In addition, limited space often prevents the use of general purpose inverters with fixed
shape, size, and cooling requirements. For these applications, it is becoming increasingly desirable to
simplify and miniaturize the power section so that the physical size, form factor, and cost requirements can
more easily be met. This paper will examine the
Figure 1a: Conventional IPM
system requirements of some typical small motor
drive applications and present five examples of
LV ASIC
Power Chips
Application Specific Intelligent Power Modules
Isolated Control
Gate Drive
(ASIPMs) targeted to address these requirements.
Signal Interface
(Opto Couplers)
The examples illustrate how power circuit
Over Current,
Control supply
Isolated Power
topologies, integrated functions, and packaging can
failure
C
Supply
be optimized to meet the requirements of specific P
LV ASIC
applications.
Isolated Control
U
Gate Drive
Signal Interface
(Opto Couplers)
II. THE ASIPM CONCEPT
Conventional IPMs (figure 1a) integrating
power devices with low voltage ASICs (Application
Specific Integrated Circuits) to provide gate drive
and protection functions have been widely accepted
for general purpose motor drive applications ranging
from 200W to more than 150kW [3][5][7]. The
success of these modules is the direct result of
several technical advantages including: (1) Reduced
design time and improved reliability offered by the
factory tested, built-in gate drive and protection
functions; (2) Lower losses resulting from
simultaneous optimization of power chips and
protection functions; (3) Smaller size resulting from
Over Current,
Over Temp.,
Cotrol supply
failure
Isolated Power
Supply
Temp. Sensor
User Supplied Interface
Figure 1b: ASIPM
HVIC
Level
Shift
C
P
U
Power Chips
Gate Drive and
Protection
LV ASIC
Input signal
conditioning
Gate
Drive
Protection, Fault Logic
and Analog Current
Feedback Processing
Current sensor(s)
Temp. sensor
the use of bare power chips and application specific control ICs. (4)
Figure 2: HVIC Chip
Improved manufacturability resulting from lower external component
counts.
Unfortunately, in spite of these advantages, the conventional
IPM’s generic, general purpose, design does not provide enough
functional integration to meet the demanding cost and size
requirements of some small motor control applications. In these
cases, it is often desirable to increase the level of integration to
include functions such as level shifting, high side power supplies and
current sensing. The ASIPM shown in figure 1b has been developed
to address these requirements. The ASIPM takes the integration a
step farther than conventional IPMs by introducing HVIC (High
Voltage Integrated Circuit) technology. The ASIPMs described in this
paper utilize custom high and low voltage integrated circuits to
provide input signal conditioning, protection logic, analog current
feedback signal processing, level
shifting and gate drive for the
Figure 3: ASIPM Integrated Functions
integrated power semiconductor
devices. A photo of a typical high
Under
Boot
Voltage
voltage integrated circuit (HVIC) is
Strap
Lock-Out
Supply
shown in figure 2.
III. SELECTING THE INTEGRATED
CONTROL AND PROTECTION
FUNCTIONS
Control
n
CPU/
DSP
Status
n
ShootThrough
Interlock
Level
Shift
Gate
Drive
SC Prot.
Fault
Status
Feedback
P
Over
Temp.
U,V,W
TS
The addition of HVIC
Analog
Current
technology to the ASIPM makes it
Gate
RS
n
Drive
possible to integrate a wide range of
N
sophisticated functions. Figure 3 is a
Under
SC Prot.
Voltage
Control
Current
block diagram showing some of the
Lock-Out
Power
Sensor(s)
functions that can be implemented.
In general, the cost and size of the
ASIPM increases with increasing
complexity. To determine which functions should be integrated for a given application, it is necessary to
consider the fundamental trade-off between performance, size and cost illustrated in figure 4. The key to
developing a cost effective ASIPM is to integrate only the functions that provide both system and cost
advantages. Table 1 gives a breakdown of the required functions in four different applications. By examining
the requirements shown in table 1 and considering the trade-off of figure 4 an optimum combination of
integrated functions can be realized. Clearly, the optimum combination will be different for different
applications. To date, five families of ASIPMs have been developed to meet the needs of specific
applications. These devices will be described in more detail
Figure 4: ASIPM Design Trade-off
Figure 5: ASIPM Power Circuit Requirements
Performance
Efficiency
Control Precision
I/O Functions
Reliability
Size
Cost
System
Requirements
Form Factor
Functional Value
Development Time
Manufacturability
Inverter
IGBTs & Free Wheel Diodes
Brake
IGBT & Diode
Converter
Diodes
Table 1: ASIPM Control and Protection Application Requirements
Control and Protection
Functions
Gate Drive
Level Shift
Boot Strap Supply
Diodes
P-Side Gate Drive
Under Voltage
Protection
P-Side Short Circuit
Protection
N-Side Gate Drive
Under Voltage
Protection
N-Side Short Circuit
Protection
Shoot Through Interlock
Over Temperature
Current Sensors and
Feedback
Fault Status Feedback
High Performance
General Purpose
Industrial Inverter
Compact High Precision
AC Servo and Vector
Drives
Basic General Purpose
Industrial and
Commercial Speed
Control/Smart Motors
Low Cost Consumer
Appliance and
imbedded inverters
Required
Required
Required
Required
Required
Required
Required
Required
Required
Required
Required
Required
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
Required due to unstable nature
of boot strap supplies
Desirable, but may not be
needed when high performance
output current sensors are used
with a high speed CPU
Generally required for reliable
power up/down
Desirable, but may not be
needed when high performance
output current sensors are used
with a high speed CPU
Generally required for reliable
power up/down
Desirable if low enough cost.
However, acceptable protection
can usually be achieved using
bus current sensors
Generally required for reliable
power up/down
Usually unnecessary in
imbedded inverter applications
Desirable for low impedance
faults and shoot-through survival
Desirable for low impedance
faults and shoot-through survival
Good safety feature. May be
required depending on users
design philosophy
Desirable
Good safety feature. May be
required depending on users
design philosophy
Desirable
Desirable for low impedance
faults and shoot-through survival.
May be implemented using bus
current sensor.
Good safety feature. May be
difficult to justify cost
Desirable for low impedance
faults and shoot-through survival.
May be implemented using bus
current sensor
Desirable, but may not meet cost
requirements
Desirable if cost effective
Three phase output current
feedback is required
Three phase output current
feedback is required
DC Bus current feedback signal
is usually sufficient
Usually unnecessary in
imbedded inverter applications
Current feedback signal is
usually not required
Multiple diagnostic fault signals
are desirable
Multiple diagnostic fault signals
are desirable
Single fault status signal is
usually acceptable
Single fault status signal is
usually acceptable
Generally required for reliable
power up/down
in the following sections.
IV. SELECTING THE POWER CIRCUIT TOPOLOGY
The power semiconductor requirements in the inverter power stage also differ from application to
application. Figure 5 shows the typical power devices that may be included in a small motor control. Table 2
gives a breakdown of the requirements in four different applications. For lowest cost, the power stage should
only include the necessary power devices. It can be observed from table 2 that the optimum power circuit
topology depends on the application requirements.
V. ASIPM EXAMPLES
Table 2: ASIPM Power Circuit Requirements
High Performance
General Purpose
Industrial Inverter
Compact High Precision
AC Servo and Vector
Drives
Basic General Purpose
Industrial and
Commercial Speed
Control/Smart Motors
Low Cost Consumer
Appliance and
imbedded inverters
Converter (Rectifier)
Usually requires three phase
rectifier
Usually requires three phase
rectifier
May require three phase, single
phase, or doubler* configurations
Brake
Usually required for rapid
deceleration
Usually not required
Usually not required
Inverter
Required - High PWM
Frequency (5kHz - 20kHz)
Required for stand alone units
Not required in DC feed multi
axis applications
Braking function generally
required but may be
implemented in the bulk power
supply of DC fed systems and
size requirements vary widely
depending on the application
Required - High PWM
Frequency (5kHz - 20kHz)
Required - High PWM
Frequency (5kHz - 20kHz)
Required - High and Low PWM
frequencies
Power Circuit
Component
The following subsections present five
Figure 6: PS212XX “DIP” ASIPM
examples of actual ASIPMs that have been
optimized to meet the needs of specific
applications. In each example the power circuit
topology, package design and integrated functions
have been tailored to a specific class of small
motor control applications. At the same time care
has been exercised to keep the integrated
functions as generic as possible so that the
module is suitable for a wide enough range of
applications to take advantage of the
economies of automated mass production.
Figure 7: “DIP” ASIPM Package Cross Section
These examples each follow one of the
Power Pins
Control Pins
application categories outlined in tables 1 and
2.
Al Bond Wire
Power Chips
IGBT, FWDi
HVIC
Au Bond Wire
A. ASIPM "DIP Series" For Consumer
Appliance Applications
The "DIP" ASIPM, PS212XX series, is
designed for basic speed control in consumer
appliance applications. For these applications,
the ASIPM must provide a small, low-cost,
efficient power stage that can be easily
Mold Resin
Aluminum Heat Sink
integrated into the finished equipment. In order
to achieve these targets, a new transfer
molded package was developed. A photograph of the
Table 3: “DIP” ASIPMs
new package is shown in figure 6 and a cross section
“DIP” ASIPM
Inverter Rating
Line-up
400W
750W
1500W
diagram is shown in figure 7. Low cost is achieved by
assembling bare power chips along with custom HVIC
Low
PS21205
PS21204
Frequency
and LVIC die on a lead frame like a giant integrated
Type
circuit. The lead frame assembly is molded in epoxy resin
High
along with an aluminum heat sink to provide good
PS21213
PS21214
Frequency
thermal characteristics. This process reduces cost and
Type
manufacturing time by eliminating the need for separate
packaging of the power devices and control ICs. In
addition, the IMS (Insulated Metal Substrate) or ceramic substrate that is Figure 8: Doubler Circuit
used in conventional hybrid modules is not required. The transfer molded
package is also well suited for high volume, low cost mass production.
The input voltage for these applications is generally between
330
VDC
100VAC and 240VAC. To cover this range, IGBTs and free wheel diodes
120VAC
with a 600V VCES rating were selected. Most of the target applications are
powered from a single phase AC source but flexibility to accommodate
three phase sources and voltage doubler (figure 8) topologies was
desired. Due to these requirements and the limited capabilities of the lead frame design, it was determined
that the rectifier converter should not be integrated in the DIP ASIPM. The IGBT inverter section is a
standard three phase bridge containing six IGBT+FWDi pairs. For optimum system cost, the decision was
made to develop two different types of IGBT chips. High speed chips are used when the application requires
switching frequencies greater than 5kHz and low speed (low saturation voltage) chips are used when the
required switching frequency is less than 5kHz. At this writing, there are four DIP ASIPMs in production and
several additional types under development. Table 3 shows the typical application and type names of these
four devices.
Figure 9 is a block diagram showing the DIP ASIPM’s integrated control and protection functions
along with some of the required
external support circuitry. The
input signal level shifting function
and under voltage protection for
the p-side IGBT chips is
accomplished using three custom
HVICs. Over current protection
and n-side drive under voltage
protection for the three low side
IGBTs is provided by a custom
low voltage ASIC.
The DIP ASIPMs built-in 5V Logic
level shift eliminates the need for Interface
to MCU
opto-couplers and allows direct
connection of all six control inputs
to the CPU/DSP. The detailed
operation and timing diagram for
the level shift function is shown in
figure 10. The falling and rising
edges of the p-side control signal
(A) activate the one shot pulse
logic which generates turn on
pulses (B, C) for the high voltage
MOSFETs. Narrow on pulses are
used to minimize the power
dissipation within the HVIC. The
high voltage MOSFETs pull the inputs to the
high side driver latch (D, E) low to set and
reset the gate drive for the p-side IGBT (F).
Power for the high side gate drive is
normally supplied using external boot strap
circuits as shown in figure 9. The operation
of the boot strap is outlined in figure 11.
When the low side IGBT is turned on, the
floating supply capacitor is charged through
the boot strap diode. When the n-side IGBT
is off, the energy stored in the capacitor
provides power for the high side gate drive.
Using this technique it is possible to operate
all six IGBT gate drivers from a single 15V
supply. The boot strap circuit is a very cost
effective method for providing power for the
high side IGBT gate drive. However, care
must be exercised to maintain the high side
supplies when the inverter is idle and during
fault handling conditions. This usually means
that the low side IGBTs must be pulsed on
periodically even when the inverter is not
running. At power up, the boot strap supplies
must be charged before the PWM is started.
Normally, this is accomplished by a burst of
pulses on the low side IGBTs.
The module is protected from failure
of the 15V control power supply by a built in
Figure 9: “DIP” ASIPM Block Diagram
VUFS
VUFB
P
VP1
UP
+VCC
Input
Signal
Condition
Level
Shift
HVIC
VVFS
Gate
Drive
& UV
lock
out
VVFB
VP1
VP
+VCC
Input
Signal
Condition
Level
Shift
HVIC
VWF
Gate
Drive
& UV
lock
out
U
VWF
VP1
WP
VPC
+VCC
Input
Signal
Condition
Level
Shift
HVIC
VN1
UN
VN
WN
FO
CFO
V
Gate
Drive
& UV
lock
out
Motor
W
+VCC
Input Signal
Conditioning
Gate
Drive
Fault Logic &
UV lock out
Protection
Circuit
CIN
VNC
N
LV-ASIC
+
RSHUNT
RSF
15V
CSF
Figure 10: High Voltage Level Shift
Floating Supply
(P)
High Voltage
Level Shifters
D
E
PIN
A One-Shot
Pulse Logic
R Q
S
Gate
Drive
(U,V,W)
B
C
F
+15
Gate
Drive
NIN
(N)
A
B
C
D
E
F
under voltage lock out circuit. If the voltage of the control
Figure 11: Boot Strap Supply Operation
supply falls below the UV level specified on the data sheet,
Charging
Floating Supply
the low side IGBTs are turned off and a fault signal is
Path
V(U,V,W)
asserted. In addition, the p-side gate drive circuits have
(P)
independent under voltage lock out circuits to protect
+
Boot Strap
Gate
against failure of the boot-strap power supplies.
Supply
Drive
The DIP ASIPM uses the voltage across an Diode
(U,V,W)
external shunt resistor inserted in the negative DC bus to
monitor the current and provide protection against overload
and short circuits. An RC filter with a time constant of 1.5 to
+
+
Gate
2µs is inserted as shown in figure 9 to prevent erroneous
15V
CIN(n) Drive
fault detection due to di/dt induced noise at switching
events. When the voltage at the CIN pin exceeds the VSC
(N)
reference level specified on the device data sheet the lower
arm IGBTs are turned off and a fault signal is asserted at
CIN(n)
the FO output. The IGBTs remain off until the fault time
(tFO) has expired and the input signal has cycled to its off
state. The duration of tFO is set by an external capacitor
CFO.
V(U,V,W)
The DIP ASIPM has seven microprocessor
compatible input and output signals. All signals are 5V
Figure 12: “DIP” ASIPM
TTL/CMOS compatible and referenced to the common ground
Interface Circuit
of the control power supply allowing direct connection to the
ASIPM
+
+
MCU. Figure 12 shows a typical external interface circuit. On
VD
5V
15V
and off operations for all six IGBTs in the ASIPM are
controlled by the active low control inputs. Normally, these
inputs are pulled high to the 5V logic supply of the MCU with
an external resistor. The MCU commands the IGBT to turn on
5.1KΩ
5.1KΩ
6
by pulling the respective input low. Hysteresis is provided on CPU/DSP
UP, VP, W P,
UN, VN, W N
all inputs to prevent oscillations and enhance noise immunity.
The fault signal output is in an open collector configuration.
FO
When a fault occurs the ASIPM pulls the fault line low.
GND
B. ASIPM "Version 3" For Basic General Purpose
Industrial
Speed
Control
(Smart Motors)
Table 4: “Version 3” ASIPMs
Short Circuit
Type
Typical Motor IGBT Rating Inverter Output
OC
The
“version
3”
Level (SC)
Rating (kW)
(IC/VCES)
Trip
Current IO
PS1103X series of ASIPMs was
(Amps)
(Amps)
(ARMS)
developed for applications such
4A/600V
1.5
5.3
8.0
PS11032
0.2/220VAC
as pumps, hoists, and conveyors
8A/600V
3.0
10.6
16
PS11033
0.4/220VAC
that require limited control
performance consisting primarily
15A/600V
5.0
17.7
30
PS11034 0.75/220VAC
of speed regulation. In these
20A/600V
7.0
24.7
40
PS11035
1.5/220VAC
applications, it is often desirable
30A/600V
11
39
60
PS11036
2.2/220VAC
to miniaturize and simplify the
power stage so that the inverter
can be mounted on, or integrated into the motor. The “version 3” series of ASIPMs consists of five types
designed for 0.2 to 2.2kW micro inverter applications. Table 4 summarizes the key characteristics of each of
the five module types in the PS1103X ASIPM family.
The packaging selected for the “version 3” ASIPM is a low profile design using an aluminum base
IMS (Insulated Metal Substrate) substrate. A photo of the “version 3” ASIPM is shown in figure 13. A cross
section diagram of the low profile IMS package is shown in figure
14. The power chips, control IC and support components are
assembled on the IMS substrate much like a conventional
surface mount printed circuit board. This process is easily
automated, low cost and quite flexible.
A block diagram of the “version 3” ASIPM is shown in
figure 15. Careful selection of integrated functions and advanced
processing technologies allowed a single HVIC to be used for the
gate drive and protection of all six IGBTs. This single IC design
yields low cost and extremely compact size. The ASIPMs
integrated functions are powered from a single 15V control power
supply referenced to the negative DC bus.
Built-in, boot strap circuits supply power for the high side
gate drive circuits eliminating the need for separate isolated
Figure 13: PS1103X
“Version 3” ASIPM
power supplies. Incorporating
the high side power supplies
Figure 14: Cross Section of IMS ASIPM Package
and level shifting into the
Signal
Epoxy
Power Terminals
ASIPM reduces high voltage Plastic
Terminals
Case
Resin
spacing requirements on the
control
PCB
allowing
a
significant savings in circuit
board space.
The PS1103X “version
3” ASIPM’s power circuit
consists of six rectifier diodes Multi Layer Insulated
Aluminum Bond
Gate Drive and Control
Silicon
forming a three phase bridge Metal Substrate
Wires
Circuits
Chips
and six IGBT, free wheel diode
pairs forming a three phase
inverter stage. The brake circuit is not required for most of the target applications so it was omitted to reduce
the size and cost of the module. A circuit diagram of the power circuit is included in figure 15. Openings are
provided in both the positive and negative DC bus connections. All of the IGBT and free wheel diodes are
the latest Mitsubishi/Powerex third generation technology utilizing shallow diffusion and 2~3µm design rules
[1].
Built in short circuit and over current protection allow maximum utilization of power device capability
while avoiding nuisance tripping. This is achieved using a time dependent fault trip level. Figure 16 shows
the time dependence of the
Figure 15: ASIPM “Version 3” Block Diagram
over current and short circuit
protection functions. When a
severe low impedance fault
P1
causes the current to exceed
R
S
more than two times the
Gate Drive
230VAC
T
UV Lock Out
modules IC rating, short circuit
Level Shift
N1
protection is activated and
Gate Drive
+V
UV Lock Out
shut down occurs very quickly
V
P2
Level Shift
15V
~2µs.
Under
overload
Gate Drive
UV Lock Out
U
conditions, the trip time
Level Shift
U
V
V
Motor
extends to 10µs. Over current
W
Input
Signal
W
Gate Drive
Conditioning
U
5V Logic
UV
V
protection is activated when
Interlock
Lock Out
Interface
W
to MCU
Fault Output SC
the peak current indicates that
Protection
FO
Logic
the load current has exceeded
Analog Current
V
Feedback
250% of the modules IO(RMS)
HV-ASIC
N2
GND
rating.
A buffered analog bus
CC
D
P
P
P
N
N
N
AMP
Figure 16: ASIPM “Version 3” Short circuit
and over current protection function
Figure 17: ASIPM “Version 3” Analog Bus
Current Feedback Signal Performance
5
IC (A)
Short Circuit
trip level
IC(rated) X 2
4
VAMP(200%)
Conditions:
VD=15V, Tj= 25C
Protection
Level
Over Current
trip level
VAMP
(V)
3
2
IORMS(rated) x
250% x √2
VAMP(100%)
1
Typical IC
Waveform
0
0
Current Feedback Signal
Output Characteristic
2
tW (µs)
10
0
100
200
300
Bus Current (%) Normalized to IORMS(rated) x √2
Figure 18: ASIPM “Version 3” Shoot
current feedback signal is provided for system
Through Interlock Protection
control. The signal is derived from a shunt that
measures the sum of the currents in the Active Low P-Side
off
VCIN(P)
control input
emitters of the low side IGBTs (see figure 15).
on
The HVASIC amplifies the signal from the Active Low N-Side V off
CIN(N)
control input
on
shunt to provide a scaled analog feedback
signal of 4V when the peak load current P-Side IGBT Gate VGE(P)
Voltage
0
reaches a level equivalent to 200% of the
N-Side
IGBT Gate
modules rated IO(RMS). Figure 17 shows the
VGE(N)
Voltage
0
characteristics of the analog feedback signal.
The HVASIC also provides shoot
Normal
N-Side erroneous
P-Side on command
Operation
“noise” rejected delayed until N-Side off
through interlock logic for additional protection
against noise and control signal anomalies.
Figure 18 is a timing diagram showing the
Table 5: “Version 3” ASIPM Control Signals
Signal Name
Designation
Description
operation of the interlock function. The interlock
function rejects input signals that command the
Control Inputs
UP, VP, WP,
Inputs for controlling on/off
UN, VN, WN,
operation of the IGBTs in the IPM.
upper and lower IGBTs in a leg to be on
Fault
Signal
FO
Fault output signal
simultaneously. Operation of the interlock in the
Analog
Current
V
Analog
current feedback signal
AMP
“version 3” ASIPM does not produce a fault
Feedback
signal.
The module is protected from failure of
Figure 19: ASIPM “Version 3”
the 15V control power supply by a built in under voltage lock out
Interface Circuit
ASIPM
circuit. If the voltage of the control supply falls below the UV level
+
+
VD
5V
15V
specified on the data sheet, the low side IGBTs are turned off
and a fault signal is asserted. In addition, the p-side gate drive
circuits have independent under voltage lock out protection to
protect against failure of the boot-strap power supplies.
5.1KΩ
5.1KΩ
The PS1103X series ASIPM has eight microprocessor CPU/DSP
6
UP, VP, W P,
compatible input and output signals. All signals are 5V
UN, VN, W N
TTL/CMOS compatible and are referenced to the common
FO
ground of the control power supply to allow direct connection to
10KΩ
the MCU. Table 5 summarizes the ASIPM's input and output
VAMP
signal names and function definitions. Figure 19 shows a typical
0.1nF
GND
external interface circuit for the “version 3” ASIPM. On and off
operations for all six IGBTs in the ASIPM are controlled by the
active low control inputs. Normally, Figure 20: Miniature motor drive using “Version 3” ASIPM
these inputs are pulled high to the 5V
logic supply of the MCU with an
external 5.1KΩ resistor. The MCU
commands the IGBT to turn on by
pulling the respective input low.
Hysteresis is provided on all inputs to
prevent oscillations and enhance noise
immunity. The fault signal output is in
an open collector configuration. When
a fault occurs, the fault line pulls low. If
the fault is caused by an SC or OC
condition, the output asserts a fixed
1.8ms pulse. In the case of a UV lock
fault the signal is maintained until the control supply
Table 6: “Version 2” ASIPMs
returns to normal. An example of a compact inverter
Peak Output Short Circuit
Inverter
Type
Typical
designed around the “version 3” ASIPM is shown in
Protection
Current at
Output
Motor
figure 20.
C. ASIPM "Version 2" For Precision Vector and
AC Servo Drives
Rating
(kW)
Current
(ARMS)
CL Warning
(AMPS)
Level (SC)
(Amps)
PS11021
0.2
0.8
5.3
10
PS11022
0.4
1.5
10
20
0.75
3.0
17
38
1.5
5.0
25
40
2.2
7.0
35
60
PS11023
The "Version 2" ASIPM, PS1102X series is
designed for miniature high performance servo and
PS11024
vector drives. In these applications, it is desirable to
PS11025
integrate sophisticated control functions such as a
current limit warning and three phase analog current
feedback. The increased integration simplifies the power
stage and reduces its cost. A simplified power stage also
helps to improve the reliability of complex multi-axis motion
control systems. The “version 2” series of ASIPMs consists
of five types designed for 50 to 750W servo drives or 200 to
2200W high performance inverters. Table 6 summarizes the
key characteristics of these devices.
The packaging selected for the “version 2” ASIPM is
the same low profile, aluminum base IMS utilized for “version
3”. A photo of the “version 2” ASIPM is shown in figure 21.
A block diagram of the “version 2” ASIPM is shown
in figure 22. In order to provide the sophisticated control
functions required for high performance applications, it was
necessary to use a LVASIC for the control and protection of
the low side IGBTs and a HVASIC for the level shift, gate
drive and protection of the high side IGBTs. Like the “version 3”
ASIPM the “version 2” ASIPM has built in boot-strap supply circuits
and P and N side under voltage lock out.
The “version 2” ASIPM power circuit consists of six IGBTs
and six fast recovery free wheel diodes forming a three phase
inverter stage. The input rectifier was omitted because many of the
target applications are DC fed inverter modules for multiaxis
systems. For stand alone inverters a separate matching three
phase rectifier module is available. A photo of the matching rectifier
module is shown in figure 23. The braking circuit was not
Figure 21: PS1102X
“Version 2” ASIPM
Figure 23: Matching Converter
Module for ASIPM
Figure 22: ASIPM “Version 2” Block Diagram
CBU-
CBU+
Gate Drive
UV Lock Out
CBV-
CBV+
Gate Drive
UV Lock Out
CBW-
CBW+
Gate Drive
UV Lock Out
Level
Shift
R
230VAC
S
U
T
S
T
V
Motor
W
Matching Converter
Module - RM**TN-H
Analog
Current
Signal
Processing
CU CV CW
Gate Drive & Short Circuit Protection
Fault Logic
CL
FO
OT
Control UV Protection
UN
VN W N UP
VP
WP
Analog Current Feedback 5V Logic Interface to MCU
GND VD
15V
integrated because the requirements of the target applications range from no brake in the case of regulated,
DC fed, multi-axis systems to very large braking devices in systems with heavy regeneration. A circuit
diagram of the power stage is included in figure 22.
In the “version 2” ASIPM the low side IGBTs are protected from short circuit conditions by circuits
that monitor the current mirror outputs on the IGBT chips. If the current through the device exceeds the SC
level shown in table 6, the IGBT is immediately but softly turned off. The soft turn off is used to help minimize
transient voltages that can occur during an emergency shut down. The SC level is set at about three times
the IGBTs nominal rating. At this current level the IGBT is in imminent danger of being damaged so an
immediate shut down is warranted. If the short circuit protection is activated the module will assert a fault
output signal. The short circuit protection is automatically reset when the fault timer (tFO expires) and the
control input signal of the IGBT involved returns to the off state.
If the current through any of the low side IGBTs or free wheel diodes exceeds the current limit level
shown in table 6, a warning signal will be asserted on the CL output of the module. At the CL level, the
device is not in imminent danger of being damaged so the power devices are not disabled and normal
inverter operation will continue. The CL signal is a warning that is intended to be used by the system control
to either stop inverter operation or attempt output current regulation depending on the requirements of the
application. The current limit warning is derived from the analog current feedback signals described below.
The “version 2” ASIPM has a built in temperature sensor that monitors the base plate temperature
of the module. If the temperature exceeds the OT level specified on the device data sheet, all six IGBTs are
turned off and a fault signal is asserted. The temperature sensor is particularly useful for detecting conditions
such as cooling fan failure, extreme ambient temperatures, improper mounting or heat sink problems.
Normal operation of the module will resume when the base plate cools below the over temperature reset
level. The built in temperature sensor simplifies manufacturing by eliminating the need for mounting and
calibrating external heat sink temperature sensors.
In many high performance applications inverter output current sensors are required for system
control. In order to simplify the power stage design and eliminate the need for hall current sensors, the
“version 2” ASIPM integrates three phase current sensing and provides analog feedback signals
proportional to the inverter output currents.
The feedback signals are generated by sampling the low side arm currents and processing them to
create an analog voltage proportional to the output phase currents. The process for deriving these signals is
illustrated in figure 24. The
current in the low side IGBT
Figure 24: Three phase
and free wheel diode is
analog current feedback
(U,V,W)
converted to a voltage
I
C
using the shunt RS. The
Gate Drive
voltage across RS is then
amplified by amp 1 so that it
VIN
swings ±1.1V when the
Delay
output current is at 200% of
RS
AMP 1
N
the modules IO(RMS) rating.
Vhold
The non inverting input of
AMP 2
amp 1 is supplied with a
+
2.25V reference that sets
+
VC
V0
the zero current output
Chold
voltage (VC0). The zero
current level is shifted up to
VC0 so that the output signal
off
is always positive with
VIN
respect to logic common
on
and
can
be
easily V
HOLD
connected
to
the
microprocessor's
analog
inputs. The output of AMP 1
IC
is connected to a sample
and hold circuit that is
activated by a delayed low
side IGBT gate drive signal.
During the negative half
VC
cycle the phase output
current is reconstructed
from the IGBT current
samples taken on every
high frequency PWM cycle. If gate drive signals are applied to the low side IGBT while its free wheel diode is
conducting the positive half cycle of the output phase current will also be reconstructed. The output of the
sample and hold circuit is buffered by AMP 2 to produce the analog current feedback signal VC. The
performance of the analog current feedback is
shown in figure 25. The “version 2” ASIPM
Figure 25: Three phase analog
provides analog current feedback signals for all
current feedback performance
three output phases.
5
The “version 2” ASIPM has 11
Current Feedback Signal Output Characteristic
microprocessor compatible input and output
signals. All signals are referenced to the
4
common ground of the control power supply
Conditions:
VD=15V, TC= -20 ~ +100C
allowing direct connection to a CPU. Table 7
Worst Case
Error Band
summarizes the ASIPM's input and output V 3
150mV
C
signals. Figure 26 shows the recommended (V)
2
interface circuit for the “version 2” ASIPM. On
and off operations for all six IGBTs in the
Analog signal feedback
ASIPM are controlled by the active low control
1
hold range
inputs. The fault signal and current limit warning
outputs are in an open collector configuration.
0
When a fault or current limit condition occurs
-300
-400
-200 -100
0
100
200
300
400
Load Current (%) Normalized to IORMS(rated) x √2
the respective output turns on and pulls the
Figure 26: ASIPM “Version 2”
Interface Circuit
5V
+
+
15V
5.1KΩ
Table 7: “Version 2” ASIPM Control Signals
ASIPM
VD
Signal Name
Designation
Description
Control Inputs
UP, VP, WP,
UN, VN, WN
Fault Signal
Current Limit
FO
CL
Analog
Current
Feedback
CU, CW, CV
Inputs for controlling on/off
operation of the six IGBTs
in the IPM.
Fault status output signal
Current limit warning
signal
Analog feedback for
output phase currents
5.1KΩ
CPU/DSP
6
UP, VP, W P,
UN, VN, W N
FO, CL
10KΩ
signal line low.
CU, CV, CW
0.1nF
GND
D. ASIPM "Version 1" and “1200V” For compact high
performance general purpose motor drives
The "Version 1" PS1101X and “1200V” PS1201X ASIPMs are designed for compact high
performance general purpose industrial motor drives. These modules have basically the same three phase
analog current feedback, level shifting, and boot strap supply schemes as the “version 2” ASIPM. The main
difference is that shoot through interlock and p-side short
circuit protection are added, multi output fault signaling is
Figure 27: PS1101X
provided, and the power circuits are more complete. These
“Version 1” ASIPM
additional functions make the “version 1” and “1200V”
Table 8: “Version 1” ASIPMs
Type
Typical
Motor
Rating
(kW)
Inverter
Output
Current
(ARMS)
Peak Output
Current at
CL Warning
(AMPS)
Short Circuit
Protection
Level (SC)
(Amps)
PS11011
0.1
0.8
3.1
6.0
PS11012
0.2
1.5
5.8
12.0
PS11013
0.4
3.0
10.8
24.0
PS11014
0.75
5.0
17.3
43.0
PS11015
1.5
7.0
24.7
53.0
Figure 28: PS1201X “1200V” ASIPM
ASIPMs the most complex of all types currently available.
Table 9: “1200V” ASIPMs
Type
Typical
Motor
Rating
(kW)
Inverter
Output
Current
(ARMS)
Peak Output
Current at
CL Warning
(AMPS)
Short Circuit
Protection
Level (SC)
(Amps)
PS12012
0.2
1.0
3.9
14.4
PS12013
0.4
1.6
5.8
14.4
PS12014
0.75
2.6
11.0
26.8
PS12015
1.5
4.0
15.6
38.0
Figure 29: ASIPM “Version 1” Block Diagram
DC Link
Capacitor
Brake Resistor &
Precharge Circuit
P1
B
P2
CBU-
CBU+
Gate Drive SC
Protection
UV Lock Out
CBV-
CBV+
Gate Drive SC
Protection
UV Lock Out
CBW-
CBW+
Gate Drive SC
Protection
UV Lock Out
Level
Shift
R
230VAC
S
U
T
S
T
V
Motor
W
N
Analog Current
Feedback Signal
Processing
CU CV CW
Gate Drive & Short Circuit Protection Logic
Input Signal Conditioning
UP
Analog Current Feedback
VP
W P UN
VN W N
Fault Output Logic
Br
CL FO1 FO2 FO3
5V Logic Interface to MCU
Over Temp.
Control Power UV
and OV
Protection
VDL GND VDH
5V
15V
The “version 1” series consists of five types designed for 100 to 1500W inverters operating from a 240VAC
line. The “1200V” series consists of four types designed for 200 to 1500W inverters operating from a
460VAC line. Tables 8 and 9 summarize the key characteristics of these devices.
These devices also utilize the low profile, aluminum base IMS package design. A photo of the
“version 1” ASIPM is shown in figure 27 and the “1200V” ASIPM is shown in figure 28. A block diagram of
the “version 1” ASIPM is shown in figure 29 and a block diagram of the “1200V” ASIPM is shown in figure
30. Like “version 2” a LVASIC is used for the control and protection of the low side IGBTs and a HVASIC is
used for the level shift, gate drive and protection of the high side IGBTs.
The “version 1” ASIPM’s power circuit consists of six rectifier diodes forming a three phase bridge,
six IGBTs and six fast recovery free wheel diodes forming a three phase inverter stage and a seventh IGBT
and free wheel diode for dynamic braking. A circuit diagram of the power stage is included in figure 29. An
opening is provided in the positive bus for limiting inrush current. The IGBT chips have current mirror
emitters that are used by the module’s internal circuits to provide short circuit protection. The “1200V”
ASIPM is the same except that the three phase rectifier is omitted. The power circuit is shown in figure 30. A
separate matching converter module is available for use with the “1200V” ASIPM.
The gate drive circuits in the “version 1” and “1200V” ASIPMs are powered from a single 15V
control power supply and a 5V logic supply. Both power supplies are referenced to a common ground that is
at the negative DC bus potential. All seven IGBTs are independently controlled with logic level input signals
referenced to the 5V supply. The signals are processed by the low voltage ASIC which provides gate drive
for the low side IGBTs and sends control signals to the HVIC for high side gate drive. The HVIC provides
level shifting and gate drive for the high side IGBTs. Built in charge pump circuits supply power for the high
side gate drive circuits eliminating the need for separate isolated power supplies.
In the “version 1” and “1200V” ASIPMs all six IGBTs are protected from short circuit conditions by
circuits that monitor the current mirror outputs on the IGBT chips. If the current through the device exceeds
the SC level shown in tables 8 and 9, the IGBT is immediately but softly turned off. If the short circuit
protection is activated on a low side IGBT, the module will assert an FO1 fault output signal. The short circuit
protection is automatically reset when the control input signal of the IGBT involved returns to the off state.
Figure 30: ASIPM “1200V” Block Diagram
CBU-
CBU+
CBV-
CBV+
CBW-
CBW+
B
Gate Drive SC
Protection
UV Lock Out
P
Gate Drive SC
Protection
UV Lock Out
Gate Drive SC
Protection
UV Lock Out
PhotoCouplers
R
460VAC
S
U
T
S
T
Motor
V
W
N
Matching Converter
Module - RM**TN-2H
Analog Current
Feedback Signal
Processing
CU CV CW
Gate Drive & Short Circuit Protection Logic
Input Signal Conditioning
UP
Analog Current Feedback
VP
W P UN
Fault Output Logic
VN W N
Br
CL FO1 FO2 FO3
5V Logic Interface to MCU
OT
Control
Power UV
and OV
Protection
VDL GND VDH
5V
15V
If the current through any of the low side IGBTs or free wheel diodes exceeds the current limit levels
shown in tables 8 and 9, a warning signal will be asserted on the CL output of the module. At the CL level
the power devices are not disabled and normal inverter operation will continue.
If input on signals are asserted for both IGBTs in the same arm as if to cause a shoot through
condition, the module will block the signals, immediately turn off the involved devices, and assert an FO1
fault signal. The shoot through interlock provides an extra level of protection against erroneous input signals
caused by noise or controller malfunctions. Normal operation will resume automatically after both of the
involved input signals have been cycled.
The “version 1” and “1200V” ASIPMs have built in temperature sensors that monitor the base plate
temperature of the module. If the temperature exceeds the OT level specified on the device data sheet, all
seven IGBTs are turned off and an FO3 signal is asserted.
If the ASIPMs main 15V control supply voltage is under the data sheet specified UV level, over the
specified OV level or if the 5V logic power supply is under
its specified UV level, all six IGBTs will be disabled and an
Figure 31: ASIPM “Version 1”
FO2 fault signal will be asserted. If any one of the high side
and “1200V” Interface Circuit
charge pump supplies drops below its UV level the
ASIPM
+
+
associated IGBT will be turned off. Normal operation will
VDH
5V
15V
resume as soon as the voltages reach the specified reset
VDL
5.1K
5.1K
5.1K
CPU/DSP
7
UP, VP, W P,
UN, VN, W N,
Br
FO1, FO2,
FO3
CL
CU, CV, CW
0.1nF
Table 10: “version 1” and “1200V” ASIPM
Control Signals
Signal Name
Designation
Description
Control Inputs
UP, VP, WP,
UN, VN, WN, Br
Fault Signals
Current Limit
FO1, FO2, FO3
CL
Analog
Current
Feedback
CU, CW, CV
Inputs for controlling on/off
operation of the seven
IGBTs in the IPM.
Fault status output signals
Current limit warning
signal
Analog feedback for
output phase currents
10KΩ
GND
levels. Hysteresis is built into the UV and OV trip logic in order to prevent oscillations.
The “version 1” and “1200V” ASIPMs have 14 microprocessor compatible input and output signals.
All signals are referenced to the 5V logic power supply allowing direct connection to a CPU. Table 10
summarizes the ASIPM's input and output signals. Figure 31 shows a typical external interface circuit.
VI. CONCLUSION
ASIPMs (Application Specific Intelligent Power Modules) consisting of a combination of power
devices, low voltage ASICs and high voltage ASICs are effective for simplifying and miniaturizing the power
section of small motor drives. Maximum system benefit is achieved when the package design and integrated
functions are optimized to meet the requirements of specific applications. This paper has outlined these
system considerations and presented a series of examples demonstrating the effectiveness of this
technology.
VII. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
G. Majumdar, et al. "A New Generation High Speed Low Loss IGBT Module", ISPSD, May 1992
J Yamashita, et al. "A Study on the Short Circuit Destruction of IGBT's" , ISPSD, May 1993
G. Majumdar, et al. "A New Generation High Performance Intelligent Module" PCIM Europe May
1992
TM
Powerex "IGBTMOD and Intellimod Application and Technical Data Book" Second Edition,
PUB#9DB-200, 1998
E. Motto, et. al. "A New Generation of Intelligent Power Devices for Motor Drive Applications" IEEE
IAS Conference October 1993
E. Motto "Protecting High Current IGBT Modules From Over Current and Short Circuits" HFPC
Conference May ,1995
John Donlon, et. al. "A New Converter/Inverter System for Windpower Generation Utilizing a New
600 Amp, 1200 Volt Intelligent IGBT Power Module" IEEE IAS Conference October 1994
E. Motto, et. al. “A New Intelligent Power Module With Microprocessor Compatible Analog Current
Feedback, Control Input, and Status Output Signals”, 1996 IEEE IAS Conference Proceedings
Eric R. Motto “A New Ultracompact ASIPM with integrated HVASIC” 1997 Powersystems World
conference proceedings
G. Majumdar et. al. “Novel Intelligent Power Modules for Low-Power Inverters” 1998 IEEE PESC
Proceedings
S. Noda et. al. “A Novel Super Compact Intelligent Power Module” 1997 PCIM Europe conference
proceedings