IEEE TRANSACTIONS ON MAGNETICS, VOL. 48, NO. 9, SEPTEMBER 2012
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Self-Enabled “Error-Free” Switching Circuit for Spin Transfer Torque
MRAM and Logic
Yahya Lakys
, Wei Sheng Zhao , Thibaut Devolder , Yue Zhang , Jacques-Olivier Klein
Dafiné Ravelosona , and Claude Chappert
,
IEF, Université Paris Sud, Centre d’Orsay, F-91405 Paris, France
CNRS, UMR 8622 91405 Orsay, France
Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to
build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g.,
A at 65 nm), simple switching
scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate,
which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing “error-free” as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power
efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm
design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area,
power, and speed performance.
Index Terms—Error-free, high reliability, low power, magnetic circuits, PVT variations, stochastic switching.
I. INTRODUCTION
T
HE hybrid integration of spin-based components with
CMOS technologies has proven its effectiveness [1]–[4].
Based on spin transfer torque (STT) switching approach [5],
[6], a spin-polarized current
higher than a threshold
value
allows switching the magnetic tunnel junction (MTJ),
storage element of STT-MRAM [7], [8]. MTJ is mainly composed of three layers (see Fig. 1): two ferromagnetic (FM)
layers and one oxide barrier (e.g., MgO). For practical applications, the magnetic anisotropy of one FM layer is fixed and
the other is free to get binary states. Many industrials have
already considered the integration of STT-MRAM into their
products thanks to its nonvolatility, low power consumption,
and hardness to radiations. Although STT switching has proven
sub-nanosecond potential [9], the switching operation of STT
is stochastic and some desired data may not be stored correctly
on the MTJs [10]. The duration of the reversal events can
vary significantly from one event to the next, with a standard
deviation almost as large as the average switching duration
[10] and sigmoidal switching distributions with exponential
tails [11], as exemplified in Fig. 2, for a MgO barrier based
MTJ [12]. This results from unavoidable thermal fluctuations
of the magnetization [11], which randomly interfere to activate
or slow down magnetization reversal.
According to the experimental measurements shown in Fig. 2
and the Néel-Brown model (1)–(3) [13], increasing
value
or adding extensive margins on the driver pulse duration
are the most efficient solutions to improve switching probability
and tolerate the high process voltage temperature (PVT) variations [8], [14], [15]. Another known problem of STT-MRAM is
the erroneous switching resulting from a low read-current
Manuscript received January 12, 2012; revised March 09, 2012; accepted
April 06, 2012. Date of publication April 16, 2012; date of current version August 21, 2012. Corresponding author: W. S. Zhao (e-mail: weisheng.zhao@upsud.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMAG.2012.2194790
Fig. 1. (a) Vertical structure of an MTJ nanopillar composed of CoFeB/MgO/
CoFeB thin films. (b) Spin transfer torque switching mechanism: the MTJ state
changes from parallel (P) or “0” to anti-parallel (AP) or “1” as the positive dior
, on the contrast, its state will return to
rection current
.
P state with the negative direction current
[16]. While sensing the states of MTJs,
flowing through
them may change the stored data. These issues limit its potential to obtain a good trade-off among power, area, and speed
performance for memory and logic applications.
(1)
(2)
(3)
the driver pulse duration,
where is the attempt period,
the Boltzmann constant, the temthe critical current,
the energy barrier,
the saturation magnetizaperature,
the permeability in free space,
the coercive field,
tion,
the volume of free layer.
and
In this paper, we present a self-enabled “error-free” switching
circuit to overcome both the power and reliability issues of conventional circuits. The stochastic behaviors of STT switching
mechanism are exploited as an advantage instead of being
avoided.
0018-9464/$31.00 © 2012 IEEE
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Fig. 2. Stochastic behaviors of STT switching [11], high
faster speed and higher switching probability.
IEEE TRANSACTIONS ON MAGNETICS, VOL. 48, NO. 9, SEPTEMBER 2012
value induces
II. THE SELF-ENABLED “ERROR-FREE” SWITCHING CIRCUIT
Fig. 3(a) shows the conventional STT switching circuit.
Each MTJ is associated with one transistor addressed by
bit lines (e.g., BL0). An external signal “Enable” controls
the activation or deactivation of circuit to store the “Input”
data into the MTJ in nonvolatile mode [17]. Fig. 3(b) shows
the corresponding operations. As shown previously, the STT
switching is stochastic and the nanoscale size of MTJ leads
to its property sensitive to PVT variations, state change of
MTJ may happen at any moment inside the fixed write pulse
(e.g., during
or
). Thereby a sufficiently long
duration of “Enable” is required to ensure expected switching
operations. This results in unnecessary energy loss, slow speed,
and shorter lifetime of oxide barrier. Using higher
is
another possible solution, which is able to keep fast speed
by sacrificing greatly the area efficiency.
Fig. 4(a) and (b) show respectively the proposed self-enabled
circuit schematics and its corresponding operations. A sense
amplifier (S.A) associated to the MTJ detects its state and outputs the data in logic level. The “self-enable” signal depends on
the comparison result between “Output” and “Input” data. For
instance, it becomes “ON” as “Output” is different from “Input”
data. The fixed long writing pulse is replaced by a sequence of
short duration
including both switching and sensing operations. Thanks to the stochastic behaviors of STT magnetic
switching, the state of MTJ can be changed just after one short
write pulse, as shown in Fig. 4(b). After that, “self-enable” is
set to “OFF” and no current flows through the MTJ. Different
from a self-adaptive write circuit designed for memristor [18],
the proposed circuit takes benefits from the stochastic behaviors
of STT switching. Moreover, periodic sensing is used to obtain
the STT-MRAM storage in logic level for the comparison with
“Input” data. This is due to the relatively low tunnel magnetoresistance (TMR) or
ratio of MTJ (e.g., 150%–250%)
[1]. The frequency of read operations equals normally to the
global clock (e.g., 500 MHz).
This switching circuit with self-enable mechanism presents
a number of advantages. Firstly, it allows “error-free” as the
switching operation becomes fully deterministic instead of stochastic behaviors caused by the intrinsic spin transfer torque and
PVT variations. As the write pulse duration is shortened and the
number of switching operation is also reduced, the lifetime of
Fig. 3. Conventional STT switching circuit and strategy with sufficiently long
driver pulse duration. (a) Circuit schematics. (b) Fixed duration for input and
enable signals.
Fig. 4. Self-enabled “error-free” switching circuits and strategy with adaptive
driver pulse duration (a) Scheme of proposed switching circuit (b) Varied duration for “self-enable” signal.
oxide barrier can be greatly improved. Compared with the conventional solution shown in Fig. 3, there are some short read
LAKYS et al.: SELF-ENABLED “ERROR-FREE” SWITCHING CIRCUIT FOR SPIN TRANSFER TORQUE MRAM AND LOGIC
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TABLE I
PARAMETERS AND VARIABLES PRESENT IN THE FITTING FUNCTIONS
the conventional sense/switch circuit area for STT-MRAM. As
the switching circuits are often widely shared among many elements in memory array, this area overhead can be negligible
[15].
III. SIMULATION RESULTS
Fig. 5. Detailed scheme of self-enabled switching circuit. (a) Pre-charge
sensing amplifier (PCSA). (b) Sequential sensing and combinational comparison logic circuit.
operations in this new switching strategy. As mentioned above,
a read current may erroneously switch the state of MTJ, but
the “self-enable” signal will become automatically “ON” in this
case to correct this error. Thereby, this proposed circuit provides
evident high reliability without additional negative effects.
Secondly, high power efficiency can be achieved by eliminating completely the additional power to tolerate the PVT variations and stochastic behaviors. Another power saving comes
from the reduced switching numbers as the “self-enable” signal
is activated only while the stored data is different from “Input”
data. On average, half of the switching operations can be economized, but exact power saving depends greatly on applications.
Note that, for asynchronous applications, in addition to power
saving, better operating speed could also be expected.
Fig. 5 presents the detailed self-enable circuit. As the “selfenable” operation is driven based on a number of sensing operations, a synchronized low-power sense amplifier based on
pre-charge principle (PCSA) [19] is used in the circuit to read
the data stored in the MTJs. It demonstrates a good tradeoff between sensing power and speed. One can use the complementary
MTJs to present one storage bit as shown in [19] to obtain fast
speed and good sensing reliability for logic circuits. In order to
get the minimum cell area for memory applications, we need one
MTJ to present one storage bit [see Fig. 5(a)] and the reference
, can be obtained by a larger MTJ cell
based on the same fabrication process [15]. Fig. 5(b) shows the
combinational logic circuit for input and output comparison. It
includes 24 minimum size transistors and represents
% of
By using CMOS 65 nm design kit [21] and a CoFeB/MgO/
CoFeB STT-MTJ compact model based on experimental measurements [13], [22], [23], we demonstrate by simulation the
functional behaviors and evaluate the performances of this selfenabled circuit. Table I presents the major parameters and variables used in the mixed simulation. Fig. 6 shows the transient
simulations; when input changes state [see Fig. 6(a) (1)] the
writing circuit is enabled [see Fig. 6(f) (2)], a current pulse is
generated [see Fig. 6(e) (3)] and remains available until the next
sense operation [see Fig. 6(g) (4)]. As the switching operation
[see Fig. 6(c) and (d) (5)] is finished, i.e., “Output” “Input” [see
Fig. 6(b) (6)], the writing circuit is disabled at the next sensing
operation [see Fig. 6(f) (7)] otherwise it will be enabled for another additional self-enabled period (i.e.,
) as long as the
value of “Input” data does not change. The “self-enable” signal
is closed during periodic sensing to avoid the interference between write/sense currents [see Fig. 6(f) and (g) and Fig. 4(b)].
Fig. 6(c) and (d) show that in our design the switching of two
MTJs occurs after 2.8 and 4.5 ns, respectively, adapted to the
stochastic behaviors of spin transfer torque switching.
The simulations show also that the required switching current
is as low as 139 A during at maximum
[i.e., 16
ns, see Fig. 6(f) (7), (8) or (9)]; this results in high power efficiency
Tera-OPS/Watt, 87% better than that of conventional STT-MTJ switching circuit.
IV. CONCLUSION
In this paper, we presented a new design of self-enable “errorfree” switching circuit for STT-MRAM storage element. Combinatory logic circuit is added to provide self-enabling operation based on sequential sensing operation. Compared to conventional STT switching circuits, this new design presents important improvements in terms of switching power and reliability, which are the critical issues limiting the wide application of STT- MTJ based memory and logic circuits [7], [8],
[24], [28]. By using CMOS 65 nm design kit and a precise
STT-MTJ compact model, hybrid MTJ/CMOS simulations confirm its reliable switch/sense operations and higher power efficiency than conventional switching circuits with low area overhead. This circuit can be also extended to other emerging nonvolatile storage devices suffering from stochastic behaviors like
resistive switching memories [29].
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IEEE TRANSACTIONS ON MAGNETICS, VOL. 48, NO. 9, SEPTEMBER 2012
Fig. 6. Transient simulation of the self-enabled switching circuit. (a) Input signal. (b) Output signal. (c) State of
. (d) State of
. (e) MTJ writing
, which is self-enabled. (f) Self-enabled signal to control the read/write operation of STT-MRAM storage elements. (g) Sensing signal, its frequency
current
equals normally to the global clock.
ACKNOWLEDGMENT
The authors wish to acknowledge the support from the
French national projects CNRS PEPS NVCPU, ANR-MARS,
and NANOINNOV SPIN.
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