The 22nd Microelectronics Workshop
Development Status of JAXA
Point-Of-Load DC/DC converter
(Point-Of-Load:POL)
Electronic Devices and Materials Group
Aerospace Research and Development Directorate
Japan Aerospace Exploration Agency
Yoshiyuki YANO ○, Naomi IKEDA , Satoshi KUBOYAMA
October 16,2009
1
¾Background
¾Target specification and user requests
¾ Approach to the solution
¾Development status of Control-IC for POL
¾Development status of MOSFET for POL
¾Result of POL evaluation
¾Development plan of POL
¾Conclusion
Evaluation Board
Prototype
EM
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Background
Jaxa has developed 64bit MPU and 36Mbit burst SRAM and is
developing SOI ASIC and FPGA for space applications. These
devices and recent space systems require power-supply with
following performance.
- Low output voltage 1.2V to 3.3V
- High output current >3A
- Low voltage drop
at the load
- Fast load response
-- Solution --
¾Point Of Load (POL) Power Supply
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Power supply system with POL
Circuit Board
POL
Isolated
•FPGA
DC/DC
Converter
•5V Logic etc.
Isolated
DC/DC
POL
Converter
•MPU
Spacecraft
Power Bus
Isolated DC/DC
converter
POL type DC/DC
converter
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64bit MPU
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Target specification for POL
- Non Isolated synchronous buck converter
- High efficiency - more than 90%
- Output voltage range : 3.3V to 1.2V
- Output power : 7W or 3A max
- Input range : 4.5V to 16V DC
- Adjustable output voltage
- Over current limiter
- Under Voltage Lock Out(UVLO) with hysteresis
- Output overvoltage protection
- External on/off control
- TID: > 1kGy(Si) (100krad(Si))
TID: Total Ionizing Dose
- SEE(LETth): > 64MeV/(mg/cm2)
LET: Liner Energy Transfer
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User requests to POL
¾Compact size and light weight
- Installation near target device(MPU, FPGA, etc.)
- Small footprint
¾Low profile
64bit MPU
- Double-sided mounting on circuit board
¾High efficiency
- Less power loss
- Easy heat spreading design
POL
（prototype）
¾High reliability
- Ensure reliability of power-supply systems
Circuit board
ＭＰＵ
POL
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Approach to the solution for requests 1/4
¾Compact size and light weight
- Bare chip mounting of Control-IC,MOSFETs and diodes
- Reduced external circuit elements (resistors, capacitors)
- Down sized output inductor
- Double-sided element mounting structure
15mm
19mm
- Small size : 19 x 15mm (length and width)
- Light weight: < 10g
- Required only input and output capacitors(optional)
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Approach to the solution for requests 2/4
¾Low profile
- Single multilayered ceramic substrate
- Double-sided element mounting structure and optimized
element placement
A-side: low profile chips, B-side: taller profile elements
6.0mm（typ.）
Only 6 mm (typ.) of height
Header
A-side
Control IC
MOSFET
C
R
Lead
Multilayered ceramic substrate
C
Ferrite Core
C
B-side
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Approach to the solution for requests 3/4
¾High efficiency
- Synchronous rectification PWM Control-IC
- Logic level input n-ch MOSFET(Vth=1 to 2V)
- Fly wheel diode
- Optimized output inductor : Conductor thickness, winding
pattern layout
¾Efficiency: > 90%
- 91%: Vin=10V, Vout=3.3V, Iout=2.0A
- Up to 94%: Vin=5V, Vout=3.3V, Iout=1.5A
(Test result of evaluation board)
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Approach to the solution for requests 4/4
¾High reliability
- All electric parts in hermetic sealed package
- Screening and QT in accordance with JAXA-QTS-2020B
- Output inductor: No magnetic wires and micro-soldering
- Operating temperature range: -55oC to 125oC(Tc)
Tc: case temperature
- Shock: 1500G, 0.5 ms, 6 axis
- Vibration： 20G, 3 axis, half-sine
- QT will be completed in FY 2010
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Block diagram of POL
MOSFET
Control-IC
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Target specification for Control-IC
¾Synchronous rectification PWM Control-IC
- 4.5V to 30V input and 1.2V to 3.3V output voltage range
- Protection features: Soft start, Over current limiter, Under
voltage lock out(UVLO), Output overvoltage protection
- Automatic resume operation from protection mode
(no reset signal required)
- TID: > 1kGy(Si) (100krad(Si))
TID: Total Ionizing Dose
2
SEE:SIgle Event Effects(SET,SEL)
- SEE(LETth): > 64MeV/(mg/cm )
LET: Liner Energy Transfer
Control-IC (Prototype)
die size 2.6 x 2.3mm
Manufactured by Fuji Electric Device Technology Co.,Ltd.
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Control-IC(Evaluation sample) SEE results
¾Condition (performed at RIKEN)
- Bias: Vin=5V, Vout=3.3V, output current=3.3A
- Ion: Kr (LET=33 MeV/(mg/cm2)), range=84μm
¾Test results
- SET was observed, which lead to temporal drop of Vout
- Output shutdown and abnormal output that require reset were not
SET：Single Event Transient
observed
Output voltage drop
Vout 1V/div
Effect of SET
HI-Side MOSFET gate
5V/div
LO-Side MOSFET gate
5V/div
10μsec/div
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Cause of SET
R
R
Vref
C
VER
－
R
Vref
＋
Error AMP
－
PWM
＋
VER
OSC
PWM
OSC
Vref: temporal drop
200mV/div
VER : spiking
reduced PWM duty
2μsec/div
SET: Vref output
Vout : temporal drop
- Reflect measures to SET in control-IC design and
eventually achieve tolerance to SET.
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Target specification and test results for MOSFET
¾n-ch trench type MOSFET for POL
Parameter
Unit
Target specification
VDSS
V
min
30
VGS
V
-
±10
VGS(th)
V
RDS(on)
mΩ
max
Qgs
nC
Qgd
nC
TID
-
SEE
-
GATE
Condition
-
40
-
±10
Vds=Vgs, Id=1mA
typ
1.6
22
Id=8A, Vgs=4.5V
typ
15.4
max
20
typ
10.2
max
26
Vgs=4.5V, Vds=15V,
Id=8A
typ
7.5
1.0 to 2.0
Id=1mA
test result
No significant changes in BVdss, Idss, and Vth
hardened
-
see sheet 18
SOURCE
Trench type power MOSFET (Prototype)
die size: 2.5 x 3.0 mm
Manufactured by Fuji Electric Device Technology Co.,Ltd.
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Planner and trench structure
Trench type MOSFET
Planar type MOSFET
source
p+
gate
n+
source
gate
n+
p+
p+
n+
p+
p-
p-
p-
p-
n-
n-
n+
n+
ID current path
drain
drain
Planer type: 2SK2806
- Ron: 22mΩ
- Qgs: 20nC
Equivalent size chip
- Qgd: 26nC
Low-voltage, low Ron,
compact size
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ID current path
Trench type
- Ron: 13mΩ
- Qgs: 12nC
- Qgd: 8.9nC
-57%
-17%
-53%
Trench type MOSFETs are
more suitable
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Efficiency with planar and trench
Efficiency[%]
Efficiency[%]
Efficiency (Vout=3.3V)
MOSFET prototype
MOSFET prototype
Load Current [A]
Load Current [A]
2SK2808 : Commercial MOSFET (Planar type)
Prototype MOSFET : Specially designed for the POL(Trench Type)
Better efficiency was obtained by using prototype MOSFET
VIN=6V : +0.5%
VIN=15V : +1.1%
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SEE and TID test result for prototype MOSFET
¾SEE test result (performed at TIARA)
- Kr (surface LET=40 MeV/(mg/cm2)):
- No increase either in IDS or IGS was observed under
VDS=15V and VGS=-5V
- Xe (surface LET=69 MeV(mg/cm2)):
- No increase either in IDS or IGS was observed under
VDS=15V and VGS=-2.5V
¾TID test result
- No significant changes in BVDSS, IDSS, and Vth were
observed after 100krad irradiation.
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Test result for POL evaluation board
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Development schedule of POL
FY2007
FY2008
FY2009
FY2010
Element evaluation
Control IC
Qualification Test(QT)
Element evaluation
MOSFET
Qualification Test(QT)
Examination
POL
Element evaluation
BBM
EM
FM
Qualification Test(QT)
QT of POL will be completed in FY 2010
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Conclusion
¾ Features of POL DC/DC converter
- Non isolated buck converter
- More than 90% Efficiency
- Preset output voltage: 3.3V, 2.5V, 1.8V, 1.5V, 1.2V
- Adjustable output voltage: 1.2V to 3.3V
- 4.5V to 16V input voltage range
- 7W or 3A max output
- Soft start, Over current limiter, UVLO, Output over voltage
- Hermetic Flat-Package, size: 19 x 15 x 6 mm(typ.)
- Weight : > 10 g
- Operation temperature range : -55oC to 125oC (Tc)
- Shock:1500G , vibration：20G
- Radiation hardened
- QCI based on JAXA-QTS-2020B (Screening and group A,B,C,D)
- QT will be completed and qualified in FY 2010
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Appendix
Package Outline
1
26
13
14
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Appendix
Pin assignment
No
Pin code
Pin function
1-4
RTN
Power return
5-8
INPUT
DC Power input
9
N/A
-
10
ENABLE
External on/off control input
11
OVER CURRENT
Over current adjustment
12
SOFT START
Capacitor connection pin for soft start
13
CASE
Frame ground
14
SIG RTN
Signal return
15
SYNC IN
External clock input
16
ADJUST
Output voltage adjustment
17
OVER VOLTAGE
Output over voltage protection input
18-23
OUTPUT
Power output
24-26
RTN
Power return
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