1
Can RSFQ Logic Circuits be Scaled to
Deep Submicron Junctions?
Alan M. Kadin, Cesar A. Mancini, Marc J. Feldman, and Darren K. Brock
Abstract—Scaling of niobium RSFQ integrated circuit
technology to deep submicron dimensions (linewidths of 300 nm
or less) should permit increased clock rate (up to 250 GHz) and
increased areal density of Josephson junctions (up to 1 million
junctions/cm2), without the need for external shunt resistors. It is
shown how existing circuit layouts can be scaled down to these
dimensions, while maintaining the precise timing essential for
correct operation. Additional issues related to the practical
realization of such circuits are discussed, including effects of selfheating and models for the generation and propagation of sub-ps
single-flux-quantum pulses.
Index Terms—High-speed electronics, integrated circuits,
Josephson junctions, superconducting devices.
I. INTRODUCTION
T
HE basis for the phenomenal progress of silicon digital
electronics has been scalability; smaller and smaller
transistors have allowed a seemingly inexorable increase
in circuit density and clock speed for CMOS integrated
circuits. In recent years, a complete technology of niobium
(Nb) superconducting integrated circuits has matured to the
point where complex digital circuits with thousands of
Josephson junctions can be routinely fabricated at established
foundries with high uniformity and yield [1]-[3]. Most of
these circuits have been based on Rapid Single Flux Quantum
(RSFQ) logic, in which the information is carried in the
presence or absence of single-flux-quantum (SFQ) voltage
pulses generated by damped Josephson junctions [4]-[6]. The
industry standard has been based on a rather modest 3-µm
linewidth; even so, complex Nb RSFQ circuits operating (in
liquid helium at 4.2 K) at clock speeds in excess of 20 GHz
have become routine [7]-[10]. Furthermore, scaling to smaller
dimensions should yield dramatic increases in speed and
circuit density. Indeed, simple RSFQ circuits using small
numbers of deep submicron junctions have been responsible
for probably the fastest digital circuits demonstrated in any
technology, with speeds above 700 GHz [11]. The major
Manuscript received September 18, 2000. This work was supported in
part at the University of Rochester by NASA JPL contract #961638 under
the HTMT project, and at HYPRES by ONR contract #N00014-00-0C-0024
A.M. Kadin was with the University of Rochester, Department of
Electrical and Computer Engineering, Rochester, NY 14627 USA, and is
now with HYPRES, Inc., 175 Clearbrook Road, Elmsford, NY 10523 USA
(e-mail kadin@hypres.com).
C.A. Mancini was with the ECE Dept., University of Rochester, and is
now with Motorola, Inc., Austin, TX 78729 USA (e-mail cesar.mancini
@motorola.com).
M.J. Feldman is with the ECE Dept., University of Rochester (e-mail
feldman@ece.rochester.edu).
D.K. Brock is with HYPRES, Inc. (e-mail brock@hypres.com).
superconducting electronics foundries are now in the process
of moving to smaller dimensions to take advantage of these
improvements [12], [13].
In this paper, we review the basic scaling laws for Nb
Josephson junctions in RSFQ circuits, and extend them to the
other key circuit elements: inductors and resistors. In this
way, we show how complete circuit layouts can be scaled
down in a way that preserves the relative timing of SFQ
pulses, which of course is essential for the proper high-speed
operation of these circuits. Furthermore, we show how a
major change in circuit design occurs when the scale reduces
below about 0.3 µm, since external resistors are no longer
needed to damp the junctions; the intrinsic damping is
sufficient. Finally, we address several critical issues in the
performance of circuits based on these deep submicron
junctions. These include issues of self-heating in bias resistors
and junctions, alternative models for these junctions, and
resistive losses above the energy gap of Nb. Although other
superconducting materials (such as NbN and YBCO) that
operate at somewhat higher temperatures will be briefly
discussed, the primary focus is on scaling the well-established
Nb technology for circuits that operate at 4-5 K.
II. SCALING OF JOSEPHSON JUNCTIONS
The basic scaling laws for Josephson junctions in RSFQ
circuits are well known [5], but we review them here in order
to point out some important practical issues. The junction
fabrication process defines the thickness of the tunneling
barrier d ~ 1-2 nm, which in turn determines the critical
current density Jc, which is exponentially dependent on d.
Once Jc is fixed, there are two key constraints on the junction
scale a:
1) The junction must be large enough to avoid thermal
fluctuations, and
2) The junction should be smaller than the Josephson
penetration depth λJ.
For a large-scale digital integrated circuit, the first constraint
assures that the bit-error rate is sufficiently small, since the
thermal fluctuation current is proportional to the absolute
temperature T. For junctions biased near the critical current Ic
at a temperature of 4.2 K, this constraint corresponds to a
minimum value of Ic ≈ 100 µA [4]. So as the junction scale is
reduced, Jc should be correspondingly increased in order to
maintain this same value of Ic = 100 µA for the minimal-size
junction. The scaling relation from this then takes the form
a≈
100 µA J c
(1)
The second constraint assures that the supercurrent flows
uniformly within the area of the junction, so that for any given
2
100
Nb Junction Scales for Ic =100 µA
10
λJ
a , λJ
1
a
0.1
100
1,000
10,000
100,000
Critical Current Density J c [A/cm 2]
value of Jc, the total Ic will scale with the area. While not
Fig. 1. Scaling of minimum junction scale and Josephson penetration depth
with critical current density for Nb Josephson junctions, assuming a
minimum critical current Ic ≈ 100 µA.
essential, this constraint makes junction design and layout
much easier. There are some applications within RSFQ
technology for long Josephson junctions larger than λJ (e.g.,
for high-precision clock generators [14]), but most junctions
in RSFQ logic should be in the small junction limit. The value
of λJ is given by the standard expression [6]
Φ0
(2)
λJ ≈
,
2π µ 0 ( 2 λ + d ) J c
where λ is the magnetic penetration depth of the superconductor, Φ0 = h/2e is the flux quantum, and µ0 = 1.26 µH/m
is the permeability of free space. Taking a typical value of
λ = 90 nm for Nb films used in integrated circuits, one
obtains
λJ ≈
1500 µA / J c .
(3)
Comparing this to Eq. (1), note that both a and λJ have the
same scaling dependence on Jc (also plotted in Fig. 1), and
that λJ ≈ 4a for any junction scale. This means that there is
always a wide range of values of Ic above the minimum value
of 100 µA that can be used in the design of RSFQ circuits.
It is also worth noting that this relationship between a and
λJ is not assured for other materials and operating
temperatures. If one considers NbN operating at T ≈ 9-10 K,
then the minimum value of Ic should scale up to 200 µA
(double that for 4-5 K). Furthermore, NbN films in multilayer technologies are typically somewhat disordered on an
atomic level [15], leading to an enhanced value of
λ ≈ 270 nm. Taken together, these give λJ ≈ 1.5a for any
value of Jc. Although the relation λJ > a is still maintained,
the range of critical currents above the minimum is greatly
reduced. This is even more the case for a high-temperature
superconductor (HTS) such as YBCO, where an operating
temperature of 40-50 K leads to a minimum Ic ~ 1 mA, and a
typical value of λ ~ 220 nm leads to the relation λJ ≈ 0.8a.
This may complicate the design of HTS RSFQ circuits.
The other critical consideration for Josephson junctions in
RSFQ circuits is that they be sufficiently damped to prevent
hysteresis upon exceeding the critical current, so that the
junction returns to the zero-voltage state immediately after an
SFQ pulse. This is generally analyzed in terms of a shunted
junction model (RSJ or CRSJ), in which the ideal Josephson
junction is shunted with a linear capacitance C and a linear
resistance R [6]. The junction itself can be characterized as a
nonlinear inductor of magnitude given by the Josephson
inductance LJ = Φ0/2πIc. Such a parallel network has two
characteristic times, RC and LJ/R. If the former time is larger,
the junction is underdamped; in the other limit, it is
overdamped. The dimensionless damping parameter βC is
often used:
2πI c R 2 C
RC
,
(4)
βc = Q2 =
=
Φ0
LJ / R
where Q is the usual quality factor of the parallel linear LCR
resonator. Critical damping (βc ~ 1) is typically preferred.
For an ideal superconductor-insulator-superconductor (SIS)
tunnel junction, the effective shunt resistance is given by the
normal-state tunneling resistance Rn, related to the critical
current Ic via the general relation (well below the
superconducting critical temperature Tc) IcRn = π∆/2e, where
2∆ is the superconducting energy gap. The intrinsic damping
parameter β c0 can then be written in terms of intrinsic junction
parameters in the form
2π ( I c R n ) 2 C ′
β c0 =
,
(5)
Φ0 Jc
where the specific capacitance C' = C/A = ε/d (where ε is the
permitivity of the insulator) is only very weakly
(logarithmically) dependent on Jc. Neglecting this, the key
scaling relation is given by β c0 ∝ 1 / J c ∝ a 2 .
Because of the very small insulating layer (d~ 2 nm) of the
tunnel junction geometry, Josephson junctions are generally
highly underdamped with β c0 >> 1. However, one can then
add an additional shunt resistance R s ≈ R n / β c0 in parallel
with the junction, in order to achieve critical damping (βc~1)
for the effective combined resistance.
For the widely used Nb/AlOx/Nb trilayer tunnel junctions,
C' ≈ 50 µF/cm2 and IcRn = 2.4 mV, yielding the dependences
(also plotted in Fig. 2)
β c 0 ≈ (100 kA / cm 2 ) / J c ≈ 10 a 2 [µm].
(6)
For standard fabrication with a = 3 µm, this corresponds to Jc
= 1 kA/cm2 and βc0 = 100. But for a ≈ 0.3 µm (Jc ≈ 100
kA/cm2), βc0 = 1 even without a shunt resistor Rs. When one
takes into account the weak dependence of C' on Jc, this
Junction Scale a [µm]
1000
10
3
1
0.3
100
βC0
10
1
100
300
1000
3000
10000
30000
100000
Current
Density
Jc [A/cmfor2] unshunted Nb
Scaling Critical
dependence
of damping
parameter
Fig. 2.
Josephson junctions.
3
crossover occurs for a slightly smaller scale, for a ≈ 0.25 µm,
but the general trends remain virtually unchanged.
For RSFQ circuits, the high-frequency performance is
determined by the pulsewidth of the SFQ pulse generated by a
Josephson junction with β c<≈1. The time-integral of the
voltage pulse is Φ0 =2 mV-ps, the pulse height is Vc ≈2IcR,
and the pulsewidth is τ ≈ Φ0/2IcR [6]. For an intrinsic Nb
junction giving the ultimate performance, Vc ≈ 4.8 mV and
τ ≈ 0.4 ps. For a larger shunted junction with βc ≈ 1,
2I R
1.5mV
Vc ≈ c n ≈
; τ ≈ 0.4ps β c 0 ≈ 1.3ps × a[µm]. (7)
a [µm]
β c0
Of course, for a < 0.3 µm, external shunting can no longer be
used to improve performance; shunting can only broaden the
pulse. The scale dependence of τ is plotted in Fig. 3.
III. SCALING OF RSFQ CIRCUITS
Josephson junctions are the central elements of RSFQ
circuits, but they are not the only elements. Equally important
are inductors and resistors. As we will show below, these can
also be scaled down in size in a consistent way. In this case,
the speed of complex RSFQ circuits should scale with the
reciprocal pulse width 1/τ. In particular, it is a rough rule of
thumb that the maximum clock frequency of a synchronous
RSFQ circuit is approximately
75 GHz
1
≈
fc ≈
,
(8)
10τ
a [µm]
where again this scaling relation should continue only down
to a scale of 0.3 µm, for an ultimate maximum clock speed of
about 250 GHz. This relation is also plotted in Fig. 3. These
numbers are for Nb; for NbN with IcRn ~ 4 mV, the corresponding ultimate maximum is 420 GHz for a < 0.25 µm.
In current RSFQ technology, resistors are used both as
resistive shunts Rs for the Josephson junctions, and also as
bias resistors Rb for proper dc current distribution. These
resistors are generally patterned from a resistive layer made
from a metal such as molybdenum (Mo) which is not
superconducting (at least at 4 K), with a sheet resistance Rsq
that is typically 1 Ω/square. For Nb junctions having
Ic =100 µA, Rs scales as 8 Ω/a, and Rb is typically at least
several times larger. So as the junction scale is reduced, it will
be necessary to increase resistance values. Junctions are
10
6
1000
Critical Current Density J c [A/c m 2 ]
10
4
10
Clock
Speed
100
f (GHz)
TABLE I
SUMMARY OF SCALING RULES*
Quantity
Transformation
Current
Voltage
Flux
Distance on chip
Time delays
Resistance
Capacitance
Inductance
Junctions/area
Power/area
I→I
V → Vα
Φ→Φ
∆x → ∆x/α
∆t → ∆t/α
R → Rα
C → C/α2
L→L
N → Nα2
P → P α3
f
τ
1
0.1
0.1
This formula assumes that the thickness of the Nb layers is
larger than λ ~ 90 nm, and that the thickness of the insulating
layer separating the two is d ~ 200 nm. It also assumes that
the microstrip width w >> d, so that edge effects may be
neglected. Then a typical inductor may be ~ 20 squares long.
RSFQ circuit layouts are composed of lines and patterns in
a set of aligned layers (resistive, superconducting, and
insulating). As the patterns for the junctions are reduced in
scale, one would like, if possible, to have similar reductions
for the other elements as well. This can be achieved in a
consistent manner, provided that Rsq and Vb are increased by
the same factor. These transformations down in scale by a
factor α are summarized in Table I. Note that this is for the
regime throughout which shunt resistors are still needed, for a
> 0.3 µm.
It is not difficult to adjust the fabrication process to
maintain the scaling in this regime. The primary change is to
increase the sheet resistance of the resistor layer by up to a
factor of 10 from a typical value (for 3 µm linewidth) of
1 Ω/sq. This can be easily achieved either by decreasing its
thickness, or by using a material with somewhat larger
resistivity, such as a metallic alloy or compound. The
fabrication processes for superconducting and insulating
layers can stay essentially the same as the scale decreases.
The effective sheet inductance Lsq will start to decrease for
very narrow lines; this can be countered (up to a point) by a
2
10
Pulse
Width
τ (ps)
generally biased in parallel with a single bias voltage Vb, at a
current that is typically ¾ of Ic. So it will be necessary to
increase Vb as well to maintain dc bias currents.
Inductors are also ubiquitous in RSFQ design, and are
used both in transport structures (such as the Josephson
transmission line) and storage loops. A typical value of an
inductor is determined by LIc ~ Φ0/2, so that L ~ 10 pH. Since
the minimum Ic should be fixed at 100 µA as the scale is
reduced, these values of L should also be scale-invariant. In
RSFQ circuits, these small inductors are generally made using
sections of superconducting microstrip transmission line, i.e.,
a narrow Nb line above a Nb ground plane. This minimizes
the magnetically coupled crosstalk between different parts of
the circuit. The value of inductance in such a structure can be
given approximately in terms of the effective inductance per
square
L sq ≈ µ 0 (2λ + d ) ≈ 0.5 pH.
(9)
1
10
Junction Scale a (µm)
Fig. 3. Scaling of SFQ pulse width and RSFQ clock speed for Nb junctions.
4
*Scaling down by factor of α, in regime where shunt resistance still needed.
slight decrease in the thickness of the superconducting strip,
so as to increase the kinetic inductance contribution.
The most important result summarized in Table I deals
with time delays. If all on-chip patterns are shrunk by a factor
α, then all times will be reduced by the same factor. This
includes time delays due to junctions as well as time delays
due to pulse propagation on transmission lines. So even as the
pulses become narrower, their relative timing in the circuit
will remain consistent. This is essential in preserving circuit
margins as we go up to higher speeds.
There will be, of course, a major change in circuit design
when the junctions no longer need to be shunted, i.e., for
a < 0.3 µm for Nb. A resistor layer will still be needed for
bias resistors (unless an alternative biasing scheme can be
implemented – see comments below), but removal of the
shunt resistors can lead to an increase in junction density, as
well as an increased flexibility in circuit design. However, a
large fraction of the circuit area is already taken by other
circuit elements – bias resistors, inductors, dc bias lines, clock
and signal lines – so that this further increase in density will
be somewhat limited. Finally, there would be no major
speedup following strictly from shunt removal, since most of
the time delays in RSFQ circuits are due to the junctions
themselves, rather than from pulse propagation between
junctions. Further reduction in junction scale may be possible,
but would not yield further increase in speed, since the pulse
width is already at its intrinsic minimum.
IV. ISSUES IN DEEP SUBMICRON JUNCTIONS
Although we have shown that scaling RSFQ circuits to deep
submicron junctions is feasible, there are several key issues
that will become important in designing circuits on this scale.
First, local heat dissipation will become substantial for this
technology, despite its ultra-low-power nature. Second, the
simple resistively shunted junction model may not be
sufficient to simulate these sub-picosecond SFQ pulses. And
finally, these pulses have frequency components above the
superconducting energy gap of Nb, so that resistive loss in
superconducting lines may start to become significant.
A. Heating in RSFQ Circuits
Let us first consider dynamic heating in the junction itself.
One of the key advantages of RSFQ logic, of course, is that it
operates at extremely low power, with zero voltage except
during an SFQ pulse. Nevertheless, as Table I indicates, the
power density goes up as α3, so that scaling down by a factor
of 10 increases power density by a factor of a thousand. To be
more specific, the energy dissipation ∆E associated with a
single SFQ pulse is ∆E ~ IcΦ0 ~ 2 × 10-19 J for Ic ~ 100 µA. If
a circuit operates at the maximum frequency of 250 GHz (and
assuming a continuous stream of pulses, as in a clock
distribution circuit), then the average power <p> ~ 50 nW. If
this is dissipated on the scale a ~ 0.3 µm, this corresponds to
a power density P ~ 50 W/cm2. This will tend to heat up the
region near the junction, with the temperature rise dependent
on how the heat is carried away. At these low temperatures,
the major bottleneck in heat flow lies at the boundary between
different materials, such as a Nb film and the silicon
substrate. This thermal boundary resistance is strongly
3
dependent on temperature, rising sharply (typically as 1/T ) as
the temperature is reduced. An estimate of the effective
thermal boundary resistance between a metal such as Nb in
good contact with a Si substrate is RT ~ 0.1 cm2K/W at 4 K
[16]. Taking the above power estimate yields a temperature
rise ∆T = PRT ~ 5 K! This may be an overestimate, since RT
decreases as T rises, but this clearly indicates the nature of the
problem. The situation may be lessened significantly by heat
spreading in the superconducting leads, on the scale of the
“thermal healing length” η = κdRT (where κ is the thermal
conductivity of the leads and d is the film thickness), before
passing through to the substrate [17]. Using an estimate of η
~ 1 µm gives a reduced temperature rise ∆T ~ 0.5 K, which is
more manageable, if still quite significant. If design rules
ensure that such heat sources are placed at least about 1 µm
apart (which is not too restrictive given the area necessary for
the other circuit components), then such dynamic heating may
be acceptable even in large circuits.
An even larger source of heating is associated with static
heating in the dc current bias resistors. On this deep
submicron scale, the bias power per junction should be
p ~ IcVb ~ 2 µW. If this is dissipated in a bias resistor 0.3 µm
wide by 10 squares long, the power density is P ~ 200 W/cm2
(four times larger than that due to the dynamic heating of the
junction), which would be likely to heat the resistor above
Tc ~ 9 K for Nb. While the resistor value itself is largely
independent of T, the problem is that the superconducting
contacts with this resistor would be driven normal.
Furthermore, if ~100,000 junctions cover an entire chip
~ 0.5 cm on a side (scaling from typical total junction counts
~ 1000 on the 3-µm scale), this gives a total heat dissipation
of ~ 200 mW, which could easily heat up the entire chip. A
related issue is the problem of getting ~ 10 A in and out of
such a chip without exceeding local critical currents, since
standard RSFQ design uses parallel biasing for most
junctions. Alternative biasing schemes or major reduction in
Vb [18], [19] may have to be implemented to avoid such
problems.
B. Dynamic Models for Intrinsic Junctions
The standard model for simulating Josephson junctions in
RSFQ circuits is the CRSJ model, which assumes a shunt
resistance and capacitance independent of voltage, and a
sinusoidal current-phase relation with Ic independent of
frequency. This has been found to agree well with
experimental results for externally shunted junctions up to
frequencies of order 100 GHz. But some of these assumptions
may not be valid for intrinsic junctions generating sub-ps
pulses. In particular, it is well known that the resistance of
ideal tunnel junctions is highly nonlinear (with a large subgap resistance). Furthermore, the magnitude of Ic is believed
to roll off at frequencies higher than the energy gap voltage
(f > 2∆/Φ0e = 4∆/h = 1.4 THz for Nb), and may also exhibit
some resonant enhancement at this gap frequency (known as
the “Riedel singularity”). These theoretical properties of an
5
ideal Josephson junction with negligible capacitance were
incorporated into the “Werthamer model”, which was solved
numerically many years ago [20]. A key feature of this model
visible in the dc current-voltage characteristics is the presence
of resonances at the energy gap and its sub-harmonics
V = 2∆/ne, as well as clear evidence of a large sub-gap
resistance.
However, submicron Josephson junctions with high critical
currents have been fabricated, and exhibit considerably
different behavior from that predicted by the Werthamer
model [21], [22]. In particular, although they do exhibit some
(weak) sub-harmonic gap structure, they do not exhibit a large
sub-gap resistance. An alternative model based on
superconducting-normal-superconducting
(SNS)
microcontacts (perhaps atomic-scale “pinholes”) has also been
elaborated by Averin [23], [24] and shows sub-harmonic gap
structure due to a phenomenon known as “multiple Andreev
reflection” in the contact. However, it is not at all clear that
this is the appropriate physical model to describe small tunnel
junctions.
Simulations of SFQ pulses using the Werthamer model were
also carried out some years ago [25], and were found to be
remarkably similar in pulse height and pulsewidth to those
from a simple RSJ model with the same Ic and Rn, despite the
considerable differences in detailed equations. Furthermore,
simulations of some RSFQ circuits using these nonlinear
junctions also seemed to behave quantitatively in a rather
similar way.
More recently, Xu et al. [26] carried out preliminary
simulations of SFQ pulse generation using the Averin
equations. Choosing junction parameters that correspond to a
very clean metallic contact with weak scattering (high
transparency), they found significant pulse broadening and
delay, relative to that from either the RSJ or Werthamer
models. It is perhaps unlikely that these extreme parameters
correspond to the intrinsic junctions actually fabricated and
tested. Nevertheless, this deserves further investigation, in
that it might indeed affect the ultimate limits of RSFQ
performance.
It may also be possible to modify the simple CRSJ model to
incorporate one or more aspects of these alternative models in
an approximate way, without adding major computational
complexity. For example, a high-frequency rolloff in Ic could
be simulated using standard filters already included in circuit
simulators. However, until there is a better understanding of
the appropriate model to adapt, it would seem that the simple
CRSJ model can continue to provide a guide to the
approximate behavior of ultrafast RSFQ circuits.
In terms of the fabrication technology of deep submicron
Nb tunnel junctions, it is significant that recent work at Stony
Brook [22] has demonstrated that junctions down to 0.2 µm
and Jc up to 200 kA/cm2 can be manufactured with the high
yield and uniformity (at least on a small scale) necessary for
integrated circuits. Furthermore, simple RSFQ circuits
fabricated by these methods showed proper operation up to at
least 700 GHz [11], without indicating any insurmountable
problems in performance (although heating was mentioned as
a possible limitation). This is very promising for the
development of large-scale manufacturing of RSFQ circuits
composed of deep submicron junctions.
C. Losses above Energy Gap
A superconducting film exhibits strictly zero resistance only
at zero frequency, but resistive losses (in high-quality Nb
samples) are quite small up to the energy gap frequency
f=2∆/h ~ 700 GHz for Nb. For this reason, one is justified in
ignoring the effect of surface resistance on Nb lines for SFQ
pulses at lower frequencies. However, an SFQ pulse of width
τ ~ 0.4 ps from an intrinsic junction has an effective
bandwidth of approximately 1/2τ ~ 1.2 THz, with significant
components at even higher frequencies. At moderate
frequencies the two-fluid model can be used to characterize
electromagnetic properties of superconductors, but at these
extremely high frequencies, the Mattis-Bardeen equations are
more appropriate [27], [28]. The key result is that at
frequencies well above the energy gap, the effective surface
impedance is that corresponding to normal, nonsuperconducting Nb.
To determine the effect of this high-frequency loss on
RSFQ circuits, let us consider the effect on superconducting
microstrip transmission lines, which are used both as lumped
inductors in active circuits and as passive lines for SFQ
pulses. Taking an estimated normal-state resistivity for Nb at
low temperatures ρn ~ 3 µΩ-cm (consistent with λ ~ 90 nm
via the dirty-limit relation µ0λ2 = ρnh/8∆ [27]) yields a surface
resistance Rsur ~ 0.3 Ω for a film ~100 nm thick at frequency f
~1 THz. This corresponds to a resistance per square
(including both the line and the ground plane) of
2Rsur ~ 0.6 Ω. This should be compared to the inductance per
square Lsq ~ 0.5 µH. The total impedance Zsq can then be
crudely estimated as
Zsq = 2Rsur + j2πfLsq ~ 0.6 + j 3.7 Ω,
(10)
using the effective pulse bandwidth of 1.2 THz for the
frequency f. A lumped element composed of this line would
then be predominantly inductive, so that one would expect
only a slight effect on active RSFQ circuits. This was
confirmed in a simulation of a simple RSFQ circuit using
inductors exhibiting a frequency dependence similar to that of
the Mattis-Bardeen equations. The timing and margins of a
simulated submicron RSFQ destructive readout (DRO) circuit
operating at 200 GHz were found to be virtually the same
using either the lossless or slightly lossy inductors [29]. But it
is important to note that this conclusion might well be
different for an impure superconductor with a high normalstate resistivity, such as NbN, where the resistive loss would
be much larger.
Such high-frequency losses would seem to be more serious
for SFQ pulses on long, passive transmission lines, where the
pulse would broaden and attenuate [28]. The attenuation
length δ on a microstripline takes the approximate form
δ = Z0w/Rsur, where Z0 is the characteristic impedance and w
the strip width. Estimating Z0 ~ 20 Ω and w ~ 0.3 µm, and
using Rsur ~ 0.3 Ω from above, one obtains an attenuation
length δ ~ 20 µm. However, this may be less serious than it
might initially appear. Only the frequency components above
6
the energy gap would attenuate; one would still be left with
essentially an SFQ pulse with τ ~ 0.7 ps, still very narrow.
Such SFQ pulses may well be acceptable for certain purposes
in high-speed RSFQ circuits, and the narrower pulses can be
regenerated by junctions where needed.
[6]
[7]
[8]
V. CONCLUSIONS
The title of this paper asks the question, “Can RSFQ logic
circuits be scaled to deep submicron junctions?” Based on
this analysis, the answer seems to be a clear “Yes”, despite
some remaining uncertainties. There is a direct path to
increasing the clock speeds of complex Nb RSFQ integrated
circuits to ~ 250 GHz as the junction scale is decreased from
3 µm down to ~ 0.3 µm, a factor of ~ 10 smaller and faster
than those now being manufactured. It is possible to shrink
existing layouts and maintain optimized timing and margins if
the sheet resistance and voltage bias are increased
proportionally. Even further increases in density (although not
in speed) may be achieved by eliminating shunt resistors on
the 0.3 µm scale and below. Early demonstrations of simple
circuits of this type suggest that they should be
manufacturable on a large scale. This should lead to circuit
densities approaching a million junctions per square
centimeter. At this scale of integration, local and global
heating will become serious design constraints, particularly in
regard to the biasing scheme. In terms of RSFQ circuit
simulations, the correct physical model for these junctions
remains to be determined, but it is likely that a variation of
the simple CRSJ model can continue to be useful for
developing and optimizing these circuits. Resistive losses at
frequencies above the energy gap do not appear to be a
serious problem for Nb.
This is not to imply that process of scaling to deep
submicron dimensions will be easy. On the contrary, it is a
formidable challenge, which will require major investments
over an extended period throughout the superconducting
electronics industry. But if this can be accomplished, the
revolutionary high-speed performance should enable
application of these circuits to a wide variety of systems in
computing, communications, and instrumentation, moving
superconducting electronics into the mainstream of modern
commercial technology.
[9]
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