Technology
Advantages for Analog/RF & Mixed-Signal Designs
Andreia Cathelin
STMicroelectronics, Crolles, France
SOI Consortium Forum, Tokyo, January 21st , 2016
Agenda
• At a glance
• ST 28nm UTBB FD-SOI CMOS: Simpler Analog Integration
• Advantages for analog design
• Advantages for RF/mmW design
• Advantages for Mixed-Signal design
• Conclusion and takeaways
Nota: all measurement data from ST 28nm FD-SOI CMOS, unless otherwise specified
2
Transistor
Bulk
Gate
Source
Substrate
Gate
Drain
Punch
Through !
Typical Transistor in today
CMOS System on Chip
Source
Drain
Ultra-Thin Buried oxide
Substrate
Change of Substrate adding
the thin Buried oxide
Improving power Efficiency – Bringing high flexibility in SoC integration
While keep very similar manufacturing flow
3
Fully Depleted Transistors
FinFET
FinFET & FD-SOI : Just a rotation ultimately converging when scaling BOX to TOX
Addressing Digital Markets
FinFet
Consumer
Multimedia
High end servers
Networking
Infrastructure
Internet of Things,
Wearable
Smartphone
Available from
28nm node
Laptops & tablet-PC
Automotive
Ultimate Digital Integration
Ultimate Digital + AMS + RF + … Integration
5
Example: Ultra Low Power in IoT
34 mW*
SoC Architecture
6
SoC Power Consumption
Power
Supply Loss
RF
RF
Analytics
CPU & Memories
Analytics
<10 mW*
Power Management
CPU &
Memories
Other
Previous
Generation (40LP)
<5 mW**
FD-SOI
28nm
FD-SOI
28nm optimized
design
X3 to X6 Power Consumption Improvement with FD-SOI
* Measured on Silicon / Product Simulation
** Projection
ST 28nm FD-SOI Transistor Flavors
7
Low VT (LVT) CMOS in FD-SOI; flipped-well
PMOS
G
G
S
D
S
D
BOX
Nominal
VBB
VBBP
BOX
LVT
PMOS
NMOS
G
G
S
D
BOX
BOX
GND
P-Sub
3
Bulk type CMOS
FBB
VBBN+0.3
3
0.6
VBBN
RVT
PMOS
RVT
NMOS
RBB
VDD
-3
P-Well
N-Well
-0.3
-3
PMOS
S
FBB
-3
P-Sub
D
VDD
GND
P-Well
N-Well
VBBP
LVT
NMOS
Biasing mode
-0.3
3
RBB
GND
NLVT
NRVT
PLVT
PRVT
RBB
0.4
FBB
0.2
Vth (V)
VBBN
NMOS
0.0
FBB
-0.2
-3
Regular VT (RVT) CMOS in FD-SOI
VBBP+0.3
3
RBB
-0.4
-0.6
-3
-2
-1
0
VB (V)
1
2
3
for Simpler Analog Integration
ST 28nm FD- SOI makes analog/RF/HS designer’s life easier
Improved Analog Performance
Speed increase in all analog blocks
Higher gain for a given current density
Higher bandwidth
Improved Noise
Efficient Short Devices
Very large VT tuning range
High performance frequency
behavior
Lower gate and parasitic capacitance
Lower noise variability
Better matching for short devices and
efficient design with L>Lmin
Analog parameters wide range tuning via a
new independent “tuning knob” (back-gate)
fT/ fmax >300GHz for LVTNMOS and high
performance passives enabling RF/mmW/HS
integration with technology margin
Lower power
Smaller designs
Improved design margins
wrt PVT variations
Novel flexible design
architectures
8
Advantages in Analog Design
Efficient Short Devices
9
Improved Noise
Improved Analog Perf.
NMOS_SOI_W=9(µm)
model
1,E-06
SId/Id²(/Hz)
L=0,903(µm)
L=0,03(µm)
1,E-07
1,E-08
1,E-09
NRVT_Bulk_W=9(µm)
model
1,E-10
L=0,903(µm)
1,E-06
1,E-11
1,E-08
1,E-07
1,E-06
1,E-05
1,E-04
SId/Id²(/Hz)
Idrain(A)
• Higher Gm for a given current density
L=0,03(µm)
1,E-03
1,E-07
L=9,903(µm)
1,E-02
L=0,273(µm)
1,E-08
1,E-09
1,E-10
1,E-11
1,E-08
1,E-07
1,E-06
1,E-05
1,E-04
1,E-03
Idrain(A)
NMOS
0,45
C028_SOI
C045
σ(log(W*L*SId/Id²))
0,4
C028_LVT
0,35
0,3
0,25
0,2
0,15
0,1
0,05
• Efficient use of short devices :
• Lower gate capacitance
• Performance example:
Higher achievable bandwidth or
lower power for a given
bandwidth
• High analogue gain @ Low L
• Low Vt mismatch (Avt ~ 2mv/µm)
• A 10µm/100nm device has a
DC gain of 100, & a sVt of only 2mV !
0
0
5
10
15
20
25
1/sqrt(W*L)(µm-2)
• Same normalized drain current
noise between BULK and FD-SOI
• Lower noise variability for FD-SOI
• Improved noise in FD-SOI
Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, STMicroelectronics
1,E-02
Advantages in Analog Design-II
10
Very large VT tuning
range by FBB
FBB
ST 28nm LVT NMOS
(typical)
VT [mV]
+3V
VBBN
Bulk
FD-SOI
P-Sub 0V
Forward body bias [V]
• Flip-well devices:
• Large Forward Body Bias (FBB) range
• Negligible control current
VBBP
FD-SOI
-3V
(flip-well flavor/LVT devices)
• Use back-gate as « VT tuning knob »:
• Unprecendented ~250mV of tuning
range for FD-SOI vs.
• ~ 10’s mV in any bulk
Courtesy, A. Cathelin, STMicroelectronics
P-sub
Analog Filter Design Example
11
VDD
• Filters with several 100’s MHz
bandwidth
Regulator
drop
(>20%)
- PVT + ageing affect system operation
- Need to tune/trim independently several
parameters impacting overall system:
•
•
•
•
VFilter
cut-off frequency,
linearity,
noise,
all for an optimal power consumption
Regular CMOS Tuning/trimming solution: Voltage
regulator impacting directly the signal path behavior
FD-SOI revolutionary solution: individual transistors body
biasing oxide-isolated from the signal path behavior
Tuning
margin
Filter
supply
Global
supply
Typical example of Analog Filter
• Inverter-based analog functions:
• attractive implementations: simple and
compact
• scale nicely with technology nodes
• Here: analog low-pass Gm-C filter
• Typical implementation:
• Fixed capacitors
• Tune the filter cut-off frequency by
tuning Gm
Bulk
specific solution:
Tune local Vdd
Local VDD
FD-SOI
specific solution:
Tune all VBB’s
12
Tuning Gm with VDD
OK: gm variation; NOK: linearity
Local VDD
• Major issue: it changes also
linearity and noise behavior
gm
• Tune Gm value with local VDD
VDD
high
nominal
low
0
Vinput
13
FD-SOI: Tuning gm with Vbody
OK: gm variation; OK: linearity
• New tuning knob (and off the signal path): VBBP and VBBN
• Compensate VDD variations
• Tune gm back to nominal
gm
0
Without back-gate bias
high
nominal
low
Vinput
gm
VDD
• Ensure constant linearity operation
0
With back-gate bias
Vinput
14
Inverter-based Analog Filter
15
• RF low-pass Gm-C filter using CMOS
inverters
‒ Tuned by back-gate instead of supply
(no signal path interference)
‒ Supply regulator-free operation
• Energy efficient
• Low voltage operation (VDD = 0.7V)
‒ Competitive linearity
• Compared to similar circuit in 65nm bulk
[2], at same noise level, get X2 linearity for
/4 power level
[J. Lechevalier at al, ISSCC2015]
[2] Houfaf, et al., ISSCC 2012
[5] Saari, et al., TCAS-I 2009
[6] Mobarak, et al., JSSC 2010
[7] Kwon, et al., TMTT 2009
• Compared to best-in-class filters [7], at
same noise level and Fc, get competitive
linearity for /14 power level
• Best in class in terms of the compromise
noise-linearity-power
• Integrated in ST 28nm FD-SOI CMOS
Advantages in RF/mmW Design
Active devices high frequency performance
Performant passive
devices
Nbt = 1
Nbt = 2 to 6
• For ST 28nm FD-SOI LVTNFET: fT/ fmax >300GHz
• For RF operation
frequency :
•
•
•
•
Work with L = 100nm
MAG = 12dB @10GHz
NFmin ~ 0.5dB @ 10GHz
Work @ current density: 125
µA/µm
• For mmW operation
frequency (intrinsic models):
•
•
•
•
Work @ Lmin
MAG = 12dB @60GHz
NFmin ~ 1.3dB @ 60GHz
Work @ current density: 200
µA/µm  33% less power than
in 28LP bulk
• Operation frequency range :
2 GHz - 50 GHz
• Inductance range: 0.1 nH 28 nH
• Q factor range: 20 - 35
• Size: 60x60 µm² – 600x600
µm²
Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, C. Durand STMicroelectronics
16
60GHz PA
dc consumption [mW]
1200
65nm
1000
PA
40nm
Other TX blocks
800
600
90nm
400
65nm
65nm
200
Dissipated power [mW]
60-GHz transceivers (RF TX part)
17
High dc consumption
Low average PAE
WiGiG with max.
operation probability @
8dB back-off  high
linearity with optimized
power
High PAPR
0
JSSC 2011
ISSCC
2011
JSSC 2013
ISSCC
2014
ISSCC
2014
Output
power
Average
at 8-dB
back-off
power
Solve the general trade-off linearity and
power consumption
Average PAE
8-dB
at
back-off
PAE
[%][%]
back-off)
(at 8-dB
50% power in mmW TRx spent in PA
Output
power [dBm]
10
9
8
7
6
5
4
3
2
1
0
CMOS 40nm
CMOS 65nm
JSSC, 2012
JSSC, 2013
RFIC, 2014
ISSCC, 2014
RFIC, 2014
JSSC, 2010
ESSCIRC,
2014
MWCL, 2015
12
13
14
15
16
17
18
1-dB compression point [dBm]
19
20
Novel mmW Power Amplifier
thanks to FD-SOI and wide-range body biasing
18
• Revisit classical Doherty power
amplifier architecture
Classical Doherty
Power Amplifier
• Two different class power amplifier
in parallel
VDD, RFOut+
FD-SOI-specific
Doherty
Power Amplifier
Class C
RFOut-, VDD
Class AB
VB1
Class AB
VB2
Class C
VB1
• Ability of gradualy change the overall
class of the PA (mix of class AB and class
C) thanks to wide range FBB
 optimise in the same time power
efficiency and linearity
• Remove signal path power splitter
as in classical implementations
 reduced signal path losses
RFIn+, VG_DC
VG_DC, RFIn-
60GHz Configurable PA
Technology
This work
S. Kulkarni
ISSCC 2014
D. Zhao
JSSC 2013
D. Zhao
JSSC 2012
E. Kaymaksut
RFIC 2014
A. Siligaris
JSSC 2010
28nm UTBB FD-SOI
40nm
40nm
40nm
40nm
65nm PD-SOI
NA
Low/High power
NA
NA
NA
Operating mode
High gain
High linearity
Supply voltage [V]
1.0
1.0
0.8
0.9
1.0
1.0
0.9
1.8
Freq. [GHz]
61
60
60
63
61
60
77
60
Gain [dB]
35
15.4
15.1
22.4
16.8 / 17
26
9
16
PSAT [dBm]
18.9
18.8
16.9
16.4
12.1 / 17
15.6
16.2
14.5
P1dB [dBm]
15
18.2
16.2
13.9
9.1 / 13.8
15.6
15.2
12.7
PAEmax [%]
17.7
21
21
23
22.2 / 30.3
25
12
25.7
PAE1dB [%]
9
21
21
18.9
14.1 / 21.6
25
11.1
22.6
PAE8dB_backoff [%]
1.5
8
7.5
3
- / 4.7
5.8
3.5
2.7
117
126
77.4
120
140
79
31
26
24
PDC [mW]
331
74
58
88
56 / 75
#
PDC_8dB_backoff [mW]
332
124
84
94
56 / 78
#
100xP1dB/PDC
9.6
72
0.162
Active area [mm²]
ITRS FOM [W.GHz²]
89
161,671
1,988
1,198
#
14.5 / 32
0.081
0.074
0.33
0.1
0.573
6,925
641 / 2,832
13,009
236
1,038
[A. Larie et al., ISSCC2015]
*
: with pads
#
• Fully WiGiG compliant (linearity and
frequency range)
• New PA architecture: continuously
reconfigurable power cells
• Continuous operation class tuning
thanks to body bias with 2 extreme
modes:
• High gain mode: Highest ITRS FOM
• 10X better than previous SoA
• High linearity mode: Break the linearity /
consumption tradeoff
28
ITRS FOM = PSAT.PAEmax.Gain.Freq²
19
*
• ULV high efficiency operation
(Vdd_min = 0.8V)
: estimated
• Integrated in ST 28nm FD-SOI CMOS
Advantages in MS Design
Variability
Switch performance
Lower capacitance
• Lower juction capacitance
makes a substantial difference in
high-speed circuits
• Drastic reduction of self-loading
in gain stages
• Drastic reduction of switch selfloading
• Tighter process corners and less
random mismatch than
competing processes
• Benefits:
• Simpler design process, shorter
design cycle
• Improved yield or improved
performance at given yield
• Improved gate control allows smaller
VTH
• Backgate bias allows for VTH
reduction by tuning
• Results is an unprecedented quality
of analog switches
• Compounding benefits: smaller R ->
smaller switch -> compact layout ->
lower parastics -> even smaller
switch
• Key for high performance data
converters and other SwitchedCap. Circuits
• Two-fold benefit:
• Leads to incremental
improvements
• Allows the designer to use circuit
architectures that would be
infeasible/inefficient in bulk
technologies
Courtesy, S. Le Tual, STMicroelectronics; B. Murmann, Stanford Univ.
20
High-Speed Time Interleaved-ADC example
• Lower Vth, less variability
• Better switch: RON & linearity
• Faster logic
Technology
• Increased comparator BW
• Reduced switch parasitics
• Energy efficient operation
[S. Le Tual et al., ISSCC2014]
Verma
ISSCC 2013
• Reduced S/D capacitances
Tabasy
VLSI 2013
40nm CMOS 65nm CMOS
Kull
VLSI 2013
This Work
32nm SOI
28nm FD-SOI
Architecture
TI-FLASH
TI-SAR
TI-SAR
TI-SAR
Power Supply (V)
0.9
1.1 / 0.9
1
1
Sampling Rate (GS/s)
10.3
10
8.8
10
Resolution (bits)
6
6
8
6
Power Consumption (mW)
240
79.1
35
32
SNDR @ Nyquist (dB)
33
26
38.5
33.8
Active Area (mm2)
0.27
0.33
0.025
0.009
FOM @ Nyquist (fJ/conv)
700
480
58
81
Max Input Frequency (GHz)
6
4.5
4.2
20
Gain/Skew Calibration
Yes
Yes
Yes
No
• Integrated in ST 28nm FD-SOI
CMOS
O : 28FD-SOI or 32nm SOI
Courtesy, B. Murmann, Stanford Univ.
21
Takeaways for Analog/RF/mixed-signal
• ST 28nm FD-SOI CMOS arguments:
• For Analog/RF design:
• FBB as VT tuning knob  ultra large tuning range for VT
• Very good analog performance  lower power consumption
and operate at L>Lmin for design margin
• For RF/mmW design, operate at Lmin and add:
• Deep submicron technology features:
• Front-end: performant fT, fmax
• Back-end + FD-SOI features: performant passive devices
• For mixed-signal/high-speed design:
• Improved variability
• Switch performance
• Reduced parasitic capacitance
Efficient
Flexible
Simple
22
Take-aways charts per field
Analog/RF design in FD-SOI
• FD-SOI arguments:
• FBB as VT tuning knob  ultra large tuning range for VT
• Very good analog performance  lower power consumption and operate at L>Lmin for
design margin
• Consequences on analog/RF design:
• Operate amplifiers at constant Gm
• Employ new tuning strategies
• Competitive noise and linearity behavior
• Obtain strong design independence with respect to PVT variations
• New robust design oportunities
24
RF/mmW design in FD-SOI
• FD-SOI arguments:
• FBB as VT tuning knob  ultra large tuning range for VT
• Very good analog performance  lower power consumption
• Deep submicron technology:
• Front-end: performant fT, fmax
• Back-end + FD-SOI features: performant passive devices
• Consequences on RF/mmW design:
• New family of reconfigurable topologies; new design architectures
• Power efficient solutions
• State of the art implementations with concomitent optimisation for each system-level parameter
• New robust design oportunities
25
Mixed-signal / High-speed
design in FD-SOI
• FD-SOI arguments:
• Improved variability
• Switch performance
• Reduced parasitic capacitance
• Consequences on MS design:
• State of the art HS Data Converters
• Drastic improvement of the Nyquist FOM (FOM=P/(fs*2ENOB) )
• New robust design oportunities and new design architectures enabled
26