On the usage of FBB for inverter-based Analog
and RF 28nm UTBB FDSOI circuits :
example of a 450MHz Gm-C filter
with IIP3> 1dBv over a 0.7-1V power supply
Andreia Cathelin
STMicroelectronics, Crolles, France
FDSOICE Workshop, LetiDays, June 22nd, 2015
Grenoble, Minatec
Outline
2
 Introduction
• FD-SOI technology
• Transconductor
• Filter implementation
• Measurement results
• Conclusions
Introduction
3
• Analog filters are generic blocks for any type of
wireless communication systems
• Filters with several 100’s MHz bandwidth
‒ Energy efficient wireless communication SoC’s
‒ Need to tune independently several parameters impacting
overall system:
• cut-off frequency,
• linearity,
• noise,
• all for an optimal power consumption
• Inverter-based analog functions are attractive
implementations (Gm-C filters, variable amplifiers, …)
Gm-C integrator
4
• Ideal:
Gain [dB]
Gm
‒H s =
sC
‒ 90° phase shift
• Real:
0
0
Phase
‒ Finite rout  finite DC gain
‒ Parasitic poles
-90⁰
Gm
2πC
f
f
Inverter based transconductor [1]
5
• High Dynamic Range per power [3]
• No internal nodes
‒ Wideband Gm
• Negative resistance
1
‒ Zdifferential = gmc−gmb
‒ High DC gain
• Common mode control
1
‒ Zcommon = gmb+gmc
[1] Nauta, JSSC 1992
[3] Klumperink, et al., TCAS-II 2003
Inverter-based filters
6
Tuned by supply voltage
VDD
Regulator
drop
(>20%)
• LDO Regulator
Voltage headroom
VFilter
 Power
VFilter
Tuning
margin
Filter
supply
Global
supply
Inverter-based filters
7
Tuned by supply voltage
VDD
Regulator
drop
(>20%)
• LDO Regulator
Voltage headroom
VFilter
 Power
VFilter
Tuning
margin
Global
supply
Filter
supply
Eliminate the regulator by
using FD-SOI technology
Outline
8
• Introduction
 FD-SOI technology
• Transconductor
• Filter implementation
• Measurement results
• Conclusions
28nm UTBB FD-SOI
9
• Buried Oxide (BOX)
‒ No drain- & source-to-bulk diodes
‒ Flip-well
• Transistor body as “back-gate”
 VT tuning
FD-SOI
(flip-well flavor)
Bulk
28nm UTBB FD-SOI
10
• Flip-well
‒ Large Forward Body Bias (FBB) range
‒ Negligible control current
FBB
+3V
VBBN
P-Sub 0V
VBBP
FD-SOI
(flip-well flavor)
-3V
P-sub
28nm UTBB FD-SOI
11
• Back-gate as ‘VT tuning knob’ [4]
~ 250 mV tuning range
VT [mV]
~ 10’s mV in bulk
NMOS (typical)
Bulk
FD-SOI
Forward body bias [V]
[4] Jacquet, et al, JSSC 2014
Outline
12
• Introduction
• FD-SOI technology
 Transconductor
• Filter implementation
• Measurement results
• Conclusions
Inverter as V-I converter
13
• Non-matched βn & βp (β =
W
μCox )
L
Iout
‒ Non-linearity
‒ Distortion
Vtn
Vtp
0
VFilter
Vin
βn = βp
βn < βp
Differential
Iout
14
gm
Vid
βn = βp
βn < βp
VDD-Vtn+Vtp
0
Vid
gm
Tuning gm with VFilter
15
VFilter-Vtn+Vtp
• Ideal (calculated)
‒ Square law devices
‒ Constant gm
VFilter
0
Vid
gm
high
nominal
low
• Real devices
‒ Mobility reduction
‒ Triode region
‒ Exponential region
0
Vid
Fixed supply operation
16
• Eliminate LDO regulator
• VFilter = VDD
VDD
VFilter
Bulk
Vfilter = VDD
FD-SOI
Back-gate tuning in FD-SOI
17
• Compensate VDD variations
0
Without back-gate bias
VDD
high
nominal
low
Vid
gm
gm
 tune gm back to nominal
 constant fC & linearity
‒ Without regulator
0
With back-gate bias
Vid
Outline
18
• Introduction
• FD-SOI technology
• Transconductor
 Implementation
• Measurement results
• Conclusions
Filter Implementation - I
19
• LC ladder prototype
‒ 3rd order Butterworth low-pass
• Impedance scaling
Voltage swing x2
Gm Implementation - I
20
• 28nm node  technology margin
• L > Lmin improves rout
‒ L = 110nm for all transistors
‒ Better linearity & matching
‒ Only frequency tuning, no Q-tuning
Gm Implementation - II
21
•
1
gmb+gmc
•
1
= rout  DC gain
gmc−gmb
 CM stability
Minimize
gmb & gmc [2]
 minimize power & noise
[2] Houfaf, et al., ISSCC 2012
Filter Implementation - II
22
Chip implementation
23
• Filter path
‒ Buffers, matching
• Reference path
‒ De-embed
transfer function
Chip photo
24
• ST 28nm UTBB FD-SOI
• Filter area: 0.04 mm2
‒ Gm’s: ~0.01 mm2
‒ Capacitors: ~0.03 mm2
Outline
25
• Introduction
• FD-SOI technology
• Transconductor
• Filter implementation
 Measurement results
• Conclusions
Transfer function - I
VDD = 0.9V, fc tuning by back-gate
fC = 190 MHz
fC=1.08 GHz
26
Corner frequency tuning - I
VBBN = |VBBP|
27
Linearity - I
Cut-off frequency [MHz]
VBBN = |VBBP|
28
Corner frequency tuning - II
VBBP independent from VBBN
1V
0.9V
0.8V
0.7V
29
Linearity - II
VBBP independent from VBBN
0.9V
1V
0.8V
0.7V
30
Linearity - III
•
Filter tuned to fC = 450 MHz, at optimum IIP3
•
2-tone test (300 MHz ± 0.5 MHz)
31
Transfer function - II
• Filter tuned to fC = 450 MHz, at optimum IIP3
fC= 450 MHz
32
Transfer function - II
• Filter tuned to fC = 450 MHz, at optimum IIP3
33
Noise Measurements
• Filter tuned to fC = 450 MHz, at optimum IIP3
34
Comparison with state of the art
35
This work
Technology
28nm FD-SOI CMOS
Order
Supply voltage [V]
Cut-off freq. [MHz]
Input ref. noise
[nVrms/√Hz]
in-band IIP3 [dBVp]
3
[2]
[5]
[6]
[7]
65nm 65nm 0.13um 0.18um
CMOS CMOS CMOS CMOS
3
5
2
3
1
1.2
1.2
1.8
4700
275
200
300
0.7
454
0.8
454
0.9
457
1
459
5.9
6.1
6.1
5.9
6.6
7.8
35.4
5
1.2
4.0
4.0
2.4
-3
-12.5
4
6.9
Power diss. [mW]
4.0
4.6
5.2
5.6
19
36
21
72
SFDR/BW [dB/Hz]
109
110
110
109
105
98
100
113
[2] Houfaf, et al., ISSCC 2012
[5] Saari, et al., TCAS-I 2009
[6] Mobarak, et al., JSSC 2010
[7] Kwon, et al., TMTT 2009
Normalized SNR
36
• Trade-off
‒ Noise vs power
‒ Linearity vs noise
• Compare circuits
‒ Normalized Signal-to-Noise Ratio [3]:
NSNR dB = IIP3 dBm − 20dB − Ni dBm − PDC [dBm]
Normalized to:
1% IM3
1Hz BW
1mW
[3] Klumperink, et al., TCAS-II 2003
Comparison with state of the art
37
This work
Technology
28nm FD-SOI CMOS
Order
Supply voltage [V]
Cut-off freq. [MHz]
Input ref. noise
[nVrms/√Hz]
in-band IIP3 [dBVp]
Power diss. [mW]
SFDR/BW [dB/Hz]
NSNR [dB]
3
[2]
[5]
[6]
[7]
65nm 65nm 0.13um 0.18um
CMOS CMOS CMOS CMOS
3
5
2
3
1
1.2
1.2
1.8
4700
275
200
300
0.7
454
0.8
454
0.9
457
1
459
5.9
6.1
6.1
5.9
6.6
7.8
35.4
5
1.2
4.0
109
137
4.0
4.6
110
139
4.0
5.2
110
138
2.4
5.6
109
137
-3
19
105
125
-12.5
36
98
111
4
21
100
117
6.9
72
113
131
[2] Houfaf, et al., ISSCC 2012
[5] Saari, et al., TCAS-I 2009
[6] Mobarak, et al., JSSC 2010
[7] Kwon, et al., TMTT 2009
Inverter-based filters:
from tuning by supply …
38
VDD
Regulator
drop
VFilter
Tuning
margin
Vtp
Voverdrive
Vtn
Filter
supply
Global
supply
Inverter-based filters:
from tuning by supply …
39
VDD
Regulator
drop
VFilter
Tuning
margin
Vtp
Voverdrive
Vtn
Filter
supply
Global
supply
Inverter-based filters:
… to tuning by back-gate
40
• Using back-gate tuning in FD-SOI
 Constant Gm
 Constant Fc
VDD
Vtp
Voverdrive
Filter
supply
Vtn
No need for tunable supply!
Global
supply
Conclusions
41
• Inverter based analog/RF design in FD-SOI
‒ Added degree of freedom: VT tuning
‒ New robust design opportunities
• 450MHz low-pass Gm-C filter
‒ Tuned by back-gate instead of supply
‒ Supply regulator-free operation
• Energy efficient
• Low voltage
‒ Competitive linearity
• Best NSNR of recent Gm-C filters
Acknowledgements
42
• Original paper presented at ISSCC 2015
• This work is issued from a MS internship study in ST, student J.
Lechevallier from University of Twente
Bibliography
43
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High-Data-Rate Communications,” IEEE ISSCC Dig. Tech. Papers, pp. 362–364, Feb. 2012.
• [3] E. A. M. Klumperink, B. Nauta, “Systematic comparison of HF CMOS Transconductors,”
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• [4] D. Jacquet, et al., “A 3 GHz Dual Core Processor ARM Cortex TM-A9 in 28nm UTBB FDSOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization,” IEEE J.
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