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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
An 8-W 250-MHz to 3-GHz Decade-Bandwidth
Low-Noise GaN MMIC Feedback Amplifier
With > +51-dBm OIP3
Kevin W. Kobayashi, Senior Member, IEEE
Abstract—This paper describes a GaN monolithic microwave
integrated circuit (MMIC) cascode feedback amplifier design
which achieves up to 8 W of output power and greater than
+51 dBm OIP3 across a 250–3000-MHz decade bandwidth. The
LNA also achieves 20 dB of flat-gain across the band. The design
was fabricated with a 0.25-µm GaN HEMT technology with an
fT ~ 50 GHz and a BVgd > 60 V. A 40-V 750-mA high-bias LNA
design achieves an OIP3 of 51.9 dBm, P1dB of 38.5 dBm, and
NF ~ 3 dB at 2 GHz. A 40-V 500-mA medium-bias LNA design
achieves a lower NF ~ 2.5 dB, an OIP3 of 48.4 dBm, and a P1dB
of 36.8 dBm at the same frequency. At an optimum low-noise bias
of 20 V and 300 mA, a NF ~ 0.96 dB, an OIP3 of 43.4 dBm, and
a linear P1dB of ~32.2 dBm was also obtained. The combination
of high OIP3 and low NF from these GaN MMIC LNA designs
exceed that achieved by many state-of-the-art PHEMT, HBT, and
HFET technologies for decade-BW MMIC amplifiers operating
in the popular wireless and wire-line S- and C-band frequency
ranges. The linear GaN LNA performance demonstrated here can
enable new generations of software-defined and reconfigurable
radios which require ultra-linearity over multiple octaves of
bandwidth.
Index Terms—Bandwidth, broadband, cascode, gallium nitride
(GaN), high OIP3, linear, low noise, multidecade, power, softwaredefined radio (SDR).
I. INTRODUCTION
T
HERE are common trends in future wireless and wire-line
infrastructure systems that include increased bandwidth
of operation, greater spectral efficiency (bits/Hz), and deeper
and broader network coverage while consuming less energy.
Flatter and wider bandwidth amplification is desirable to accommodate larger modulation bandwidths as well as enable system
flexibility for reconfiguring a radio for multiple modes and modulation schemes from a common hardware platform. Higher
linearity is required for enabling spectrally efficient modulation and improving data throughput for RF, cable, and fiberoptic network applications. Higher transmitter power and higher
receiver sensitivity (low noise) is needed to improve network
reach for broader and deeper network coverage. Thus, there is
an increasing need to improve the basic performance parameters
of linearity, efficiency and sensitivity of front end components
across a wider bandwidth of operation.
Manuscript received January 19, 2012; revised March 17, 2012; accepted
May 15, 2012. Date of publication August 03, 2012; date of current version
October 03, 2012. This paper was approved by Guest Editor Payam Heydari.
The author is with RF Micro Devices, Torrance, CA 90505 USA (e-mail:
kevin.kobayashi@rfmd.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2012.2204929
Fig. 1. Summary of state-of-the-art GaN MMIC noise figure performance.
Gallium-nitride (GaN) semiconductor technology can
enhance the performance of these infrastructure front-end
components over previous GaAs technologies due its wider
bandgap, higher electron mobility, and superior thermal conductivity which results in higher power density, linearity, and
comparable sensitivity (low noise) over a wider operating
bandwidth. This paper describes a new benchmark in OIP3 and
dynamic range performance for a decade-bandwidth low-noise
MMIC amplifier design that operates with a flat gain, NF, and
OIP3 response from baseband to -band, which covers the
popular infrastructure frequency applications such as CATV,
fiber-to-the-premise (FTTP), wireless base-stations (BTSs),
and software-defined radios (SDRs).
Fig. 1 illustrates the state-of-the-art noise figure performance
for previously reported GaN-based MMIC LNAs in the - and
-band frequency regime. Early GaN HEMT MMIC LNA
demonstrations in literature were initially motivated by a need
for robustness and survivability for the harsh and hostile RF
environment of military applications [1]–[5], [8], [10], [11].
They have resulted in broadband low noise amplifiers with
high survivability and decent wideband noise figures typically
averaging around 1.5–2.5 dB, but were limited to below 1 W of
1-dB output power compression as indicated in Fig. 1 (middle
band of traces). The corresponding OIP3 linearity was modestly
lower than 40 dBm with the exception of a narrowband data
point of 43 dBm [3]; however, it should be noted that many of
these designs were optimized for flat gain response over very
broad bandwidths. Recently, GaN LNAs have demonstrated
more impressive 0.5-0.9 dB [6] noise figure across a multi-octave bandwidth from 2 to 8 GHz and a record 0.2-dB noise
0018-9200/$31.00 © 2012 IEEE
KOBAYASHI: 8-W 250-MHz to 3-GHz DECADE-BANDWIDTH LOW-NOISE GaN MMIC FEEDBACK AMPLIFIER WITH > +51-dBm OIP3
figure [7] at a cooler T ambient of 10 C. Moreover, these
LNAs obtained a higher 1-dB compression output power of
2 W (32.9 dBm), as indicated by the lower band of traces in
Fig. 1, and demonstrated flat and high OIP3’s of 45–46 dBm
across the band. Although these results demonstrated flat
low-NF and high-OIP3 responses across multiple octaves of
bandwidth, they do not possess the desirable flat gain response
due to the use of the inductive-source noise-matching technique. Although the inductive-source matching is a technique
that allows broadband noise-matching for conventional LNAs,
it also acts as negative feedback that increases with frequency
and results in a 5-dB gain roll-off from 18.7 dB of gain at
250 MHz down to 13.5 dB of gain at 3 GHz [6].
In this work, the focus was on achieving flatter broadband
gain using a cascode feedback topology and optimizing the design to obtain the highest OIP3 linearity in a 3-GHz bandwidth
while minimizing the impact to noise figure. In a previous
paper related to the present work [12], a 3-dB gain-bandwidth
was achieved over a 250–3000-MHz frequency with a nominal gain of 20 dB. The Cascode LNA [12] also resulted in
NFs 2.5-3 dB with an output power capability of 8 W, as
indicated in Fig. 1 (upper left traces). The corresponding OIP3
is better than 51 dBm across the band and benchmarks the
highest linearity in the OIP3-NF (dynamic range) trade-space
for GaN MMIC LNAs and is a 5–6-dB improvement in
OIP3 capability compared with other technologies in this
NF range for decade-bandwidth of operation, including the
inductive-source-matched LNA of [6] and [7].
In this present work, we discuss in greater detail the design
and analysis of the GaN Cascode-feedback MMIC amplifier design, including the GaN HEMT device noise characteristics, the
design trades between the common-source and Cascode topologies, the stability, and noise analysis, and will reveal a new wideband LNA low-NF performance benchmark.
This paper is organized as follows. Section II will describe
the Cascode feedback LNA designs, Section III will discuss
the measured and simulated -parameter, stability, and NF
performance as well as the IP3 and output characteristics, and
Section IV will summarize and conclude this work.
II. GAN CASCODE FEEDBACK MMIC DESIGN
Feedback amplifiers are noteworthy for their decade bandwidth performance and ability to operate down to baseband frequencies. Applications requiring baseband operation are CATV,
fiber optics, and SDRs. The emphasis of this work was to maintain flat gain while achieving the highest OIP3 linearity across
a 3-GHz band which may address future CATV, FTTP, basestation, and SDR system applications. While Darlington feedback amplifiers are noted for their superior OIP3-BW and flat
gain, they have modest noise figures due to the additive noise
of the low-gain input transistor. Distributed amplifiers are also
noted for their broadband power capability but were not considered here due to their modest noise figure which is fundamentally limited by their resistive input transmission line termination. While low noise techniques using active terminations
have yielded lower noise in distributed amplifiers [13], there
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TABLE I
COMMON-SOURCE VERSUS CASCODE-BASED LNA TOPOLOGY
is typically a fundamental tradeoff with linearity using an active input termination. In this work, feedback amplifiers using
common-source and Cascode device topologies were considered. Table I gives a summary of the key tradeoffs between
using a common-source configuration versus a Cascode configuration in a feedback amplifier. Since we are emphasizing flat
gain and highest OIP3 performance across a decade of bandwidth, the Cascode was considered based on its wider gainbandwidth over the common-source configuration due its suppression of the Miller effect (capacitance multiplication) [14],
however, more importantly, the Cascode may be operated at
twice the supply voltage which can enable 4–6-dB improvement in output power and OIP3 over a common-source amplifier. The disadvantages of the Cascode is the marginal stability
due to the higher maximum available gain (describe later in reference to Fig. 4) and slightly higher NF due to the additional
common-gate transistor of the Cascode which contributes additional channel noise compared to a common-source amplifier.
In the Introduction, it was mentioned that the focus of this
work was to obtain 50 dBm OIP3 over a 250–3000-MHz
bandwidth while achieving flat gain and minimizing the impact to noise figure. In order to optimize the design for OIP3
linearity, the upper limit in bias voltage and current needs
to be determined for the unit cell of the GaN process technology, since generally IP3 and output power will increase
with higher supply voltage and current. The designs of this
work employ Northrop Grumman’s 0.25- m GaN HEMT on
SiC substrate technology with full MMIC capability including
back-side vias, 150-pF/mm metal–insulator–metal (MIM)
capacitors, thin-film resistors (TFRs) and two levels of interconnect metal. The HEMT transistors have an fT 50 GHz and
a BVdg 60 V. Device dc gm is 285 mS/mm. The practical
operating voltage for class-A bias was determined to be a
conservative Vds
20 V although the device breakdown
would allow up to 28-V operation. Optimizing OIP3 and output
power involves increasing current density to a reliable limit
which, in this case, is limited by the maximum allowable
channel junction temperature. A typical maximum reliable
(junction temperature) for GaN is 200 C (a general rule of
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
Fig. 2. (a) Thermal simulation of an LNA. (b) T-junction estimation of a unit four-finger transistor.
Fig. 3. Comparison of dc –
configured devices.
curves: (a) common-source and (b) Cascode-
Fig. 4. Comparison of simulated maximum available gain (MAG) of
20 V and
(a) common-source and (b) Cascode-configured devices for
250 mA/mm.
thumb for GaN) but may vary depending on the details of the
specific process. At the time of this development, 200 C was
used as a general guideline for the design. Thermal analysis
of a four-finger 500- m total gate width unit cell was done
using a combination of a popular thermal simulation tool and
simple calculations modeling the physical layout. A pictorial
illustration of the thermal simulation of an example LNA
layout is shown in Fig. 2(a) along with the thermal distribution
within the fingers of a 500- m unit cell in Fig. 2(b). The results
reflect a
of 205 C at an
bias of 250 mA mm, and
this is the maximum current density guideline used for our
subsequent Cascode LNA feedback designs which Cascodes
two devices operating at a
of 20 V and 250 mA/mm of
current in an attempt to demonstrate maximum OIP3 and linear
output power.
Fig. 3 gives a comparison of the – characteristics of a
single common-source device operating at 20 V versus a Cascode device operating at 40 V. The 50- load-lines are shown
for reference where the quiescent bias current is set at the maximum current density of 250 mA/mm as indicated by the dots.
For the LNA design, the standard system impedance of 50 is
assumed as the load impedance of the amplifier, although, by
inspection, a lower impedance load would improve the linear
operation of either of the two device configurations which are
unfortunately constrained by the maximum practical bias current density of 250 mA/mm. However, by using the Cascode, a
higher operating
may be used while maintaining the same
junction temperatures. This results in higher saturated and linear
output power swing even though the knee voltage of the Cascode configuration has shifted to the right by roughly 15–20 V.
One benefit that can be seen by the Cascode – characteristics is the lower output conductance represented by the flat –
curves at higher voltages. Another benefit is the sharpness of the
knee voltages which are more abrupt than the common-source
transistor. Both of these features are subtle but are thought to
be conducive of better RF linear device operation. It should be
noted at this point that the gate of the common-gate device of the
Cascode may be adjusted such that the knee of the – curve of
the Cascode is shifted to the left resulting in a smaller
bias
for the common-source transistor of the Cascode. While this can
optimize P1dB of the Cascode, it was experimentally found that
the best OIP3 was obtained when
of the common-source
was roughly equal to
of the common-gate, even when
was adjusted down to maintain a
equal to a constant 20 V. It is believed that the Cascode operates more linearly when both devices operate with a high
voltage due
to the low output conductance and inhibition of drain modulation. For the remainder of this paper, the results for a given
operating voltage assumes that the voltage is equally split
between the common-source and the common-gate transistors
of the Cascode.
Another advantage of the Cascode versus the Commonsource configuration is its higher and broader maximum available gain which was simulated using a unit device cell size
KOBAYASHI: 8-W 250-MHz to 3-GHz DECADE-BANDWIDTH LOW-NOISE GaN MMIC FEEDBACK AMPLIFIER WITH > +51-dBm OIP3
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Fig. 5. 400- m gate width (four-finger) HEMT low noise characteristics: (a) NFmin at various current densities and (b) optimum noise source impedance, gamma
opt (Gopt), for various device gate widths.
Fig. 6. Detailed schematic of the GaN MMIC LNA and external bias-tee used in the characterization of the MMIC.
of total
500 m biased at a
of 20 V and
of
250 mA/mm, as illustrated in Fig. 4. The Cascode configuration
(b) has roughly 10 dB higher maximum available gain across a
wide frequency range than the common-source device (a) for
the same current density and gate width. Also shown are the
demarcation lines between the regions of conditionally stable
gain (
) and unconditionally stable gain (
) for each
trace. The trade off for the higher and wider gain is the wider
conditional stability through most of the Cascode’s available
gain bandwidth up to 66 GHz (the inflection point), compared
to 25 GHz for the common-source. However, stability can
be managed in the design using a series gate snubbing resistor
(
shown in the schematic of Fig. 6), where the simulated
and measured stability -factor results will be discussed in
Section III.
It is important to reemphasize that the focus of this LNA design work is, first, to achieve flat gain over a decade-bandwidth
from 250 to 3000 MHz while obtaining 50 dBm of OIP3 and,
second, to minimize (the impact on) noise figure. In order to
achieve high IP3 over a wide band, high device bias current density, measured in mA/mm of gate periphery, is required. This
conflicts with the low optimum noise current density bias that is
typically used in LNA designs. Fig. 5(a) illustrates the minimum
noise figure (NFmin) versus frequency of a four-finger 200- m
total gate width GaN HEMT transistor at various bias current
densities. This figure shows that the optimum noise bias occurs
at a low current density less than or equal to 100 mA/mm where
an NFmin of 0.6 dB is obtained at 2 GHz. As the current density is increased, so does the NFmin of the device. Because of
the high fT of this process which is 50 GHz, the NFmin degrades by only 0.15 dB in the band of interest ( 4 GHz) as
current density is increased to 300 mA/mm. At higher frequencies out of the band of interest, the NFmin degrades more dramatically ( 0.3 dB at 10 GHz) as current density is increased.
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Fig. 7. Effect of
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
on (a) gain and return loss and (b) noise figure performance.
Thus, a high current density of 250 mA/mm was determined
to be the best operating bias point for reliable, wide IP3-bandwidth, and decent noise figure for the designs of this work. In
order to achieve OIP3 50 dBm, it was determined that 3 mm
of total gate width ( 750 mA total bias) would be required for
a Cascode operating with a 40-V supply. Fig. 5(b) shows the
gamma optimum impedance for various gate peripheries (at a
current density of 250 mA/mm). For broadest noise match, it
is preferred to use a total gate periphery of around 1 mm where
the gamma opt is closest to a 50- system impedance. However,
this would only allow 250 mA of total bias current and would
not be adequate to achieve the 50-dBm OIP3. Using a 3-mm
total gate periphery would be adequate for an IP3-bandwidth of
50 dBm up to 3 GHz, but the noise figure would be compromised.
In this work, two different Cascode feedback amplifier designs were implemented—a high-bias design and a mediumbias design, both based on the Cascode feedback topology depicted in the simplified schematic in Fig. 6. The high-bias design is based on a total gate width of 3 mm and a nominal bias
of 40 V and 750 mA. This design uses the maximum gate periphery that would allow 3 GHz of 20-dB flat gain and high
IP3-bandwidth performance while maintaining a minimum of
10-dB return loss. The medium-bias design is based on a smaller
total gate width of 2 mm with a nominal bias of 40 V and
500 mA, in an attempt to achieve better input return-loss and
noise figure, but at the expense of OIP3 and output power performance. The main difference between the high-bias (3-mm gate)
and medium-bias (2-mm gate) design is the size of the active
device geometry. Referring to the schematic of Fig. 6, the basic
design employs - - feedback about a Cascode transconductance device. The feedback inductance is sometimes used to
reduce feedback and increase gain at the higher band edge. The
designs of this work do not exploit the inductive feedback for
peaking the gain and are instead represented by narrow width
parasitic micro-strip lines of 20 m 400 m in geometry.
In these designs, the feedback is dominated by the high resistive
impedance of 500 of the - feedback, which
employs a light amount of feedback between the output and
the input of the Cascode device structure to improve the broadband input and output return-loss match. Since the Cascode has
Fig. 8. Microphotograph of the “high-bias” (
code LNA feedback design. Chip measures 1.6
3 mm) GaN MMIC Cas1.3 mm .
a higher maximum available gain than the common-source configuration as previously illustrated, a series gate stability resistor
on the gate of the common-gate transistor of the Cascode
is used to obtain unconditional amplifier stability in the band of
interest. A nominal value of
30 was found to provide
reasonable stability -factor ( ) and its effect on noise figure
was a negligible increase of 0.05 dB. The measured and simulated stability -factor is given in the next section.
Fig. 7(a) and (b) illustrates the simulated performance effect
that the feedback resistor
has on the gain, return loss,
and noise figure performance of the high-bias 3-mm gate
periphery design. Fig. 7(a) shows that increasing the
from
500 to 3 K has the effect of higher gain roll-off across the
250–3000-MHz band while also degrading the input and output
return loss from 10 dB to 5 dB. The noise figure, on the
other hand, improves from 1.3 dB to 1 dB when the
is increased from 500 to 3 K , shown in Fig. 7(b). In order
to obtain excellent gain flatness and return losses better than
10 dB, a feedback resistor or 500 is used for both high-bias
(3-mm) and medium-bias (2-mm) designs. The Cascode is used
KOBAYASHI: 8-W 250-MHz to 3-GHz DECADE-BANDWIDTH LOW-NOISE GaN MMIC FEEDBACK AMPLIFIER WITH > +51-dBm OIP3
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Fig. 9. Measured (dashed) and simulated (solid) -parameters of the (a) 40-V 750-mA high-bias LNA and (b) 40-V 500-mA medium-bias LNA designs.
Fig. 10. Measured and simulated stability
-factor for the (a) 40-V 750-mA high-bias LNA and (b) 40-V 500-mA medium-bias LNA designs.
to distribute the voltage and manage the self-heating of the
individual unit cell HEMT transistors as discussed previously,
so that the channel junction temperatures may be minimized
while allowing an overall voltage operation of 40 V needed to
obtain high OIP3. The
voltage of both the common-source
and common-gate transistors in the Cascode is evenly split but
other distributions of
voltages can be employed to further
optimize the combination of noise figure and OIP3. In this
work, we have found experimentally that evenly splitting the
voltages results in high OIP3 linearity across the band.
Fig. 8 gives a microphotograph of the high-bias GaN MMIC
LNA design, which measures roughly 1.6 1.3 mm in size.
The layout is symmetrical and device unit cell combining
was optimized from both a thermal and electrical standpoint.
The high-bias design combines six 500- m unit cells for the
common-source and common-gate transistors of the Cascode
while the medium-bias design combines four 500- m units
cells for each transistor of the Cascode.
III. MEASURED RESULTS
Both 40-V 750-mA high-bias and 40-V 500-mA mediumbias MMIC designs were attached to a gold plated metal carrier for good thermal grounding and then fully characterized on
an RF probe station. All measurements were obtained at room
temperature and an output bias-tee was used to supply
and
to the MMIC chip as illustrated in the schematic of Fig. 6.
Fig. 9(a) and (b) gives the simulated and measured -parameters of the 40-V 750-mA high-bias and 40-V 500-mA medium-
bias designs, respectively. Both have a nominal low-frequency
gain of 20 dB at 250 MHz with 3 GHz of 3-dB bandwidth.
These plots show general good agreement between simulated
and measured -parameters for both designs. The simulations
predict flatter gain-bandwidths beyond 3 GHz, however, the
measured results meet the targeted bandwidth of 3 GHz. Regarding the measured results, the low frequency operation is
limited by the finite on-chip feedback capacitor which may be
increased in size to obtain performance down to 10 MHz if required. The
and
of the high-bias design of Fig. 9(a)
are better than 10 dB across most of the band and may easily
be tuned below 10 dB at the upper band edge using a series
wire-bond inductance and an open-stub or shunt capacitor element at the input. This high-bias design was scaled up in device
periphery in order to obtain the highest OIP3 over the intended
bandwidth and as a result, the input and output impedances were
reduced to roughly 30 and marginal 10-dB return-losses. The
medium-bias design of Fig. 9(b) achieves a significant improvement in
and
due to the use of 33% smaller device
periphery and the increase in input impedance of the transistors. It also achieves much better gain flatness through 3 GHz,
as shown in Fig. 9(b). Generally, the simulations do not predict the resonance in the input impedance and may be due to
electromagnetic layout circuit interaction at the input and in the
feedback path that were not taken into account using electromagnetic simulation.
The corresponding simulated versus measured stability
-factor is given in Fig. 10(a) and (b) for both high-bias and
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Fig. 11. Measured and simulated noise figure performance for both 40-V
750-mA high-bias and 40-V 500-mA medium-bias LNA designs.
medium-bias designs. The simulated results show the effect of
the
resistor on -factor for various values. A -factor
greater than 1 indicates unconditional two-port circuit stability.
The nominal value used in both designs are
30
applied to the gate of the common-gate transistor of the Cascode. The simulated -factor increases as
is increased
from 15 to 45 and is unconditionally stable in the frequency
of interest. As mentioned before, the impact to noise figure is
negligible over this value range. The measured -factor is also
well behaved (
) over the frequency band of interest, with
the exception of the high-bias design -factor dipping slightly
lower than 1 at around 8 GHz. The simulated -factor performance of the high-bias design (while not perfectly matched to
the measured data) suggests that a slightly higher
of 45
may push the -factor above 1 based on the simulation trend.
At low frequency it is noted that the -factor dips below 1 and
is a common characteristic of RC feedback designs where the
C provides an open circuit and zero feedback. In this region,
stability resembles that of a transistor without feedback and
is typically solved external to the chip using a combination
of choke inductor which provides a low impedance at low
frequencies, series input and output coupling capacitors, and
damping circuits which are beyond the scope of this work.
Fig. 11 gives the simulated and measured NF performance
of both MMIC designs. The 40-V 500-mA medium-bias design
achieves a measured NF less than 3 dB across a 3.5-GHz band
with a midband NF 2.5 dB @ 2 GHz. The 40 V–750 mA
high-bias design achieves less than 3.8 dB NF up to 3.5 GHz
with a midband NF of 3 dB. Considering the estimated
and the high output linearity that these designs achieve, these
are excellent noise results as indicated in Fig. 1. The simulated
NF of both designs, however, show predicted noise figures that
are less than 1.4 dB up to 3 GHz and are roughly 1.5–2 dB
lower than the measured noise figure data in this frequency
region for both cases. It should be noted that the models do not
account for gate shot noise, surface leakage noise, or elevated
junction temperature due to self-heating, all of which may be
a function of transistor bias voltage and current. In order to
demonstrate the broadband low noise capability of these LNAs,
the larger 3-mm periphery high-bias design was also measured
at a
20 V and an
300 mA which corresponds
to the technology’s optimum low noise bias current density of
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
Fig. 12. Measured and simulated noise figure performance of the high-bias
(3-mm) design at the optimum low noise current bias of 100 mA/mm and a
20 V.
100 mA mm. Fig. 12 gives the simulate and measured noise
figure response at this bias and reveals a dramatic reduction in
broadband noise figure. At 2 and 3 GHz respectively, a noise
figure of 0.96 dB and 1.5 dB were obtained. However, this
low noise is not achieved without compromising the output
characteristics. At this optimum-noise bias, the amplifier
achieves a respectable
43.3 dBm,
dB 32.2 dBm
and P3dB of over 2 W. What is revealing about the optimum
noise bias noise figure result is that it matches more closely to
the simulated noise figure in Fig. 12. This further suggests that
there is some bias dependent noise contributors that are not
accounted for in the device simulation model.
In an attempt to understand this discrepancy, a simple physical-based calculation of the noise figure contributions of the
40-V 750-mA high-bias LNA was plotted in Fig. 13. This
Figure breaks down the noise contributions into: 1) the thermal
noise of the gate, channel, and source contact resistances
; 2) the thermal noise of the feedback
resistor (
); and 3) the channel thermal noise
(1/gm), and a fixed “other noise” contribution which is hypothesized to be gate shot noise,
. This plot shows that
the thermal noise contributions due to
, , and
are not
very significant. The thermal noise contribution of the feedback
resistor contributes about 0.6 dB across the band and is slightly
significant at low frequencies but insignificant relative to the
channel thermal noise at frequencies above 2 GHz. The overall
shape of the measured noise figure follows the shape of the
frequency dependent channel thermal noise,
(1/gm). By
adding an effective Igate shot noise
(corresponding
to a forward gate current of 0.3 mA of the Cascode), an
additional 1.4-dB noise results and the total calculated noise
matches the measured noise. The gate current characteristics of
these few sample die may be underestimated by the simulation
model and appears to be a function of
and
bias. If we
assume that the gate shot noise becomes insignificant at lower
and
, then the calculated noise figure is roughly in the
1–2-dB range across the band which is close to the simulated
and measured noise figure of the optimum-noise-biased LNA
of Fig. 12, biased at a
10 V and
100 mA mm.
This is still a very coarse analysis and not entirely conclusive,
KOBAYASHI: 8-W 250-MHz to 3-GHz DECADE-BANDWIDTH LOW-NOISE GaN MMIC FEEDBACK AMPLIFIER WITH > +51-dBm OIP3
2323
Fig. 13. Calculated noise contributions of the high-bias LNA design operating
150 C).
at 40-V 750-mA (
Fig. 14. Output IP3 performance for both 40-V 750-mA high-bias and 40-V
500-mA medium-bias LNA designs.
but it is a simple and reasonable explanation for the higher
measured noise figure of this preliminary demonstration.
OIP3 was characterized for the 40-V 750-mA high-bias and
40-V 500-mA medium-bias designs and are given in Fig. 14.
Care was taken to ensure a 3:1 IM3 (third-order inter-modulation spur) slope with input power at the measurement power
level. The 40-V 500-mA medium-bias design achieves an
48 dBm up to 4 GHz while the 40-V 750-mA high bias
design achieves a remarkable
51 dBm up to 4 GHz,
and a midband OIP3 of 51.9 dBm at 2 GHz. While there is not
a lot of OIP3 performance published on GaN MMICs, based on
literature, this is believed to be state-of-the-art OIP3-NF performance combination for GaN MMIC amplifiers that operate
from baseband to C-band frequencies. With respect to typical
HFET performance, the GaN MMIC in this paper demonstrates
5–6 dB higher OIP3 for similar or better noise (details to be
discussed later). It should also be noted that these GaN MMIC
LNAs have 20 dB of flat gain across the band in comparison to
the narrowband tuned transistor performance which is typically
described in literature. Fig. 15 illustrates the high-bias design’s
OIP3 dependence on
voltage. For each
bias, the
voltage is evenly split between the top and bottom transistors
of the Cascode where
. These measurements
indicate a strong IP3 dependence on
with 6 dB change
in IP3 when
is doubled from 20 to 40 V. This may be
explained by the – curve of the Cascode topology in Fig. 3
which suggests that the knee voltage scales proportionately
with higher
(when
and
are equal) and that a
20-V
will correspond to a 10-V knee (assuming
and
are equal) and a 40-V
will correspond to a 20 V
knee, or double the linear voltage swing. It should be noted
that the distribution of the
and
voltages may be
optimized for different linearity-noise combinations tailored
for specific applications.
To put the GaN Cascode LNA’s decade-bandwidth OIP3 performance in perspective, it is worth comparing its performance
with the RF industry’s Darlington feedback amplifier design,
which is known for its superior OIP3-BW performance [15],
[17]–[20], but modest noise figure as previously mentioned.
Fig. 16 gives an OIP3 versus frequency performance comparison for several key Darlington amplifier technology bench-
Fig. 15. Output IP3 performance as a function of
high-bias LNA design.
for the 40-V 750-mA
mark results. The Darlington feedback design has been employed with InGaP HBT, E-mode PHEMT [19], [20], and, more
recently, GaN HEMT technology [15] resulting in exceptional
OIP3-BW performance. The GaN Cascode FB designs of this
work demonstrate as much as a 10-dB improvement in absolute OIP3 over these previous Darlington feedback MMIC amplifier technology benchmarks illustrating the higher OIP3-BW
performance capability of GaN with the lower noise Cascode
feedback approach.
The LNAs’s corresponding P-1dB and Psat output power
versus frequency response is given in Fig. 17 for both 40-V
750-mA high-bias and 40-V 500-mA medium-bias designs.
The medium-bias design achieves a
36 dBm (4 W)
across the band with a
dB 36.8 dBm (4.8 W) at 2 GHz.
The high-bias design achieves a Psat and P1dB of 39.2 dBm
(8.3 W) and 38.5 dBm (7.1 W) at 2 GHz, respectively. This is
believed to be among the highest output powers recorded for a
low noise amplifier design for any semiconductor technology.
An important observation is the small delta between Psat
and P1dB across the band which is within 1 dB, indicating
a very abrupt compression. This abrupt compression may be
attributed to the Cascode’s sharp knee voltage and low output
conductance of its – characteristics discussed earlier.
Fig. 18 gives state-of-the-art noise figure performance for
GaN, GaAs PHEMT, HBT, and HFET-based - and -band
LNAs, gain blocks (GBs), and discrete transistors. This
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
Fig. 16. IP3 comparison with previously reported Darlington-based feedback
amplifiers in E-PHEMT, InGaP HBT, and GaN technologies.
Fig. 18. Summary of - and
for various technologies.
Fig. 17. P1dB and Psat performance for both 40-V 750-mA high-bias and 40-V
500-mA medium-bias LNA designs.
two-dimensional performance trade-space is a general way to
illustrate the dynamic range capability of various technologies. By inspection it can be seen that NFs
1 dB can be
obtained by both E-mode and D-mode PHEMTs, however
they are typically limited to
42 dBm in OIP3 due to their
modest breakdown and operating voltages. HFETs on the
other hand can achieve OIP3s up to 47 dBm but with higher
NFs 2–4.5 dB, while GaAs HBTs can efficiently achieve
high OIP3s above 50 dBm but this is accompanied by even
higher NF in the 4.3–7-dB range which is due to their finite
dc beta and high base shot noise. GaN technology has been
able to demonstrate superior OIP3-NF performance in this
2-D trade-space, as indicated by the oval area in Fig. 18 and
is due to its intrinsic material and HEMT device properties.
For example, OIP3s between 44–46 dBm have been obtained
with NFs between 0.45–0.85 dB for GaN HEMT LNAs[6],
[7]. This work benchmarks state-of-the-art
51 dBm
across a 250–3000-MHz bandwidth with respectable NFs
in the 2.5–3-dB range, demonstrating the highest linearity
in the OIP3-NF (dynamic range) trade-space for GaN-based
LNAs. This result is a 5–6-dB improvement in OIP3 capability
compared to other technologies in this NF range. Moreover, it
-band LNA, GB, discrete IP3-NF performance
should be noted that the GaN data-points of this work represent
decade-bandwidth MMIC performance whereas many of the
other technologies represent narrowband tuned results.
Finally, Table II gives a summary of GaN MMIC - and
-band LNA and feedback amplifier design performance. Previously reported GaN LNA MMICs have demonstrated OIP3s
of 46 dBm. The lowest noise figures have been achieved using
an inductive-source-matched feedback amplifier [6], [7] with
noise figures below 1-dB and OIP3 as high as 46 dBm. However, the gain of the inductive-source-matched design has a fast
gain roll-off across a 2–8-GHz band even though the IP3 and
NF response is relatively flat. On the other hand, GaN-based
Darlington and distributed amplifiers have demonstrated excellent gain flatness and decent IP3’s which can easily be improved
if the bandwidth is traded off. However, both of these topologies have modest noise figures in the 3–6-dB range and are
inherently limited by their basic design topologies. The GaN
HEMT Cascode feedback designs of this work demonstrate the
best combination of ultra high IP3 and good noise figure with
flat gain across a decade of bandwidth up to 3 GHz. For example, the 40-V 750-mA high-bias Cascode design of this work
achieves the highest OIP3 ( 51 dBm) reported for a GaN feedback MMIC LNA design with a respectable noise figure in the
range of 2.5–3 dB. Table II also gives two key linearity figures of merit in the last two columns;
and
dB . These figure-of-merits are useful when
comparing the back-off linear efficiency of infrastructure LNAs.
The Cascode LNA MMIC of this work achieves among the
highest OIP3/Pdc LFOM 5.2:1 and the highest
dB
13.4 dB demonstrated so far for a broadband GaNbased MMIC LNA and indicates a good approach for achieving
decade-bandwidth, high linearity, and low noise performance.
However, it should be noted that state-of-the-art linear-optimized GaN HEMT device technology is relatively new compared with more mature GaAs HEMT linear-optimized technologies, and it is expected that much better GaN linear efficiency figure-of-merit benchmarks will be reported in the future.
KOBAYASHI: 8-W 250-MHz to 3-GHz DECADE-BANDWIDTH LOW-NOISE GaN MMIC FEEDBACK AMPLIFIER WITH > +51-dBm OIP3
SUMMARY OF GAN MMIC
- and
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TABLE II
-BAND LNA AND FEEDBACK AMPLIFIER DESIGN PERFORMANCE
IV. CONCLUSION
High linearity and low noise have been demonstrated for a
GaN Cascode feedback LNA across a decade-bandwidth from
250 to 3000 MHz which is believed to be an improvement
in state-of-the-art OIP3-NF performance over GaAs HEMT-,
HBT-, and HFET-based LNAs and GB MMICs in the - and
-band regime. The GaN Cascode feedback designs of this
work were shown to achieve better OIP3 bandwidth performance than previously reported Darlington feedback amplifiers
fabricated with E-PHEMT, InGaP HBT, and GaN HEMT technologies that are known for their excellent linearity-bandwidth
performance. The GaN Cascode feedback MMIC amplifiers
of this work show promising linearity and noise performance
that can be enabling for future infrastructure systems such as
extended range CATV, FTTX, flexible base-stations, and SDRs.
ACKNOWLEDGMENT
The author would like to acknowledge the contributions
of T. Sellas, C. Kitani, R. Dry, D. Willis, D. Jin, J. Johnson,
D. Aichele, J. Shealy, K. Krishnamurthy, R. Vetury, C. Young,
A. Upton, B. Nelson, D. Runton, J. Martin, N. Hilgendorf,
and many other RFMD engineers whose works and ideas are
represented here. I would also like to acknowledge Northrop
Grumman for their support of their GaN technology including
the following contributors; R. To, W.-B. Luo, I. Smorchkova,
B. Heying, W. Sutton, Y.C. Chen, M. Wojtowicz, A. Oki,
S. Grimm, E. Rezek, W. Simmons, and F. Kropschot.
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Kevin W. Kobayashi (M’93–SM’10) was born in
San Diego, CA, in 1963. He received the B.S.E.E. degree from the University of California at San Diego,
La Jolla, in 1986, and the M.S.E.E. degree from the
University of Southern California, Los Angeles, in
1991.
From 1986 to 2000, he was with TRW, Redondo
Beach, CA, working on the design and insertion of
HBT, HEMT, and MESFET MMICs into TRW satellite systems. During that time, he had contributed to
the design of many of the first GaAs MESFET and
HBT MMICs which were inserted and flown in space qualified systems. He was
one of the original pioneers of III-V HBT MMIC design technology which led
to the commercialization of GaAs HBT technology in mobile phones and wireless products in the 1990s for companies like RFMD and Sirenza Microdevices.
While at TRW, he was a corecipient of three TRW chairman’s awards for Innovation for the development of GaAs HBT technology for TRW systems (1991),
for adapting GaAs HBT IC technology to commercial applications (1995), and
for the development of a high-performance 1- m GaAs HBT IC Technology
for flight payload applications and emerging commercial business (1997). He
has also been a key contributor to the development of InP HBT MMIC tech-
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 10, OCTOBER 2012
nology benchmarking some of the Industry’s first and highest performance InP
HBT MMICs in the 90’s. He was also a TRW Principal Investigator for a multiyear MMIC Linearization R&D project aimed at cost-effective techniques for
improving linearity and dynamic range performance for next generation high
data rate fiber and RF communication systems. In 1998, he was promoted to
TRW Technical Fellow for his contributions to the development of HBT MMIC
design and technology. In 2000, he joined Sirenza Microdevices (formerly Stanford Microdevices) as the Director of wire-line product development where he
established their fiber IC product line. From 2001 to 2004, he held the positions
of Director and Senior Director of advanced design, focusing on new product
initiatives in the Hi-REL/military, broadband IC, and mixed signal areas. He
has been involved in establishing and managing the patent IP at Sirenza and has
contributed over 18 patents for Sirenza’s fiber IC and core RF amplifier product
lines. In 2004, he was promoted to Executive Engineering Fellow leading advanced R&D projects at Sirenza. In September of 2007, he joined RF Micro
Devices as an RFMD Fellow after the merger between Sirenza Microdevices
and RFMD. He has been the primary author of over 125 technical papers that
have been published in IEEE journals, IEEE refereed conferences, and technical
magazines. In addition, he holds 47 U.S. patents in the field of microwave semiconductor device and IC design with several patents pending.
Mr. Kobayashi served four years as an associate editor for the IEEE JOURNAL
OF SOLID-STATE CIRCUITS (JSSC) from 1998 to 2002 and had served on the
TPC and executive committees of the GaAs IC symposium from 1988 to 2006.
He was the 2005 General Conference Chairman, for the Compound Semiconductor IC (formerly GaAs IC) symposium and the 2006 advisor Chairman. He
also served as the 2007 International microwave symposium (IMS) special and
focused sessions chairman. Since 2001, he has been involved with the TPC and
steering committee of the Radio Frequency Integrated Circuits (RFIC) conference and has held the posts of RFIC symposium chairman for panel sessions
(2008), student papers (2009), publicity (2010), publications/digest (2011) and
co-chair of the 2012 workshops.