Hspice Introduction (Basic) Zou Zhige 2009 Winter Contents 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 2 1 SPICE Overview ¾ SPICE : Simulation Program with Integrated Circuit Emphasis ¾ Developed by University of California/Berkeley (UCB) ¾ Numerical Approach to Circuit Simulation ¾ Circuit Node/Connections Define a Matrix ¾ Must Rely on Models for Behavior of Various Circuit Elements ¾ Simple (e.g. Resistor) ¾ Complex (e.g. MOSFET) ¾ Most of the SPICE tools are originated from Berkeley’s SPICE program Zou Zhige VLSI, EST 3 Contents 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 4 2 HSPICE Data Flow Zou Zhige VLSI, EST 5 Netlist Statements and Elements TITLE * or $ .OPTIONS First line is Input Netlist File Title Commands to Describe Circuit Set Conditions for Simulation Analysis(AC,DC,TRAN..) & .TEMP Statements to Set Sweep Variables .PRINT/.PLOT/.PROBE/.GRAPH Set Print, Plot, and Graph Variables .IC or .NODESET Sets Initial State .VEC `digital_vector_file` Sets Input Stimuli File Sources (I or V) Sets Input Stimuli Schematic Netlist Circuit Description + In first Column ,+, is Continuation Char. .SUBCKT/.ENDS Sets/Ends Subcircuit Description .MEASURE (Optimization Optional) Provides Scope-like Measurement Capability .LIB or .INCLUDE Call Library or General Include Files .MODEL Library Element Model Descriptions .DATA or .PARAM Specify parameters or Parametric Variations .ALTER Sequence for In-line Case Analysis .DELETE LIB Remove Previous Library Selection .END Required Statement to Terminate Simulation Zou Zhige VLSI, EST 6 3 Netlist Structure Title ---------------------Æ Title Statement Controls ---------------Æ .option nomod nopage | .tran 1 10 | .print v(5) i(r1) |-------Æ .plot v(3) v(in) * voltage sources Sources -------------Æ v3 3 0 dc 0 ac 0 pulse 0 1 0 0.1 0.1 4 8 vin in 0 sin(0 2 10k 0.5 0) * Components Components -------Æ c2 2 0 2pf| r1 1 0 1k | m1 1 2 3 4 mod L=10u W=30u |----Æ x3 2 3 INV *Model & Subcircuit Models & Subckts Æ .model... or .LIB or .Subckt End file---------------Æ .end Zou Zhige VLSI, EST 7 Element and Node Naming Conventions ¾ Instance and Element Names: ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ C Capacitor D Diode E,F,G,H Dependent Current and Voltage Controlled Sources I current J JFET or MESFET K Mutual Inductor L Inductor M MOSFET Q BJT R Resistor O,T,U Transmission Line V Voltage Source X Subcircuit Call Zou Zhige VLSI, EST 8 4 INDEX 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 9 Sources ¾ ¾ ¾ ¾ ¾ V6 6 0 DC=5V AC=1V Pulse (PULSE Function) Sinusoidal (SIN Function) Exponential (EXP Function) Piecewise Linear (PWL Function) Zou Zhige VLSI, EST 10 5 Example PULSE Vin 1 0 PULSE ( 0V 5V 10ns 10ns 10ns 40ns 100ns ) Zou Zhige VLSI, EST 11 Example PWL v3 3 0 pwl(0 0.5 10n 0.5 20n 4.5 2u 4.5 2.01u 0.5 4u 0.5 4.01u + 2.49 6u 2.49 6.01u 2.6 8u 2.6 8.01u 2.4 10u 2.4) Zou Zhige VLSI, EST 12 6 INDEX 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 13 Analysis Types & Orders ¾ DC Operating Point : First Calculated for ALL Analysis Types .OP …… ¾ DC Sweep & DC Small Signal Analysis : .DC …… ¾ Transient Analysis: .TRAN …… ¾ AC Sweep & Small Signal Analysis : .AC …… ¾ Other Advanced Modifiers : Temperature Analysis, Optimization Zou Zhige VLSI, EST 14 7 DC Operating Point Analysis Initialization and Analysis: ¾ First Thing to Set the DC Operating Point Values for All Nodes and Sources : Set Capacitors OPEN & Inductors SHORT ¾ Using .IC or .NODESET to set the Initialized Calculation ¾ If UIC Included in .TRAN ==> Transient Analysis Started Directly by Using Node Voltages Specified in .IC Statement Zou Zhige VLSI, EST 15 DC Operating Point Analysis ¾ .OP Print out (1). Node Voltages; (2). Source Currents; (3). Power Dissipation; (4). Semiconductors Device Currents, Conductance, Capacitance Zou Zhige VLSI, EST 16 8 DC Sweep & DC Small Signal Analysis DC Analysis Statements : ¾ .DC : Sweep for Power Supply, Temp., Param., & Transfer Curves ¾ .OP : Specify Time(s) at which Operating Point is to be Calculated ¾ .PZ : Performs Pole/Zero Analysis (.OP is not Required) ¾ .TF : Calculate DC Small-Signal Transfer Function (.OP is not Required) Zou Zhige VLSI, EST 17 DC Sweep & DC Small Signal Analysis .DC Statement Sweep : ¾ Any Source Value ¾ Any Parameter Value ¾ Temperature Value ¾ DC Circuit Optimization ¾ DC Model Characterization Zou Zhige VLSI, EST 18 9 AC Sweep & Small Signal Analysis AC Analysis Statements : ¾ .AC : Calculate Frequency-Domain Response ¾ .NOISE : Noise Analysis Zou Zhige VLSI, EST 19 AC Sweep & Small Signal Analysis .AC Statement Sweep : ¾ Frequency Element ¾ Temperature ¾ Optimization ¾ .param Parameter Zou Zhige VLSI, EST 20 10 Transient Analysis Transient Analysis Statements : ¾ .TRAN : Calculate Time-Domain Response ¾ .FOUR : Fourier Analysis ¾ .FFT : Fast Fourier Transform Zou Zhige VLSI, EST 21 INDEX 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 22 11 Output Files Summary Zou Zhige VLSI, EST 23 Output Commands ¾ .PRINT Statement : Print Numeric Analysis Results ¾ .PLOT Statement : Generates Low Resolution Plot in .lis file ¾ .PROBE Statement : Allows Save Output Variables Only into the Graph Date Files ¾ .MEASURE Statement : Print Numeric Results of Measured Specifications Zou Zhige VLSI, EST 24 12 Algebraic Expressions ¾ Parameterization : .PARAM WN=5u LN=10u VDD=5.0V ¾ Algebra : .PARAM X=‘Y+5’ ¾ Functions : .PARAM Gain(IN, OUT)=‘V(OUT)/V(IN)’ ¾ Algebra in Element : R1 1 0 r=‘ABS(V(1)/I(M1))+10’ Zou Zhige VLSI, EST 25 Index 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 26 13 Elements and Device Models ¾ What’s Elements? ¾ What’s Models? ¾ Instance ¾ Device’s Characteristics Zou Zhige VLSI, EST 27 (1). Types of Elements ¾ Passive Devices : ¾ R ---- Resistor ¾ C ---- Capacitor ¾ L ---- Inductor ¾ Active Devices : ¾ ¾ ¾ ¾ ¾ K ---- Mutual Inductor D ---- Diode Q ---- BJT J ---- JFET and MESFET M ---- MOSFET ¾ Other Devices : ¾ Subcircuit (X) ¾ Behavioral (E,G,H,F,B) ¾ Transmission Lines (T,U,O) Zou Zhige VLSI, EST 28 14 Passive Devices Parameters R1 12 17 1K TC1=1.3e-3 TC2=-3.1e-7 Zou Zhige VLSI, EST 29 BJT BJT Model Syntax : .MODEL mname NPN (PNP) <param=val> ......... BJT Syntax Examples : Q100 NC NB NE QPNP AREA=1.5 AREAB=2.5 + AREAC=3.0 IC= 0.6, 5.0 Zou Zhige VLSI, EST 30 15 MOSFET Model Syntax MOSFET Element Syntax Mxxx nd ng ns <nb> mname <L=val> + <W=val> <AD=val> <AS=val> + <PD=val> <PS=val> <NRD=val> + <NRS=val> + <OFF> <IC=vds,vgs,vbs> <M=val> + <TEMP=val> <GEO=val> <DELVTO=val> Zou Zhige VLSI, EST 31 MOSFET Element Statement Examples: M1 24 2 0 20 MN L=5u W=100u M=4 M2 1 2 3 4 MN 5u 100u M3 4 5 6 8 N L=2u W=10u AS=100P + AD=100p PS=40u PD=40u .OPTIONS SCALE=1e-6 M1 24 2 0 20 MODN L=5 W=100 M=4 Zou Zhige VLSI, EST 32 16 MOSFET Model Statement Examples .MODEL MODP PMOS LEVEL=2 VTO=-0.7 + GAMMA=1.0...... .MODEL NCH NMOS LEVEL=39 TOX=2e-2 UO=600.......... Zou Zhige VLSI, EST 33 Corner_LIB of Models .LIB TT or (FF|SS|FS|SF) .param toxn=0.0141 toxp=0.0148...... .lib ‘~/simulation/model/cmos.l’ MOS .ENDL TT or (FF|SS|FS|SF) .LIB MOS .MODEL NMOD NMOS (LEVEL=49 + TOXM=toxn LD=3.4e-8 , ......) .ENDL MOS Zou Zhige VLSI, EST 34 17 Index 1. SPICE Overview 2. Simulation Input and Controls 3. Sources and Stimuli 4. Analysis Types 5. Simulation Output and Controls 6. Elements and Device Models 7. Optimization 8. Control Options & Convergence 9. Graphic Tools 10. Applications Demonstration Zou Zhige VLSI, EST 35 Hspice用户界面 Zou Zhige VLSI, EST 36 18 波形工具AvanWaves Zou Zhige VLSI, EST 37 查看仿真结果 title .options post probe .probe v(a) v(b) v(out) 双击 Zou Zhige VLSI, EST 38 19 分析仿真结果 由波形可知实现了 与门的功能 Zou Zhige 多信号波形显示在overlay和 stacked两种模式间切换,目前 为stacked,将切换为overlay Waves zoomer 点击右键 VLSI, EST 39 分析仿真结果 加指针可以显示时间、电 压等,可用来测量与门输 出的tr, tf, td等指标 Zou Zhige VLSI, EST 40 20 Simple Case Zou Zhige VLSI, EST 41 Netlist * Project of NMOS Characteristics M1 2 1 0 0 MN W=5U L= 2U M=1 *M? D G S B Model W L M VGS 1 0 1V VDS 2 0 5V .OP .lib 'D:\*.LIB' MOS_TT .DC VDS 0 5 0.1 VGS 1 5 1 .PRINT DC V(2) I(M1) .OPTION .END Zou Zhige VLSI, EST 42 21 仿真结果 Zou Zhige VLSI, EST 43 Two-stage OP AMP Design * Target specification : * CL = 10pF, Av>5000, * GB=5MHz * 1 < CMR < 4 , 0.5 < Vout < 4.5 * SR > 10 V/us , Pdiss < 2 mW , Zou Zhige VLSI, EST 44 22 NETLIST *Two stage OP design * Netlist information M1 3 IN1 5 0 MN L=2UM W=9.9UM M=1 M2 OUT1 IN2 5 0 MN L=2UM W=9.9UM M=1 M3 3 3 VDD VDD MP L=2UM W=21.6UM M=1 M4 OUT1 3 VDD VDD MP L=2UM W=21.6UM M=1 M5 5 BIAS 0 0 MN L=2UM W=30. 5UM M=1 M6 OUT OUT1 VDD VDD MP L=2UM W=14.1UM + M=10 M7 OUT BIAS 0 0 MN L=2UM W=10UM M=10 Zou Zhige VLSI, EST 45 NETLIST (Cont.) * Feedback CAP CC OUT1 OUT 3.5PF CL OUT 0 10PF * Voltage sourses VDD VDD 0 5 VIN1 IN1 0 DC 2 VIN2 IN2 0 DC 2 AC 1 Zou Zhige VLSI, EST 46 23 NETLIST (Cont.) .DC …… .PRINT …… .lib 'D:\Hspice\*.lib' mos_tt .option post nomod .TEMP 27 .END Zou Zhige VLSI, EST 47 ICMR Analysis IN2 Æ OUT VIN1 IN1 0 DC 0 .DC VIN1 0 5 0.1 .PRINT V(VIN1) V(OUT) Zou Zhige VLSI, EST 48 24 DC Operation Point Analysis VIN2 IN2 0 2.5 .dc vin1 0 5 0.1 .print dc v(vout) Zou Zhige VLSI, EST 49 DC Small Signal TF analysis ¾ TF analysis: .tf V(out) vin1 .dc vin1 2.495 +2.505 100u .print dc v(out) Zou Zhige VLSI, EST 50 25 DC Small Signal TF analysis **** small-signal transfer characteristics v(out)/vin1 input resistance at vin1 output resistance at v(out) = -314.1943 = 1.000e+20 = 22.9429k total voltage source power dissipation= 48.2779m watts Zou Zhige VLSI, EST 51 AC Frequency Analysis vin2 2 0 2.5v vin1 1 0 DC 2.5v AC 1 .OP * AC Analysis function .ac dec 10 10 100MEG .print ac vdb(vout) vp(vout) vdb(4) vp(4) Zou Zhige VLSI, EST 52 26 AC Frequency Analysis Result ¾ GB = 4MHz ¾ Phase Margin is 60 degree Zou Zhige VLSI, EST 53 AC Frequency Analysis (Cont.) vin2 2 0 2.5v vin1 1 0 DC 2.5v AC 1 .ac dec 10 10 100MEG .meas ac Unit_gain when vdb(out)=0 .meas ac phase_mar FIND vp(out) when vdb(out)=0 Result (from the List file) unit_gain= 4.0694E+06 phase_mar= 6.2236E+01 Zou Zhige VLSI, EST 54 27 Unity-Gain Transient Response vin1 in1 0 pwl(0 0.5 10n 0.5 +20n 4.5 2u 4.5 2.01u 0.5 +4u 0.5 4.01u 2.49 6u +2.49 +6.01u 2.6 8u 2.6 8.01u 2.4 +10u 2.4) .tran 0.05u 10u 0 10n .print tran v(out) Zou Zhige VLSI, EST 55 PSRR Analysis VDD VDD 0 DC 5 AC 1 .ac dec 10 10 100MEG .probe ac vdb(out) vp(out) Zou Zhige VLSI, EST 56 28 The END Thank You! 29