XU-RT
V 1.01 7/19/16
XMC with Dual 2.5 GSPS A/D, Dual 2.8 GHz DAC, Kintex Ultrascale FPGA, 4GB Memory and x8 PCIe
FEATURES
• Two 2.5 GSPS, 14-bit A/D channels
• Two 2.8 GSPS 16-bit DACs
• 1.0Vp-p, AC-Coupled, 50 ohm, SMA inputs
and outputs
• Xilinx Kintex Ultrascale XCKU060/085 FPGA
• 2 Banks of 64-bit, 2GB DRAM (4 GB total)
• Ultra-low jitter programmable clock
• Arbitrary Waveform Generation Memory
Controller for DACs
• Gen3 x8 PCI Express providing >7.0 GB/s
sustained transfer rates
• XMC Module (75x150 mm)
• 40W typical
• Conduction Cooling per VITA 20
• Ruggedization Levels for -40 to 85C and 0.1
g2/Hz vibration/ 40g shock environments
• Adapters for PXIe, VPX, desktop/rackmount
PCI and cabled PCI Express systems
APPLICATIONS
•
•
•
•
•
•
Wireless Receiver
WLAN, WCDMA, WiMAX front end
RADAR
Medical Imaging
High Speed Data Recording and Playback
IP development
SOFTWARE
• MATLAB/VHDL FrameWork Logic
• Windows/Linux Drivers
• C++ Host Tools
DESCRIPTION
The XU-RT integrates complex, 2.5 GSPS digitizing and 2.8 GHz signal
generation with real-time signal processing on an XMC IO module for
demanding DSP applications. The tight coupling of the analog I/O to the
Kintex Ultrascale FPGA core realizes architectures for SDR, RADAR, and
LIDAR front end sensor digitizing and processing. The PCI Express system
interface sustains transfer rates at 7.2 GB/s for data recording and integration
as part of a high performance real-time system.
The XU-RT features a dual-channel, 14-bit 2.5 GSPS A/D and a dual-channel,
2.8 GSPS 16-bit DAC, each with bandwidth over 5 GHz, suitable for wideband,
undersampling applications.
Internal mixers and decimator/interpolator
capabilities (respectively) allow concurrent, real-time frequency conversion.
The sample clock may be sourced via an ultra-low-jitter internal PLL or
externally via a front-panel SMA and multiple cards can be phasesynchronized to the individual sample.
A Xilinx Kintex Ultrascale XCKU 060/085 with 4GB DDR4 RAM, addressable
as two 64-bit banks, provide a very high performance DSP core f or demanding
applications such RADAR and wireless IF generation . The close integration of the
analog IO, memory and host interface with the FPGA enables real-time signal
processing at extremely high rates.
The XU family can be fully customized using VHDL and MATLAB and the
FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-theloop development using the graphical, block diagram Simulink environment with
Xilinx System Generator.
IP logic cores are also available for SDR applications that provide multi-channel
down/up converters and real-time spectrum analysis. These IP cores transform the
XU-RT module into versatile transceiver, ready for integration into your application.
Software tools for host development include C++ libraries and drivers for Windows
and Linux. Application examples demonstrating the module features and use are
provided, including streaming DAC samples from disk. The XU-RT can be used with
the Andale high speed data record/playback system for arbitrary waveform
generation from recorded data at sustained rates of 7200 MB/s.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Innovative Integration
products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Innovative Integration standard warranty. Production processing does not necessarily
include testing of all parameters.
07/20/16
©2016 Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
XU-RT
This electronics assembly can be damaged by ESD. Innovative Integration recommends that all electronic assemblies and
components circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can
cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated
circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its
published specifications.
ORDERING INFORMATION
Product
XU-RT
Part Number
80337-<CFG><ER>
Description
XMC module with dual-channel, 14-bit 2.5 GSPS A/D, dual-channel 2.8 GSPS 16-bit DAC, Kintex
Ultrascale, 4GB DRAM.
<CFG> is configuration.
0 - Kintex Ultrascale XCKU060, speed grade 2, Gen3 PCIe, AC-Coupled A/D, AC-Coupled DAC,
1 - Kintex Ultrascale XCKU085, speed grade 2, Gen3 PCIe, AC-Coupled A/D, AC-Coupled DAC
<ER> corresponds to -L0, -L1, -L2, -L3 or -L4 rating from Operating Environment Table below.
XU-RT FrameWork
Logic
55048
XU-RT FrameWork Logic board support package for RTL and MATLAB. Includes technical
support for one year.
67048G
Coax cable with SMA (plug) to BNC (female), 1 meter
Desktop XMC-PCIe
Adapter
80363
Adapts XMC to desktop PCI Express gen 3
I/O Extension Board
80369
Exposes eight J16 GTH links via dual QSFP connectors and 16 Digital I/O via Samtec connector
Desktop XMC-PCIe
Adapter
80259
Adapts XMC to desktop PCIe gen2 exposing eight J16 GTH links via eight SATA3 connectors and
16 Digital I/O via MDR 68 connector
XMC-PXIe Adapter
80341
Adapts XMC to PXI Express 8 HP format. Integrated mezzanine board exposes eight J16 GTH
links via dual QSFP connectors and 16 Digital I/O via Samtec connector
XMC-cPCI/PXI
Adapter
80207
3U compact PCI carrier card for XMC PCI Express modules, 64-bit PCI. Support for PXI clock and
trigger features (logic dependent).
DAQ Node
90181
Remote XMC enclosure with x1 cabled PCI Express.
3U VPX Adapter
80260
Conduction-cooled for forced-air 3U VPX adapter for XU with REDI cover option
ePC-Duo
90602
Windows/Linux Embedded Computer with Dual XMC IO Sites and Integrated Timing Support
ePC-Nano
80342
A Windows/Linux Embedded Single Board Computer with XMC IO Site and 1 GbE Link
VPXI-ePC
90271
Air Cooled 4U 1/2 Rack OpenVPX Windows/Linux/VxWorks Computer with Four
Peripheral/Payload Slots
Andale
90036
Wideband Data Recorder with up to 144 TB Hard Disk Array
Cables
SMA to BNC cable
Adapters
Embedded PC Host
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
2 of 16
XU-RT
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
3 of 16
XU-RT
Illustration 1: Block diagram detail
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
4 of 16
XU-RT
Operating Environment Ratings
XU modules rated for operating environment temperature, shock and vibration are offered. The modules are qualified for
wide temperature, vibration and shock to suit a variety of applications in each of the environmental ratings L0 through L4
and 100% tested for compliance. Click this link “Ruggedization Levels” to see the Ruggedization Levels available.
Minimum lot sizes and NRE charges may apply. Contact sales support for pricing and availability.
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
5 of 16
XU-RT
Standard Features
Analog Inputs
Inputs
2
Input Range
1.4 Vpp
Input Type
Single ended, AC-coupled
Input
Impedance
50 ohm
A/D Device
Analog Devices AD9689
A/D
Resolution
14-bit
A/D Sample
Rate
100 MHz to 2.5 GHz
Wideband
Processors
Dual, 48-bit NCO, 4 cascaded half-band
filters
FPGA
Device
Xilinx Ultrascale
XCKU060-2FFVA1517E
XCKU085-2FLVA1517I
Speed Grade
-2 (commercial)
Size
XCKU060: ~9M gate equivalent
XCKU085: ~15M gate equivalent
Flip-Flops
XCKU060: 663,360
XCKU085: 995,040
DSP Slices
XCKU060: 2760
XCKU085: 4100
Analog Outputs
Slices
XCKU085: 4100
Block RAMs
Outputs
2 channels
Output Range
1 Vpp
Output Type
Single ended, AC-coupled
Output
Impedance
50 ohm
DAC Device
Analog Devices AD9136
DAC
Resolution
16-bit
DAC Update
Rate
100 MHz to 2.8 GHz
Filter
Selectable 1,2,4,8 interpolation,
Digital inverse SINC
XCKU060: 2760
XCKU060: 38.0 Mb
XCKU085: 56.9 Mb
GTH and GTY
Transceivers
XCKU060: 32@16.3 Gbps
Configuration
SelectMAP from on-board flash
EEPROM - JTAG during development
XCKU085: 56@16.3 Gbps
Memories
DRAM Size
4 GB total
8 devices @ 256Mb x16 each
(increase to 8GB probable as higher density
footprint compatible memories are validated
with and supported by the FPGA)
DRAM Type
DDR4 DRAM
DRAM
Controller
Controller for DRAM implemented in logic.
Each 64 bit interface uses 2.5 FPGA I/O banks,
10@ 13 bit FPGA I/O Byte lanes (4 per bank).
Total DRAM
Bandwidth
38.4GB/s maximum bandwidth (100% data
buss efficiency, applications' efficiency varies)
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
6 of 16
XU-RT
Host Interface
Monitoring
PCI Express
8-lane high speed serial interface
compliant with XMC PCIe Protocol
Layer Standard VITA 42.3-2006
Alerts
Trigger Start, Trigger Stop, Queue
Underflow, Timestamp Rollover,
Temperature Warning and Failure
PCI Express Sustained
Rate
PCIe: 7.2 GB/s/interface with 2.5
specified bit clock when limited by a
possibly minimally VITA 42.3-2006
compliant host / connection.
FPGA supports optional higher
speed protocols: (future gen4),
Aurora, user defined, etc...
Alert Timestamping
TBD: goal <= 2 sample clock periods
resolution for sample clock timed
events, others resolved by the capture
clock period used, 32-bit counter
Clocks and Triggering
Clock Sources
System Reference: Ext. or Int. TCXO
Master PLL: LMK0482x
(used for references for slave PLLs,
JESD 204B sysref, opt. trigger, etc...)
2X Slave (DAC) PLLs: TRF3765
300 to 4800 MHz in PLL mode
(DAC clock and trigger / alignment)
External Inputs: 2@ (one for each
DAC) Sine to TBD > 5100 MHz
(goal > 8000 MHz), 0 dBm nominal
AC-coupled, 50-ohm terminated,
SMA
PLL Reference
System Reference: Ext. or Int. TCXO
Master PLL: LMK04828
(used for references for slave PLLs,
JESD 204B sysref, opt. trigger, etc...)
2X Slave (DAC) PLLs: TRF3765
300 to 4800 MHz in PLL mode
(DAC clock and trigger / alignment)
Application IO
Gigabit Serial Lanes
8 Tx/Rx pairs
Gigabit Serial data rate
10 Gbps/lane full duplex
DIO Bits, total
16
Signal Standard
LVCMOS (2.5V) – NOT 3.3
compatible
Drive
+/-12 mA
Connectors
XMC J16
Power
Consumption
40W (VPWR = 5V, 1 DDR bank
and no Aurora ports instantiated, 4
lane PCIe)
65W (VPWR = 12V, 4 DDR
banks, all Aurora ports, 8 lane
PCIe)
Temperature Monitor
Software with programmable
alarms
PLL Resolution
100 kHz tuning resolution (default)
Over-temp Monitor
Disables power supplies
Jitter
Internal: TBD <300 fs rms
External: TBD approx. 50 fs additive
Power Control
Channel enables and power up
enables
Triggering
50 ohm DC coupled input, with
optional programmable levels, modes
External, software, play N frame
Heat Sinking
Conduction cooling supported
(VITA20 subset)
Channel Clocking
Both channels are synchronous
Multi-card
Synchronization
Within one ADC/DAC clock period, external timing
reference or clock inputs can synchronize cards or
external clocks with external triggers or sysrefs may be
provided and used.
Channel Clocking
Both channels can be synchronous
Physicals
Form Factor
Single width IEEE 1386
Mezzanine Card
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
7 of 16
XU-RT
ELECTRICAL CHARACTERISTICS
At 24C ambient.
Parameter
Typ
Units
Notes
Analog Input Bandwidth
5000
MHz
-3dB
SFDR
78
70
dBc
1000 MHz sine input, 95%FS, Fs = 2.5 GSPS
3000 MHz sine input, 95%FS, Fs = 2.5 GSPS
S/N
62
dBFS
340 MHz sine input, 98%FS, Fs = 2.0 GSPS
THD
TBD
dB
340 MHz sine input, 85%FS, Fs = 2.0 GSPS
ENOB
10.4
bits
340 MHz sine input, 98%FS, Fs = 2.0 GSPS
Channel Crosstalk
<-93
dB
71 MHz sine input, 9dBm adjacent channel input, Fs = 2.5
GSPS
dBFS/Hz
Input grounded, Fs = 2.5 GSPS, 64K sample FFT, nonaveraged
A/D Performance – AC coupled
Noise Density
-150
Gain Error
<1%
% of FS
Calibrated
Offset Error
<1
mV
Calibrated
Analog Output Bandwidth
5000
MHz
SFDR
82
76
81
dBc
20 MHz @ -9 dBFS, 983.04 MSPS sample rate
150 MHz @ -9 dBFS, 983.04 MSPS sample rate
20 MHz, -9 dBFS, 1966.08 MSPS sample rate
IMD
-90
82
90
dBc
20 MHz @ -9 dBFS, 983.04 MSPS sample rate
150 MHz @ -9 dBFS, 983.04 MSPS sample rate
20 MHz, -9 dBFS, 1966.08 MSPS sample rate
ENOB
11.3
bits
71 MHz sine output, AC coupled
Noise spectral density
-160
-161
dBm/Hz
150 MHz @ 0dBFS, 983.04 MHz sample rate
150 MHz @ 0dBFS, 983.04 MHz sample rate
Channel Crosstalk
<-85
dB
Aggressor = 125.1 MHz, -3 dBfs adjacent channel
Gain Error
<1 %
% of FS
Calibrated
Offset Error
<500
μV
Calibrated
Gain Error
<1 %
% of FS
Calibrated
Offset Error
<500
μV
Calibrated
DAC Performance – AC Coupled
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
8 of 16
XU-RT
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
9 of 16
XU-RT
Architecture and Features
The XU-RT module architecture integrates analog I/O with an FPGA computing core, memories and PCI Express host
interface. This architecture tightly couples the FPGA to the analog for real-time signal processing with low latency and
extremely high rates. The XU-RT is an ideal front-end for demanding applications in wireless, RADAR and medical imaging
applications.
Data flows between the IO and the
host using a packet system
Analog IO
The analog front end of the XU-RT module has
two simultaneously sampling channels of 14-bit,
2.5 GSPS A/D input and two channels of 2.8
GSPS, 16-bit DAC output. The analog I/O have an
analog input bandwidth of 5 GHz for use in
wideband and direct sampling applications.
The ADC and DAC devices connect directly to the
FPGA and employ JESD204B communications
protocol. In the standard logic, the A/Ds have an
interface component that receives the data, provides
digital error correction, and a FIFO memory for
buffering. A non-volatile ROM on the card is used
to store the calibration coefficients for the analog
and is programmed during factory test.
Data
Buffer
1GB
A/D
Packetizer
2 channels
PCI
Express
Interface
Alerts
Triggering
DAC
Data Buffer
1GB
w/ AWG Ctl
Host
Packetizer
2 channels
XU Architecture
The DAC is supported for both streaming and AWG modes. In the AWG mode, the memory controller plays a dynamic
linked list of data buffers in memory to the DAC at up to full rate. The data buffers, along with their playback parameters are
supplied by the host via PCIe or by the logic. The playback parameters include gain level, how many times to play, playback
termination methods, and next buffer to play.
Controls for triggering allow precise control over the collection of data and are integrated into the FPGA logic. Trigger
modes include frames of programmable size, external and software. Multiple cards can sample simultaneously by using
external trigger inputs. The trigger component in the logic can be customized in the logic to accommodate a variety of
triggering requirements.
FPGA Core
The XU Module family has a Kintex Ultrascale FPGA and memory at its core for DSP and control. The Kintex Ultrascale
FPGA is capable of over 8.2 TeraMACs with over 600 DSP elements in the ‘060 FPGA. In addition to the raw processing
power, the FPGA fabric integrates logic, memory and connectivity features that make the FPGA capable of applying this
processing power to virtually any algorithm and sustaining performance in real-time. The FPGA has direct access to two 64bit banks of DDR4 RAM. These memories allow the FPGA working space for computation, required by DSP functions like
FFTs, and bulk data storage needed for system data buffering and algorithms like Doppler delay. A multiple-queue controller
component in the FPGA implements multiple data buffers in the DRAM that is used for system data buffering and algorithm
support.
The XU module family uses the Kintex Ultrascale FPGA as a system-on-chip to integrate all the features for highest
performance. As such, all IO, memory and host interfaces connect directly to the FPGA – providing direct connection to the
data and control for maximum flexibility and performance. Firmware for the FPGA completely defines the data flow, signal
processing, controls and host interfaces, allowing complete customization of the XU module functionality. Logic utilization
of the standard Framework Logic is <10% of the device.
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
10 of 16
XU-RT
PCI Express Host Interface
The XU architecture delivers over 7.0 GB/s sustained data rates over PCI Express gen 3 using the Velocia packet system. The
Velocia packet system is an application interface layer on top of the fundamental PCI Express interface that provides
efficient and flexible bus-mastering transfers at high data rates with minimal host support. The packet data system controls
the flow of packets to the host, using a credit system managed in cooperation with the host software. The packets may be
transferred continuously for streams of data between host memory and XMC analog I/O or as occasional packets for status,
controls and analysis results. For all types of applications, the data buffering and flow control system delivers high
throughput with low latency and complete flexibility for data types and packet sizes to match the application requirements.
Firmware components for assembling and dissembling packets are provided in the FrameWork Logic that allow applications
to rapidly integrate data streams and controls into the packet system with minimum effort.
System Data Plane Ports and Digital IO
The XU module family has eight high speed serial data links on J16 for system interconnect, operating at up to 10 Gbps per
link, full duplex. These links enable the XU modules to integrate into switched fabric systems such as VPX to create
powerful computing and signal processing architectures. The standard logic uses these lanes as two Aurora ports of 4 lanes
each. Other protocols such as sRIO and sFPDP may be implemented in the FPGA.
J16 also 16 digital lines routed directly from the FPGA via length-matched differential pairs. Some of these signals originate
in the analog I/O FPGA banks, supporting operation synchronous with the ADC and DAC sample clocks. This is ideal for
applications such as PRI within RADAR systems or state signalling in quantum computer control.
Module Management
The XU family has facilities for temperature monitoring within the FPGA die. The temperature sensor is monitored by a
dedicated CPLD, so that power shuts when a critical temperature is exceeded. This function is independent of the FPGA.
The data acquisition process can be monitored using the Velocia module alert mechanism. The alerts provide information on
the timing of important events such as triggering, overranges and thermal overload. Packets containing data about the alert
including an absolute system timestamp of the alert, and other information such as current temperature. This provides a
precise overview of the card data acquisition process by recording the occurrence of these real-time events making the card
easier to integrate into larger systems.
FPGA Configuration
The modules uses a FLASH memory to configure the Kintex Ultrascale FPGA image. This FLASH can be programmed insystem using a supplied software applet.
During development, the JTAG interface to the FPGA is used for development tools such as ChipScope and MATLAB. The
FPGA JTAG connector is compatible with Xilinx Platform USB Cable.
Software Tools
Software development tools for the module provide comprehensive support via the Malibu Libraries, including device
drivers, data buffering, card controls, and utilities that allow developers to be productive from the outset. At the most
fundamental level, the software tools deliver data buffers to your application without the burden of low-level real-time
control of the cards. Software classes provide C++ developers a powerful, high-level interface to the card that makes realtime, high speed data acquisition easier to integrate into applications.
Software for data logging and analysis are provided with every module. Data can be logged to system memory at full rate or
to disk drives at rates supported by the drive and controller. Triggering and sample rate controls allow you to use the
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
11 of 16
XU-RT
module's performance in your applications without ever writing code. Innovative software applets include Binview which
provides data viewing, analysis and import to MATLAB for large data files.
Support for the Microsoft, Embarcadero and GNU C++ toolchains is provided. Supported OSes include Windows and
Linux, 32- and 64-bit. Ports to environments such as VxWorks can be provided on a custom basis, upon request. For more
information, the software tools User Guide and on-line help may be downloaded.
Logic Tools
High speed DSP, analysis, customized triggering and
other unique features may be added to the module by
modifying the logic. The FrameWork Logic tools
provide support for RTL and MATLAB
developments. The standard logic provides a hardware
interface layer that allows designers to concentrate on
the application-specific portions of the design.
Designer can build upon the Innovative components
for packet handling, hardware interfaces and system
functions, the Xilinx IP core library, and third party
IP. RTL source for the FrameWork Logic is provided
for customization. Each design is provided as a Xilinx
Vivado project, with a testbench illustrating logic
functionality.
Using MATLAB Simulink for Logic Design
The MATLAB Board Support Package (BSP) allows logic development using Simulink and Xilinx System Generator. These
tools provide a graphical design environment that integrates the logic into MATLAB Simulink for complete hardware-in-theloop testing and development. This is an extremely power design methodology, since MATLAB can be used to generate,
analyze and display the signals in the logic real-time in the system. Once the development is complete, the logic can be
embedded in the FrameWork logic using the RTL tools. Alternately, the HLS (high-level synthesis) features of Vivado may
be used to implement DSP algorithms from existing C/C++ source.
The FrameWork Logic User sales brochure and User Guide more fully detail the development tools. Some of the more
important logic functions are shown here.
Logic Core
PCIe Interface
Description
Features
Interface to PCI Express bus supporting x1 to x8 lanes,
Gen1, 2 or 3. Implements Velocia packet system and
SOC bus.
Supports sustained data rates of up to 7.0 GB/s. Automates DMA
transfers to the system using Velocia packet protocol.
Aurora Interface
Interface to dual, x4 Aurora port for system expansion and
data communications.
Provides up to 10.0 GB/s data port to other cards for system
expansion and data plane integration. Sub-channel support for
messaging.
Router
Velocia packet router.
Dynamically steers packets amongst source and destination logic
components.
Packetizer
Creates Velocia or VITA 49 packets.
Data packetizing and buffering for logic components for integration
into Velocia packet system.
Deframer
Parses Velocia packets and dissembles them.
Deframer is used to extract data payloads from packets for logic
component integration into Velocia packet system.
Wishbone bus provides flexible bus architecture for designers.
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
12 of 16
XU-RT
IP for XU Modules
Innovative provides a range of down-conversion channelizer logic cores for wideband and narrowband receiver applications.
The XU modules provide powerful receiver functionality integrated for IF processing with the addition of these cores.
The DDC channelizers are offered in channel densities from 4 to 256. The four channel DDC offers complete flexibility and
independence in the channels, while the 128 and 256 channel cores offer higher density for uniform channel width
applications. The DDC cores are highly configurable and include programmable channel filters, decimation rates, tuning and
gain controls. An integrated power meter allows the DDC to measure any channel power for AGC controls. Multiple cores
can be used for higher channel counts.
Each IP core is provided with a MATLAB simulation model that shows bit-true, cycle-true functionality. Signal processing
designers can then use this model for channel design and performance studies. Filter coefficients and other parameters from
the MATLAB simulation can be directly loaded to the hardware for verification.
DDC Cores
Part
Number
IP Core
Channels
Tuning
Decimation
Max
Channel Filter
Bandwidth
58014
IP-MDDC4
4
Fs/2^32
16 to 32768
Fs/16
Programmable 100 tap filter
58015
IP-MDDC128
128
Fs/2^32
512 to 16384
Fs/512
Programmable 100 tap filter
58528
IP-DDC256
256
Fs/2^32
512 to 16384
Fs/512
Programmable 100 tap filter
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
13 of 16
XU-RT
Applications Information
Cables
The XU-RT module uses coaxial cable assemblies for the analog I/O. The mating cable should have an SMA male connector
and 50 ohm characteristic impedance for best signal quality.
XMC Adapter Cards
XMC modules can be used in desktop/rackmount PC systems, PXI/PXIe or VPX chassis via available adapter cards. An
auxiliary power connector to the PCI Express adapters provides additional power capability for XMC modules when the slot
is unable to provide sufficient power. The adapter cards allow the XMC modules to be used in any PCIe or PCI system.
The XU-RT XMC modules couple Innovative's powerful Velocia architecture with two high performance 8-lane PCI Express
links connected to the carrier as well as sideband signals for control and status. Protocols such as Serial Rapid IO and Aurora
may be implemented for host communications or custom protocols.
Note that the high speed GTY IO lanes require a host card electrically capable of supporting the high speed signal pairs.
Only the eight lane adapter, P/N 80295 is suitable for high speed P16 applications.
PXIe-XMC Adapter (80341)
PCIe-XMC Adapter x8 lane
VPX-XMC Adapter (80260)
DAQ-Node (90181)
x8 PCIe to XMC
(80295)
Clock and trigger inputs
x8 PCIe to XMC
Rugged Conduction or Air Cooled
XMC Adapter with IPMI Support
eInstruments Enclosure with
Cabled PCI Express Carrier
x8 RIO ports supported on P16
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
14 of 16
XU-RT
Applications that need remote or portable IO can use either the ePC-Duo or ePC-Nano with any XMC module.
eInstrument PC with Dual PCI Express XMC Modules
(90602)
SBC-Nano, Dual Core Atom+ heatsink, 4 GB RAM, 32 GB eMMC,
XMC site
Windows/Linux embedded PC
(80342)
8x USB, GbE, cable PCIe, VGA
PC with single XMC site. 75x150mm (XMC) footprint
High speed x8 interconnect between modules
Allows use of XMC modules in autonomous, “stand-alone” applications
GPS disciplined, programmable sample clocks and triggers to XMCs
1 GbE Ethernet, USB2 links
2000 MB/s, 4 TB datalogger
Rugged L3, Conduction cooled
9-18V operation
Software transparent, runs standard Windows/Linux or RTOS variants
Optional expansion board provides 2x mSATA for up to 2 TB storage
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
15 of 16
XU-RT
IMPORTANT NOTICES
Innovative Integration Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and
other changes to its products and services at any time and to discontinue any product or service without notice. Customers
should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to Innovative Integration’s terms and conditions of sale supplied at the time of order
acknowledgment.
Innovative Integration warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with Innovative Integration’s standard warranty. Testing and other quality control techniques are used to the
extent Innovative Integration deems necessary to support this warranty. Except where mandated by government
requirements, testing of all parameters of each product is not necessarily performed.
Innovative Integration assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using Innovative Integration products. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
Innovative Integration does not warrant or represent that any license, either express or implied, is granted under any
Innovative Integration patent right, copyright, mask work right, or other Innovative Integration intellectual property right
relating to any combination, machine, or process in which Innovative Integration products or services are used. Information
published by Innovative Integration regarding third-party products or services does not constitute a license from Innovative
Integration to use such products or services or a warranty or endorsement thereof. Use of such information may require a
license from a third party under the patents or other intellectual property of the third party, or a license from Innovative
Integration under the patents or other intellectual property of Innovative Integration.
Reproduction of information in Innovative Integration data sheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with
alteration is an unfair and deceptive business practice.
Innovative Integration is not responsible or liable for such altered documentation. Resale of Innovative Integration products
or services with statements different from or beyond the parameters stated by Innovative Integration for that product or
service voids all express and any implied warranties for the associated Innovative Integration product or service and is an
unfair and deceptive business practice. Innovative Integration is not responsible or liable for any such statements.
For further information on Innovative Integration products and support see our web site:
www.innovative-dsp.com
Mailing Address: Innovative Integration, Inc.
741 Flynn Road, Camarillo, CA 93012
Copyright ©2015, Innovative Integration, Incorporated
Innovative Integration • phone 805.383.8994 • fax 805.482.8470 • www.innovative-dsp.com
16 of 16