Analog-to-Digital Converter Circuit and System
Design to Improve with CMOS Scaling
Yousof Mortazavi
Department of Electrical and Computer Engineering
The University of Texas at Austin
PHD DEFENSE
April 16, 2015
COMMITTEE MEMBERS
Brian L. Evans
Arjang Hassibi
Todd E. Humphreys Earl E. Swartzlander, Jr.
Ahmed H. Tewfik
CMOS Scaling of Digital Integrated Circuits
Metal-­‐Oxide-­‐ Semiconductor (MOS) Transistor •  Scaling CMOS transistor dimensions results in
–  exponential increase in number of transistors per chip [Moore’s law]
–  lower capacitance, delay, active power dissipation, cost
Feature size
3 μm
0.8 μm
16 nm
# of Transistors
29K
3.1M
10B+
Die Photo/Year
Intel x86
(1978)
Source: http://en.wikipedia.org/wiki/Transistor_count
Intel Pentium
(1993)
Oracle Sparc M7
(exp: 2015)
Background | Architecture | Prototypes | Nonlinearity | Conclusions
2
CMOS Scaling of Mixed-Signal/Analog Circuits
•  Analog circuits generally don’t scale like digital circuits
•  State-of-the art CMOS processes are digital-friendly, but analog-hostile
Good:
reduced: capacitance, active power increased: speed Bad:
reduced: supply voltage, voltage headroom
Ugly:
increased: mismatch, noise, short-channel effects, nonlinearity
reduced: intrinsic transistor gain, signal-to-noise ratio, dynamic
range
“Good, Bad, Ugly” sketch courtesy of Kevin Graham: http://www.kevingrahamart.com/
3
Analog-to-Digital Converters
•  Typical ADC: •  An=aliasing filter (ideally) enforces band-­‐limitedness to BW •  Sampling is lossless if fs >2 =
2 BW (Nyquist rate) q
•  Quan=za=on is lossy, i.e. it a12
dds noise 2
q
=
12
FS
= N
2
(1)
(1)
(2)
•  Signal-­‐to-­‐quan=za=on noise ra=o: SQNR = 6.02 N + 1.76 (dB) Background | Architecture | Prototypes | Nonlinearity | Conclusions
4
Analog-to-Digital Converter Area Trend
1000
ISSCC
VLSI Symposium
Area (mm2)
100
10
1
0.1
0.01
0.001
1997
1999
2001
2003
2005
2007
2009
2011
2013
2015
Year
B. Murmann, "ADC Performance Survey 1997-2015," [Online].
Available: http://web.stanford.edu/~murmann/adcsurvey.html.
Background | Architecture | Prototypes | Nonlinearity | Conclusion
5
Contributions
Analog-to-Digital Converter Circuit and System Design
to Improve with CMOS Scaling
Time-Based Delta
Sigma ADC
Architecture &
Modeling
•  Novel architecture with loop delay calibration
•  Combines time-based information
processing & noise shaping
Two Prototype
ADC Chips
•  Prototype chips demonstrate proof of concept
•  Among smallest area in literature
Nonlinearity
Estimation and
Correction
•  Up to 16 dB improvement in SNDR with digital
calibration
•  Diagnostic tool for identifying linearity bottleneck
Background | Architecture | Prototypes | Nonlinearity | Conclusion
6
Delta Sigma Modulation (DSM)
•  Idea: – start with low-­‐resolu=on quan=zer (1 to few bits) – use feedback to shape noise spectrum as high-­‐pass, and – use oversampling and digital lowpass filtering to reduce noise 1st Order DSM Background | Architecture | Prototypes | Nonlinearity | Conclusion
7
Time-Based Signal Processing
1001…
Time-Based
Time-to-Digital
Voltage-to-Time
Signal
Converter
Converter
IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 3, MARCH 20
Processing
•  Benefits from scaling perspec=ve: – Improved =ming accuracy with CMOS scaling – Digital implementa=on – Not thermal noise limited, no need for large (a) Band-limiting DTC output. (b) Extending the ⌃ concept to DTC.
capacitances 3-­‐bit Flash TDC [Roza97] Fig. 12.
Block diagram for a flash TDC.
Figure 2.7: A 3-bit flash time-to-digital converter [17]
Background | Architecture | Prototypes | Nonlinearity | Conclusion
8
Digitally-Assisted Analog Scheme
•  A trend in the literature, to improve analog circuit performance
through digital methods [Murmann2010]
Digital Nonlinearity Compensation
•  The availability of cheap (power/area) digital circuits makes
these methods more attractive as processes scale.
Analog
Nonlinearity
Digital
Inverse
•  Example:
Vin
Dout
Dout,corr
Parameters
Modulation
System
ID
Use system
ID to
determine
optimum
post distortion
Background
| Architecture
| Prototypes
| Nonlinearity
| Conclusion
9
Thesis Statement
Architect low-area delta-sigma data converters
that scale with CMOS technology by replacing
voltage-domain with time-domain processing.
Background | Architecture | Prototypes | Nonlinearity | Conclusion
10
Prior Art
•  Voltage Controlled Oscillator (VCO)-Based Delta Sigma ADC
•  Time-Based Delta Sigma ADCs
–  Using asynchronous delta sigma modulator
–  Time-to-Digital Converters (TDCs)
Background | Architecture | Prototypes | Nonlinearity | Conclusion
11
VCO-Based Delta Sigma ADC
•  Continuous-time integration (1/s) is inherent.
•  Sampling VCO phase at periodic intervals gives quantized
phase.
•  VCO nonlinearity (KVCO) is an important limitation.
–  [Rao2011] proposes two-level PWM modulator to avoid the problem
Voltage
controlled
osc.the
–  [Taylor2013] uses digital calibration
and post-correction
to mitigate
problem
23
Background | Architecture | Prototypes | Nonlinearity | Conclusion
12
Prior Art
•  Time-Based Delta Sigma ADCs
–  Asynchronous delta-sigma modulation [Dhanasekaran2009, Taillefer2009,
Daniels2010]
–  Time Encoding Quantizer (TEQ)-based ADCs [Prefasi2009]
Background | Architecture | Prototypes | Nonlinearity | Conclusion
13
First Contribution
Time-Based Delta Sigma ADC
Architecture & Modeling
Image source: http://www.intel.de/content/www/de/de/cofluent/intel-cofluent-studio.html
14
Time-Based Processing Encoding/Operands
Conventional Pulse
Pseudo-Differential Pulses
Figure
3.2: Definition of pulse and
pseudo-di↵erential
(conceptual) pu
Pulse Width
Addition
Pulse
Width Subtraction
is simple
to understand;TINhowever, for
TIN
TIN both accuracy and robustness, ps
TIN
Trigge r
Tadd
Trigge r
Trigge r
Trigge r
Tsub
Tsub
di↵erential pulses are often preferred. A pseudo-di↵erential pair of p
Tadd
(Tb,rise , Tb,f all ) as shown in Fig. 3.2, encode pulse width in the time dur
TOUT
TOUT
0
TOUT
TOUT
between the rise transition of Tb,rise and that of Tb,f all .
0
t
t
0
0
t
(a)
(b)
(b)
The advantages
of pseudo-di↵erential
pulses
Background(a)
| Architecture
| Prototypes
| Nonlinearity
| Conclusion
t
for encoding analog
15
System Model
VTC/Adder
DCU
TDC/DTC
DTC
Voltage-to-Time Converter
(VTC)/Adder
Samples
Z
Vin(V)
VTC
T1 Pha se
Detector
U(z)
T4
Vin @ t = kTs
Converts it to ΔTin[k]
Excess
Delay
Z
-1
-1
TDC
T2
DOUT[k]
Y(z)
V(z)
E(z)
T3
(a)
kTs
Sam pling Time
(k+1)Ts
T4
Adds it to the
feedback pulse T4
Result = T1
Σ
td,VTC/Adder
td,Exe ss D elay
T1
td,Phase Dete ctor
T2
ΔTIn[k]
td,DTC/TDC
Δ
T3
Tsub[k] = Dout [k-1] Δ
Background | Architecture | Prototypes | Nonlinearity | Conclusion
(b)
16
System Model
VTC/Adder
DCU
TDC/DTC
DTC
Digital-to-Time Converter
(DTC)
Z
Vin(V)
VTC
T1 Pha se
Detector
U(z)
Subtracts from T2
Dout[k-1] units
T4
Time-to-Digital Converter
(TDC)
Sam pling Time
quantizes the result to get
Σ
Excess
Delay
Z
-1
-1
TDC
T2
DOUT[k]
Y(z)
V(z)
E(z)
T3
(a)
kTs
(k+1)Ts
T4
td,VTC/Adder
T1
td,Phase Dete ctor
Dout[k]
td,Exe ss D elay
T2
ΔTIn[k]
td,DTC/TDC
Δ
T3
Tsub[k] = Dout [k-1] Δ
Background | Architecture | Prototypes | Nonlinearity | Conclusion
(b)
17
System Model
VTC/Adder
DCU
TDC/DTC
DTC
Delay Control Unit (DCU)
and Excess Delay
Z
Vin(V)
VTC
T1 Pha se
Detector
U(z)
ensure uniform sampling
T4
by adjusting
td, Excess Delay
Excess
Delay
Z
-1
-1
TDC
T2
DOUT[k]
Y(z)
V(z)
E(z)
T3
(a)
kTs
Sam pling Time
(k+1)Ts
T4
Σ
td,VTC/Adder
td,Exe ss D elay
T1
td,Phase Dete ctor
T2
ΔTIn[k]
td,DTC/TDC
Δ
T3
Tsub[k] = Dout [k-1] Δ
Background | Architecture | Prototypes | Nonlinearity | Conclusion
(b)
18
TDC/DTC
•  TDC = Time-to-Digital Converter
•  DTC = Digital-to-Time Converter
Figure 3.6: Functional block diagram of the TDC/DTC
Background | Architecture | Prototypes | Nonlinearity | Conclusion
19
Voltage-to-Time Converter/Adder
Tin
rin
rout
Vref
rin
Ramp
Gen
VRa mp_r
Vref
VRa mp_r
Tout
rout
fin
fout
Vin
fin
fout
Ramp
Gen
Vin
VRa mp_f
VRa mp_f
Figure 3.5: Functional
diagram
and timing
diagram
of the VTC/Adder.
Backgroundblock
| Architecture
| Prototypes
| Nonlinearity
| Conclusion
20
Simulink Modeling
fout
0.25
VinMin
VinMin
rout
rin
rin
fin
fout
rout
rin
fout
fin
fin
lag
dout
dout
rout
To Workspace
fout
TDC/DTC
VTC/Adder
resetb
lead
Phase Detector
Scope
resetb
lead
fout
lag
fin
rout
rin
Excess Delay
Figure 4.1: Top-Level Simulink Model of the proposed time-based
⌃ ADC
ematical sine function at the true sampling instance in each cycle (t = fin (k)).
Background
Architecture
| Prototypes
Nonlinearity
| Conclusion
This is the
reason | for
the absence
of |an
input sine
wave in the model of
21
Simulink Modeling - DCU
3
resetb
1
rin
>
1
rout
>
2
fout
td_phase_detector
2
fin
Ts
1
z
>
3
lag
<
4
lead
Td_hyst
Phase Detector
Td_hyst
Excess Delay
1
fout
1
z
3
fin
Td_hyst2
2
lag
2
rout
1
z
Td_hyst2
1
td_fixed_delay
lead
4
rin
Figure 4.5: Simulink model for the Excess Delay block of the proposed timebased ⌃ ADC
Background
| Architecture | Prototypes | Nonlinearity | Conclusion
22
Simulink Modeling
1.5
×10
-9
Phase Detector/DTC Output
1
0.5
0
0
100
200
300
400
500
600
700
800
500
600
700
800
500
600
700
800
500
600
700
800
Digital Output
6
4
2
0
0
100
200
300
400
Lag Signal
1
0.5
0
0
100
200
300
400
Lead Signal
1
0.5
0
0
100
200
300
400
Figure 4.8: Waveforms for di↵erent signals in the behavioral model of the
Background | Architecture | Prototypes | Nonlinearity | Conclusion
proposed time-based ⌃ ADC.
23
Role of DCU in Reducing Distortion
DCU Disabled
Spectrum exhibits major harmonic distortion
due to non-uniform sampling
DCU Enabled
Spectrum is virtually distortion free
Background | Architecture | Prototypes | Nonlinearity | Conclusion
24
Role of DCU in Reducing Distortion
DCU Disabled
DCU Enabled
Background | Architecture | Prototypes | Nonlinearity | Conclusion
25
Effect of DTC Element Mismatch
Background | Architecture | Prototypes | Nonlinearity | Conclusion
26
Effect of TDC Element Mismatch
Background | Architecture | Prototypes | Nonlinearity | Conclusion
27
Comparison of DTC/TDC Element Mismatch
Background | Architecture | Prototypes | Nonlinearity | Conclusion
28
Second Contribution
Prototype ADC Chips
Image source: http://www.intel.de/content/www/de/de/cofluent/intel-cofluent-studio.html
29
First Generation Chip in TSMC 180nm
TSMC = Taiwan Semiconductor Manufacturing Company
Background | Architecture | Prototypes | Nonlinearity | Conclusion
30
First Generation Chip Details
Table 5.1: First-Generation Chip Parameters
Parameter
Value
Process
TSMC 180nm 6M 1P
Supply Voltage (VDD )
1.8
Oversample Frequency (fs )
144
Quantizer (TDC) Number of Bits
3
DAC (DTC) Number of Bits
3
TDC LSB ( )
80
td,VTC/Adder
2.1
td,PhaseDetector
0.57
td,DTC
1.24
td,ExcessDelay (Average)
2.8
Area
0.0275
Units
V
MHz
bits
bits
ps
ns
ns
ns
ps
mm2
Table 5.2: Summary of Measurement Results of First-Generation
Quantity Value Units
5.2.1 VTC/Adder
fs
144
MHz
Recall from Chapter 3 that the VTC/Adder consists of two identical
OSR
36
half circuits, each of which have a ramp generator and a continuous-time
comBW
2.0
MHz
fin 6.1. 146.1 kHz
parator. The circuit topology of the VTC/Adder is shown in Fig.
Vin,pk pk
400
mV
SNR
dB
The ramp generator consists of a wide-swing current
source (I44.6
B =
SNDR
34.6
dB
200µA), an integrating capacitor (CI = 110fF), and digital switches to creTHD
-35.0
dB
ate a 0 to 640ps full scale T⌃ [k] corresponding to a (0.28V-0.68V)
ENoBlinear range
5.5
bits
Power
2.7
mW
of Vin with Vref = 0.28V.
The continuous-time
is a| Nonlinearity
PMOS-input folded-cascode
Background
| Architecture comparator
| Prototypes
| Conclusion dif-
5.3.3
Experimental Results
31
First Generation Chip Waveforms
0
7
modulator output
decimated output
-20
5
Amplitude (dBFS)
Modulator Output (dout)
6
4
3
2
-40
-60
-80
1
0
200
400
600
Sample
800
1000
-100
10 4
10 5
10 6
Frequency (Hz)
10 7
Figure 5.10: Magnitude FFT spectrum of a 146.1 kHz sinusoid sampled with
Figure 5.9: Time-domain waveform showing 1 cycle of a 146.1 kHz sine wave.
fs = 144 MHz
Input is a 146.1 kHz sinusoid
Background | Architecture | Prototypes | Nonlinearity | Conclusion
32
First Generation Chip Waveforms
0
0
-10
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
-40
-60
-30
-40
-50
-60
-80
-100
10 4
-70
-80
10
5
6
10
Frequency (Hz)
10
7
0.5
1
Frequency (Hz)
1.5
2
×10 6
Figure 5.12: Magnitude FFT spectrum of a 146.1 kHz sinusoid sampled with
fs
Figure 5.11: Averaged Magnitude FFT spectrum of a 146.1 kHz sinusoid samfs = 144 MHz, OSR = 36, Showing DC to 2·OSR
.
led with fs = 144 MHz,Navg = 30
Background | Architecture | Prototypes | Nonlinearity | Conclusion
33
Second Generation Chip in IBM 45nm SOI
Phase = 1
kTs
Sampling Time
T4
Σ
T1
f2
f3
0
Table 6.1: Second-Generation Chip Parameters
Parameter
Value
Process
IBM 45nm SOI 10M 1P
r
Supply Voltage
(VDD )
1.8/1.0
r
Oversample Frequency (fs )
640
r
Quantizer
(TDC)
Number of Bits
4
r
f
f
DAC
(DTC)f Number of Bits
4
f
V
TDC LSB ( )
15.8
td,VTC/Adder
714
r
r
f
f
td,PhaseDetector
116
td,DTC
302
td,ExcessDelay
(Average)
400
Figure 6.5: Complete
PWM-based
⌃ ADC System
Area
0.0192
td,VTC/Adder
td,Phase Detector
T2
Δ
(k+1)Ts
td,Excess Delay
1
Dout[k]
THERMOMETER TO BINARY
out
ΔTIn[k]
Reused in both
phases
td,DTC/TDC
T3
Q
DD
Q
DD
Q
DD
Q
DD
6
7
Clk out
Phase = 1
Tsub[k] = Dout[k-1] Δ
2
0
3
1
DTC/TDC (in TDC Phase)
VTC/Adder
VIN,REF
VIN
1
Ramp Gen
start
Legend
Analog
Voltage
Fall Pulse
Rise Pulse
DCU
Vramp
DTC/TDC (in DTC Phase)
rst
2
1
2
...
ctrl
lead,lag
4
0 (fixed)
1
0
Phase
Detector
4
0
2
1
s
Phase = 0
s
lead,lag
Excess Delay
3
3
Dout[k-1]
Units
V
MHz
bits
bits
ps
ps
ps
ps
ps
mm2
Table 6.2: Summary of Measurement Results of Second-Generation Chip
Quantity Value Units
6.2.1 VTC/Adder
fs
705
MHz
Similar to the VTC/Adder of the first-generation
OSR chip,36the VTC/Adder
BW
9.8
MHz
of the second-generation chip consists of two identical half circuits, each of
fin
500
kHz
which have a ramp generator and a continuous-time
As
Vin,pk pkcomparator.
600
mVshown
SNR chip also
41.2includes
dB levelin Fig. 6.1, the VTC/Adder of the second-generation
SNDR
37.5
dB
shifters that translate the logic levels from the ENoB
core supply voltage
(1.0V)
6
bits to
THD for adding
-39.6 level-shifters
dB
the I/O supply voltage (1.8V) and back. The reason
Power
8.0
mW
is that the comparators and ramp generators operate with the 1.8V supply
15
Figure 6.6:
Core
Dimensions
are 160
µm ⇥ 120 µm
and
are Layout.
designed
using I/O
(thick-gate)
devices
for improved
headroom and
Background
| Architecture
| Prototypes
| Nonlinearity
| Conclusion
34
fs
OSR
BW
fin
705
36
9.8
500
600
41.2
37.5
6
-39.6
8.0
MHz
MHz
kHz
mV
dB
dB
bits
dB
mW
Second Generation Chip in IBM 45nm SOI
Vin,pk pk
SNR
SNDR
ENoB
THD
Power
0
15
-20
Amplitude (dBFS)
Modulator Output (dout)
modulator output
decimated output
10
5
-40
-60
-80
0
-100
200
400
600 800 1000 1200 1400
Sample
10 6
Frequency (Hz)
10 8
Figure 6.9: Time-domain waveform showing 1 cycle of a 0.5 MHz sine wave.
Figure 6.10: Magnitude FFT spectrum of a 500 kHz sinusoid sampled with fs
= 705 MHz
87
Input is a 500 kHz sinusoid
Background | Architecture | Prototypes | Nonlinearity | Conclusion
35
0
0
-10
-10
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
Second Generation Chip in IBM 45nm SOI
-30
-40
-50
-30
-40
-50
-60
-60
-70
-70
-80
10 4
-80
6
10
Frequency (Hz)
10
8
2
4
6
Frequency (Hz)
8
×10 6
Figure 6.12: Magnitude FFT spectrum of a 500 kHz sinusoid sampled with fs
Figure 6.11: Averaged Magnitude FFT spectrum of a 500 kHz sinusoid samfs
= 705 MHz, OSR = 36, showing DC to 2·OSR
.
pled with fs = 705 MHz, NF F T = 64K, Navg = 30
Background | Architecture | Prototypes | Nonlinearity | Conclusion
36
Test Setup
Xilinx
Spartan
6 FPGA
Background | Architecture
| Prototypes
| Nonlinearity
SUPP 3:
Measurement
setup | Conclusion
37
Comparison Table
Gen1
Design
Parameters
Gen2
Table 5.1: First-Generation
TableChip
6.1: Parameters
Second-Generation Chip Parameters
Parameter
Value
Units Value
Parameter
Units
Process
TSMC
- 45nm SOI 10M 1P
Process180nm 6M 1P IBM
(VDD )
1.8/1.0
V
Supply Voltage (VDD ) Supply Voltage 1.8
V
Oversample
Frequency
640
MHz
Oversample Frequency (f
144 (fs )
MHz
s)
Quantizer
4
bits
Quantizer (TDC) Number
of Bits (TDC) Number
3 of Bits
bits
4
bits
DAC (DTC) Number ofDAC
Bits (DTC) Number
3 of Bits
bits
TDC LSB ( 80)
15.8
ps
TDC LSB ( )
ps
td,VTC/Adder2.1
714
ps
td,VTC/Adder
ns
td,PhaseDetector
116
ps
td,PhaseDetector
0.57
ns
td,DTC 1.24
302
ps
td,DTC
ns
400
ps
td,ExcessDelay (Average) td,ExcessDelay (Average)
2.8
ps
2
Table
5.2:
Summary
of
Measurement
Results
of
First-Generation
Chip
Table
6.2:
Summary
of
Measurement
Results
of
Second-Generation
Ch
Area 0.0275
0.0192
mm2
Area
mm
QuantityQuantity
Value Units
Value Units
MHz
f144
705
MHz
s
5.2.1 VTC/Adder 6.2.1 VTC/Adderfs
OSR
36
OSR
36
Similar
the BW
VTC/Adder
of the
first-generation
Recall from Chapter 3 that
the to
VTC/Adder
consists
of two
identical
2.0
MHz
BW
9.8
MHzchip, the VTC/Adder
fin and
f146.1
500 identical
in
of have
the second-generation
chipa consists
of kHz
two
half circuits, each of which
a ramp generator
continuous-time
com-kHz half circuits, each of
600
mV
Vin,pk pk Vin,pk400pk
mV
Measured
whichofhave
a ramp generator
andina Fig.
continuous-time
comparator. As shown
parator. The circuit topology
the VTC/Adder
is
shown
6.1.
SNR
41.2
dB
SNR
44.6
dB
Results
in Fig. 6.1, the VTC/Adder
the
second-generation
chip also includes level37.5(I =dB
SNDR ofSNDR
34.6
dB
The ramp generator consists of a wide-swing
current
source
B
ENoB
6 corebits
THD
-35.0 fromdB
shifters that translate
the logic
levels
the
supply voltage (1.0V) to
200µA), an integrating capacitor (CI = 110fF),
and
digital
switches
to cre-dB
-39.6
ENoB THD
5.5
bits
the I/O supply voltage (1.8V)Power
and
The
for adding level-shifters
8.0 reason
2.7back.linear
mW
ate a 0 to 640ps full scale T⌃ [k] correspondingPower
to a (0.28V-0.68V)
rangemW
is that the comparators and ramp generators operate with the 1.8V supply
of Vin with Vref| Architecture
= 0.28V.
Background
| 15
Prototypes | Nonlinearity | Conclusion
38
Analog-to-Digital Converter Area Comparison
1000
ISSCC
VLSI Symposium
Area (mm2)
100
10
1
0.1
0.01
0.001
1997
1999
2001
2003
2005
2007
2009
2011
2013
2015
Year
B. Murmann, "ADC Performance Survey 1997-2015," [Online].
Available: http://web.stanford.edu/~murmann/adcsurvey.html.
Background | Architecture | Prototypes | Nonlinearity | Conclusion
39
Third Contribution
Nonlinearity Calibration
Image source: http://www.intel.de/content/www/de/de/cofluent/intel-cofluent-studio.html
40
Nonlinearity Due to Element Mismatch
•  In the presence of DTC (DAC) element mismatch Multibit
DSMs exhibit harmonic distortion.
•  To lower the distortion, need
–  extremely good matching, and/or
–  dynamic element matching (DEM) schemes.
•  Alternatively:
–  Lookup table (LUT) that maps each code out of the modulator to the true
value of the DTC can perfectly cancel nonlinearity.
•  Problem:
–  How do we estimate the DTC element mismatch?
Background | Architecture | Prototypes | Nonlinearity | Conclusion
41
A
Simulated
-80 Estimation/Calibration
-100
10 4
10 5
10 6
Frequency (Hz)
10 7
Figure 7.6: Spectrum showing linearity improvement using the calibration
algorithm for simulated data that matches the estimated mismatch of the first
generation chip. Uncalibrated THD = 35.4 dB, calibrated THD = 49.1 dB.
THD is improved by 13.7 dB for OSR = 14, BW = 5.14 MHz
Table 7.4: Simulated first generation ADC performance with/without calibration for OSR = 36, BW = 2.0 MHz
Uncalibrated Calibrated Improvement Perfect Cal. Units
SNR
45.5
46.0
0.5
46.0
dB
SNDR
35.1
44.8
9.9
44.8
dB
THD
-35.5
-50.7
15.0
-50.7
dB
ENoB
5.5
7.2
1.7
7.2
bit
Background | Architecture | Prototypes | Nonlinearity | Conclusion
42
First Generation Chip Calibration
Table 7.1: Meaured first generation ADC performance with/without calibration for OSR = 14, BW = 5.14 MHz
Uncalibrated Calibrated Improvement Units
SNR
41.1
41.3
0.2
dB
SNDR
33.7
40.0
6.3
dB
THD
-34.5
-45.7
11.2
dB
ENoB
5.3
6.3
1
bit
Table 7.2: First generation ADC performance with/without calibration for
OSR = 36, BW = 2.0 MHz
Uncalibrated Calibrated Improvement Units
SNR
44.6
44.8
0.2
dB
SNDR
34.6
44.0
9.4
dB
THD
-35.0
-51.0
16.0
dB
ENoB
5.5
7.0
1.5
bit
Background | Architecture | Prototypes | Nonlinearity | Conclusion
43
Second Generation Chip Calibration
Table 7.5: Measured second generation ADC performance with/without calibration for OSR = 36, BW = 9.8 MHz
Uncalibrated Calibrated Improvement Units
SNR
44.6
44.8
0.2
dB
SNDR
34.6
44.0
9.4
dB
THD
-35.0
-51.0
16.0
dB
EnoB
5.5
7.0
1.5
bit
Background | Architecture | Prototypes | Nonlinearity | Conclusion
44
Mismatch Coefficients
Background | Architecture | Prototypes | Nonlinearity | Conclusion
45
Summary of Contributions
•  Contribution 1: Architect and model novel time-based delta sigma ADC
–  Replace voltage-domain with time-domain processing to enable scaling
–  Calibrate loop delay to reduce non-uniform sampling effects
–  Reuse elements of TDC/DTC to save area
•  Contribution 2: Fabricate and test two prototype two ADC chips
–  TSMC 180nm CMOS
–  IBM 45nm SOI
•  Contribution 3: Analyze and mitigate major nonlinearity
–  Estimate element mismatch coefficients
–  Perform digital post-correction
Background | Architecture | Prototypes | Nonlinearity | Conclusion
46
Future Work
•  Reduction in DTC unit delay element mismatch by
–  utilizing (non-inverting) buffers rather than inverters, or
–  using the same structure of DTC/TDC but with feedback that truncates
the LSB, or
–  using extra inverter stages and implementing a dynamic element
matching scheme.
•  Circuit-level improvements
–  Improve thermal/flicker noise in front-end circuits, mainly comparator
–  Reduce power consumption of front-end by removing replica of ramp
generator and comparator in the VTC/Adder and replacing it with a
calibrated delay cell.
Background | Architecture | Prototypes | Nonlinearity | Conclusion
47
Summary of Relevant Work by Presenter
•  Y. Mortazavi, S. M. Mortazavi Zanjani, A. Brennan, D. Allen, M. Ranjbar, A 12.6 μW 70+ dB DR 2nd Order
CT ΔΣ Audio ADC in 55nm CMOS, 2015 IEEE Custom Integrated Circuits Conference, Sep. 28-30, 2015,
San Jose, CA USA, to be submitted.
•  W. Jung, Y. Mortazavi, B. L. Evans, and A. Hassibi, “An all-digital PWM-based ∆Σ ADC with an inherently
matched multi-bit quantizer/DAC,” 2014 IEEE Custom Integrated Circuits Conference, Sep. 15-17, 2014,
San Jose, CA USA.
•  Y. Mortazavi, W. Jung, B. L. Evans, and A. Hassibi, “A mostly-digital PWM-based ∆Σ ADC with an
inherently matched multi-bit quantizer/DAC,” IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, under review.
•  M. Nassar, J. Lin, Y. Mortazavi, A. Dabak, I. H. Kim and B. L. Evans, ``Local Utility Powerline
Communications in the 3-500 kHz Band: Channel Impairments, Noise, and Standards'', IEEE Signal
Processing Magazine, Special Issue on Signal Processing Techniques for the Smart Grid, vol. 29, no. 5,
pp. 116-127, Sep. 2012.
•  M. Nassar, K. Gulati, Y. Mortazavi, and B. L. Evans, ``Statistical Modeling of Asynchronous Impulsive
Noise in Powerline Communication Networks'', Proc. IEEE Global Communications Conf., Dec. 5-9, 2011,
Houston, TX USA.
•  A. G. Olson, A. Chopra, Y. Mortazavi, I. C. Wong, and B. L. Evans, ``Real-Time MIMO Discrete Multitone
Transceiver Testbed'', Proc. Asilomar Conf. on Signals, Systems, and Computers, Nov. 4-7, 2007, Pacific
Grove, CA USA. [Won Best Student Paper Award for the Architecture and Implementation Track].
48
References
[Murmann2010] – B. Murmann, “Trends in low-power, digitally assisted A/D conversion,” IEICE Trans. on
Electronics, vol. E93-C, no. 6, pp. 718–729, 2010.
[Rao2011] – S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P. Hanumolu, “A 71dB SFDR open
loop VCO-based ADC using 2-level PWM modulation,” 2011 Symp. VLSI Circuits, pp. 270–271, June
2011.
[Taylor2013] – G. Taylor and I. Galton, “A reconfigurable mostly-digital delta-sigma ADC with a worst-case
FOM of 160dB,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 983 – 995, Feb. 2013.
[Dhanasekaran2009] – V. Dhanasekaran, M. Gambhir, M. Elsayed, E. Sanchez-Sinencio, J. Silva-Martinez, C.
Mishra, L. Chen, and E. Pankratz, “A 20MHz BW 68dB DR CT ∆Σ ADC based on a multi-bit timedomain quantizer and feedback element,” IEEE Solid-State Circuits Conf., Feb 2009, pp. 174–175,175a
[Taillefer2009] – C. S. Taillefer and G. W. Roberts, “Delta–sigma A/D conversion via time-mode signal
processing,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 1908–
1920, 2009.
[Daniels2010] – J. Daniels, W. Dehaene, M. S. J. Steyaert, and A. Wiesbauer, “A/D conversion using
asynchronous delta-sigma modulation and time-to-digital conversion,” IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. PP, no. 99, pp. 1 –1, 2010.
49
Questions?
50
The method used to estimate the DTC mismatch is loosely based on
Element Mismatch Estimation
[41]. Given the modulator has an input large enough to hit all of the 2N oB
codes, the estimation algorithm is the following:
1. Calculate X[k], the windowed-FFT of the modulator output (x[n]).
2. Repeat the following for u 2 1, 2, . . . , 2N oB 2
95
(a) Calculate Iu [k], the windowed-FFT of the event that the modulator
code equals u, i.e., 1(x[n] = u).
(b) Correlate a predetermined set of bins (k1 , . . . , kj ) from X[k] with
the same bins from Iu [k]. Call the result ✏[u].
(c) Where x(n) = u, replace x(n) with T (u) = u + ✏[u].
Mathematically,
P kj
1
✏[u] = Pk=k
kj
{<(X[k]Iu [k]) + =(X[k]Iu [k])}
k=k1 {<(Iu [k]Iu [k]) + =(Iu [k]Iu [k])}
(7.1)
where <(·) and =(·) denote the real and imaginary parts of the argument,
respectively.
In the case of a sinusoidal input, the predetermined set of bins (k1 , . . . , kj )
Background | Architecture | Prototypes | Nonlinearity | Conclusion
can simply be chosen in a manner to remove the bins nears the input frequency.
51