CMOS RF Modeling for GHz Communication IC’s
Jia-Jiunn Ou, Xiaodong Jin, Ingrid Ma, Chenming Hu, and Paul R. Gray
Department of Electrical Engineering & Computer Sciences
University of California, Berkeley, CA 94720
Introduction
With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process [1]. A
major barrier to the realization of robust commercial CMOS
RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies.
The conventional microwave table-lookup-based approach
requires a large database obtained from numerous device
measurements and computationally intense simulations for
accurate results. This method becomes prohibitively complex
when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range
of bias conditions and operating frequencies is desirable.
BSIM3v3 has been widely accepted as a standard CMOS
model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high
frequencies by utilizing a complicated substrate resistance
network and extensive modification to the BSIM3v3 source
code [2]. This paper first describes a unified device model
realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies
the accuracy of the model to measured data on both device
and circuit levels.
BSIM3v3 RF Model
The new BSIM3v3 RF model is realized with the addition
of three resistors Rg, Rsubd, and Rsubs to the existing
BSIM3v3.1 model (shown in Fig. 1). Rg models both the
physical gate resistance as well as the non-quasi-static (NQS)
effect. Rsubd and Rsubs are the lumped substrate resistances
between the source/drain junctions and the substrate contacts.
The values of Rsubd and Rsubs may not be equal as they are
functions of the transistor layout (illustrated in Fig. 2).
To demonstrate the accuracy of the model, s-parameters of
the BSIM3v3 RF model, BSIM3v3 model, and measured data
of a 0.35µm NMOS device are plotted in Fig. 3. The
improvement can be clearly seen from the S22 but hardly from
S11. A better picture and more physical insight may be
obtained by separating the terminal impedance into the real
and imaginary parts with the following six parameters,
Rin = real(1/ y11) ; Cin = −1/ imag(1/ y11)/ ω ;
Rout = 1/ real(y22) ; Cout = imag(y22)/ ω ;
gm = real(y21) ;
dc characteristics but not the high frequency behavior. Fig. 5
shows the simulated Rout and Cout of a 0.5µm NMOS device
with various body biases. Good agreement has been achieved
between the 2-D simulation and the proposed model.
Parameter Extraction
Rg can be extracted in part from the gate sheet resistance.
With the NQS effect, lumped Rg may be obtained from the
measured Rin. For a fixed cell layout, Rsubd can be extracted
from Rout by connecting the drain as port2. Similarly Rsubs is
found by using the source as port2. It is recommended to
adjust the low frequency source/drain junction capacitance to
fit the s-parameter data accounting for distributed RC effects
and measurement inaccuracies.
Circuit Evaluation
To test the robustness of the BSIM3v3 RF model, a circuit
level evaluation was performed using two different
approaches. As a first example, a 5GHz single-ended lownoise amplifier (LNA) using a 0.35µm device was simulated
using BSIM3v3 RF model, as shown in Fig. 6(a). The tablelookup method was employed to compute overall circuit performance from the measured device data and the results were
compared with the SPICE simulation. Fig. 6(b) shows a good
agreement between the two methods for the S21. In the second example, a 2GHz differential LNA was designed and fabricated in a 0.6µm CMOS process, as shown in Fig. 7(a). Fig.
7(b) shows the measured voltage gain compared to the simulated results. Clearly the low frequency BSIM3v3 model
overestimates the peak voltage gain by 2dB, while the RF
model accurately predicts the circuit performance within the
frequency of interest.
Conclusion
The BSIM3v3 RF model, which requires only three additional parameters and no modification of existing model
source code, has been proposed for accurately predicting
CMOS device behavior up to 10GHz. Both device and circuit
level evaluations were conducted and show excellent agreement. With the BSIM3v3 RF model, well suited for simulating both RF and mixed-signal circuits, it is now possible to
design highly integrated CMOS communication systems with
a unified device model and simulator.
Acknowledgment
Cfb = −imag(y12)/ ω ,
where ω is the frequency in rad/s (gate is port1, drain port2,
and body shorted to the source). As shown in Fig. 4, excellent
agreement up to 10GHz has been achieved. In particular, the
proposed model significantly improves the agreement
between the model and data for Rin and Rout over a wide frequency range.
A unique problem in modeling CMOS is the body bias
effect. To study this effect at high frequencies, a 2-D device
simulator was used to generate both dc and s-parameter data.
The results show that the body bias mainly affects the device
This work is supported by National Semiconductor Fellowship and SRC 97-SJ-417. The authors would like to thank
SGS-Thomson and TSMC for wafer fabrication and G. Zhang
for assistance on model extraction.
References
[1] P. Gray and R. Meyer, “Future directions of silicon IC’s for RF
personal communications,” in CICC, pp. 83-90, May 1995.
[2] W. Liu, et al., “RF MOSFET modeling accounting for distributed
substrate and channel resistances with emphasis on the BSIM3v3
SPICE model,” in IEDM, pp. 309-312, Dec. 1997.
0-7803-4700-6/98/$10.00 (c) 1998 IEEE
B
S
D
S
B
D
Rsubd
epi
1GHz
Rg
G
B
1GHz
D
10GHz
10GHz
Rsubs
S
S
BSIM3v3 RF
BSIM3v3
measured
S
(a) S11
(b) S22
Fig. 1. Proposed BSIM3v3 RF model.
Fig. 2. Cross sectional view and top view
of a typical transistor cell layout.
(Ω)
25
Fig. 3. Smith Chart representation of a NMOS device with
L=0.35µm, W=160µm, Wfinger=10µm, Vgs=2V and Vds=2V.
(mS)
50
(Ω)
600
BSIM3v3 RF
BSIM3v3
measured
20
40
400
15
30
10
20
BSIM3v3 RF
BSIM3v3
measured
200
5
10
0
-5
1
2
3
(a) Rin
5
10
(GHz)
0
1
2
(pF)
(pF)
0.5
3
(c) Rout
5
10
(GHz)
BSIM3v3 RF
BSIM3v3
measured
0.3
0.2
2
3
(b) Cin
5
10
(GHz)
2
3
(e) gm
5
10
(GHz)
5
10
(GHz)
60
40
0.1
1
1
80
0.2
BSIM3v3 RF
BSIM3v3
measured
0.1
0
0
(fF)
100
0.3
0.4
BSIM3v3 RF
BSIM3v3
measured
0
1
2
BSIM3v3 RF
BSIM3v3
measured
20
3
(d) Cout
5
10
(GHz)
0
1
2
3
(f) Cfb
Fig. 4. Terminal impedance illustration of a NMOS device with L=0.35µm, W=160µm,
Wfinger=10µm, Vgs=2V and Vds=2V. Rg=9Ω and Rsubd=90Ω are extracted in this case.
(Ω)
1000
BSIM3v3 RF
2-D simulation
900
Vbs=−1V
1
3
5
(a) Rout
10
(GHz)
(fF)
60
Out
50Ω
150/0.6
Bias
In +
In −
600/0.6
25Ω
3nH
0.8nH
9mA
(a) circuit schematic
(dB)
20
(dB)
25
10
23
(a) circuit schematic
BSIM3v3 RF
2-D simulation
56
Vbs=0V
52
21
0
BSIM3v3 RF
table lookup
Vbs=−1V
48
44
Out +
0.2pF
0.25pF
1.5nH
2
0.9pF
6.5nH
Out −
50Ω
Vbs=0V
700
600
2nH
Vbs=−2V
800
Vdd
3.3V
Vdd 2V
Vbs=−2V
1
19
-10
2
3
(b) Cout
5
10
(GHz)
Fig. 5. 2-D simulation result vs. BSIM3v3 RF model
with various body biases, L=0.5µm, W=100µm,
Vgs=2V, and Vds=2V.
2
3
5
(b) | S21 |
10
(GHz)
Fig. 6. A single-ended 5GHz LNA using
a 160µm/0.35µm NMOS device.
0-7803-4700-6/98/$10.00 (c) 1998 IEEE
1.8
BSIM3v3 RF
BSIM3v3
measured
1.9
2.0
2.1
(b) voltage gain
2.2
(GHz)
Fig. 7. A 2GHz differential LNA designed
and fabricated in a 0.6µm CMOS process.