Indian Journal of Engineering & Materials Sciences
Vol. 18, June 2011, pp. 175-182
Design of harmonic noise frequency filtering down-converter with asymmetrical
inductance tank in InGaP/GaAs HBT technology
Cong Wang & Nam Young Kim*
RFIC Laboratory, Kwangwoon University, 447-1 Wolgye-dong, Nowon-ku, Seoul 139-701, Korea
Received 31 May 2010; accepted 13 May 2011
A harmonic noise frequency filtering (HNFF) down-converter is fabricated using asymmetric inductance tank (AIT) in
InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) technology. In the
voltage-controlled oscillator (VCO) design, internal inductance is found to lower the phase noise which is based on an
analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer (DBM) to convert radio
frequency (RF) carrier to intermediate frequency (IF) through local oscillator (LO). Furthermore, final power performance is
improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high-power DBM,
and output amplifier that have been designed to optimize phase noise and output power. The proposed VCO exhibited a
phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip
down-converter shows a third-order input intercept point (IIP3) of 12.55 dBm, a third-order output intercept point (OIP3) of
21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, the conversion
gain is 8.9 dB through an output buffer. The total on-chip down-converter is implanted in 2.56 × 1.07 mm2 of chip area.
Keywords: Harmonic noise frequency filtering (HNFF), Asymmetric inductance tank (AIT), Double balanced mixer
(DBM), Phase noise, Voltage-controlled oscillator (VCO)
In the tremendous growth of wireless handheld
devices, high performances become a major
consideration in MMIC designs. This paper explores
high-performance on-chip down-converter MMIC
design for HBT VCO and DBM co-design through
their applications in an RF front-end transceiver.
Integrated VCOs are important blocks in
communication systems, which are used in virtually
all types of up-conversion, down-conversion,
frequency modulation, and high-frequency generation
systems. While most VCOs are designed to generate a
sinusoidal voltage waveform, their use and required
performance vary widely1,2. An integrated circuit
reduces the size of the devices such as on-chip
inductors and capacitors; thereby it can improve the
spectral purity of VCOs. Also, the varactor diode
which is used for frequency tuning of VCOs can also
be realized on the same chip. A further advantage is
that 1/f noise is reduced by using the ledge function of
the HBT process3. Many VCOs constructed with the
InGaP/GaAs HBT technology have been developed to
achieve the characteristics of low power consumption,
low phase noise, and high operation frequency4,5.
——————
*Corresponding author (E-mail: nykim@kw.ac.kr)
In this paper, the uses of AIT structure, highquality tank, and HNFF technique are described to
design the proposed VCO. In order to improve the
phase noise performance of the integrated LC VCO,
the core structure of the VCO is based on a crosscoupled differential configuration. This topology has
been widely adapted in low gigahertz regimes due to
its simplicity and differential operation5,6. One
advantage of this architecture is its high loop gain
which makes it as a popular solution for differential
VCO designs in RFIC/MMIC. The frequency
conversion process is necessary for the quality of the
signal as well as the wider communication area using
a small antenna. Therefore, the mixer is a critical
block for this process to perform the frequency
translation. The most important elements to consider
in the mixer design are high gain, low noise, and low
power consumption. The main topology of the
proposed DBM is double balanced Gilbert cell
topology. This topology is a fundamental building
block which is used in a wide array of IC applications
including modulators, de-modulators, and RF mixers.
This RF mixer can produce positive conversion gain
and multi-decade bandwidth operation. It requires low
LO power with compact size. Furthermore, its baseband and multi-decade bandwidth performance make
INDIAN J. ENG. MATER. SCI., JUNE 2011
176
it attractive for wideband instrumentation and RF
communications7. Recently, active Gilbert cell mixers
with high conversion gain are reported8,9.
Enhanced LC VCO and DBM Co-Design
Asymmetrical inductance tank structure
The proposed VCO consists of a LC tank, a pair of
emitter follower buffers, and a negative resistance
block. A cross-coupled differential structure with
capacitive coupling feedback is used to reduce the
1/f noise. To realize a high quality factor, the core of
the VCO with AIT and symmetrical inductance tank
(SIT) structure will be concerned which is shown in
Fig. 1a and 1b, respectively. To obtain low phase
noise performance, the high Q resonator is optimized;
this is one of the most important aspects of oscillator
design10. As we know, the quality factor can be
expressed as the phase of the open-loop transfer
function Φ (w) at the resonance of the LC tank in an
oscillator
QTank =
R
ω0 dφ
= P
2 dω ω = ω ω 0 L
0
where RP is the parallel resistance of the LC tank at
the resonant frequency (ωo), and L is the inductance of
the tank11. If the asymmetrical inductor is used in
tank, the RP will be two times better than the
symmetrical tank as shown in Fig. 2. In the view
of the layout, the area of inductor in AIT is about
1.5 times bigger than SIT. The inductance of AIT
should be 1.5 times bigger than SIT, because the
inductance is proportional to the area of the inductors.
ωo depends on the center carrier frequency, therefore
it will be almost the same in both the AIT and the
SIT. In order to acquire a high Q value, inductors with
low parasitic series resistance are chosen because
these inductors have high Q values and provide low
phase noise in the oscillator. To this end, the Q-factor
of the AIT is definitely superior to the SIT, which is
shown in Fig. 3. The proposed VCO can be modeled
simply as a lossy LC tank combined with a noiseless
energy restorer that keeps constant oscillation
amplitude. The phase noise for this model can be
analytically calculated as:
(a)
(a)
Asymmetrical inductance tank structure
(b)
Symmetrical inductance tank structure
Fig. 1—Brief circuits of the LC VCOs: (a) AIT; (b) SIT
… (1)
(b)
Fig. 2—Equivalent circuits of the LC tank: (a) AIT-VCO;
(b) SIT-VCO
Fig. 3—Q values of the asymmetrical and symmetrical inductor tank
WANG & KIM: DESIGN OF HARMONIC NOISE FREQUENCY FILTERING DOWN-CONVERTER
 2kT
L(∆ω ) = 10 log 
 Psig

 ωo


∆
2
Q
ω

 tan k
2



… (2)
where k is Boltzmann’s constant, T is the
temperature, ωo is the oscillation frequency, Psig is the
signal power, Qtank is the Q factor of the LC tank, and
∆ω is the offset form the oscillation frequency. It tells
us that phase noise improves as both the carrier power
and Q factor increase. Increasing the signal power
improves the ratio simply because the thermal noise is
fixed, while increasing Q improves the quadratic ratio
because the tank’s impedance falls off as 1/Qtank∆ω12.
A comparison of the phase noise simulation
performance as a function of offset frequency
between the AIT-VCO and the SIT-VCO and the
fabricated VCOs are shown in Fig. 4, respectively.
The most important point to note here is that the
phase noise of the AIT-VCO is greater than 3.4 dB at
1 MHz offset than SIT-VCO. As a result, the AIT
structure can be optimized with high RP and Q factor
when compared with the SIT.
But using the AIT, the wave shape of the core stage
has a little distortion in the headroom, which came from
the asymmetric capacitor in the resonator part. It can be
eliminated with symmetric capacitance in the AIT.
Harmonic noise frequency filtering technique
In the differential LC oscillator, the current source
is required to fix the bias current that supplies high
impedance with the switching active devices of the
differential pairs in series combination. In the case of
perfectly balanced circuit, odd harmonic circulate
Fig. 4—Phase noise simulation results of the AIT-VCO and SITVCO (the fabricated AIT-VCO and SIT-VCO are shown on the
upper right)
177
with no current flowing through the current source in
out-of-phase-operation. But even harmonics flow in a
common-mode path through the active devices, LC
resonator circuit and current source are in the in-phase
operation. The low noise frequency of the current
source is initially up-converted to high frequency
noise around the fundamental frequency due to the
mixing effect of non-linear transconductance and
intrinsic capacitance of the active oscillators. Because
of very small level of the third and higher order
harmonics in the VCO, the effect of the second
harmonic can be considered. That means it is
necessary to create condition of current source
bypassing for the second harmonic. It is necessary to
use the special filtering techniques for the second
harmonic suppression to get pure spectral purity and it
also can overcome the problem of noise in VCOs13.
The VCO includes a feedback oscillation signal path
and a frequency control path. The phase noise of the
oscillator is primarily generated by these two paths,
into which the noise is injected. The proposed HNFF
shorts the noise signals, including the supply voltage
and feedback noise, to ground. The capacitance is
chosen to down the noise frequency in parallel with
whatever capacitance is present at the feedback source
of the differential pair as shown in Fig. 5. There are
numerous literatures regarding noise reduction
techniques in VCOs13-15. However, these techniques
required the use of two or more inductors to reduce
noise in the VCO which will have a very huge size.
If VCOs are used by the HNFF, only filtering
capacitor (C1) is needed because the proposed HNFF
technique includes the internal inductance of the tank
Fig. 5—Schematic circuit of the differential LC VCO using HNFF
technique
178
INDIAN J. ENG. MATER. SCI., JUNE 2011
and negative resistance cell. Small value C1 (2.722 pF)
and inductance (almost under 0.5 nH) act like
low-pass filter until 5th order harmonics. Therefore,
the harmonic noises can be removed. In Fig. 5, arrow
(1) shows the flow of the 2nd harmonics in the loop.
Before the 2nd harmonics flow out of the output
buffer, the noises of the harmonics short to the ground
through arrow (2). Figure 6 shows the phase noise
variation as a function of control voltage with and
without HNFF technique and the fabricated
two VCOs, respectively. The phase noise at 1 MHz
offset increased from -124.52 dBc/Hz for the VCO
without harmonic noise frequency filtering capacitor
to -129.7 dBc/Hz for HNFF-VCO. Therefore HNFF
technique can be adapted to reduce phase noise due to
the bypassing for the 2nd harmonic.
The cross-coupled transistors (Q1 and Q2) form a
positive feedback loop in the VCO, and two buffer
circuits (Q3 and Q4) can be isolated to the VCO core by
means of the load impedance. In addition to contributing
noise, Q1 and Q2 saturate heavily if the peak swing at
tank node exceeds. In order to solve this issue, a
capacitive divider (C2) can be inserted in the feedback
path allowing greater swings and higher common-mode
level at tank nodes than at the bases of Q1 and Q2.
Figure 7 shows the schematic circuit of the designed
high-power DBM.
The circuit is designed in such a way that the
transistor in LO input part acts as a switch (Q1, Q2,
Q3, and Q4) and can be operated in the cutoff area by
applying minimum bias. The bias points of Q5 and
Q6 are in the saturation region and those of Q1-Q4
are within a linear region. Besides, C1 is the signal
path for the balanced input signal. By itself, the RF
input differential pair is not linear enough for useful
applications, so it must be linearized. A common
technique to achieve it is known as resistive
degeneration using resistors R1 and R216,17.
Furthermore, linearity is improved by inserting a
broadband resistor (R5) at the RF port, but it increases
the noise figure. Both the LO differential input ports
have on-chip broadband 50 ohm resistive terminations
Vdc=5 V
I=72.6 mA
IF +
IF -
Vb2
LO +
R6
R7
R8
R3
Q1
Q2
Q3
Q4
LO R4
Vb1
Design of the high-power DBM
The DBM utilizes a Gilbert cell core in this paper
because of its low DC power consumption, high
linearity, and good spurious output rejection. Also, it
can provide a high gain and very low noise figure.
Strict symmetry is maintained for the balanced
structure to minimize the amplitude and phase errors.
Fig. 6— Phase noise simulation results of the HNFF-VCO and
the VCO without harmonic noise frequency filtering capacitors
(the fabricated VCOs are shown on the upper right)
R9
RF
R10
Q5
R5
R1
Q6
R2
C1
Ibias
Fig.—7 Schematic circuit of the DBM core
Fig.—8 Schematic circuit of the integrated down-converter
WANG & KIM: DESIGN OF HARMONIC NOISE FREQUENCY FILTERING DOWN-CONVERTER
(R3 and R4), resulting in excellent broadband return
losses and superior inter-modulation performance.
Co-design of the enhanced LC VCO and DBM
Figure 8 shows a complete schematic circuit of the
integrated down-converter consisting of the presented
VCO, DBM, and output buffer. The output buffer is a
cascode differential pair with inductive emitter
degeneration represented by L1 and L2. This
configuration is chosen to reduce the Miller
capacitance and increase the power gain. Off-chip
pull-up inductors (L3 and L4) enable a high output
voltage swing. AC coupling capacitors (C1) help
improving the power matching to 50 ohm.
Results and Discussion
A microphotograph of the fabricated downconverter with a die size of 2.56 × 1.07 mm2 is
depicted in Fig. 9. It is fabricated using a commercial
InGaP/GaAs HBT process in which the HBT devices
had a cutoff frequency (fT) of 48 GHz and a maximum
oscillation frequency (fMAX) of 80 GHz.
The fabricated HNFF down-converter is measured
using RF on-wafer probes. The chip is mounted on a
printed circuit board (PCB) with silver epoxy. In this
chip, the DC contact is created using golden wire
(length: 10 mm; diameter: 1 mm) to provide a stable
DC supply. Figure 10 shows a PCB for chip
179
measurement and probe tips contacting on the chip.
Key parameters are measured using various
equipments, such as probe station, spectrum analyzer,
signal generator, power supply, and vector network
analyzer.
HNFF VCO with AIT
Figure 11 shows the phase noise and output
spectrum characteristics of the proposed VCO. It
produces an output power of -10.251 dBm (including
the cable loss) and has superior phase noise of -117.3
dBc/Hz and -133.93 dBc/Hz at 100 kHz and 1 MHz
offset frequencies respectively from the carrier
frequency of 1.721 GHz. The oscillation frequency
and output power variation as a function of control
voltage sweep are depicted in Fig. 12. The oscillation
Fig. 11—Phase noise of the proposed VCO measured at the lowest
tuning voltage (output spectrum of the VCO is shown on the lower left)
Fig. 9—Microphotograph of the fabricated down-converter
Fig.—10 PCB and probe tips contacting on the chip
Fig. 12—Variation of oscillation frequency and output power as a
function of tuning voltage
INDIAN J. ENG. MATER. SCI., JUNE 2011
180
frequency is varied from 1.46 GHz to 1.721 GHz with
a control voltage from 0 to 3 V. Using the HNFF
capacitors produces low phase noise performance
since the noises in both the feedback oscillation signal
path and the frequency control path are reduced. This
is also due to an increase in the parallel resistance and
the Q factor of the tank. Therefore, the proposed VCO
shows low phase noise performance. But the output
power is not good enough, which mainly depends on
the active device, bias condition, and matching
network. There are several possible explanations for this
result. Some of this loss can be attributed to test setup
losses (around ~ 1.5 dB) which are not calibrated out of
these measurements. Second may be a problem with the
buffer amplifier biasing because the output power is
decreased from the simulation value. It is believed that
the buffer amplifier design is responsible for the
majority of the loss since the buffer amplifier did not
bias to the expected current in the proposed VCO.
Finally, the reason of the low output power may be the
mismatching of the matching network at the output. A
smaller output device could have been used to match 50
ohm since the 1/gm is equaled to 50 ohm. But the design
is current limited in driving the output. More current is
thus run in the source follower stage to drive the output
and it is deliberately chosen to not match the output to
minimize the power loss. Therefore, before this buffer
amplifier and matching circuit design are used in future
iterations, the reason behind the faulty biasing and
matching must be determined.
A widely used figure-of-merit (FoM) is defined18 as
DBM with the differential cascode output buffer
Integrated matching resistors provide broadband
return loss without matching networks. Figure 13
shows the return loss of the RF port is under -20 dB in
the frequency range from 400 MHz to 12 GHz, while,
the return loss of the LO port is under -10 dB in the
frequency range of 400 MHz to 8 GHz. Also, the flat
conversion gain is obtained as +2.6 dB from 400 MHz
to 10 GHz.
Fig. 13—Conversion gain of the DBM as a function of RF
frequency and RF, LO return loss
 f 
 P 
FOM = L(∆f m ) − 20 log 0  + 10 log diss  … (3)
 1mW 
 fm 
In this work, we achieve FoM of -181.3 dBc/Hz. It
shows a much better performance than the other
VCOs in different frequencies and processes. Table 1
presents the VCO performances from recent
literatures with this work.
Fig. 14—The measured IMD3 of the fabricated DBM
Table 1– Summary of the previously published VCO performances
Reference
Frequency
Tuning Range
Phase Noise
FoM
Process
[19]
[20]
[21]
[21]
[22]
[23]
[24]
Present work
(GHz)
0.915
1.22
12.2
13.5
5.6
2.18
0.78
1.721
(MHz)
160
341
600
800
500
511
107
261
(dBc/Hz)
-119 @ 1MHz
-120 @ 1MHz
-113.8 @ 1MHz
-111.8 @ 1MHz
-117 @ 1MHz
-123 @ 1MHz
-120 @ 1MHz
-133.96 @ 1MHz
-174.1
-173.5
-180.7
-176.6
-180.7
-180
-180
-181.3
BiCMOS
0.18 µm CMOS
InGaP/GaAs HBT
InGaP/GaAs HBT
BiCMOS
0.18 µm CMOS
0.18 µm CMOS
InGaP/GaAs HBT
WANG & KIM: DESIGN OF HARMONIC NOISE FREQUENCY FILTERING DOWN-CONVERTER
181
In order to measure the inter-modulation effect,
especially the third order inter-modulation, two
signals with a 1 MHz offset are applied to the input
port of the mixer. Figure 14 shows when the applied
input power is -10 dBm, then the third order intermodulation distortion (IMD3) is 53.7 dBc. The inputreferred third order intercept point (IIP3) and the
output-referred third order intercept point (OIP3) are
calculated by using these results, IIP3 is found to be
+16.78 dBm and OIP3 is +19.38 dBm. The integrated
differential output buffer generated a high outputreferred 1 dB compression point (P1dB, out) of 10 dBm,
which is shown in Fig.15.
Fig. 15—The measured P1dB compression point
Down-converter
The current consumption of the fabricated downconverter is 94 mA at DC supply voltage of 5 V.
Figure 16 shows the return loss of the RF port is
under -20 dB in the frequency range of 100 MHz to
4.1 GHz and -31 dB at the center frequency. Return
Fig. 16—Simulation and measurement results of RF return loss
(the results of IF return loss is shown on the lower right)
Fig. 18—Measured P1dB compression point
Fig. 17—The measured IMD3 of the proposed down-converter
(RF power: -10 dBm; LO power: -10 dBm)
Fig. 19—Fundamental and 3rd order harmonics versus RF power
of the two-tone test
182
INDIAN J. ENG. MATER. SCI., JUNE 2011
loss of IF port is about -26 dB. The leakage of RF-toIF ports measured at -30 dBm (RF power) is -57 dB.
Figure 17 shows when the applied input power is -10
dBm, the IMD3 is 48.86 dBc. The measurement
results of the one-tone test are shown in Fig. 18. The
conversion gain is about 8.9 dB to compensate for
cable loss at an RF power level of -30 dBm and an
LO power level of -10 dBm. IIP3 is found to be 12.55
dBm and OIP3 is 21.45 dBm. Figure 19 shows the
IIP3 and the OIP3 point, respectively.
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Conclusions
The LC-tuned VCO and down-conversion DBM
are two major building blocks of a high-frequency
radio front-end receiver. In this paper, both circuits
have been examined and designed to combine each
module for down-converter system on chip (SoC)
applications. However, total current consumption is
greater than in the CMOS design which is an inherent
characteristic of the technology. The VCO has
superior phase noise performance due to the HNFF
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1
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Acknowledgment
This research was supported by the MKE (The
Ministry of Knowledge Economy), Korea, under the
ITRC (Information Technology Research Center)
support program supervised by the NIPA (National IT
Industry Promotion Agency) (NIPA-2011-C10901111-0002). This work was also supported by the
Research Grant of Kwangwoon University in 2011.
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