LULEÅ TEKNISKA UNIVERSITET
Systemteknik, EISLAB
Jonny Johansson
Exam in Electronics
Course code
Exam date
Location
Exam time
E0007E
2008-01-14
C840, C842
09.00 – 13.00
Grade 5
Grade 4
Grade 3
25 – 30 credits
20 – 24 credits
15 – 19 credits
Teacher on call
Jonny Johansson
0920-491703
Allowed aids
BETA
Calculator
Course literature, i.e.:
Sedra & Smith, Comer & Comer, Jaeger, or Horenstein
Good Luck!
1(6)
E0007E
2(6)
SME129
Part I
This part consists of 7 tasks. Each of these gives a choice of several answers, whereof only
one is correct. Please choose one of the answers for each task. No motivation for your choice
needs to be given.
1.
(2 credits)
A zener diode:
A.
B.
C.
D.
2.
Can be used to give a stable reference voltage when driven with a reverse current.
Has zero forward voltage drop.
Is never used to regulate voltage.
Has a fixed voltage drop of 0.7 V.
(2 credits)
The positive input (V+) and the negative input (V-) of an operational amplifier (op-amp) are
often treated as having the same potential (“virtual short”). This is:
A.
B.
C.
D.
3.
Always valid.
Valid as long as the op-amp works linearly in a feed-back loop.
Valid only when the op-amp is used as a comparator without feedback..
Wrong but still commonly used anyway.
(2 credits)
Which of the gates depicted below will not work properly?
A.
B.
C.
D.
No. 1
No. 2
No. 3
No’s 1 & 2
A
A
B
A
B
B
Y
Y
Y
A
A
B
A
B
B
1)
Figure 1. Gates for task 3.
2)
3)
3(6)
SME129
4.
(2 credits)
Estimate the noise margin for low input (NML) for an inverter having the transfer function
indicated in the graph below.
A.
B.
C.
D.
NML ≈ 1.2 V
NML ≈ 1.5 V
NML ≈ 0.5 V
NML ≈ 0.7 V
vOUT (V)
5
5
vIN (V
Figure 2. Inverter transfer characteristic for task 4.
5.
(2 credits)
Consider the following statements regarding the transconductance (gm) of a transistor:
1) gm for a MOS transistor is dependent on bias current only.
2) gm for a MOS transistor is dependent on a number of parameters, including transistor
geometry.
3) gm for a BJT transistor is dependent on bias current only.
4) gm for a BJT transistor is dependent on a number of parameters, including transistor
geometry.
The combination grouping all true statements are:
A.
B.
C.
D.
1&3
2&3
2&3
2&4
4(6)
SME129
6.
(2 credits)
Which sequence of actions is most appropriate when analyzing a transistor circuit ?:
A. Draw small-signal schematic; analyze small signal schematic; calculate bias point;
calculate small-signal parameters.
B. Calculate small-signal parameters; draw small-signal schematic; analyze small signal
schematic; calculate bias point;.
C. Calculate bias point; analyze small signal schematic; draw small-signal schematic;
calculate small-signal parameters.
D. Calculate bias point; calculate small-signal parameters; draw small-signal schematic;
analyze small signal schematic.
7.
(2 credits)
The primary mechanism that creates conduction between collector and emitter in a BJT is:
A. Injections of carriers from emitter into base, diffusion of the carriers through the thin
base, carriers swept over by electric field from base to collector.
B. A thick base region that generates a vast amount of free carriers.
C. The formation of an inversion layer under the base.
D. Tunneling of electrons from collector to emitter at high collector-emitter voltage, with
the base controlling the tunneling resistance.
5(6)
SME129
Part II
This part consists of three tasks. For each of these, a full solution is required. Please motivate
approximations and assumptions that you make.
8.
(5 credits)
The transistor in figure 3 has β = 100. Design the BJT amplifier (i.e. choose RB1, RB2, RC,
and RE) shown in figure 3 to have a total midband gain (vout/vsig) of about -60 V/V with a bias
current of about 1 mA. Ignore the output resistance (ro) of the transistor.
+6 V
+6 V
RB1
RC
10 µF
10 µF
+
10 µF
10 kΩ
+
-
-
RB2
vsig
vout
RE
Figure 3. Amplifier schematic for task 8.
9.
(6 credits)
An OP07 is used in the non-inverting configuration as shown in figure 4. Please use the data
sheet attached to this exam and perform the following calculations. Use typical parameter
values at 25 degrees C for a power supply of ±15 V:
A. Choose the resistor R to minimize the influence of input bias currents.
B. Calculate the worst case output DC voltage that will result from input offset voltages
and currents.
C. Calculate the bandwidth of the design.
D. Calculate at what frequency the output signal will be slew rate limited when an input
signal amplitude of 0.5 V is used.
6(6)
SME129
R
+
OP07
+
+
-
10 kΩ
vIN
vOUT
560 Ω
Figure 4. Schematic for task 9.
10.
(5 credits)
Consider the circuit shown in figure 5 below. Draw the full small-signal schematic and
calculate the overall midband voltage gain (Gv = vout/vsig) of the amplifier. Ignore the output
resistance (ro) of the transistor.
+12 V
56 kΩ
Transistor param.
(W/L) = 10
k’n = 140 µA / V2
Vt = 0.7 V
+12 V
4.7 kΩ
10 µF
10 kΩ
10 µF
+
18 kΩ
+
-
vsig
47 kΩ
vout
-
1 kΩ
10 µF
3.3 kΩ
Figure 5. Amplifier schematic for task 10.
OP07C
VERY LOW OFFSET
SINGLE BIPOLAR OPERATIONAL AMPLIFIER
■ EXTREMELY LOW OFFSET : 150µV/ max.
■ LOW INPUT BIAS CURRENT : 1.8nA
■ LOW Vio DRIFT : 0.5µV/°C
■ ULTRA STABLE WITH TIME :
2µV/month max.
■ WIDE SUPPLY VOLTAGE RANGE :
±3V to ±22V
N
DIP8
(Plastic Package)
DESCRIPTION
The OP07 is a very high precision op amp with an
offset voltage maximum of 150µV.
PIN CONNECTIONS (top view)
Offering also low input current (1.8nA) and high
gain (400V/mV), the OP07C is particularly suitable
for instrumentation applications.
ORDER CODE
Package
Part Number
Temperature Range
N
OP07C
-40°C, +105°C
Offset Null 1
1
8
Offset Null 2
Inverting Input
2
7
VCC
Non-inverting Input
3
6
Output
4
5
N.C.
V CC
•
N = Dual in Line Package (DIP)
November 2001
1/4
OP07C
SCHEMATIC DIAGRAM
VCC
R2A
R2B
Offset
Null
R1A
N2
R7
C1
R1B
N4
T15
T9
T10
T18
D8
T5
Non-inverting
input
Inverting
input
D9
T3
T6
T4
R3
D6
D1
D4
D3
T8
R9
Output
D7
T1
R4 D2
T7
C3
C2
D11
R10
D5
T2
T12
T17
R5
T16
T13
T11
D10
T14
R6
R8
VCC
INPUT OFFSET VOLTAGE NULLING CIRCUIT
Offset Null 1
Offset Null 2
20kΩ
VCC
ABSOLUTE MAXIMUM RATINGS
Symbol
2/4
Parameter
Value
Unit
±22
V
VCC
Supply Voltage
Vid
Differential Input Voltage
±30
V
Vi
Input Voltage
±22
V
Toper
Operating Temperature
-40 to +105
°C
Tstg
Storage Temperature
-65 to +150
°C
OP07C
ELECTRICAL CHARACTERISTICS
VCC = ±15V, Tamb = 25°C (unless otherwise specified)
Symbol
Vio
DVio
Iio
Parameter
Min.
Typ.
Max.
Unit
Input Offset Voltage
0°C ≤ Tamb ≤ +105°C
60
150
250
µV
Long Term Input Offset - Voltage Stability - note 1)
0.4
2
µV/Mo
Input Offset Voltage Drift
0.5
1.8
µV/°C
Input Offset Current (Vic = 0V)
0°C ≤ Tamb ≤ +105°C
0.8
6
7
nA
DIio
Input Offset Current Drift
15
50
pA/°C
DIib
Input Bias Current Drift
15
50
pA/°C
Ro
Open Loop Output Resistance
60
Ω
Rid
Differential Input Resistance
33
MΩ
Ric
Common Mode Input Resistance
120
GΩ
Vicm
Input Common Mode Voltage Range
0°C ≤ Tamb ≤ +105°C
±13
±13
±13.5
CMR
Common-mode Rejection Ratio (Vic = Vicm min.)
0°C ≤ Tamb ≤ +105°C
100
97
120
SVR
Supply Voltage Rejection Ratio (VCC = ±3 to ±18V)
0°C ≤ Tamb ≤ +105°C
90
86
104
Avd
Large Signal Voltage Gain
VCC = ±15, RL = 2kΩ, VO = ±10V
0°C ≤ Tamb ≤ +105°C
VCC = ±3, RL = 500Ω, VO = ±0.5V
120
100
100
400
±12
±11.5
±13
±12.8
±12
V
dB
dB
V/mV
400
Output Voltage Swing
Vopp
0°C ≤ Tamb ≤ +105°C
SR
GBP
ICC
en
in
1.
RL = 10kΩ
RL = 2kΩ
RL = 1kΩ
RL = 2kΩ
V
±11
Slew Rate ( RL = 2kΩ, CL = 100pF)
0.17
V/µs
Gain Bandwidth Product (RL = 2kΩ, CL = 100pF, f = 100kHz)
0.5
MHz
Supply Current - no load
0°C ≤ Tamb ≤ +105°C
VCC = ±3V
2.7
Equivalent Input Noise Voltage
f = 10kHz
f = 100Hz
f = 1kHz
Equivalent Input Noise Current
f = 10kHz
f = 100Hz
f = 1kHz
0.67
5
6
1.3
11
10.5
10
20
13.5
11.5
nV
-----------Hz
0.3
0.2
0.1
0.9
0.3
0.2
pA
-----------Hz
mA
Long term input offset voltage stability refers to the average trend line of Vio vs time over extended periods after the first 30 days of operation.
3/4
OP07C
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
Millimeters
Inches
Dimensions
Min.
A
a1
B
b
b1
D
E
e
e3
e4
F
i
L
Z
Typ.
Max.
Min.
3.32
0.51
1.15
0.356
0.204
1.65
0.55
0.304
10.92
9.75
7.95
0.020
0.045
0.014
0.008
Max.
0.065
0.022
0.012
0.430
0.384
0.313
2.54
7.62
7.62
3.18
Typ.
0.131
0.100
0.300
0.300
6.6
5.08
3.81
1.52
0.125
0260
0.200
0.150
0.060
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systems without express written approval of STMicroelectronics.
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