Intl. Journal of Microcircuits and Electronic Packaging
A Modular, Chip Scale, Direct Chip Attach MEMS
Package: Architecture and Processing
Jordan Neysmith and Daniel F. Baldwin*
AdAPT - Advanced Assembly Process Technology Laboratory
George W. Woodruff School of Mechanical Engineering
Georgia Institute of Technology
813 Ferst Drive NW
Atlanta, Georgia 30332-0405
Phone: 404-894-4135
Fax: 404-894-9342
e-mail: daniel.baldwin@me.gatech.edu
*Corresponding author
Abstract
This paper describes the development of a chip scale microelectromechanical system (MEMS) carrier compatible with modern
surface mount assembly. Such a package could facilitate the commercial implementation of many MEMS devices currently feasible
only as prototypes. In order to achieve the project goals, work focused on the reduction of MEMS package volume and on the
incorporation of solder interconnect technology. The design integrated advances in the fields of MEMS fabrication and microelectronics packaging. A through-wafer electrical interconnect structure was developed in order to permit “face-up” device orientations
and to minimize the package footprint. An interchangeable polymer assembly system and configurable cap structure allowed the
package components to be combined in a modular fashion. Such flexibility should permit this one package architecture to serve the
needs of a variety of MEMS applications. All processing and assembly was conducted at the wafer level after which a standard dicing
process singulated individual packages. Conducting unit operations at the wafer level simplified much of the packaging process flow
by alleviating alignment, bonding, and handling concerns. The resulting packages were fully compatible with high-throughput
surface mount equipment.
Key words:
MEMS, Packaging, Electrical Interconnect, Polymer Bonding,
and Wafer Level.
1. Introduction
For MEMS to achieve a significant presence in the commercial microelectronics market, packaging strategies need be developed that are compatible with low cost electronics packaging
and assembly such as state-of-the-art surface mount technology
(SMT). Compatibility simplifies the insertion of MEMS prod-
ucts into existing integrated circuit (IC) assembly lines. Direct
chip attach (DCA) assembly also permits the realization of chip
scale MEMS packages. Wafer level processing is another crucial aspect of any advanced packaging scheme. Placing individual MEMS die into standard lead frame packages is a slow
and arduous solution, with the additional disadvantage of limited pin count. More promising alternatives draw on concepts
applied to chip scale package (CSP) and multichip module (MCM)
design.
This paper presents the details of a modular, chip scale, direct
chip attach MEMS package architecture. A novel through-wafer electrical interconnect structure allows “face-up” device-toboard assembly and minimizes the package footprint. A
configurable cap structure, bonded to the MEMS substrate using
polymer adhesives, creates modularity in order to address the
diverse operational requirements of numerous MEMS devices.
All processing and assembly is conducted at the wafer level.
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A Modular, Chip Scale, Direct Chip Attach MEMS Package: Architecture and Processing
2. Background
Only within the last decade has the engineering community
begun to seriously address the lack of packaging capabilities for
MEMS. The packaging challenge is significant due to the need
for interaction between the MEMS device and various environmental domains (physical, chemical, optical, and magnetic). Any
interaction requirements must be met in addition to the standard
IC assembly provisions of mechanical support, power and signal
distribution; environmental protection, and thermal management.
Work has recently been published on a variety of MEMS packaging approaches. MEMS have been successfully packaged in ceramic carriers; with glass caps; in MCM foundries; and by molded
lead-frame equipment1-4. Many other enclosures and Chip Scale
Package concepts have also been proposed5-7. Generally, published work has focused on individual components or contributing technologies, with little emphasis on complete packaging
solutions. Application specific and hermetically sealed packages dominate the field.
a silicon cap and intermediate polymer bond layer were chosen.
At this stage, the need for thermal management was not addressed due to the low level of circuit integration on most MEMS
die. Compensating features can be added to the package architecture when the need for thermal management increases.
Figure 1 depicts a solid model of the package architecture.
The individual components were a silicon substrate (neither device nor circuitry were present), through-wafer conductive vias,
patterned silicon cap and polymer bond region. All fabrication
steps described in this paper were carried out on 2" P-type <100>
SSP test grade 275µm thick silicon wafers of 1-10!-cm resistivity.
Cap
Bond Region
Cavity
Vias
Substrate
3. Package Architecture
Figure 1. Model of an assembled package.
For a majority of bulk and surface micromachined MEMS,
the complete device is already supported on a rigid substrate.
4. Fabrication Methodology
This substrate can be considered part of the package and can be
relied on to provide mechanical support.
To supply numerous electrical input and output (I/O) chan4.1. Interconnect Fabrication
nels without a large package footprint, DCA techniques such as
Flip Chip processing are required. Unfortunately, there are many
In order to minimize the package footprint, electrical routing
situations where a MEMS device should remain “face-up” in
was
done through the silicon substrate using high aspect ratio
order to simplify interaction with its surroundings. To accomconductive
vias. On the wafer backside, these conductive vias
modate this orientation constraint, it is necessary to route the
were
capped
with solder bumps for compatibility with DCA aselectrical contacts to the backside of the MEMS substrate. Sevsembly
techniques.
A schematic cross section of one via is shown
eral batch approaches have been demonstrated based on throughin
Figure
2.
wafer via systems8-12. In this case, a novel through-wafer conductive via structure was implemented. The structure is space
efficient and vias can be located in either a peripheral or area
array pattern. Individual vias are capped with solder bumps to
Passivation
allow assembly to Printed Circuit Boards or stacking with other
microelectronic die.
Silicon
To ensure reliable device operation, most MEMS must be at
least partially isolated from their operational environment. One
appropriate solution is to cap the device. A properly designed
Metal
cap will not only protect sensitive device regions from attack by
destructive agents but can also provide inlet and outlet ports for
regulated interaction with the surrounding environment. In orBump
der to join the cap and substrate, a bond between their mating
surfaces must be established. Published research details an abundance of potential bonding processes, including direct bonding13,
Figure 2. Schematic of a through-wafer electrical intersolder reflow14; permeable polysilicon15; compression bonding16;
connect.
localized heating17; and polymer adhesives18,19. For this project,
The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number 4, Fourth Quarter, 2000 (ISSN 1063-1674)
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Intl. Journal of Microcircuits and Electronic Packaging
The via holes were defined in a 20µm thick liquid photoresist
over all test sites. For the solder paste, no flux was required. For
using contact optical lithography. After resist development, the
the solder spheres, a water soluble commercial fluxing agent was
vias were dry etched in an inductively coupled plasma chamber
applied to the UBM prior to sphere placement and reflow. A
using an iterative, fluorine-based recipe. The etch rate varied
region of bumped sites is shown in Figure 3.
with hole diameter, from approximately 5µm/min for a 200µm
opening to approximately 3µm/min for a 50µm opening. Although the resulting sidewalls were nearly vertical, showing a
taper of less than 2o, they exhibited a striated texture similar to
Aluminum
micrograss (aka: black silicon). The nominal peak-to-peak roughness of these sidewall striations was measured at 6µm.
Silicon dioxide was used to insulate the via holes prior to
deposition of a conductive layer. The oxide layer was thermally
grown at 1100oC to a surface thickness of 1.02µm with a refractive index of n=1.45. In order to create a conductive path through
the via, a metal thin film was deposited onto the oxide. Aluminum was chosen since it is commonly used in IC metallization
Solder
and adheres well to silicon dioxide without a seed layer. On the
UBM
Spheres
wafer backside, the use of aluminum also provided a natural solder mask during bump processing, as eutectic lead-tin (Pb/Sn:37/
63) solder does not wet aluminum. The aluminum was deposFigure 3. Through-wafer electrical interconnect structures
ited by magnetron sputtering to a surface thickness of 9000Å,
(bottom view).
from both sides of the wafer. The resulting sidewall coverage
was estimated, by Scanning Acoustic Microscopy (SEM), to be
approximately 2000Å. The aluminum was patterned with a com4.2. Cap Processing
mercial phosphoric, acetic, and nitric acid (PAN) etch using a
dry-film photoresist mask. Poor dry film adhesion to the alumiA wide variety of materials could be considered when making
num resulted in random mask delamination during the etch.
a cap structure, depending on the requirements of the device.
Reactive ion etch (RIE) removal using a chlorine-based plasma
Semiconductors, glasses, ceramics, metals, and plastics are all
chemistry was investigated to circumvent the delamination probcandidate materials. Initial bonding work was done with silicon
lems. However, dry film hardening during the RIE process made
for ease of processing and to avoid thermal expansion mismatch.
subsequent mask stripping difficult and the RIE process was not
Additionally, the existence of a significant body of work for silipursued. Delamination was reduced by increasing the applicacon bonding will allow meaningful comparison of polymer adtion temperature of the dry film resist.
hesives and other joining methods22.
After patterning the aluminum layer, select wafers were placed
To fabricate the caps, a silicon wafer was coated with a plasmain a tube furnace under nitrogen for 60min at 400oC. This anenhanced chemical vapor deposition (PECVD) silicon nitride
neal step was performed to improve the thin film adhesion by
film of thickness 870Å and refractive index n=2.08. This nitride
ensuring thorough reduction at the Al/SiO2 interface. The anfilm was patterned in a buffered oxide etch bath using a photoreneal step also tends to slightly decrease the resistivity of the alusist mask, which defined a grid of 7mm square openings spaced
minum film. The reason for the observed improvement in elec10mm apart on center. After stripping the photoresist, the silitrical performance is moot although it may be attributed to recon bulk was etched in a 6M solution of KOH at 80oC under
crystallization. In addition, annealing may help disperse the
gentle agitation. This etch created recesses in the silicon wafer
embedded aluminum oxide layer that grows when the sample is
corresponding to the 7mm square nitride mask openings. The
exposed to air while being turned for backside sputtering20.
average silicon etch rate was 0.23µm/min; etching was retarded
Once the aluminum was processed, an under-bump metalby the boron-doped layer in the P-type wafers. Etching was carlurgy (UBM) was sputtered onto the wafer around each via. The
ried out to an arbitrary depth of 100µm. The peak-to-peak cavity
UBM consisted of 1.4µm copper over 1000Å titanium, patterned
surface roughness was ± 0.1µm. Although not described in this
by wet etching in nitric acid, and hydrofluoric acid, respectively.
paper, further processing could be carried out on the cap to proThe titanium was deposited as an adhesion and diffusion barrier
vide inlet and outlet ports for fluidic or optical interconnects.
layer while the copper served as the solder wetting layer21.
To test the feasibility of capping vias by forming a solder bump
4.3. Bonding
over the annular UBM, eutectic Pb/Sn:37/63 solder paste and
Once MEMS devices and conductive vias have been fabripreformed solder spheres were manually applied to UBM sites
cated,
temperature excursions beyond 420oC are unwanted as
on test wafers. The wafers were then passed through a reflow
they
may
induce ion migration and degradation of any integrated
oven using a standard temperature profile. The UBM outer dicircuitry.
Processing temperatures in excess of the solder meltameters ranged from 200µm to 500µm, encircling vias that ranged
ing
point
are
also undesirable as each reflow cycle tends to weaken
in diameter from 50µm to 200µm. Bumps formed successfully
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A Modular, Chip Scale, Direct Chip Attach MEMS Package: Architecture and Processing
solder joints through the growth of intermetallic compounds.
These constraints negate any global direct bonding techniques,
such as fusion and anodic bonding, which require that the bulk
silicon reach excessive temperatures.
Several approaches that circumvent the temperature constraint
have been explored. Unfortunately, most methods are only effective for specific material combinations and some rely on hazardous chemicals that pose an additional processing challenge23. The
use of polymer bonding layers is encouraged due to their low cost
and ability to mate numerous material combinations. Polymer
formulations can be tailored to suit a range of performance envelopes and cure conditions (thermal and ultraviolet). However,
their lack of hermeticity and inability to maintain high vacuum
limit polymer performance.
In this paper, bond strength data for three polymer materials
are presented. The first material is a B-staged bisbenzocyclobutene
(BCB), the second is a polydimethylsiloxane (PDMS) silicone
elastomer and the third is an electronic film adhesive (EF2100).
BCB is a common dielectric in the microelectronics industry,
PDMS has been proposed as a material for fluidic circuit molding24 and EF2100 is used commercially for attaching substrates,
lids or heat sinks to microelectronic components. These materials were selected for their minimal outgassing; low moisture uptake; chemical resistance; operating temperature range, and ease
of processing. For initial strength evaluation, 5mm square,
unpatterned test die were placed individually onto a polymercoated handle wafer. The mating surfaces studied were bare silicon, silicon dioxide and silicon nitride as these are common surfaces exposed for bonding on a MEMS die. These materials also
allow a comparison of polymer adhesion between hydrophobic
(Si) and hydrophilic (SiO2 and Si3N4) surfaces. For reliability
analysis, bonding was carried out at the wafer level between solid
substrates and patterned, coated cap wafers. The mating surfaces of these assembled package samples were silicon nitride.
The BCB was dispensed statically and spun at 3000rpm for
30s with a ramp rate of 1000rpm/s. Curing was done following
the manufacturer’s recommendations in a furnace continuously
purged with nitrogen. Post cure thickness was approximately
3µm. For PDMS, the base material and curing agent were mixed
according to the manufacturer’s guidelines. The highly viscous
liquid was then applied using the same spin parameters as the
BCB. The cure phase was carried out in air on a hotplate for 15
minutes at 150oC, following a 2oC/s ramp from 50oC. Post cure
layer thickness was measured at 15µm. The EF2100 film was
cut to shape and applied manually. Curing took place at 170oC
for 1hr in an ambient air oven. The film thickness used in this
testing was 250µm and a pressure of 500Pa was applied during
the cure process to ensure good contact between the film and
adjoining surfaces.
5. Results and Discussion
5.1. Interconnect Performance Analysis
Preliminary via resistance testing was done with a simple 2point measurement system, although the intrinsic probe resistance was taken into account. Results are summarized in Table 1
showing mean values and standard deviation. The results are
based on measurements from 100 vias of each diameter and show
both pre-anneal and post-anneal values. Statistical analysis indicated that via diameter and measured resistance were inversely
proportional. Analysis also found that the effect of annealing
was not statistically significant. The sample data in all cases
showed large variability, which was found to be independent of
location on the wafer. The cause of this variability has not yet
been determined but etch inconsistency, incomplete cleaning in
the via throat and dry film delamination during aluminum patterning are three sources being investigated.
Table 1. Via resistance.
Via Diameter
[µm]
200
100
75
50
Pre-anneal Resistance
[Ω]
1.91 ± 3.97
23.27 ± 28.97
49.39 ± 63.88
382.1 ± 195.1
Post-anneal Resistance
[Ω]
1.79 ± 3.88
17.71 ± 22.50
26.97 ± 51.68
204.3 ± 131.7
Solder bump shear strength data are provided in Table 2. The
results show consistent shear strength values, except in the case
of the 200µm vias. These particular readings were exaggerated
due to solder wicking into the via throat, as seen in Figure 4.
The presence of a solder plug increased the force required to
shear each 200µm via bump site. Similar wicking was not seen
in smaller diameter vias, such as the one shown in Figure 5,
where surface tension forces likely precluded sidewall wetting.
Further study of the interactions among via diameter, solder composition and flux material may shed additional light on the
wicking phenomenon.
Table 2. Solder bump shear strength.
UBM
TiCu, Sputtered
Base Ti
TiCu, Sputtered
Base Al
Shear Strength [MPa]
Via Diameter [µ
µ m]
200µm
100µm
13.08
8.02
± 2.14
± 1.31
11.42
9.27
± 1.14
± 1.16
75µm
9.27
± 1.47
10.06
± 1.04
50µm
10.12
± 2.73
9.91
± 1.81
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Intl. Journal of Microcircuits and Electronic Packaging
Silicon
trapped during die placement or created during the cure phase.
The EF2100 film showed a similar voiding pattern to that of
PDMS but the voids themselves were much smaller, always less
than 100µm in diameter.
Solder
Plug
Solder Bump
Figure 4. Solder bump wicking into via.
Silicon
Mold
Void
Solder Bump
Table 3. Polymer adhesive strength.
Interface
[MPa]
BCB-Si
BCB-SiO2
BCB-Si3N4
PDMS-Si
PDMS-SiO2
PDMS-Si3N4
EF2100-Si
EF2100-SiO2
EF2100-Si3N4
Shear Strength
[MPa]
11.7 ± 1.1
12.9 ± 2.0
10.2 ± 1.6
2.8 ± 1.2
5.5 ± 1.1
4.2 ± 0.7
32.3 ± 3.5
11.8 ± 0.9
11.7 ± 1.1
Tensile Strength
[MPa]
3.0 ± 0.2
1.8 ± 0.6
2.0 ± 0.5
1.5 ± 0.3
1.3 ± 0.5
1.0 ± 0.2
11.7 ± 0.5
7.2 ± 1.4
6.7 ± 1.3
In addition to the strength evaluation, some reliability analysis was also conducted on packages assembled with the polymer
adhesives. Samples were placed into either air-to-air thermal
cycling (-55oC/+125oC) or temperature-humidity exposure (85oC/
85%RH) chambers. Using C-mode Scanning Acoustic Microscopy (C-SAM), the bond regions were inspected for voiding and
delamination. After 300 cycles of air-to-air or 200hrs of temperature-humidity exposure, no void development was detected.
Slight delamination around the cavity perimeter was found in
the PDMS samples but delamination was not detected in samples
assembled with the other two polymers.
6. Conclusions
A modular, chip scale, direct chip attach MEMS package has
been developed. Fabrication steps were carried out at the wafer
level in order to maximize throughput. A novel through-wafer
electrical interconnect structure that allows “face-up” device-to5.2. Bonding Results
board assembly and minimizes the package footprint has been
fabricated and tested. The feasibility of forming solder bumps
Shear and tensile bond strength values were obtained for each
over vias, surrounded by annular UBM structures, was proven.
material combination. Each element of Table 3 contains a mean
High variability in the electrical resistance of this interconnect
value and standard deviation of results from fifteen die tested to
structure indicated the need for improved process characterizafailure. The shear test data suggests a clear strength difference
tion. Improved electrical performance could make this structure
in favour of BCB and EF2100, which show more than twice the
useful for MEMS and 3D IC packaging scenarios. Polymer adshear strength of PDMS. Tensile test results also support this
hesives have been evaluated to determine their suitability for use
conclusion. It is not possible to make a definitive statement rein MEMS packaging applications. Robust performance during
garding adhesion differences among the three surfaces studied
strength and reliability testing indicate that polymer adhesives
for either BCB or PDMS. However, EF2100 appears to have
could be an important material set for MEMS packaging applisuperior adhesion to hydrophobic surfaces, as compared to hycations.
drophilic ones.
In order to improve the performance of the through-wafer inVisual inspection of all strength test samples detected small
terconnect
structures, nickel electroplating will be explored. This
areas of voiding. For BCB, voids were occasionally found clusmodification
should reduce the via resistance by providing a much
tered near the center of a test site. This location suggests that the
thicker
conductive
layer in the via itself. Nickel plating should
voids, which were less than 200µm in diameter, resulted from
also
simplify
the
UBM
processing since a thick nickel layer can
outgassing during cure. Sporadic, random voids up to 500µm in
replace
the
titanium-copper
stack tested in this project. Reliabildiameter were found in all PDMS test sites. They may have been
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Figure 5. Solder bump without wicking into via.
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© International Microelectronics And Packaging Society
A Modular, Chip Scale, Direct Chip Attach MEMS Package: Architecture and Processing
ity testing of the interconnect structure will also be conducted.
Further analysis of the effect of polymer adhesives on MEMS
operation will be pursued in the form of leakage modeling, validation and performance comparison. The package architecture
described is well suited for this sort of analysis since a many
materials can be used to join the cap and substrate, providing
various levels of hermeticity.
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About the authors
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Stacking of Microsystems”, ASME MEMS’99, Nashville, Tennessee, November 14-19, pp. 537-540, 1999.
10. J. Gobet et al., “IC Compatible Fabrication of Through-WaJordan Neysmith received a M.S. Degree in Mechanical Enfer Conductive Vias”, SPIE Conference on Micromachining
gineering from the Georgia Institute of Technology in 2000 and
and Microfabrication Process Technology III, Austin, Texas,
a B.S. Degree in Mechanical Engineering from Yale University
September 29, pp. 17-25, 1997.
in 1998. His recent work has focused on the development of
11. H. Kanbach et al., “3D Si-on-Si Stack Package”, Internamicrosystem packaging strategies. He was a Woodruff fellowship recipient during his graduate studies.
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Intl. Journal of Microcircuits and Electronic Packaging
Daniel F. Baldwin is an Assistant Professor at the Georgia
Institute of Technology having joined the faculty from Bell Laboratories where he worked on electronic product miniaturization.
He received his Ph.D. and S.M. Degrees in Mechanical Engineering from MIT in 1994, and 1990, respectively. Dr. Baldwin
has extensive experience in polymer processing and electronics
manufacturing with expertise in electronic packaging, advanced
materials processing and manufacturing systems design; two U.S.
patents; and over 70 scholarly publications. He currently leads
the Low Cost Flip Chip Processing program for the NSF Packaging Research Center at Georgia Tech, the Low Cost Electronics
Assembly Processing Program for the Georgia Tech Center for
Board Assembly Research and the Advanced Interconnect Technologies research program at the Georgia Tech Manufacturing
Research Center. Dr. Baldwin is serving as Chairman of the
ASME MEMS Packaging Committee and is on the board of advisors for the Society of Manufacturing Engineering Association
for Electronics Manufacturing. He was the recipient of the 1999
Society of Manufacturing Engineers Milton C. Shaw Outstanding Young Manufacturing Engineer Award; the 1998 American
Society of Mechanical Engineers Electrical and Electronics Packaging Division Young Engineer Award; the 1998 Outstanding
Research Faculty of the Year Award; and the 1996 Packaging
Research Center Outstanding Faculty of the Year Award for his
exemplary contributions in research, education, technology transfer and infrastructure development.
The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number 4, Fourth Quarter, 2000 (ISSN 1063-1674)
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© International Microelectronics And Packaging Society