National Conference on Recent Trends in Engineering & Technology
High Slew Rate Op-Amp Using Dynamic Circuit
In 0.35µm CMOS Technology
1
2
3
4
Chintan Patel
Mahendra Prajapati
Pankaj Prajapati,
Kirit Patel
Electronics Engg. Dept
Electronics Engg. Dept.
E.C Dept.
E.C Dept.
BVM Engg. College
BVM Engg. College
S.S.P College
L.D.R.P Engg. College
V.V. Nagar,Gujarat
V.V.Nagar, Gujarat
Visnagar, Gujarat
Gandinagar, Gujarat
Email: 1chintan_patel08@gmail.com, 2 mahin11@yahoo.co.in, 3 pp12479@gmail.com , 4 kiritvlsi@gmail.com
Abstract-- A 0.35 µm op-amp configuration with a slew rate
in excess of 10 V/µs and a unity gain bandwidth of 5 MHz
with load capacitance of 10 pf is proposed.Dynamic
technique that runs on a large current source when the rate of
change of input is larger than a pre-decided value. All the
operational amplifier parameter
like Common Mode
Rejection Ratio(CMRR) , Input Common Mode Ration
(ICMR),Open loop gain, Bandwidth, unity gain bandwidth,
are same before and after the Dynamic bias circuit is added .
Keywords
–
Common
Mode
Rejection
Ration,
Complementary metal Oxide Semiconductor, Input Common
Mode Ratio, Open Loop Gain, Output Offset Voltage,
Width/Length,
I. INTRODUCTION
This paper relates to operational amplifiers and more
particularly to a high precision operational amplifier which is
intermittently operational and providing a low quiescent
power requirement when in stand by state while proving high
slew rate when activated.
CMOS Op-amps typically have their slew rates of the
order of 10 V/ns. CMOS opamps with their slew rates an
order of magnitude larger have been proposed. Dynamic
current boosting is a popular technique employed to increase
the slew rate. In [1], a large current source is turned on
whenever the input crosses a preset value of slope.
Slew Rate= I/C
Static Bias
Circuitry
+
Input to Op-Amp
Output
Fig-1 Block Diagram of High Slew Rate Op-amp
So one other solution is dynamic current is flow during
charging and discharging of capacitance otherwise normal
current flow. So power dissipation is somewhat controllable.
But our other circuit parameter should not be changed.
Design part is divided in two parts:
A. Design of Operational Amplifier.
B. Proposed Dynamic Bias Circuit.
A. Design for Op-Amp [4]
(1)
Thus, for a given capacitance, the power consumption
imposes a definite limit to the slew rate. A possible solution
controlled input stage or dynamic biasing [1].
For stand by operation, circuits are turned off very
briefly and then powered down as quickly as possible to
minimize power consumption
II. DESIGN
As shown in fig-1 is the block diagram of high slew rate
operational amplifier. We require high slew rate as well as
low power consumption. Slew Rate depends upon two
parameter current and load capacitance but we can not play
with load capacitance. Only design parameter iss current but
if we increase current statically then power dissipation will
increases.
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Reference
Differentiator,
comparator and
dynamic bias
Ckt
TABLE
I
OP-AMP DESIGN SPECIFICATION
Device Technology
Open loop gain
Vdd
Vss
Slew rate
ICMR
Pdiss
Cl
Unity Gain Bandwidth
0.35 µm
>7000 v/v
2.5 V
-2.5 V
>10 v/µs
-1 to 2 v
<2mw
10 pf
5Mhz
By taking this specification started the design of the op-amp
[4] and calculating the (W/L) ration of fig-2. First assume that
VSG4 = VSG6. This will cause “proper mirroring” in the M3-M4
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B.V.M. Engineering
College, V.V.Nagar,Gujarat,India
National Conference on Recent Trends in Engineering & Technology
mirror. Also, the gate and drain of M4 are at the same
potential so that M4 is “guaranteed” to be in saturation.
So if the balance condition is satisfied, then VDG4 = 0 and M4
is saturated.
B. Proposed Dynamic Bias Circuit
As shown in fig-1 both input are connected in dynamic bias
circuit. Consider Vin+ input we first require differentiator so
when out input speed is high then our circuit become active.
Here, we take square wave input for checking purpose. So our
differentiator output spike is coming. Spike output is
depending on differentiator circuit. RC circuit is used as
differentiator. Output is depending upon three parameter R, C
and input speed (rise time and fall time).So these three are our
design parameter. We design the circuit like that if our input
speed is decrease than 10ns than spike output value is near
about 1v. So this 1v output can turn-on other MOS circuit. M9
and M10 are act as differentiator for Vin+. M9 acts as MOS
capacitor. And M10 act as MOS Resistor. PMOS is used as
resistor because of mobility of hole is less than electron. So
PMOS gives high resistance value.
Now consider 1v positive and 1v negative spike comes
at the input of M11 and M12. During positive spike M11 turns
on and during negative spike M12 turns on. So current is
flowing through that during short amount time. Here M13 and
M14 transistor are in fixed bias. So current flowing through it
is constant. Whenever high current flow then drain node
voltage is increase because of loading effect. So it can turn on
the transistor M15 and M16 which is heavy current sink so near
about 1mv dynamic current is flowing in the circuit during
transition so our slew rate increase Total three main parts of
dynamic circuit differentiator, Comparator, Heavy Current
sink. As shown in fig-3 transistor M9 and M10 are work as
differentiator for Vin+ M11, M12, M13, M14 are work as
comparator for both and M15 and M16 work as heavy current
sink. For Vin- M18, M17 work as differentiator and rest part are
same.
By considering the load capacitance 10pf we proposed
our design and calculating the (W/L) of the figure 3.
III. SIMULATION RESULTS
Simulation is more concentration on Slew rate. Slew rate is
nothing but how fast output can swing without distorted. For
this we are apply pulse (i.e .VIN+ 2 0 PULSE (-1v 1v 0ns 2ns
2ns 10µs 50µs)) and checking the output with and without the
dynamic bias circuits as shown in fig-5 and fig-4 respectively
in SPICE. Now we have to also consider other parameter of
op-amp that is not to be change by after applying the dynamic
bias circuit.
I) For open loop gain calculation we apply a sinusoidal signal
(Vin+ 2 0 SIN (0 100u 1k)) at the input of op-amp with 10pf
load capacitor.
II) For ICMR we apply DC input (DC Vin+ -2.5v 2.5v 0.1v)
at the input terminal with stepping of 0.1v
(III) For output offset voltage we apply small amount of
voltage (.DC VIN+ -5mv 5mv 1mv) at input with stepping of
1mv.
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IV) For CMRR we apply a common input to both terminal
and calculate using CMRR= 20log(Ad/Ac).
TABLEIII
OP-AMP PARAMETERS WITH AND WITHOUT BIAS CIRCUIT
Parameters
Technology
Open loop gain
Vdd
Vss
Slew Rate
ICMR
Unity
Gain
Bandwidth
Phase margin
CMRR
Without Dynamic
Bias
0.35µm
9984 v/v
2.5 V
-2.5 V
9.09 v/µs
-1 to 2v
5 MHz
With Dynamic
Bias
0.35µm
9947 v/v
2.5 V
-2.5 V
200 v/µs
-1 to 2v
5 MHz
70
86.991db
69
86.75db
Vss
M3
M4
M6
C
M2
Vout
Vin
Node-6
M7
Vbias
M6
Vss
Fig-2 Operational Amplifier
Fig-3 Dynamic Bias Circuit
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National Conference on Recent Trends in Engineering & Technology
Fig-4 Slew Rate without Dynamic circuit
Fig-5 slew rate with dynamic circuit
Fig-7 with dynamic circuit
Fig-8 output off set voltage without dynamic bias
Fig-9 output off set voltage with dynamic bias
Fig-6 bias without dynamic
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College, V.V.Nagar,Gujarat,India
National Conference on Recent Trends in Engineering & Technology
V. CONCLUSIONS
Slew rate of operational amplifier is depending on two
parameter capacitance and current flowing through circuit.
Capacitor is not design parameter so the only one design
parameter is current but if increase current statically the
power dissipation in the circuit is increases. So, concept of
dynamic biasing is come to picture. So design the operational
amplifier with dynamic biasing circuit we can achieve less
power dissipation and high slew rate at the same time.
REFERENCES
[1] Ramirez-Angulo, J, Carvajal, R.G., Lopez-Martin,” High
slew rate two stage A/AB and AB/AB op-amps with phase
lead compensation at Output node and local common mode
feedback” IEEE International Symposium on Volume, Issue,
18-21 May 2008
[2] P.C. Subramanian, C.R. Manoj and T.M. Karemulla,
“High Slew-Rate CMOS Operational amplifier”, IEE 2003,
Electronics Letters Online No: 20030457
[3] Klinke, R., Hosticka, Pfleiderer. H J: 'A Very-HighSlew-Rate CMOS Operational amplifier', IEEEJ Solid-Stare
Circuits, 1989.24, (3), pp. 744- 746
[4] Den. R.U, 'High Slew-Rate Operational Amplifier
Architecture'. US Patent 6,310,520 BI, October 30, 2001
[5] Allen, P.E., and Hulberg. D R.: 'CMOS analog Circuit
design' (Oxford University Press, 2002. 2nd edn.)
[6]
K.De Langen, J.H Huijsing,”Compact Low-Voltage
Power Efficient Operational Amplifier Cells for
VLSI”IEEE J.of solid St Circuits.vol 33, No 10, Oct, 1998,
pp.1482-1496.
[7] Lee, B W., and Sheu. B J.: 'A High-Slew-Rate CMOS
Amplifier for Analog
Signal Processing', IEEE J SolidState Circuits, 1990, 25, (3). o..n. 885-889
13-14 May 2011
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B.V.M. Engineering
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