Custom & Multichip Packaging
Contract Manufacturing
Micross’ contract assembly offers design and engineering support, BOM
procurement, and a wide selection of package, substrate and interposer materials.
Micross provides comprehensive semiconductor packaging services for
multiple electronic components, including digital, mixed signal, analog,
multi-chip and System-in-Package (SiP). We design, build and test
hermetic QML and chip scale packaging for various markets including
down-hole, aerospace, satellite and military.
We combine advanced processes and product development to provide
full turnkey support for prototype to volume production of flip chip and
wire bond packages including single chip, multichip and SiP applications
on organic substrates or ceramic substrates.
By ensuring delivery of finished wafers through our relationships with
silicon OCMs, and full coordination of customer BOM requirements,
we offer complete supply-chain management services for microelectronic assemblies.
Micross supplies modules and contract assembly services for multiple
platforms: industrial, airborne; commercial and government satellites;
missile and ordnance; C4ISR and medical.
Micross Components can support your
custom design with:
• Complete turnkey product - including program
and vendor management of all elements
throughout the product lifecycle
• Co-development of a statement of work (SOW)
Custom Multichip Packaging (MCP) is a die based system or sub-system
assembled into a single package which is then mounted to the PCB.
In its simplest form factor, two or more of the same die are combined
in one industry standard package that is smaller than the equivalent
single die packages combined. This provides the user with density and
performance two to three generations ahead of current semiconductor
fab processes.
Typically, multichip or system in a package devices are comprised of
multiple memory die, but often include a processor, gate array, ASIC, or
other logic as demanded by the customers application. They can also
be combined with other components such as registers, clocks, sensors,
triggers, passives, MEMS, voltage regulators, etc.
• Co-design, starting with schematic, netlist or
product definition and documentation
• Environmental requirements review
• Package and material selection for optimization
of electrical and environmental performance,
thermal management, PCB second level
reliability and cost
• Qualification requirements vis-à-vis package
definition, electrical test and characterization
expectations
• Evaluation of the power requirements vs.
proposed package design; analyzed in
conjunction with the creation of the initial layout,
die placement and floor planning and routing
• Analysis of thermal and mechanical elements
• Customer defined package and pin assignments
Micross serves the defense aerospace, medical, industrial and space
markets with these technologies. Design, assembly and test are
performed in an on shore MIL-PRF-38535, MIL-PRF-38534 facility
certified by DSCC to class V and H.
• Obsolescence management
• Counterfeit mitigation
• DNA marking
• Die revision control
• On shore design, assembly and test
• Use of COTS standard silicon from our die
distribution partners
September 2013 • Revision 3.8
7725 N. Orange Blossom Trail
•
Orlando, FL 32810 •
407.298.7100
•
sales.americas@micross.com
•
www.micross.com
Custom & Multichip Packaging
Contract Manufacturing
• Through-hole
• PIND
ƒƒ Pin Grid Array (PGA)
• Lead failure
ƒƒ Ceramic Dual-In-Line Package (CDIP)
ƒƒ Zig-Zag in-line (ZIP)
• Hermetic testing
ƒƒ Metal can
• Fine and gross leak test
Services
• SPC, technical support
• Die banking and parts management
• Centrifuge
• Total turnkey manufacturing, full BOM
management
• Mechanical shock and vibration
Test
• DMS/obsolescence mitigation
Facility and Quality
ƒƒ MIL-PRF-38535, Class V (assembly)
• Die banking and diminished sources (End of
Life) support. Micross die bank is equipped with
state-of-the-art climate control systems and
nitrogen-purged dry boxes. We store and handle
inventory per military/industry specifications and
provide internal class A and B die inspection.
ƒƒ Laboratory Suitability (MIL-STD-883)
• Obsolete and legacy products support
• DSCC QML
ƒƒ MIL-PRF-38534, Class H
(Class K in process)
ƒƒ MIL-PRF-38535, Class Q
• SMD, Q and M level
• Flexible, personalized customer support
• Certification of wafer traceability lot to Class H or
Class K requirements.
• Temperature cycling
Engineering & Analytical Services
• Hot probe to 150°C
ƒƒ Can be tooled for full functional test
ƒƒ Capacity dependent on complexity of die and
die/wafer
• Full temperature upscreening
• Testing for memory, mixed signal, LSI, VLSI,
linear, logic, ASICs, RF, and discretes
• Custom test equipment
• Test equipment
ƒƒ Agilent 83000
• All die preparation, sample assembly, evaluation
and test per Table C-II in-house with full
traceability and MIL-STD-883 DSCC Laboratory
Certification.
• Scanning Electron Microscopy (SEM)
• NSTS 5300.4
• Lot Acceptance Testing
ƒƒ Testronics 201 and FET9400
• Capabilities for Class S manufacturing
• Design of substrates, plastic/laminate or
hermetic ceramic
ƒƒ Linear Test Systems LTX TS80
• Test, burn-in and qualification
ƒƒ Delta flex pick & place handlers
• Visual inspection insures defect free die products
ƒƒ Symtek handlers - X1 & X4
• Wafer probe insures post-assembly integrity
ƒƒ Temptronics temperature forcing systems
(-65°C to +150°C capability)
• AS9100 Rev. C registered
• Customer specific, Source Control Drawing (SCD)
Packaging Options
ƒƒ Mixed Signal LTX Credence D10
• Decapsulation
ƒƒ Memory test - Teradyne J937
• Demarking and ink or laser mark
ƒƒ Teradyne A585
• Pick and place automation for quick and precise
custom packaging
• Surface mount
ƒƒ Plastic Ball Grid Array (PBGA)
• Component evaluation and qualification
ƒƒ Chip Scale Package (CSP)
• Package and sub-assembly design
ƒƒ Ceramic and HiTCE Ceramic BGA
• Device characterization
(see Table 1)
ƒƒ Automated Bench Test
• Full static/dynamic burn-in
ƒƒ Burn-in boards
ƒƒ Convection ovens
ƒƒ Static and dynamic Wakefield chambers
Class 100 Clean Room
• Infant mortality testing
ƒƒ Ceramic Flat Pack (FP)
ƒƒ ECL test system
• Sonoscan (CSAM), X-ray
ƒƒ Ceramic Quad Flat Pack (CQFP)
• Stud pull, bond pull
ƒƒ Ceramic gull wing
ƒƒ Plastic, Small-Outline, J-leaded (CSOJ)
• Moisture resistance
ƒƒ SOJ, QFP, and TSOP as open cavity
• Steam age/solderability
ƒƒ Plastic, Thin Quad Flat Package (TQFP)
• Salt spray
ƒƒ Ceramic Leadless Chip Carrier (CLCC)
• Thermal shock/thermal analysis
September 2013 • Revision 3.8
7725 N. Orange Blossom Trail
•
Orlando, FL 32810 •
407.298.7100
•
sales.americas@micross.com
•
www.micross.com
Custom & Multichip Packaging
Contract Manufacturing
• Flip-chip attach assembly including flux, high
accuracy placement, reflow and precision
automated capillary underfill
• Mixed technology combinations of bare die and
packaged parts enable reduced form factors and
cost management
• State of the art die placement machine –
placement accuracy of ± 10µm
ƒƒ Bonding capabilities include: gold ball, gold
and aluminum wedge
ƒƒ AMBYX memory, large capacity ovens
ƒƒ AEHR ovens
• Greater functionality in a faster timeto-market window than could be done
through silicon integration or ASIC
development.
• Auto/manual wire bonding
ƒƒ K&S and F&K Delvotec automatic wire
bonders
Assembly
• Reduced cost compared to an ASIC.
ƒƒ 0.7 to 3.0 mil aluminum ultrasonic
• 3D and advanced IC packaging equipment
• Increased density and performance with
reduced PCB area utilization; reduced
down routing at the PCB level and
reduced weight. Reduced down routing
can provide potential PCB layer reduction
and lower PCB costs.
ƒƒ 0.7 to 2.0 mil gold thermosonic
• Multi-chip package or monolithic
ƒƒ Heavy gauge 5 to 20 mil aluminum
• More than 10,000 sq. ft. of clean rooms
• Bond pull-destruct/non-destruct
ƒƒ Class 100
• Hermetic seal
ƒƒ Class 10,000
ƒƒ Gold-tin eutectic solder reflow
• Die materials - Silicon, SOS, GaAs, SiC
• Design optimization through use of the
most cost effective silicon solutions;
assembling various semiconductor
technologies, die geometries, or silicon
from different fabs in the same multichip
package.
ƒƒ Parallel seam seal
• Bare die on most substrates - FR4, Flex, LCP, BT,
BN, Ceramic, Polyimide
ƒƒ Resistance welding – TO packages
ƒƒ Glass frit seal
• Encapsulation, transfer mold, glob-top or dam
and fill
• Solder re-flow
• Wafer processing
• Vacuum bake
ƒƒ Wafer thinning to .004”
Multichip designs are assembled on an
interposer or substrate to create a customized,
integrated product for a unique application.
Within the multichip package, the designer
can utilize bare die (wire bond or flip chip),
WLCSP devices or stacked die. The critical
benefits of this technology include:
• Improved signal integrity from reduced
trace lengths.
• Lead trim/form
ƒƒ Cut range up to 8” or 250mm2
• Reduced PCB assembly complexity and
wider pitches, leading to simplified
Class 3 PCB compliance.
ƒƒ Die sorting - automatic pick and place
ƒƒ Wafer maps converted/uploaded to ALPS for
binning, sorting to gel pack, waffle pack, tape
and reel, or directly packaged
• Allows the OEM to upgrade products,
meet tech refreshes, or pre-planned
product improvements, by using die
shrinks in the same package.
• Automatic die attach
ƒƒ Eutectic
ƒƒ Epoxy
• Depending on environmental
requirements, the MCP can be in a
ceramic hermetic or plastic encapsulated
packages.
ƒƒ Solder
Typical material properties of widely used interposers for multichip packaging
Material
Thermal
Conductivity
TCE
Dielectric
Constant
Description
-40°C
25°C
125°C
W/mK
1MHz
High TG laminates (~300)
12-13
14-15
16-17
0.2
4.7
High TCE ceramic
8-8.5
8.5-9.0
10-11
2.0
9.4
Alumina ceramic Al2O3
5
6
7
18
10
Typical Conductor Material
3.2GHz
Description
Cu
9.5
Cu (paste)
W
September 2013 • Revision 3.8
7725 N. Orange Blossom Trail
•
Orlando, FL 32810 •
407.298.7100
•
sales.americas@micross.com
•
www.micross.com
Custom Capabilities
Robotic Hot Solder Dipping & Solder Exchange
Micross SXT™ (Solder Exchange Technology) is a robotic, automated solder-dipping process
developed by Micross Components to increase component reliability and mitigate tin-whisker
formation. With Micross SXT™, unwanted finish can be replaced on a wide range of electronic
components regardless of packaging style.
The GEIA-STD-0006 compliant process includes:
• Robotic-controlled six-axis dipping
• Solder dipping under a nitrogen blanket
• Solder-level sensing for accurate solder dipping
• Integral component wash and dry facility
• Preheating of components to negate thermal shock
• Lead tinning/solder dip
• Terminal finish conversion
• Solder exchange from Pb free (RoHS) ↔ SnPb
Hi-Rel Lead Attach
BGA Modifications
• Thermocompression weld lead
and high-temp solder lead
attachment processes
• BGA re-balling for conversion
to tin-lead (SnPb)
• Ball attach
• J, Gullwing, and Spider Gullwing
• BGA re-work
lead forms
Test
Trim & Form Components
• Trim, form, and solder dip to SOIC,
SOJ packages (other packages
not limited to DIP, PSOP, TSOP,
FP’s and QFP’s)
• Realign and Reform
Component Leads
• X-ray fluorescence
analysis (XRF)
• Ionic cleanliness test
• Solderability testing
• Particle Impact Noise Detection
test (PIND)
• Fine and gross leak testing
3D Scanning Tape & Reel
• Lead integrity/bond strength
Anti-Counterfeit Program & BOM Management
Micross Components is uniquely positioned to take a trusted role in your semiconductor supply chain to
provide a counterfeit-free purchasing experience. Throughout our 35+ year history of providing authentic
high-reliability products, we’ve developed the software and the skills needed
to handle everything from diodes to microprocessors.
If counterfeit protection is what you’re looking for... Get Real. Get Micross.
September 2013 • Revision 3.8
7725 N. Orange Blossom Trail
•
Orlando, FL 32810 •
407.298.7100
•
sales.americas@micross.com
•
www.micross.com