1 Assembly and Packaging (Part 1) Chapter 20 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, TFE4180 Semiconductor Technology, Norwegian University of Science and Technology ( NTNU ) TFE4180 Semiconductor Manufacturing Technology 2 Objectives • Describe the general trends and design constraints of assembly and packaging. • State and discuss the traditional assembly methods. • Describe the different traditional packaging options. TFE4180 Semiconductor Manufacturing Technology 3 Introduction • Final assembly and packaging, the back-end of the IC manufacturing process • Two distinct processes TFE4180 Semiconductor Manufacturing Technology 4 Traditional Final Assembly and Packaging Process (Encapsulation) Wafer test and sort Wire bond Die Separation Plastic packaging Die Attach Final packaging and test TFE4180 Semiconductor Manufacturing Technology 5 Four Important Functions of IC Packaging 1. 2. 3. 4. Protection from environment and handling damage Interconnections for signals into and out of the chip Physical support of the chip Heat dissipation TFE4180 Semiconductor Manufacturing Technology 6 Dual in-line package (DIP) Quad flat pack (QFP) Single in-line package (SIP) Plastic leaded chip carrier (PLCC) Thin small outline package (TSOP) Leadless chip carrier (LCC) TFE4180 Semiconductor Manufacturing Technology 7 Design Constraints for IC Packaging TFE4180 Semiconductor Manufacturing Technology 8 Levels of IC Packaging 1st level packaging: IC-packaging Metal leads for mounting onto printed circuit board Leads 2nd level packaging: Printed circuit board (PCB) assembly Surface mount chips are soldered on top of copper pads ont the PCB. Pins Pins are inserted into holes then soldered on rear of PCB. Edge connector plugs into main system PCB subassembly Final product assembly: Final assembly of circuit boards into system Main electronics assembly board TFE4180 Semiconductor Manufacturing Technology 9 Traditional Assembly TFE4180 Semiconductor Manufacturing Technology 10 Four Steps of Traditional Assembly • • • • Backgrind Die separation Die attach Wire bonding TFE4180 Semiconductor Manufacturing Technology 11 Backgrind Downforce Rotating and oscillating spindle Wafer on rotating chuck Table rotates only during indexing of wafers TFE4180 Semiconductor Manufacturing Technology 12 Advantages of Thinning Wafers • • • • Thinner wafers are easier to dice into chips Improved thermal dissipation Reduces thermal stresses in thin ULSI packages Thinner chips reduce the size profile and weight of the final IC package TFE4180 Semiconductor Manufacturing Technology 13 Die Separation Wafer Stage Blade TFE4180 Semiconductor Manufacturing Technology 14 Die Attach Lead Frame Lead Die Plastic DIP - Selected die is attached - Automated process http://www.youtube.com/watch?v=syMdS02P3_w TFE4180 Semiconductor Manufacturing Technology 15 Different Methods of Die Attaching • Epoxy attach • Eutectic Au-Si attach • Glass frit attach 15 TFE4180 Semiconductor Manufacturing Technology 16 Epoxy Attach Chip Epoxy Lead Frame TFE4180 Semiconductor Manufacturing Technology 17 Eutectic Au-Si Attach Gold/Silicon eutectic alloy Silicon Gold Film Lead Frame TFE4180 Semiconductor Manufacturing Technology 18 Glass Frit Attach Mixture of silver and glass particles suspended in an organic medium TFE4180 Semiconductor Manufacturing Technology 19 Wire Bonding Electrical connection from chip surface to inner lead terminal http://www.youtube.com/watch?v=VwOEQodkBrY TFE4180 Semiconductor Manufacturing Technology 20 Wire Connection Between Bonding Pad and Lead Frame Die Moulding compound Bond wire Bonding pad Leadframe Pin Tip TFE4180 Semiconductor Manufacturing Technology 21 Different Methods of Wire Bonding • Thermocompression bonding • Ultrasonic bonding • Thermosonic ball bonding 21 TFE4180 Semiconductor Manufacturing Technology 22 Thermocompression Wedge Bonding Heat Pressure Leadterminal Device Bond pad Wedge bond TFE4180 Semiconductor Manufacturing Technology 23 Ultrasonic Bonding Ultrasonic energy Tool moves upward Wedge tool Wire fed Pressure Wire Al bonding pad Die (1) (3) (2) Ultrasonic energy Pressure Tool moves upward Wire Breaks Lead Frame (4) (5) TFE4180 Semiconductor Manufacturing Technology 24 Ball Bonding Gold Wire Capillary tool Pressure + Ultrasonic energy Bonding ball on pad Die H2 Torch Die Ball (1) (3) (2) Pressure and heat Lead Frame (5) Tool moves up Wire Fed (4) Tool moves upward Wire Breaks at the bond (6) TFE4180 Semiconductor Manufacturing Technology 25 Comparison Among Methods Type Pressure Temperature Ultrasonic energy Wire Pad Au, Al, Au Thermo Compression High 300-500 oC No Ultrasonic Low 25 oC Yes Ball bonding Low 100-150 oC Yes Au, Al Al, Au Au Al, Au TFE4180 Semiconductor Manufacturing Technology 26 Wirebond Quality Measuring • Visual inspection • Pull test TFE4180 Semiconductor Manufacturing Technology 27 Visual Inspection • Used to detect wirebonding failures Wire broken Wire missing Ball short circuit 27 TFE4180 Semiconductor Manufacturing Technology 28 Pull Test • Quantitative assessment of wirebond quality Hook Terminal Device Chip under test Holder TFE4180 Semiconductor Manufacturing Technology 29 Traditional Packaging • Metal packaging • Plastic packaging • Ceramic packaging TFE4180 Semiconductor Manufacturing Technology 30 Metal Packaging • Was common in early history of Semiconductor industry • Still used today in special cases Gold‐plated header Die Wirebonds Leads TFE4180 Semiconductor Manufacturing Technology 31 Transistor Outline (TO) Type Metal Package Laser diode in TO39 package [1] Voltage regulator in TO3 package [2] Used for packaging this type of devices: • • • • Semiconductor lasers, solid-state lasers with a diode pumping Photodetectors, matrix photodetectors (CCD, FPA) X-Ray detectors Transistors, operational amplifiers, etc. TFE4180 Semiconductor Manufacturing Technology 32 Plastic Packaging • Industry mainstay since its introduction • Highly popular due to: o flexibility of the lead shape (gull-wings, J-leads, PIH) o high volume production techniques Die Leadframe Leadframe [3] Tie bar Tie bar removal lines TFE4180 Semiconductor Manufacturing Technology 33 Plastic Packaging Packaging procedure • • • • Molding Deflashing Component lead forming Lead finish TFE4180 Semiconductor Manufacturing Technology 34 Plastic Dual In-Line Package (DIP) A type of through-hole mount package with lead pins protruding from both sides of the package. DIP20 package [4] DIP6 package [5] Used for packaging this type of devices: Microcontrollers, logic elements, memory, operational amplifiers, buffers, optocouplers, timers, signal generators, etc. TFE4180 Semiconductor Manufacturing Technology 35 Single In-Line Package (SIP) A single row of leads protruding from the bottom of its body. SIP's are often used in packaging: • networks of multiple resistors • single on chip amplifier solutions • voltage regulators Power controller in SIP package [6] Audio power amplifier in SIP package [7] Resistor network in SIP package [8] TFE4180 Semiconductor Manufacturing Technology 36 TSOP with Gull Wings TSOP - Thin Small Outline Package Gull Wings – shape of the pins • • • • Low profile Tight lead spacing High pin count Used for surface mount SDRAM [9] DRAM [10] TSOPs are often used in packaging memory modules (SRAM, Flash memory, FSRAM and E2PROM) TFE4180 Semiconductor Manufacturing Technology 37 QFP with Gull Wing and Surface Mount Leads • QFP – Quad Flat Pack • Socketing such packages is rare and through-hole mounting is not possible. • Used for packaging memory, processors, controllers, ASIC, DSP, etc. 80‐pin Microprocessor in TQFP package [12] TQFP ‐ Thermally Enhanced package [11] TFE4180 Semiconductor Manufacturing Technology 38 PLCC with J-Leads • PLCC - Plastic Leaded Chip Carrier • Used for surface mount • Used for packaging memory, processors, controllers, ASIC, DSP PAL from TI in 28 pin package [14] EEPROM from ALTERA [13] TFE4180 Semiconductor Manufacturing Technology 39 Leadless Chip Carrier (LCC) • Available in plastic and ceramic packaging • Used for packaging CMOS image sensors, MEMS, crystal oscillator filters, antenna switch modules LCC from Tektronics [15] TFE4180 Semiconductor Manufacturing Technology 40 Ceramic Packaging Used for the state of the art devices that require: • maximum reliability • high-power • hermetic seal Two main methods of ceramic packaging: • Refractory ceramic (used for high performance IC packaging) • Laminated ceramic (low cost approach used to create CerDIP package) OpAmp from AD in CerDIP package for use in harsh environment [17] CPGA [16] TFE4180 Semiconductor Manufacturing Technology 41 g{tÇ~ lÉâ TFE4180 Semiconductor Manufacturing Technology 42 References [1] http://www.thorlabs.com/images/large/21973‐lrg.jpg [2] http://media.digikey.com/photos/Texas%20Instr%20Photos/296‐TO‐3‐8.jpg [3] http://www.ue.com.hk/index.php/SOIC_%28Small_Outline_Integrated_Circuit_Packages%29 [4] http://www.chinaicmart.com/uploadfile/ic‐doc/261‐20‐DIP.jpg [5] http://media.digikey.com/photos/Fairchild%20Semi%20Photos/46‐6‐DIP%20WHITE.jpg [6] http://www.infineon.com/cms/en/corporate/press/news/releases/2009/INFXX200906‐063.html [7] http://sjostromaudio.com/pages/hifi‐projects/36‐hifi‐projects/82‐qrp01‐the‐gainclone‐high‐performance‐power‐ amplifier?showall=1 [8] http://www.emartee.com/product/41417/Resistor%20Network%2010K%20OHM%209P%208RES%20SIP [9] http://rocky.digikey.com/weblib/Micron/Web%20photos/557‐86‐TSOP.jpg [10] http://s.eeweb.com/resized/images/remote/http_s.eeweb.com/quizzes/2011/02/22/dram‐tsop‐ 1298440075_500_327.png [11] http://www.analog.com/en/technical‐library/packages/qfp‐quad‐flat‐pack/tqfp‐thermally‐enhanced/index.html [12] http://en.wikipedia.org/wiki/File:PIC18F8720.jpg [13] http://ca.digikey.com/1/1/1042179‐ic‐max‐7000‐cpld‐64‐68‐plcc‐epm7064lc68‐15.html [14] http://media.digikey.com/photos/Texas%20Instr%20Photos/296‐28‐PLCC.jpg [15] http://component‐solutions.tek.com/services/ic‐packaging/packaging‐tech/#leadless‐chip‐carrier [16] http://www.interfacebus.com/ic‐package‐Ceramic‐PGA‐package‐dimensions.html [17] http://www.analog.com/en/technical‐library/packages/dip‐dual‐inline‐package/cerdip‐side‐or‐bottom‐ brazed/index.html 42 TFE4180 Semiconductor Manufacturing Technology