Electrical Analysis of IC Packaging with Emphasis on Different Ball Grid Array Packages
Khouzema B. Unchwaniwala, Michael F. Caggiano
Department of Electrical and Computer Engineering
Rutgers – The state university of New Jersey
94 Brett Road, Piscataway, NJ 08854
Phone: 732-445-5248, Fax: 732-445-2820
khuzem@ece.rutgers.edu, cagg@ece.rutgers.edu
Abstract
Parasitics associated with integrated circuit packaging are
beginning to affect the performance of the integrated circuit
with the rise in operating frequencies. Hence it has become
necessary to properly model the various components of the
package to provide better understanding of these effects. This
paper provides equivalent circuit models for the different
components of a package, such as the package leads in small
outline packages and the Quad flat-packs, the solder balls used
in ball grid arrays, through via holes & wire bonds in
packages. These electrical characteristics have thereafter been
used to model different package types currently used in the
industry with major emphasis being on the type of chip
connect or the first level interconnection. The electrical
parameters obtained confirm that most of the packages have to
be flip chip based when compared to wire bonded and overmolded alternatives as the frequencies of operation increases
to the high GHz range.
1. Introduction
The number of transistors in an integrated circuit are
increasing, with certain ASIC’s having up to 10e7 transistors
(the INTEL Pentium processor has roughly 3.1x10e6
transistors). With increase in complexity of the devices, the
interconnection from the die to the printed circuit board keeps
changing. Also the increase in switching speeds, power
dissipation and multiple die in package is leading towards the
emergence of various new packaging trends.
An ‘electronics package’ as defined in [1], is that portion
of an electronic structure, which serves to protect an
electronic/electrical element from its environment and the
environment from the electronic/electrical element and should
also allow for the complete testing of the packaged device.
Some would say the basic function of a package is to provide
signal distribution, heat dissipation, power distribution and
circuit support and protection. But with circuits approaching
higher frequencies, the function of a package is not just
limited to the above-mentioned functions.
Initially the electrical performance of the packaged
electrical component was limited by the component itself and
very little because of the package. But with rise in operating
range of frequency, parasitics associated with the package
began to affect the performance of the device.
A variety of electronic requirements for smaller, lighter,
faster, and less expensive products have not only led to better
fabrication techniques but also to better packaging techniques.
With increase in frequency range of operation, the electrical
performance of different packages decides the packaging used
for a particular application. Flip chip in packaging is
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beginning to be realized as a better packaging alternative for
their ability to reduce precious real estate used on the printed
circuit (wiring) board and also better electrical performance
instead of using the comparatively high inductance wire
bonds.
Ball Grid Array (BGA) packages from being an alternative
solution for high performance and high pin count applications
has become a standard choice for medium and high pin count
applications. A variety of CSP/BGA packages are flip-chip
based due to size and performance advantages when compared
to wire bonded and over-molded alternatives. This paper looks
into the electrical performance of different types of packages
with more emphasis on Flip chip connected silicon die in
BGA packages as they are the more likely packaging choice
for a mixed signal integrated circuit.
This paper models the different components of a package,
like the package leads in Dual-in-line package (DIP) and the
Quad flat packs (QFP), the solder balls used in Ball grid
arrays (BGA), through via holes, wire bonds in packages etc.
The electrical characteristics of different shapes and sizes of
solder balls have also been sought. These electrical
characteristics have thereafter been used to model different
package types being currently used in the industry. The Sparameters obtained are general electrical characteristics for
the signal route followed from the die pad to the printed
circuit (wiring) board.
2. Design Tool
The Maxwell Q3D Extractor is an interactive software
package that is used to electrically characterize threedimensional interconnect structures such as those found in
connectors, PCB’s, MCM’s etc. The software is used to solve
capacitance, partial inductance and resistance matrices. It uses
the multipole expansion technique for extraction of electrical
parameters.
The basic operation is to draw the structure, specify
material properties for each object, identify conductors, and
specify source excitations. The system then generates the
necessary circuit parameters used to generate the lumped
equivalent circuit models. These circuit models can then be
used to give the S-parameters for the different packaging
structures.
3. Equivalent circuit models for components that make a
package
For accurate electrical characterization of an electronic
package, it is important to have proper circuit models for the
components that make up the package including the wirebond,
the on package stripline/microstrip, the package leads as in
most Flat-packs and Small outline packages, Through via
2001 Electronic Components and Technology Conference
holes, Flip chip attach, and solder balls as in most Ball Grid
Array packages.
3.1: First Level Interconnection
First level interconnection is the interconnection between
the Integrated circuit and the electronic package. It is the
connection that provides the electrical contact between the IC
and the package. Usually, this interconnection is wire bonded
or flip chip attached and in some case tape bonded.
Wire bond
Most packages, including Quad Flat-packs to Ball Grid
Arrays, use wire bonds to connect the silicon die to the
package. It is important to get the electrical characteristics of
typical wire bond structures, as in fig. 1, that are used in highspeed IC packaging. Maxwell’s Q3D Extractor was used to
model the wire bond structure and get the equivalent circuit
for the structure. An experimental 1000um * 400um chip
(600um thick silicon) was mounted on a substrate having a
dielectric of 4.0. Wire bonds of different lengths were
structured to observe the effect on overall insertion loss. Gold
was used as the material for the wire bonds of diameter 25um.
Table 1. provides the electrical parameters for these wire
bonds.
Cap.
Cap.
to
to
Chip Substrate
ground
ground
(F)
(F)
1.4
1.02
0.06
25fF
8.5fF
1.7
1.40
0.08
25fF
8.5fF
Table 1. Electrical parameters for different lengths of wire
bonds with dimensions as specified above
Wire
‘L’
(mm)
Inductance
(nH)
Fig. 1 Lumped element representation of wire bonds
Resistance
(Ω)
Wire bond trace lengths were determined by measuring the
total trajectory of the wire bond in three dimensions and not
simply the lateral distances. Also according to [6], there is no
major difference in insertion loss between ball-wedge bonds
and wedge-wedge bonds. Hence we shall ignore it for this
project. Other important parameters for wire bonds are the
mutual inductance and capacitance between wire bonds. The
equivalent circuit for the gold wire bond of length 1.4mm and
diameter 0.025mm is given in fig. 1.
To compare the S-parameter obtained from the equivalent
circuit to actual measured insertion loss mentioned in [6], we
create an exact 3D model of the wire bonds as described in
[6]. The 3D model is as follows:
The electrical characteristics of typical wire bond
structures that are used in high-speed IC packaging were
measured. Measurements were performed up to 20GHz in
frequency. A 5000*5000um chip (400um thick alumina
(99.6%)) was mounted on a substrate (400um thick alumina
(99.6%)).
Wire bonds were made from chip to substrate. Gold wire,
25 microns in diameter and 930 microns long, was used. The
trace metallization on alumina was Ti.
The results of the measured and equivalent circuit model
are as shown in fig. 2.
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Fig.2 Comparison of Equivalent circuit and measured
results
Flip Chip Attach
Packaging advancements such as flip chip and associated
direct chip attachment methods offer many significant benefits
to the designer and manufacturer of next generation electronic
products. Flip chip attach is a method of attaching the chip on
to the package substrate. In this interconnection technology,
the chip is mounted upside down onto a carrier, module, or
PCB. The solder bumps are located on the surface of the chip
in an array so that periphery limitation, such as that
encountered in wire bonding, does not limit the I/O capability.
The functions of the solder bump are as follows:
1. Electrical connection between the chip and substrate.
2. May also serve as path for heat sink.
3. Also provides structural link between chip and substrate.
Electrical characteristics of flip chip attach for different
sensitivities were evaluated.
The equivalent circuit model for the above flip chip
attaches structure with the following parameters: flip chip
height = 0.060mm, flip chip diameter = 0.060mm, flip chip
material = solder is given below in fig. 3. The flip chip bumps
are used to attach a silicon die to a polyamide Quartz substrate
2001 Electronic Components and Technology Conference
having a dielectric of 4.0. The solder bumps are placed on
aluminum pads on the die, about 0.010 mm thick. This work
does not take into account any under bump metallization or
under fill.
Fig.3 Equivalent circuit for flip chip solder bump
Fig. 4 Comparison of S-parameters for different bump
heights
As can be seen from fig. 4, change of height from 0.030 to
0.100mm makes a very small difference to the S-parameters
obtained from the flip chip bump. The thickness of the silicon
die is 600um. Similarly change of pitch (fig. 5) also has a
small effect on the S-parameters, as can be seen below. The
two different plots are for pitches of 0.15mm and 0.25mm
(center to center). Since the flip chip attach are much smaller
in dimensions as compared to the BGA solder balls, change in
height and pitch really does not make much of a difference to
the S-parameters. The change in electrical elements of the
equivalent circuit model is much too small to make a
difference.
(PCB). This can be accomplished using a Package pin as used
in most early surface mount packages or using solder balls as
used in most BGA’s and CSP’s. This paper provides
equivalent circuit models for these components. The better
option electrically certainly is the BGA solder bump.
Package leads
The size and shape of Package leads differ from one
package to another. QFP’s, DIP’s, SOP’s, SOT’s, SOIC’s and
other packages use package leads to connect the package to
the Printed circuit board. Using package leads is not a very
efficient way of connecting the package to the printed circuit
board, as it uses up precious real estate on the PCB, and also
the area under the silicon chip remains unutilized. The
package lead adds substantially to the inductance between the
silicon die and the printed circuit board. Hence, there is a
trend to shift to BGA’s and also DCA/Flip chip on Board
(FCOB), i.e. if you consider it to be a package.
Shown below is the Small outline package (SOP) lead
example (fig. 6). This paper employs the dimensions used by
Kyocera Corporation to structure the package lead in Ansoft
as shown for a Plastic SOP. The package lead adds
substantially to the inductance between the silicon die and the
printed circuit board. The dimensions are in mm.
Fig. 6 Typical SOP package lead
The Maxwell Q3D model for the above package lead
yielded the following electrical characteristics (Table 2)
Inductance
AC Resistance (1GHz)
Capacitance to ground
1.8nH
0.16ohm
37.1fF
Table 2. Electrical parameters for the above-mentioned
Package lead
Fig.5 Comparison of S-parameters for different bump pitch
The average flip chip bump height is around 0.1mm. For
example, the Delphi Delco Electronic systems co. uses a flip
chip bumping pitch of 0.25mm and a bump height of
0.127mm+-0.005mm. The attachment pad diameter is
0.152mm and the silicon die thickness is 0.65mm.
3.2: Second level interconnection
The second level interconnection is the interconnection
between the electronic package and the printed circuit board
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BGA/CSP Solder ball
A significant contributing factor to the weight and size
reduction in packaging is the adoption of a structure requiring
a small mounting area, such as a Ball grid array (BGA) or a
chip scale package (CSP). The BGA package can be identified
by the solder bumps on the bottom of the package. The solder
bumps can be arranged in a uniform full matrix array over the
whole back area of the package or in neat multiple rows along
the circumference of the package. The result is a smaller
footprint of the package on the PCB. Thus the BGA package
is considered the package of choice for high-density and high
I/O IC’s. Equivalent circuit models of the solder bump have
2001 Electronic Components and Technology Conference
been obtained for different structures of the bump as shown
below.
Fig. 7 3D models of the barrel type and Sandglass type
BGA solder bumps
In s e r tio n L o s s (d B )
According to [7], solder bumps of the sandglass type shape
showed greater reliabilities than those of the barrel type shape.
Both models use the same volume of solder but have bumps of
different height The sandglass type has not been applied to
products yet because it is not easy to form such solder bumps
when soldering many other parts in the reflow process and
also because of the better electrical parameters of the barrel
type.
2
0
-2
-4
-6
-8
-1 0
-1 2
-1 4
-1 6
-1 8
-2 0
-2 2
-2 4
-2 6
-2 8
B a r r e l ty p e s o ld e r b u m p
S a n d g la s s ty p e s o ld e r b u m p
0
10
20
30
40
50
60
F re q u e n c y (G H z )
Fig. 8 Insertion loss for different shapes of solder bumps
Through Hole Via
Through hole vias are used to connect traces on the front
and back of the package in Ball grid array packages. Also in
DIP’s and other surface mount packages, the drill hole size of
the via is determined by the pin dimensions of the chip to be
inserted in the hole. Through hole vias are also used in Cavity
down BGA’s for purely thermal purposes. Typical plating
thickness of the vias is from 1 to 4 mils. The second attribute
is the metal area surrounding the hole for signals. Also the
land area covering the via hole in BGA packages is roughly
twice the diameter of the via hole. Shown below is the via hole
with a pitch of 1mm, via hole diameter of 0.35mm and
diameter of the land area being 0.5mm. The height of the
through hole via being the height of the package substrate,
roughly 0.6mm.
Incorporating vias directly below device attach pads or
lands can eliminate short traces or stubs from land to drill
holes. The elimination of such stubs may reduce EMI
emission and sensitivity because the circuit has fewer radiating
antennae. This S-parameter difference can be seen below.
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Fig. 9 Comparison of S-parameters for via land just
below wire bond pads or with inclusion of a trace
4. S-parameters for different packages
Let us look at the various types of packages available and
how their electrical performances are. Most of the results will
be more worst-case analysis and we will also compare them to
actual measured results.
Early Surface Mount Technology
The early surface mount technology can be considered to
be the ‘Flat Pack’. This was a thin metal package with leads
exiting the body on two sides. They remained in a plane
roughly parallel to the bottom of the body. The flat pack was
replaced by a plastic package with two rows of leads bent
downwards called a DIP or Dual-in-line package. But with the
increase in the I/O pin count these were also replaced by the
Quad flat-packs, which had leads emerging out from all four
sides. The basic path from the IC to the printed circuit board
consisted of the wire bond followed by the package trace and
the package lead to the contact pad on the printed circuit
board. As can be seen, the electrical performance of the
package deteriorates with increase in frequency. Hence the
need for better packaging technologies that can reduce the
high inductances of the package leads.
S-parameters for signal lines in different packages are as
shown below. The dual in line packages have the worst
Insertion loss at high frequencies because of the bulky
components that form the package. The package leads add
high inductances and along with the bond wire make it
impossible for this package to be used for mixed-signal circuit
applications.
Ball and Column Grid Array Technology
The technology used in BGA packages came from the
technology used by IBM for flip-chip assembly. The package
has found considerable use in small consumer oriented
electronics because of the small footprint it forms on the PCB.
Electrically the BGA packages are much better as can be seen
from the simulation results. The problem being the stress
fractures analysis and other mechanical and thermal issues.
2001 Electronic Components and Technology Conference
Fig. 10 Dual-in-line package
Fig. 13 Wire bonded Plastic Ball grid array
Fig. 11 Quad Flat Pack
More recently, a cavity down approach has gained popularity.
This approach gives better electrical performance, at the
expense of somewhat larger area. The vias in these packages
are typically used to conduct heat to the top of the package.
Ball pitches for BGA packages are decreasing from 1.27mm
to 1.0mm to as low as 0.5mm for new chip scale packages.
Standard metal trace widths are 0.003” on a 0.006” pitch, and
routing vias typically consist of a 0.010” hole on a 0.020”
land.
Fig. 22 S-parameters for Dual-in-line package (DIP).
5
0
-5
Loss (dB)
-10
-15
-20
-25
Return Loss (S11)
Insertion Loss (S21)
-30
-35
-40
0
5
Frequency (GHz)
Fig. 12 S-parameters for Dual in line package
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Fig. 14 Flip chip attached Ball Grid Array Package
The below results (fig. 15) show that the Flip chip attached
BGA would be a better alternative for high frequency
Integrated circuit packaging. The cavity down BGA is also a
better option as it reduces on two levels of traces and uses just
one level of trace and hence the only vias used here are
thermal vias, which do not contribute electrically. Hence the
cavity down BGA has slightly better electrical performance
when compared to normal FPBGA /FSBGA packages.
3.5 Electrical analysis of the TI 48-SSOP
Texas Instruments 48-pin SS0P (Shrink small outline
package) for Widebus applications, given in [5], has been
modeled and the modeled data compared to the electrical
measurements provided in its application report. The output
drivers drive 0/3.3V digital signals on the package lines.
These switching lines would induce noise into neighboring
lines. The amount of cross talk induced into a particular
package line would be determined by the package parasitics
and also by the number of signals switching state. The
experimental measurements have been provided in the
applications report. This paper models this very package to
2001 Electronic Components and Technology Conference
obtain the simulation data from ANSOFT using the physical
dimensions provided in the report.
-100
-200
Fig. 25 Return Loss comparison for the different Ball grid array packages
Return Loss (dB)
-10
-20
Wire Bonded Ball Grid Array
Cavity Down Ball Grid Array
Flip Chip Attached Ball Grid Array
-30
-40
Modeled data results
Experimental results
-400
-500
-600
-700
-800
0
1
2
3
4
5
6
7
8
9
Number of bits switching states from low to high
-50
0
10
20
30
40
Fig. 16 Comparison of Ansoft versus measured results.
Frequency (GHz)
Fig. 26 Insertion Loss comparison for different ball grid array packages
0
-2
Insertion Loss (dB)
-300
Crosstalk (mV)
0
-4
-6
-8
Wire bonded ball grid array
Cavity down ball grid array
Flip chip attached ball grid array
-10
-12
0
10
20
30
40
Frequency (GHz)
Fig. 15 Return and Insertion Loss comparison for different
Ball grid array types
The simulation results were compared to the Experimental
results as shown below. The simulation results varied to 25%
or better agreement when compared to the experimental
results, but the curve seemed to give a good approximate fit
for the experimental data. The data obtained from the
Maxwell Q3D Extractor was fed into a spice file to simulate
the amount of cross talk induced in a package signal line,
which does not change state. The mutual inductance was
considered for three adjacent signal lines in the package, not
wanting to add more complexity to the spice file, and without
taking away from the accuracy of the data to a great extend.
The mutual coupling coefficient falls to below 1.5 for the
fourth nearest neighbor because of the larger pitch of the 48SSOP packages when compared to other smaller pitch
alternatives. To model the whole package in spice would
require up to 300 to 400 lines of code. The package signal
lines were terminated with 50-ohm loads at the package lead.
The wire bonds are 100 mil long wires with a self-inductance
of 2nH.
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References
1. William D. Brown, “Advanced Electronics Packaging –
with emphasis on multi chip module”, IEEE Press series on
Microelectronic systems.
2. Masaharu ITO, Kenichi Maruhashi, Hideki Kusamitsu,
Yoshiaki Morishita, Keiichi Ohata, “Millimeter-wave flipchip MMIC structure with high performance and high
reliability interconnects”, IEICE trans. Electron. Vol.E82C, No. 11 November 1999.
3. Johannes Huchzermeier, “Comparison of Electrical and
thermal parameters of widebus SMD SSOP, TSSOP,
TVSOP, and LFBGA packages”, Application report,
Texas Instruments.
4. William R. Newberry, “Design techniques for Ball Grid
Arrays”, Xynetix Design Systems.
5. A. Becker, A. Lyons, K. Guinn, Y. Lee, H. Wu and M.
Tsai, “Wire bond measurements up to 20GHz – A starting
point”, Wireless packaging research department, Bell Labs
Research.
6. “Wire bond measurements up to 20GHz – A starting point”
by A. Becker, A. Lyons, K. Guinn, Y. Lee, H. Wu and M.
Tsai, Wireless packaging research department, Bell Labs
Research.
7. “Solder joint reliability of BGA/CSP for mobile phones” by
Kinuko Mishiro, Mitsunori Abe, Shigeo Ishikawa, Yutaka
Higashiguchi and Ken-ichiro Tsubone
8. “Understanding and using surface mount technology and
fine pitch technology” by Charles I Hutchins (Ph.D.).
9. “Packaging: More than a die holder” by R. T. Maniwa,
Integrated systems design Magazine, October 1995.
10. “Ultra high speed GaAs MESFET IC modules using flip
chip bonding” by H. Kikuchi, H. Tsunetsugu, M. Hirano,
S. Yamaguchi, and Y. Imai.
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