MITSUBISHI
MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Dual-In-Line
<Dual-In-Line
Package
Package
Intelligent
Intelligent
Power
Power
Module>
Module>
PS21564
PS21564
TRANSFER-MOLD
TRANSFER-MOLD
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE
PS21564
INTEGRATED POWER FUNCTIONS
600V/15A low-loss 5th generation IGBT inverter bridge for
3 phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
•
•
•
•
•
For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). (Fig.3)
Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
Input interface : 5V line CMOS/TTL compatible. (High Active)
UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
(0.278)
Dimensions in mm
(3.556)
(2.056)
TERMINAL
HEAT SINK SIDE
TERMINAL CODE
(0.5)
(R0
(3.556)
.75
(1)
)
(1.5)
(6.5)
(10.5)
(0.5)
(1)
(1.5)
(1.8MIN)
Detail A
987
654
321
(0.5)
12 10
11
(
Type name , Lot No.
I
PH
(P
2D
HI
EP
3.3
)
TH
2)
(30.5)
HEAT SINK SIDE
(17.6)
(17.4)
(35
34
(7.62)
33
(4.62)
(7.62 × 4)
(41)
(42)
(49)
32
31
(1)
(0.5)
35
°)
(1.2)
29
30
15 13
14
(5)
A
(0.5)
Note1)
(17.6)
(17.4)
(1.778)
0.5
28 27 26 25 24 23 22 21 20 19 18 16
17
(ex. PCB LAYOUT)
DUMMY PIN
(1.778 × 26)
PCB
PATTERN
SLIT
(1.25)
(2.5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VUFS
(UPG)
VUFB
VP1
(COM)
UP
VVFS
(VPG)
VVFB
VP1
(COM)
VP
VWFS
(WPG)
VWFB
VP1
(COM)
WP
(UNG)
VNO Note2)
UN
VN
WN
FO
CFO
CIN
VNC
VN1
(WNG)
(VNG)
P
U
V
W
N
Note 1 : In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.
2 : Treat the terminal VNO of PS21564 as NC (just the same as DIP-IPM ver.2). However, external connection of VNO with N
terminal is necessary for PS21562 or PS21563.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBW–
CBW+
CBU+
CBV+
CBV–
CBU–
High-side input (PWM)
(5V line) (Note 1,2)
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
C2
C1
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
(Note 6)
Protection
circuit (UV)
DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
P
AC line input
H-side IGBTS
U
V
(Note 4)
M
W
C
AC line output
Fig. 3
Z
N1
VNC
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
N
L-side IGBTS
CIN
Drive circuit
Protection
circuit
Fo logic
Input signal conditioning
Control supply
Under-Voltage
protection
FO CFO
Low-side input (PWM)
(5V line)
(Note 1, 2) Fault output (5V line)
(Note 3, 5)
Note1:
2:
3:
4:
5:
6:
VD
VNC
(15V line)
Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
Drive circuit
P
IC (A)
H-side IGBTS
SC Protection
Trip Level
U
V
W
L-side IGBTS
External protection circuit
N1
Shunt Resistor
A
N
(Note 1)
VNC
C R
Drive circuit
CIN
B
C
Collector current
waveform
Protection circuit
(Note 2)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
0
2
tw (µs)
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Parameter
Condition
Applied between P-N
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Ratings
Applied between P-N
Tf = 25°C
Tf = 25°C, less than 1ms
Tf = 25°C, per 1 chip
(Note 1)
450
500
600
15
30
22.2
–20~+125
Unit
V
V
V
A
A
W
°C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).
CONTROL (PROTECTION) PART
Symbol
Condition
VD
Parameter
Control supply voltage
VDB
Control supply voltage
VIN
Input voltage
VFO
IFO
VSC
Fault output supply voltage
Fault output current
Current sensing input voltage
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VNC, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
Unit
20
V
20
V
–0.5~VD+0.5
V
–0.5~VD+0.5
1
–0.5~VD+0.5
V
mA
V
Ratings
Unit
400
V
–20~+100
–40~+125
°C
°C
2500
Vrms
TOTAL SYSTEM
Symbol
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
Parameter
VCC(PROT) Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Tf
Tstg
Storage temperature
Viso
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Isolation voltage
Note 2 : Tf MEASUREMENT POINT
Al Board Specification :
Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm
Control Terminals
FWDi Chip
18mm
IGBT/FWDi Chip
16mm
Al Board
Groove
IGBT Chip
N W V U P
Temperature
measurement point
(inside the AI board) Power Terminals
Temperature measurement
point (inside the AI board)
Silicon-grease should be applied evenly with a thickness of 100~200µm
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Rth(j-f)Q
Rth(j-f)F
Parameter
Junction to case thermal
resistance
(Note 3)
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Min.
—
—
Limits
Typ.
—
—
Unit
Max.
4.5
°C/W
6.5
°C/W
Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCE(sat)
Condition
Parameter
Collector-emitter saturation
voltage
IC = 15A, Tj = 25°C
VD = VDB = 15V
VIN = 5V
IC = 15A, Tj = 125°C
Tj = 25°C, –IC = 15A, VIN = 0V
VEC
ton
trr
tc(on)
toff
tc(off)
FWDi forward voltage
Switching times
VCC = 300V, VD = VDB = 15V
IC = 15A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
ICES
Collector-emitter cut-off
current
VCE = VCES
Tj = 25°C
Tj = 125°C
Min.
—
—
—
Limits
Typ.
0.60
—
—
—
—
—
—
1.45
1.55
1.50
1.20
0.30
0.40
1.50
0.50
—
—
Min.
—
—
—
—
4.9
—
0.43
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
Limits
Typ.
—
—
—
—
—
—
0.48
1.5
—
—
—
—
1.8
2.3
1.4
Max.
1.95
2.05
2.00
1.80
—
0.60
2.10
0.80
1
10
Unit
V
V
µs
µs
µs
µs
µs
mA
CONTROL (PROTECTION) PART
Symbol
ID
Parameter
Circuit current
Condition
Total of VP1-VNC, VN1-VNC
VD = VDB = 15V
VIN = 5V
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VD = VDB = 15V Total of VP1-VNC, VN1-VNC
VIN = 0V
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VSC = 0V, FO circuit pull-up to 5V with 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V
(Note 4)
VIN = 5V
Trip level
Reset level
Tj ≤ 125°C
Trip level
Reset level
CFO = 22nF
(Note 5)
Max.
5.00
0.40
7.00
0.55
—
0.95
0.53
2.0
12.0
12.5
12.5
13.0
—
2.6
2.1
Unit
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
ms
V
V
VFOH
Fault output voltage
VFOL
Short circuit trip level
VSC(ref)
Input current
IIN
UVDBt
Supply circuit under-voltage
UVDBr
protection
UVDt
UVDr
Fault output pulse width
tFO
ON threshold voltage
Vth(on)
Applied between UP, VP, WP-VNC, UN, VN, WN-VNC
OFF threshold voltage
Vth(off)
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 25.5 A.
5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F].
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Condition
Parameter
Mounting torque
Weight
Heat-sink flatness
Mounting screw : M3
Recommended 0.78 N·m
(Note 6)
Min.
0.59
—
–50
Limits
Typ.
—
20
—
Max.
0.98
—
100
Min.
Limits
Typ.
Max.
0
13.5
13.0
–1
2.0
—
300
15.0
15.0
—
—
5
400
16.5
18.5
1
—
—
V
V
V
V/µs
µs
kHz
—
—
7.5
Arms
300
–5.0
—
—
—
5.0
ns
Unit
N·m
g
µm
Note 6: Measurement point of heat-sink flatness
+ –
Measurement location
3mm
Heat-sink side
–
+
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Condition
Applied between P-N
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, Tf ≤ 100°C
Tf ≤ 100°C, Tj ≤ 125°C
VCC = 300V, VD = 15V, fc = 5kHz
Allowable r.m.s. current
IO
P.F = 0.8, sinusoidal
Tj ≤ 125°C, Tf ≤ 100°C
PWIN
ON
Minimum input pulse width
VNC
between VNC-N (including surge)
VNC variation
Note 7 : The allowable r.m.s. current value depends on the actual application conditions.
8 : The input pulse width less than PWIN might make no response.
(Note 7)
(Note 8)
Unit
V
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
VUFB
VUFS
VP1
UP
P
HVIC1
VB
VCC
IGBT1
Di1
HO
IN
VS
COM
U
VVFB
VVFS
VP1
VP
HVIC2
VB
VCC
IGBT2
Di2
HO
IN
VS
COM
V
VWFB
VWFS
HVIC3
VP1
VCC
WP
IN
VB
IGBT3
Di3
HO
COM
VS
W
IGBT4
LVIC
Di4
UOUT
VN1
VCC
IGBT5
Di5
VOUT
UN
UN
VN
VN
WN
WN
Fo
Fo
IGBT6
Di6
WOUT
VNO
VNO(NC)
CIN
VNC
GND
N
CFO
CFO
CIN
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only)
(With the external shunt resistance and CR connection)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF state.
a7. Input “H” : IGBT ON state, but during the FO active signal period the IGBT doesn’t turn ON.
a8. IGBT OFF state.
Lower-arms control
input
a6 a7
Protection circuit state
SET
Internal IGBT gate
RESET
a3
a2
a1
SC
a4
Output current Ic
a8
SC reference voltage
Sense voltage of the
shunt resistance
CR circuit time
constant DELAY
Error output Fo
a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
Control supply voltage VD
RESET
UVDr
b1
SET
UVDt
b2
RESET
b6
b3
b4
b7
Output current Ic
Error output Fo
b5
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state
RESET
RESET
SET
UVDBr
Control supply voltage VDB
c1
UVDBt
c2
c5
c3
c4
c6
Output current Ic
High-level (no fault output)
Error output Fo
Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT
5V line
DIP-IPM
10kΩ
UP,VP,WP,UN,VN,WN
CPU
2.5kΩ (min)
Fo
VNC(Logic)
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
Fig. 7 RECOMMENDED WIRING OF SHUNT RESISTANCE
Wiring inductance should be less than 10nH.
DIP-IPM
width=3mm, thickness=100µm, length=17mm
in copper pattern (rough standard)
Shunt resistor
VNC
N
Please make the connection point
as close as possible to the terminal
of shunt resistor.
Jul. 2003
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21564
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1:Tight tolerance temp-compensated electrolytic type
C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)
C2
VUFB
C1
VUFS
DIP-IPM
P
HVIC1
VP1
C3
UP
C2
VVFB
C1
VVFS
VP1
C3
VCC
VB
IN
HO
COM
VS
U
HVIC2
VCC
VB
IN
HO
COM
VS
VP
C2
C1
M
VWFS
HVIC3
VP1
CPU UNIT
C3
V
VWFB
VCC
VB
IN
HO
WP
COM
W
VS
LVIC
UOUT
VN1
VCC
C3
5V line
VOUT
UN
VN
WN
Fo
UN
VN
WOUT
Too long wiring here might
cause short-circuit.
WN
Fo
VNO
CIN
VNC
GND
N
CFO
C
CIN
CFO
C4(CFO )
15V line
A
Long GND wiring here might generate
noise to input and cause IGBT
malfunction.
B
C5
R1
Shunt
Resistance
If this wiring is too long, the SC level
fluctuation might be larger and cause
SC malfunction.
N1
Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm)
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
10kΩ resistor.
4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF → tFO
= 1.8 ms (typ.))
5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when
using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
6 : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible.
7 : Please set the R1C5 time constant in the range 1.5~2µs.
8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended.
Jul. 2003