ESD Protection in Nanometer
CMOS Process
Prof. Shurong Dong
Zhejiang University
dongshurong@zju.edu.cn
Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
2014-6-20
EDSSC 2014 Chengdu
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Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
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1、Introduction
 ESD destroy is main way of IC failure
 With the processing developing, ESD is becoming serious problem!
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1、Introduction
 ESD happens in anytime and any stage! So ESD protection should
be in IC whole lifetime.
 Two ways to implement ESD protection according to different stages！
IC Fabrication
in Fab
IC mount on
PCB board
On-Chip ESD protection, such as GGNMOS
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Custom using
Produce with IC
On-board ESD Protection,
such as TVS
5
1、Introduction
So， How to designed ESD protection ：
（1）Transparent during IC working normally；
（2）During ESD happening，ESD protection circuit should：
 Form a low resistance way by pass ESD current stress, so as to
avoid ESD current stress flow into IC internal.
 Clamp ESD voltage stress in some range to avoid overshoot！
1、Introduction
How ESD stress damage IC?
（1）Current stress:
For Example:
2KV HBM stress produce 0.91uJ heat, it can increase 160*1.2*5um MOS
temperature to 2470℃, compared with Si melting Point 1415℃， Al’s
660℃!
Typical Failure: D-S silicon filament or metal interconnect melt due to joule heating
1、Introduction
How ESD stress damage IC?
（2）Voltage stress:
For example:
Gate Oxide breakdown field E is 8-10 MV/cm. As to 0.18um/1.8V RF CMOS
processing，its Gate Oxide breakdown voltage is below 4-5V，
compared with human body recognized ESD voltage 3500V
Typical Failure: gate oxide films breakdown
1、Introduction
 ESD happen at every way, direction, place and time!
 ESD should be designed carefully : robustness, Bi-direction,
high open speed …
1、Introduction
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Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
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1、Introduction
 For Example: most of ESD destroy in 40nm process is gate
breakdown
HBM ESD Failure
MM ESD Failure
CDM ESD Failure
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1、Introduction
Key(1): Gate breakdown voltage（BV） decreased with the
process developing
 BV decreased with its gate
thinner;
 BV decreased with the channel
length shrink;
 BV is lowest when the gate
area and channel length meet
the smallest of design ruler;
Data from ESD Lab of Zhejiang University
2008-9-23
http://esd.iclab.cn
1、Introduction
Key(2): With the process development, voltage drop on the interconnect
increased while IC working voltage drop. So The rate of drop of
interconnect become obvious!
Vi/o= Iesd * (Ron + Rvdd + Rvss + Rpc)+Vpc+Von
Rmetal =
ρL
WT
Metal L
DC Rdc
Voltage drop
under 2KV HBM
Rate/40nm
I/O 2.5V
Rate/28nm
I/O1.8V
50um
0.91Ω
0.18V
6%
8.3%
100um
1.83Ω
0.37V
14.8%
20.5%
300um
1.83Ω
1.11 V
44.4%
61.7%
Data from ESD Lab of Zhejiang University
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1、Introduction
Key(3): ESD design windows shrinks obviously!
 Especially, ESD devices clamp voltage under avalanche breakdown
working state.
Data from TI
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1、Introduction
ESD design wondows in Foundry
Current
2.2V
0
20%
Safty Margin
10.5V
40nm IO ESD Window
28nm IO
ESD Window
7.4V
20%
Safty Margin
2
4
6
8
Voltage (V)
5V
1.3V
20%
Safty Margin
28nm Core
ESD Window
Current
20%
Safty Margin
3V
10
12
14
0
2
4
Voltage (V)
20%
Safty Margin
6
40nm Process and 28nm Process ESD design windows
Data from ESD Lab of Zhejiang University
2008-9-23
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Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
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2.1 、Diode for ESD
Anode
Cathode
 Diode is always used in low voltage
IC ESD protection
L
STI
N+
STI
P+
STI
N-Well
P-Sub
Leakage (A)
 Diode has low trigger voltage (0.7V),
some leakage and turn-on resistance
1e-131e-121e-111e-10 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3 1e-2
1.4
1.2
 Gate diode can improve its turn-on
uniform
Current (A)
1.0
0.8
0.6
STI Diode
Gate Diode
0.4
0.2
0.0
0.0
Data from ESD Lab of Zhejiang University
2008-9-23
http://esd.iclab.cn
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Voltage (V)
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2.1 、Diode for ESD
Different kind of Gate diode TLP curves
Leakage (A)
1e-10 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3 1e-2 1e-1 1e+0
1.0
GDA
Anode
GDB
Cathode
N+
Cathode
P+
STI
STI
N+
Anode
GDC
Poly
Poly
0.8
Poly
P+
STI
STI
N+
P+
N-Well
N-Well
N-Well
P-Sub
P-Sub
P-Sub
STI
0.6
GDA
GDB
GDC
0.4
0.2
0.0
0.0
1e-8
GDD
Cathode
Anode
Cathode
STI
N+
P+
STI
STI
N+
P+
P-Well
P-Well
P-Sub
P-Sub
STI
1e-5
1e-4
1e-3
4.0
0.6
GDD
GDE
0.4
0.2
Data from ESD Lab of Zhejiang University
2008-9-23
1e-6
2.0
2.5
3.0
3.5
Voltage (V)
1e-2 1e-1 1e+0
0.8
Poly
Poly
1e-7
0.5
1.0
1.5
Leakage (A)
1.0
Anode
GDE
Curent (A)
STI
Anode
Current (A)
Cathode
0.0
0.0
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0.5
1.0
1.5
2.0
2.5
Voltage (V)
3.0
3.5
4.0
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4.5
2.1 、Diode for ESD
Anode
GND
Cathode
Ie1
Anode
Q1
 Diodes in series can meet
different voltage demand.
P+
N+
P+
NW
Q3
N+
NW
P+
Q2
N+
NW
P+
Q1
Q1
Cathode
Ib3
Q1
P-Sub
 Owing to Darlington effect, the
leakage will increase and
voltage increasing will be
weaken with the number of
Diodes in series.
 It can be improved by
retrograde well process
Data from ESD Lab of Zhejiang University
2008-9-23
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Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
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2.2、GGNMOS for ESD

GGNMOS is widely applied in IC ESD protection owing to its simple
structure!

GGNMOS key structure parameters: channel width (W), channel length (L), drain
contact to ploy (DCP) and source contact to ploy (SCP)
Cathode
Anode
N+
N+
P+
P-SUB
L
W
DCP
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SCP
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2.2、GGNMOS for ESD
TLP results of GGNMOS in 65nm CMOS process with different W & L
Data from ESD Lab of Zhejiang University
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2.2、GGNMOS for ESD
Design ruler : (different from deep-sub-micro process ESD protection)
 The key of the 40nm process ESD are very narrow ESD window and low BV
of thin oxide thickness. The W, effected on trigger voltage and holding voltage,
should be mainly consider. L is no longer the main factor to affect the failure
current.
 90nm and 65nm process: the W mainly effect on the uniformity of current.
Small L will achieve an excellent failure current, while it also has low holding
voltage. Setting L should be trade off.
 DCP increasing will improve current uniformity so as to increase It2, because
of DCP as a ballast resistor. The best DCP for ESD protection is different under
different process. SCP is minor compared to DCP
 Both DCP & SCP have a little effect on the trigger voltage and holding voltage.
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2.2、GGNMOS for ESD
 GGNMOS can be used in 90nm &65nm, even 45nm process, but it totally can
not be used in 28nm process owing to its very high trigger and bad clamp ability!
1.6
40nm GGNMOS
28nm GGNMOS
1.4
1.2
0.018
) (
1.0
0.015
0.8
0.009
0.6
0.003
0.012
0.006
0.000
4
5
6
7
8
9
0.4
Zoom in
0.2
0.0
-2
0
2
4
6
Voltage (A)
8
10
TLP results of GGNMOS in 40&28nm CMOS
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2.2、GGNMOS for ESD
Two kinds of modified GGNMOS for low trigger
RVDD
VDD
I/O PAD
PMOS
Main
NMOS
RVDD
Core
Circuit
Power
Clamp
Rsub
RVSS
I/O PAD
VSS
SAB
P+
N+
N+
Poly
N_Well P_Well
Rsub
P+
N+
N+
VDD
Poly
N+
Itri
Itri
P_Sub
(a)
RVSS
N+
N_Well
P+
P+
Poly
P+
N+
N_Well
(b)
Rsub
Substrate R and I trigger GGNMOS
Substrate R trigger GGNMOS
S. Dong, etl, Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process, Microelectronics Reliability, Volume 51,
Issue 12, December 2011, Pages 2124-2128.
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2.2、GGNMOS for ESD
(1)Substrate-engineered GGNMOS for low trigger
Substrate R and I trigger GGNMOS
Substrate R trigger GGNMOS
It2(A)
Vt1(V)
C(pF)
It2/area
(mA/um2)
GGNMOS
2.13
6.84
0.652
2.5
Substrate R trigger GGNMOS
2.07
5.3
0.788
2.17
Substrate R and I trigger GGNMOS
2.63
3
0.891
2.33
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Outline
1、Introduction
1.1 、Overview of ESD protection
1.2 、ESD protection in Nanometer Process
2、ESD Protection in Nanometer Process
2.1 、Diode
2.2 、Gate-Ground NMOS (GGNMOS)
2.3、Silicon controlled Rectifier (SCR)
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2.3、SCR for ESD
 SCR is a excellent choice for 40&28 nm process ESD protection.
Cathode
P+
STI
STI
Anode
N+
STI
N+
STI
QP
QN
P-Well
P+
STI
RN-Well
RP-Well
N-Well
P-Sub
Leakage (A)
1e-131e-121e-111e-10 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3 1e-2
1.0
28nm Normal SCR
Current (A)
0.8
0.6
0.4
0.2
0.0
0
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4
6
Voltage (V)
8
10
12
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2.3、SCR for ESD
 SCR triggered by diode (DTSCR) has a lower trigger voltage
Cathode
P+
N+
Cathode
Anode
N+
P+
N+
N+
NW
N+
P+
NW
N+
P+
P+
PW
NW
P-Sub
Leakage (A)
1e-131e-121e-111e-10 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 1e-3 1e-2
1e-7
1.6
1.0
1e-6
1e-5
1e-4
1e-3
0.10
1.0
0.6
0.08
0.8
0.4
0.06
0.6
0.04
0.4
0.2
0.02
0.2
0.0
2
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6
Voltage (V)
8
10
1e-1
TD-DTSCR
1.2
0
1e-2
1.4
28nm Normal SCR
0.8
Current (A)
Leakage (A)
12
Zoom in
0.00
0.0
0
1
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2
3
4
5
Voltage (V)
6
1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
7
8
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2.3、SCR for ESD
Structures
Area /μm2
Vt1 /V
It2 /A
CESD /fF
Ileak /nA
GGNMOS
17*50
7.3
2.13
652
0.9
LVTSCR
6*50
7.5
1.82
130
0.35
DTSCR
12*50
2.5
1.93
96
120
ILVTSCR
9*50
2.2
1.9
50
0.3
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2.3、SCR for ESD
 Improved LVTSCR for low trigger and low capacitance (ILVTSCR)
I/O
Anode
R_nw
trigger path
C1
C2
M1
Q2
(a)
Cathode
(b)
VSS
Anode
Gate
Cathode
P+
C1
N-well
C2
C3
C4
C2
C3 C4 C5
Rg
Cathode
(b)
VSS
Cathode
C5 Gate
N+
N+
C6
Anode
C5
N+
M1
R_sub
R_pw
(a)
C4 C5
C3
C1
R_nw
Q1
D1
Diode path
Q1
Q
2
Anode
I/O
P+
P+
P-well
P-well
P-sub
LVTSCR
N+
P+
C6 C1N-well
C4 N+
N+
C3
P-well
C2 P-Sub
(c)
N+
Nw
R_sub
P+
P-well
(c)
Improved LVTSCR (ILVTSCR)
S. Dong, "Improved Low-Voltage-Triggered SCR Structure for RF-ESD Protection," Electron Device Letters, IEEE , vol.34, no.8, pp.1050,1052, Aug. 2013.
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2.3、SCR for ESD
 Floating P+ LVTSCR for high holding voltage has two snapback
with high It2
S. Dong, “Design and Analysis of an Area-efficient High Holding Voltage ESD Protection Device,“ IEEE Transaction on Electron
Device, 2015,1
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2.3、SCR for ESD
 Improved Diode trigger SCR with two snapback meet 2V ESD
design windows
S. Dong, "Minimizing Multiple Triggering Effect in Diode-Triggered Silicon Controlled Rectifier (SCR) for ESD Protection Applications,“ IEEE Electron Device
Lett.,2012,11
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END
Thanks!
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