Laboratory Experiments Series
Experiments with
DIGITAL ICs
Volume-1
Dr Jeethendra Kumar P K
Experiments with Digital ICs
1
2
Laboratory Experiments Series
Contents
Chapter – 1: Logic Gates
1.
2.
3.
4.
5.
6.
CMOS and TTL Logic Gate Characteristics
Demorgan’s Theorems
CMOS Crystal oscillator and Frequency Division
Schmitt Trigger Using Gates
Timing Diagram Of TTLGates
Universal Gates
P-5
P-14
P-21
P-26
P-28
P-31
Chapter – 2 : Arithmetic Logic Units
7. Half, Full and Binary Adder
8. Half, Full and Binary Subtractor
9. Logic Signal of a Full Adder
P-36
P-45
P-55
Chapter – 3: Flip – Flops
10. RS and D Flip-flops using Gates
11. D & JK Flip-flops Using ICs
12. Magnitude Comparator
P-62
P-66
P-69
Chapter – 4: Registers and Counters
13. Gray Code Generator
14. Synchronous 4-bit up-down counter
15. Boolean Function Generator
16. Sequential Logic Machine
17. Shift Register
18. Ripple Counter
P-75
P-83
P-90
P-97
P-105
P-108
Chapter – 5: Multiplexers and Demultiplexers
19. Decoder
20. Digital Gain Control for Opamp
P-115
P-118
Chapter – 6: Digital to Analog Converters
21. Digital to Analog Conversion Using DAC 0808
22. Digital to Analog Conversion Using R-2R network and Opamp
P-125
P-135
Chapter – 7: Data Communications
23. Amplitude Shift Keying
24. PSK Modulation and Demodulation
25. FSK Modulation and Demodulation
26. DPSK Modulation and Demodulation
27. Pulse Code Modulation and Demodulation
28. Pulse Width Modulator
Experiments with Digital ICs
P-148
P-153
P-161
P-170
P-179
P-183
3
Laboratory Experiments Series
29. Time Deviation Multiplexing (TDM)
P-190
Chapter – 8: Memories
30. Static Ram (SRAM)
P-198
Chapter – 9: Microprocessors
31. Display Of Name Using 8085 Microprocessor Kit
32. Digital Stop Clock Using Microprocessor Kit
Experiments with Digital ICs
P-204
P-211
4
Laboratory Experiments Series
Chapter-1
Logic Gates
Experiments with Digital ICs
Laboratory Experiments Series
5
Experiment-1
CMOS AND TTL
LOGIC GATE CHARACTERISTICS
Abstract
Transfer characteristic curves of TTL and CMOS logic gates are studied using
74LS00 TTL and 74C00 CMOS ICs. The sink current, source current, noise
margins are determined. The transfer curve is displayed on CRO and compared
with manufacturer’s data.
1.1 Introduction
Logic gates are electronic circuits and building blocks of digital system. It responds to HI-LO
logic inputs. Various types of logic gates are available, which performs different logic
functions. Among them NAND and NOR gates are known as universal gates. Using these
two gates all other gates can be constructed. Depending on the internal circuit logic gates are
divided in to two groups namely,
1. Transistor Transistor Logic (TTL) family
2. Complimentary Metal Oxide Semiconductor field effect transistor (CMOS) family
CMOS is the latest and more advanced logic family. It has variety of variants. TTL family is
based on bipolar junction transistor and it is inexpensive and widely used. Among the TTL
family TTL-LS series logic gates are widely used. LS refer to Low power Schottky, named
after the Schottky diode used along with the transistor in the circuit [1].
The CMOS family consists logic circuits based on P-channel MOSFETs (PMOS) and Nchannel MOSFETs (NMOS). Because of this basic constituent difference, CMOS and TTL
logic gate characteristics differ one another. One has to make sure for what application the
gates are used and decide which gates to use. For accurate timing and precise operation,
CMOS gate is preferred [2].
Figure 1.1(a) and (b) shows basic structure of TTL and CMOS family of logic gates. Figure1.2 shows pin diagram of NAND gate. Both families have same pin configuration and it is 2input quad gate. Any one gate among the four can be used for studying characteristics.
1.2 Noise Margins
Logic gates responds to HI-LO inputs. Some times due to switching transients, power supply
noise, spikes, coupling between loads can give rise to false signal which may change the
logic states. Therefore the logic circuits have to be immune to noise signals. The noise
voltage at the input of a logic gate, which causes circuit to malfunction, is called noise
Experiments with Digital ICs
6
Laboratory Experiments Series
margins. The output can be either LO or HI hence two noise margins are defined as noise
margin with “0” output NM (0) and noise margin when the output is “1” as NM (1).
VDD
V1
PMOS
V1
Vout
Vout
NMOS
V2
V2
(a)
(b)
Figure-1.1 (a) TTL-LS series logic gate basic structure
(b)CMOS series logic gate basic structure
1
2
&
3
4
5
6
9
10
8
12
13
11
7400
Figure-1.2, Pin diagram of 7400 NAND gate
1.3 Source and sink currents
Logic gates have to drive certain load. In most of the cases, loads are similar gates or other
logic circuits or it may be transistor or a resistor. Fan-out tells the goodness of a logic gate in
delivering its output to the load. The more load it drives the higher the fan out. It depends on
the output current of the logic gate. If the gate drives N number of similar gates without
change in its output status, the fan out is N. The load current depends on the structure of
output stages of the logic gate circuit shown in Figure-1.1 (a) and (b). The current delivered
by logic gate output to a load is called source current.
Logic gate output also accepts current from other sources. This current is called sink current.
The current sink capacity of the logic gate is higher than its source capacity. Figure –1.3
shows sinking and sourcing of current by the logic gates.
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7
Laboratory Experiments Series
1
3
4
I source
6
2
5
+5V
9
8
10
12
I sink
1
11
3
13
2
(a)
(b)
Figure-3(a) Source current driving load
(b)Sink current flowing in to the gate
1.4 Transfer Characteristics
V out
Vout(HI)
Vin(LO)
The graph relating input with the output is called transfer characteristics. It can be obtained
by studying input variation. The transfer curve of a NOT gate is shown in Figure-1.4, where
10% line is the limit for LO state input and 90% is the limit for high state input [3]. In other
words all the voltages below the 10% line is called Low state input Vin(LO) and all the voltage
falling above the 90% line is called high state input Vin(HI).
90%
Vin(HI)
VTH
Vout(LO) 10%
Vin
0
100%
VTH
Figure-1.4, Transfer characteristics of a inverting gate
In between, these two input levels, there is a threshold input voltages that produce equal
output voltage and it is designated as VTH. Threshold voltage is the boundary line between
logic HI and logic LO. For TTL logic gates using 5-volt power supply, HI lies within 4.5 to 5
Volt and LO lies between 0 to 0.5Volt.
4.5V < HI < 5V
…1
0V < LO < 0.5V
…2
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8
Laboratory Experiments Series
VTH = Vin = Vout
…3
For proper operation of the logic gates, the noise voltages should be well below the following
limits.
Vin(LO) + Noise < VTH
…4
Vin(HI) - Noise > VTH
…5
Hence the noise margin voltages are defined as
NM(1) = Vin(LO) max - VTH
…6
NM(0) = VTH - Vin(HI) min
…7
Where
Vin(LO) max is the maximum value of input that produce HI state output
Vin(HI) min is the minimum HI state input that produce LO state output.
Noise margin voltage is the maximum voltage that can be impressed upon an input voltage
Vin at any logic input or output terminals without upsetting the logic or causing any output to
exceed the output voltage conditions specified for HI state and LO state input.
In this experiment transfer characteristics of 74LS00 and 74C00 logic gates are drawn and the
noise margins sink current, source currents are determined.
1.5 Instruments used
Dc regulated power supply 5V/0.5A, digital dc milli ammeter 0-200mA, digital dc micro
ammeter 0-2000µA, rheostat 0-100Ω and digital dc voltmeter
1.6 Components Used
ICs 74LS00, 74C00, resistors 220,330,470,560,680,1K, 2.2K, 3.3K, 4.7K, 5.6K, 10K Ohms,
Solder less breadboard.
1.7 Experimental Procedure
The experiment consists of three parts namely,
Part A,
Transfer characteristics and noise margin determination
Part B,
Determination of sink current
Part C,
Determination of source current
Part A, Transfer characteristics and noise margin determination
Experiments with Digital ICs
9
Laboratory Experiments Series
Rehostat
100 Ohms
14
1
3
5V
2
7400
V
Vin
7
V
Vout
Figure-1.5: Transfer characteristics circuit connections
1. The circuit connections are made as shown in Figure-1.5 using 74LS00 IC. Input voltage
is set to zero volt by adjusting the rheostat (or a potentiometer) and the output voltage is
noted in Table-1.1.
2. Trial is repeated by varying input in steps of 0.2volts up to a maximum of 5 volts. The
corresponding output is noted in Table-1.1.
3. A graph is drawn taking input along X-axis and output along Y-axis as shown in Figure1.6. From the graph threshold voltage, Vth, Vin(LO) Vin(HI) are noted.
Vth = 1.35V
Vin(LO)max = 0.6V
Vin(HI)min = 2.6V
4. Experiment is repeated using 74C00 IC. The corresponding readings are tabulated in
Table-1.1 and input variation is plotted in Figure-1.6. Vth, Vin(LO)max Vin(HI)min are noted
from the graph.
Table-1.1
Output (V)
Input
(V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.25
1.28
1.30
1.4
1.5
1.6
1.8
1.85
1.9
Output (V)
Input
(V)
74LS00
74C00
74LS00
4.56
5.02
2.0
4.98
4.70
5.02
2.2
4.93
4.77
5.02
2.4
4.83
4.74
5.02
2.5
4.75
4.10
5.02
2.6
4.56
3.78
5.02
2.65
3.25
2.77
5.02
2..66
2.84
2.30
5.02
2.68
1.27
0.46
5.02
2.7
0.68
0.40
5.02
2.8
0.26
0.11
5.02
3.0
0.11
0.10
5.02
3.5
0
0.10
5.02
4.0
0
0.10
5.00
4.5
0
0.10
4.99
4.9
0
0.10
4.99
5.0
0
Variation of input and output voltages
Experiments with Digital ICs
74C00
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
10
Laboratory Experiments Series
Vth = 2.5
Vin(LO)max = 1.9V Vin(HI0min = 2.0V
Noise margins are calculated for both the ICs.
NM(O)LS00 = 1.35-0.6 = 0.76V
NM(1) LS00= 2.6 – 1.35 = 1.25V
NM(O)C00 = 2.5-1.9 = 0.6V
NM(1)C00 = 2.0-2.5 = -0.5V
74LS00
74C00
Output (V)
5
4
3
2
1
0
0
1
2
3
4
5
Input (V)
Figure-1.6: Transfer characteristics of 74LS00 and 74C00 NAND inverter
Part B, Determination of sink current
+5V
R
14
0-200mA
1
3
2
7400
7
Figure-1.7, Circuit connections for sink current determination
5. The circuit connections are made as shown in Figure-1.7 using LS00. Resistance R is set
to 1KΩ. The inputs of the gates are tied to HI. In this mode maximum current flows in to
the output of the logic gate because of low output. The current flowing is noted in Table1.2.
Experiments with Digital ICs
11
Laboratory Experiments Series
6. Trial is repeated by varying resistance up to 220Ω. Below this value of resistance the
logic output goes above 0.5Volts hence logic status is disturbed. The current flowing in
the milliammeter is noted in Table-1.2.
7. Experiment is repeated with 74C00 IC and corresponding resistance and current are noted
in Table-1.2.
8. A graph is drawn taking R along X-axis and current along Y-axis as shown in Figures
1.8(a) and 1.8(b). The curves are extrapolated to intercept the Y-axis. At this point R=0.
Hence, it is the maximum current that can flow in to the logic gate or it is the sink current.
Isink(LS00) = 34mA
Isink(C00) = 2.5mA
Source Current (mA)
Source Current (mA)
(a) : Load Variation in 74LS00
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
(b) : Load Variation in 74C00
3
2
1
0
0
5
10
15
Resistance (K Ohms)
Resistance (K Ohms)
(a)
(b)
Figure-1.8 (a) and (b), Load variations in 74LS00 and 74C00
Table-1.2
74LS00
74C00
Isink(LS00)
Isink(C00)
R(KΩ
Ω)
R(KΩ
Ω)
1.00
5.0
10
0.5
0.75
6.5
6.8
0.7
0.56
8.5
5.6
0.8
0.47
10.0
4.7
1.0
0.33
14.0
2.7
1.8
0.22
21.0
Load variation in 74LS00 and 74C00
Part C, Determination of source current
9. The circuit connections are made as shown in Figure-1.9 with 74LS00 IC. The input is
varied from LO to HI and the steady state current in the micro ammeter is noted. This is
current flowing from the output of gate-1 to input of gate-2. Hence, it is the source
current.
Isource(LS00) = 240 µA
10. Experiment is repeated using 74C00 IC.
Experiments with Digital ICs
12
Laboratory Experiments Series
Isource(LS00) = 0
In the case of 74C00, the source is found zero in micro ammeter. This is because of the
very high input resistance of MOS device.
+5V
14
0-2000 micro
1
4
3
6
2
Rheostat
5
7400
100 Ohms
7400
7
Figure-1.9, Circuit connections for source current determination
+12V
1.8K
4
5
8038
3
6
7
8
4.7K
11
10
TO CRO
Channel-A
10K
+5V
BC547
14
1
3
12
2
0.1
560
7400
100K
-12V
TO CRO
Channel-B
7
+12V
PT1-10K
Figure-1.10, Saw tooth generator feeding NAND inverter
(a)
(b)
Figure-1.11 (a) Transfer curve of 74LS00 (b) Transfer curve of 74C00
The transfer curve also can be plotted on a CRO screen. Feeding the inverter in Figure-1.5,
by a time varying ramp signal, does this. Figure-1.10 shows function generator used in
displaying transfer curve on CRO screen. The circuit consists 8038 function generator IC
producing saw tooth wave. The saw tooth waveform is current amplified by the transistor
BC547 and fed to the input of the gate. With CRO in the external position the output of the
gate is fed to the channel B of the CRO and saw tooth waveform is fed to the A channel. The
Experiments with Digital ICs
Laboratory Experiments Series
13
transfer curve obtained is shown in Figure-1.11 for both the gates. By varying the pot PT1
one can actually plot the curve on the CRO starting from lower end of the curve.
1.8 Results
The results obtained are tabulated in Table-1.3
Table-1.3
Parameters
74LS00
74C00
VTH(V)
1.35
2.5
NM(0) Volts
0.76
0.6
NM(1) Volts
1.25
-0.5
Isink (mA)
34
2.5
240
0
Isource(µA)
Characteristic parameters of LS00 and C00 Logic gates
1.9 Discussions
Looking at the characteristics curves in Figures in 1.6 and 1.11, there is a difference between
TTL LS and CMOS IC characteristics. CMOS IC has perfect characteristics with exactly
1/2Vcc as threshold voltage. The threshold voltage in the case of TTL IC is unsymmetrical
and equals to ≈ 1/3 Vcc. When gates are used in noisy surrounding, it is better to use high
threshold CMOS ICs. Similar characteristic curves can be plotted for any gates. The sink
current and source currents are important for circuit design. Higher the noise margin better is
the gate. Only merit of TTL is its large (>10 times) sink capacity that makes it better driver.
The low noise margin voltages are not a concern for CMOS because of its high threshold
voltage.
References
[1]
Malvino A P and Brown J A, Digital Computer Electronics, 3 rd Edn, 1993, Page-50.
[2]
Jeethendra Kumar P K, CMOS crystal oscillator and frequency division, LE Vol-2,
N0-1, June-2002, Page 60.
[3]
Harris Semiconductor, CMOS Logic Selection Guide 1994, Page 5-5
Experiments with Digital ICs
14
Laboratory Experiments Series
Experiment-2
DE MORGAN′′S THEOREMS
Abstract
De Morgan’s theorems are verified using HI-LO digital input and square wave
input. The logic circuits are implemented using TTL gates. The experiment
introduces a new method of studying logic gates using ac signal. The timing
diagrams are recorded.
5.1
Introduction
De Morgan proposed two theorems before the invention of logic circuits. When logic gates
were introduced these theorems are used to simplify logic equations. In algebra 1/6 is the
inversion of 6 and 1/A is the inversion of A. In Boolean algebraA is the inversion of A. It is
also called as the compliment of A. For example if A = logic HI then A is logic LO. This
inversion is performed by NOT logic gate. De Morgan’s theorem applies only to logic
circuits. The theorem is based on three terms namely
1. SUM
2. PRODUCT
3. COMPLIMENT
In logics the SUM is equivalent of addition. If A and B are two bits then the SUM is
represented as
SUM = A+B
…1
Their product is given by
PRODUCT = AB
…2
These two logics are performed by an OR gate and AND gates respectively. De Morgan’s
stated in his first theorem [1] that,
The compliment of the SUM is equal to the PRODUCT of compliments. In the form of logic
equation it is written as
(A+B) = A B
…3
The two words SUM and PRODUCT are interchangeable in the above theorem. By
interchanging these two words the second theorem is obtained which states that
The compliment of the PRODUCT is equal to the SUM of compliments. In the form of
equation it is written as
Experiments with Digital ICs
15
Laboratory Experiments Series
AB = A + B
…4
To verify equations 3 and 4 logic circuits are constructed using logic gates and their function
tables are studied using dc and ac signals.
5.2
Apparatus Used
Digital IC Trainer DIC201 (KamalJeeth make) consisting of 5V power supply, Logic
monitor, Clock system 1KHz and 2KHz, Bread Board and dual trace CRO.
5.3
Components Used
IC 74LS00, 74LS04, 74LS02, 74LS08, 74LS32.
5.4
Experimental Procedure
The experiment consists of two parts
Part – A, Response to HI-LO dc input and Part-B, Response to ac input.
Part – A, Response to HI-LO DC input
1. To verify De Morgan’s first theorem circuit is rigged as shown in Figure-5.1. The left
hand side of equation-3 represents NOR operation hence 74LS02 is used.
2. Pin 14 of LS02 is connected +5V (HI) and pin 7 is connected to GND (LO).
+5V
14
A
2
B
3
7402
1
Y1
7
Figure-5.1: NOR gate
3. A & B are the two inputs connected to memory cell, A1 A0 or B1B0 or C1C0 (or HI-LO
toggle switch)
4. Output pin 1 is connected to any one of the logic monitors Q0 or Q1…or Q9.
5. Input is set to 00 in the memory cell A1A0 (0,0) and Q0 (Y1) is noted in Table-5.1.
6. Trial is repeated for all input combinations 00,01,10,11 and the corresponding out put is
noted in Table-5.1.
Experiments with Digital ICs
16
Laboratory Experiments Series
7. The RHS of equation 3 is realized using 74LS04 NOT gate and 74LS08 AND gate ICs as
shown in Figure-5.2. Pin 14 of both the ICs are connected to +5V (HI) and pin 7 is to
GND (LO).
Table-5.1
A
B
Y1
0
0
1
0
1
0
1
0
0
1
1
0
NOR Function Table
+5V
14
A
1
2
14
1
7404
2
B
3
4
7404
7408
3
Y2
7
7
Figure-5.2: Logic Implementation of Equation-3 RHS
8. Input A and B is connected to A1A0 on the memory cell. Output Y2 is monitored on logic
monitor Q0. For different input combinations 00 to 11 the output is noted and tabulated in
Table2.
Table-5.2
A
B
Y2
0
0
1
0
1
0
1
0
0
1
1
0
Function Table RHS Equation-3
9. Compare Table-1 and Table-5. 2 for the same input the out is one and the same in both
the Tables. Indicating that whatever may be the circuit the input and output remains the
same this verifies De Morgan′s first theorem
Y1=Y2 or
A+B= A B
10. To prove De Morgan’s second theorem circuit is rigged as shown in Figure-5.3 using
NAND IC 74LS00. Pin 14 is connected to HI and Pin 7 is connected to LO
Experiments with Digital ICs
17
Laboratory Experiments Series
+5V
14
A
1
B
2
3
7400
Y3
7
Figure-5.3: NAND Gate
11. A and B are connected to input A1A0 on logic memory cell and output Y3 to logic
monitor Q0.
12. For different input combinations 0,0 to 1,1 output is noted and tabulated in Table-5.3. Y3
is LHS of Equation-4.
Table-5. 3
A
B Y3
0
0
1
1
0
1
0
1
1
1
1
0
Function LHS Equation 4
13. The RHS of equation 4 is implemented using IC 74LS04 and 74LS32 as shown in Figure
4. Pin 14 of both the ICs are connected to Hi and pin 7 to LO. Input A and B are
connected to A1 A0 on memory cell and output Y4 to logic monitor Q0 For different input
combinations from 00 to 11 output Y4 is noted in Table-5.4.
+5V
14
A
1
2
14
1
7404
3
2
B
3
4
7404
7432
Y4
7
7
Figure-5.4, Logic implementation Equation- 4 RHS
14. Comparing Table 3 and Table 4 it is found that both are identical. Therefore whatever
may be the logic circuit both tables are identical. This proves De Morgan’s 2 nd theorem
Y3=Y4
AB = A +B
Table-5. 4
A
B Y4
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18
Laboratory Experiments Series
0
0
1
1
0
1
0
1
1
1
1
0
Function Table Equation-4 RHS
Part-B Response to AC input
The experimental setup DIC201 consists of 1KHz and 2KHz square waves. These are used as
AC signals to verify De Morgan’s Theorems.
15. To verify first theorem Figures-5.1 and 5.2 are combined as shown in Figure-5.5. Inputs
are set 1KHz and 2KHz square and the outputs Y1 and Y2 are monitored on the CRO
channels one and two respectively.
1KHz A
2KHZ B
2
1
Y1 CRO Channel-1
3
74LS02
1
2
74LS04
1
3
Y2 CRO Channel-2
2
74LS08
3
4
74LS04
Figure-5.5: Verification of De Morgan’s first theorem
Y1=Y2, then the waveforms on Channel 1 and Channel 2 are identical proving De Morgan’s
first theorem. The Waveforms noted is shown in Figure –5.6.
Figure-5.6: De Morgan’s first theorem verification
16. To verify second theorem Figures-5.3 and 5.4 are combined as shown in Figure-5.7.
Inputs are set 1KHz and 2KHz square and the outputs Y3 and Y4 are monitored on the
CRO channels one and two respectively.
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19
Laboratory Experiments Series
A, 1KHz
B, 2KHz
1
3
Y3 CRO Channel-1
2
74LS00
1
2
1
74LS04
3
2
3
4
Y4 CRO Channel-2
74LS32
7404
Figure-5.7: Verification of De Morgan’s second theorem
Figure-5.8: De Morgan’s second theorem verification
Y3=Y4, then the waveforms on Channel 1 and Channel 2 are identical proving De Morgan’s
second theorem. The Waveforms noted is shown in Figure –5.8.
5.5
Results
De Morgan’s theorems are verified using HI-LO dc input and ac input. The two identical
waveforms in Figures-5.6 verify 1 st theorem and two identical waveforms in Figure-5.8 verify
2nd theorem.
A + B =A B
AB = A +B
Waveforms in Figures 6 and 8 are different indicating that
AB ≠ A B
Which true in Algebra and not true in Boolean Algebra or in Logic gates.
5.6
Discussion
In actual practice of digital circuit design ac signals are involved more than dc signals.
Keeping this in mind this experiment is proved using square wave of 1KHz and 2KHz. This
method can be applied to any gate experiments.
Experiments with Digital ICs
20
Laboratory Experiments Series
The square waves 1KHz and 2KHz generate all the four combinations of HI-LO states
00,01,10,11 as shown in Figure-5.9. During the first 0.25msecs of input clock input, 11
appear at the input A and B, during the second 0.25 Seconds 01 appears, during the third 0.25
seconds 10 appears and during fourth 0.25 time 00 appears likewise it takes only 1 msec of
time to verify the theorem. The processes continue and a continuous waveform is observed in
the CRO. Figure-5. 9 explain the output waveforms Y1 and Y3.
B-2KHz
A-1KHz
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
Y1
Y3
0
1
2 milli sec
Figure-5.9, 1KHz and 2KHz signals verifying De Morgan’s theorem
Reference
1.
Malvino A P, Brown J A, Digital Computer Electronics, 3 rd Edition, TMH, 1997, Page33.
Experiments with Digital ICs
21
Laboratory Experiments Series
Experiment-3
CMOS CRYSTAL OSCILLATOR
AND FRQUENCY DIVISION
Abstract
Using quartz crystal and CMOS NAND 74C00 Inverter 10MHz-clock signal is
generated. The clock frequency is divided to obtain divide by 2, Divide by 5, divide
by 10 and divide by 100 operations using dual decade counter 74LS390.
Introduction
Clock signals are square wave signals, which give directions to the functioning of any
multiplexed system such as ADC microprocessor etc. Clock is also used in timing
applications such as to run a stop clock. All these applications require precise timing
accuracy. In such applications clock generated by crystal is used. A quartz crystal acts like
LCR circuit, which is used in the feedback network of an amplifier. The crystal provides
positive feedback signal necessary for the generation of clock. The natural quartz crystal
exhibit piezoelectric effect [1] which provide the coupling between electrical circuit and
mechanical vibrations of the crystal. Crystals cut along certain axis has fixed frequency. The
stability is obtained because of the stable LCR values.
R1 150K
1
3
2
CLOCK
74C00
33E
10MHz
R2
33pF
33pF
Figure-1 Crystal Oscillator Circuit
It is very easy to obtain higher frequency crystal in compared to lower frequency. As the
frequency decrease the size of crystal increase there by becoming more and more brittle and
hard to make. Commercially available crystals are in the MHz range. Frequency division
obtains lower frequency clock signals. The decade counter or flip-flops ICs are used to
reduce or divide the crystal frequency. Low frequency clock signals of the order of fractions
of Hz (0.01,0.1,1..) are obtained in such process.
Figure 1 shows a crystal oscillator circuit [2] using CMOS NAND gate. The crystal oscillates
at its fundamental frequency. The mechanical vibration of the crystal is converted in to
Experiments with Digital ICs
22
Laboratory Experiments Series
electrical fluctuations resulting in oscillation. Resistor R2 is used to prevent spurious
oscillation mode.
Frequency Division
Frequency division is obtained using flip-flops or decade counter ICs. Flip-flops are divide by
2, divide 4 etc ICs. Divide by 2, divide by 5, divide by 10 or divide by 100 is obtained using
dual decade counter IC TTL IC 74LS390 [3]. Figure-2 shows its pin diagram. Using one IC
divide 100 operations is obtained. The IC has two independent decade counters each with
section A and B. Section A performs divide by 2 operation and section B performs divide by
5 operation. Combining section A and Section B divide by 10 operation is obtained.
2
1CKA
1
16
VCC
1CLR
2CKA
1QA
2CLR
1CKB
4
+
+
CTR
DIV2
DIV5
3
{
CT
2QA
1QB
74LS390
2CKB
1QC
2QB
1QD
2QC
GND
1
CT=0
8
9
14
15
2QD
12
CT=0
+
+
5
0 6
7
2
CTR
DIV2
DIV5
13
{
CT
11
0 10
9
2
74LS390
Figure-2, Pin diagrams of dual decade counter 74LS390
Divide by 2 operations
To obtain divide by 2 operation only section A is used as shown in Figure-3. The clock input
is fed to pin-1 (1CKA) and output is available at pin-3 (1QA)
+5V
Input
1CKA
Frequency
Fi
16
1
3
1QA
Y2
74LS390
8
2
Figure-3 Divide 2 Operations
Divide 5 Operations
Experiments with Digital ICs
Laboratory Experiments Series
23
This is obtained by using only the section B. Clock is fed to 1CKB (pin-4) and output is
available at pin 7 (1QD) as shown in Figure-4.
+5V
16
Input
Frequency
Fi
1CKB
4
1QD
7
Y5
74LS390
8
2
Figure-4, Divide by 5 Operations
Divide by 10 Operations
To get divide by 10 operation section A and B are combined as shown in Figure-5. The 1QA
output now becomes clock input to section B (1CKB) and divide 10 output is available at
1QD (Pin 7).
+5V
Input
1CKA
Frequency
Fi
1
16
3
1QA
4
1CKB
4 74LS390
7
8
1QD
Y10
2
Figure-5, Divide by 10 Operations
Divide by 100 Operations
Divide 100 operation is obtained by combining both the parts of LS390. Each part results in
10X10=100 divisions as shown in Figure-6. Clock is given to 1CKA. The Output 1QA
becomes the clock to 1CKB. And 1QD becomes the clock to 2CKA and finally 2QA
becomes the clock to 2CKB and the final divide by 10 output is available at 2QD as shown in
Figure 6. This is remembered as ″A clock (CKA) is energized by D output (QD) and B clock
(CKB) is energized by A output (QA)″.
Experiments with Digital ICs
24
Laboratory Experiments Series
+5V
Input
1CKA
Frequency
Fi
1
16
12
13
3
1QA
4
1CKB
LS390
7
9
15
8
14
2QD
Y100
2
Figure-6 Divide by 100 Operations
Apparatus Used
Digital IC Trainer DIC201 consisting of +15V and +5V power supply, bread board, digital
frequency counter and CRO
Components Used
CMOS NAND gate 74C00, TTL decade counter 74LS390, resistors 150K, 33Ω, ceramic
capacitor 33pF, quartz crystal 10MHz.
Experimental Procedure
The experiment consists of two parts. Part-A, Crystal clock generation, Part-B frequency
division
Part-A, Crystal clock generation
1. The crystal oscillator circuit is rigged as shown in Figure-1.
2. The pin 14 of 74C00 is connected to +15V and pin 7 to GND.
3. The output is monitored on CRO channel-1. The output waveform is observed and its
frequency is measured using digital frequency counter. Figure-7 shows 10MHz-clock
signal. And 150KHz signals.
Figure-7, 10MHz clock signal and 100KHz signal
Experiments with Digital ICs
Laboratory Experiments Series
25
Part-B, Frequency division
4.
Experiment is repeated by observing waveforms at pin number 3 (divide 2), pin number 7
(divide by 5), pin 13 for (divide 10) and at pin 9 (divide 100) signals are obtained.
5.
Taking pin 2(1CLR) and 14 (2CLR) to +5V the counter is disabled hence the out
disappeared. For enabling the counter the CLR signals is held LO.
Results
1.
The frequency of the clock generated by crystal oscillator is =10MHz
2.
The dual decade counter is enabled with LO CLR and disabled with HI CLR.
3.
Various signals observed indicate very accurate division.
Discussions
1.
Frequency division is used when clock of low frequency is required. Using LS390 it is
possible to get divide by 2,5,10,20,50,100,200,500,1000 etc. 1Hz and 0.1 Hz signals
obtained from such frequency division are used in digital stop clock.
2.
The 10MHz output observed is not a square wave. It is a sine output. A Schmidt trigger is
used to reshape it to square. This can be done using CMOS Schmidt trigger 74HCT14 or
74HC14 [4]
References
1.
Tayal D C, Electricity and Electronics, Himalaya Publishing House, 1985, Page 152.
2.
Web: www.getradar.com
3.
TTL logic, standard, TTL, Schottky, Low Power Schottky, 1988, Texas Instruments,
Page-2-919
4.
CMOS Logic Selection Guide – Harris,1994 , Page
Experiments with Digital ICs
26
Laboratory Experiments Series
Experiment-4
SCHMITT TRIGGER USING GATES
Aim of the Experiment
To construct a Schmitt Trigger circuit using NAND gates and to study the variation of
Hysteresis and to sketch the wave forms
Apparatus Used
Digital IC trainer DIC 203, CRO, Oscillator
Introduction
A Schmitt trigger (ST) has two stable states and belong to the bistable family. ST can be
constructed using transistors, Opamp or using gates. It is used to convert a periodic signal in
to a rectangular signal. It is also known as a voltage comparator or amplitude sensitive
circuit. Figure-1, shows a ST tied using TTL NAND gates. In digital circuits ST is used to
convert a slow changing wave form in to a fast changing wave form. At present ST ICs are
available in market with 4 inputs (7413), with two inputs (74132) and single input (7414).
Ina ST the output will be either LOW (0) or HIGH (1). The change in the states take place a
voltage known as threshold voltage. If the output is low and the input is increasing the level
of out then changes at threshold voltage known as Upper Threshold Point. When the output is
high and the input is decreasing then the change in output level takes place at voltage known
as Lower threshold point. The difference between upper threshold point (UTP) and lower
threshold point (LTP) voltage is known as Hysteresis. ST ICs have H varying from 0.9 to 1.7
volts.
Using gates H can be varied using a potentiometer in place of R4 in Figure-1.
Experimental Procedure
1.
2.
3.
4.
A ST circuit is constructed as shown in Figure-1
A ST variable supply is connected to the input and the voltage is set to 0 Volts.
The out is noted using digital voltmeter and recorded in table-1
Input is increased in steps of 0.5Volt and the corresponding output is noted in Table-1
Figure-1:
R4= 820 ohms
Table-1
Increasing
Decreasing
Vin(Volts)
Vout(Volts)
Vin(Volts) Vout(Volts)
0
0.7
5.0
4.2
Experiments with Digital ICs
27
Laboratory Experiments Series
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.7
0.7
0.7
0.7
4.2
4.2
4.2
4.2
4.2
4.2
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.2
4.2
4.2
4.2
4.2
0.7
0.7
0.7
0.7
5. Input is increased up to a maximum of 5Volts
6. Now the input is decreased in steps of 0.5Volt till 0 Volts and the corresponding output is
noted and recorded in Table-1
7. A graph is drawn taking input along X-axis and output along Y-axis. The graph is shown
in figure-2
8. From the graph hysteresis is calculated.
9. A sine wave oscillator is now connected to the input in place of DC source. Frequency is
adjusted to 1KHz and amplitude 5V.
10. Both the input and outputs are monitored on the CRO screen and the wave forms are
recorded.
11. Experiment is repeated for different values of R4
Results
R4
820
1000
UTP (V)
2.5
3.0
LTP(V)
2.0
1.5
Hysteresis (V)
0.5
1.5
Note:
Any other wave form such as half wave, full wave, interacted, differentiated, triangle input
can be fed to the input instead of sine wave and the corresponding out put can be recorded.
It is possible to display the Hysteresis curve on the CRO screen by feeding input to Y and
output to the X input of the CRO.
Experiments with Digital ICs
28
Laboratory Experiments Series
Experiment-5
TIMING DIAGRAM OF TTL GATES
Abstract
Timing diagrams of TTL NAND, NOR, AND and OR gates studied using 1K, 1K
inverted, 2K signal. The logic truth tables are deducted from the timing diagram.
The maximum and minimum duty cycles are determined using CRO and digital IC
applications experimental setup.
Introduction
Verification of logic truth table using HI-LO DC inputs are very common, however in
digital applications gates are used to control AC signals. A sketch of output wave in
comparison with input signal is known as timing diagram. Using 1KHz, 1KHz inverted
and 2KHz signals as inputs to 7400 NAND, 7402 NOR, 7408 AND, 7402 OR gates are
studied.
From the timing diagram truth tables the DC level read and the corresponding truth tables
are generated and compared with the standard truth table.
Figure-1: Pin diagrams
Figure-2: NAND Gate Timing Diagram
Experimental Procedure
Figure-1 shows pin diagrams various TTL gates. Out of the four gates any one is selected
for the study of timing diagram.
1. The two inputs (pin-1) is fed with 1K and (pin-2) with 1K inverted in the 7400
NAND gate and the output at pin-3 in monitored on CRO screen. The output
is compared with the input wave form and sketched on a graph sheet.
2. One of the inputs is now changed to 2KHz and output is sketched in
comparison with the input.
3. The graph in shown in Figure-2.
4. The experiment is repeated for 7402, 7408, 7432 IC and the corresponding
timing diagrams are recorded in Figures-3,4,5 respectively.
5. From the truth table logic table is constructed by reading corresponding input
and output level.
6. The table generated are shown in tables-1,2,3 and 4 respectively for NAND,
NOR, OR and AND gates.
Experiments with Digital ICs
Laboratory Experiments Series
Figure-3: NOR Gate Timing Diagram
Figure-4: OR Gate Timing Diagram
Figure-5: AND Gate Timing Diagram
Table-1
INPUTS
OUTPUTS
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
NAND 7400
Table-2
INPUTS
OUTPUTS
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
AND 7408
Table-3
INPUTS
OUTPUTS
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
NOR
Experiments with Digital ICs
29
30
Laboratory Experiments Series
Table-4
INPUTS
OUTPUTS
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
OR
Results
1. With two signals 1K and 2K four sets of digital inputs 00, 01, 10, 11 is
generated as shown in Figure-2
2. From the timing diagram logic truth tables constructed reading corresponding
DC levels as shown in Figure-2 and Figure-3. The truth tables are compared
with standard truth table.
3. The lowest output frequency in equals to lower frequency (1KHz) among the
two signals.
4. The duty cycle of the output is different in different gate. Therefore basic gates
can convert a square wave in to a rectangular pulse with duty cycle varying
from 25% to 75%.
Note: Duty cycle D = Pulse Width/ Period
D = W/T
For NAND gate D = 0.75 msec/1msec = 75%
For NOR gate
D = 0.25 msec/1msec = 25%
Experiments with Digital ICs
Laboratory Experiments Series
31
Experiment-6
UNIVERSAL GATES
Abstract
NAND and NOR gates are known as universal gates. Using these two gates other
logic gates can be constructed. In this experiment NOT, OR, AND, and XOR gates
are constructed using 7400 quad NAND gate and 7402 quad NOR gates. Boolean
equations are made use in providing a theoretical background and it is compared
with the truth table. After the experiment the student must be in a position to
identify the advantages of using 7400 and 7402 in the construction of other logic
gates.
Introduction
In the TTL family of digital ICs 7400 is a quad 2-input NAND gate and 7402 is a quad 2input NOR gate in DIP package. Figure-1 shows the pin configurations of 7400 & 7402.
Figure-1: Pin Configuration of 7400 & 7402
NOT Operation
In Figure-2 NAND & NOR gates are tied to perform NOT operation.
Figure-2: NOT operation using NAND & NOR
The Boolean equation governing the operation is given by
Y = AB for NAND gate and
Y = A + B for NOR gate
Since A=B
Y = AA = A + A = A and Y = A + A = A
This is the basic NOT operation.
AND Operation
In Figure-3 AND gate is constructed using NAND and NOR gates
Figure-3: AND Gates using NAND & NOR
The Boolean equation representing above operation is given by
Experiments with Digital ICs
32
Laboratory Experiments Series
Y = AB = AB is case of NAND and
Y = A + B = A⋅B = A⋅B
is case of NOR gate.
OR Operation
Figure-4 shows the construction of OR gate using NAND and NOR gates.
Figure-4: OR operation using NAND & NOR gates
In above Figure-4, Y output from the NAND is given by
Y = A⋅B = A + B = A + B
for NOR gate
Y = A+B= A+B
This verifies or operation.
XOR Operation
In Figure-5 NAND and NOR are tied to for XOR logic
Figure-5: XOR operation using NAND & NOR gates
In the case NAND gate
Y1 = AB
Y 2 = A ⋅ Y1
Y3 = B ⋅ Y1
Y 2 = A ⋅ Y1 = A ⋅ AB = A + AB = A + AB
Y3 = B ⋅ Y1 = B ⋅ AB = B + AB = B + AB
Y = Y 2Y 3
= Y 2 + Y3
= (A + AB) + (B + AB)
= A ⋅ AB + B ⋅ AB
= A ⋅ AB + B ⋅ AB
Experiments with Digital ICs
Y = Y 2Y 3
33
Laboratory Experiments Series
= A AB + BBA
Y = A B + BA
In case of NOR gate
Y1 = A + B
Y 2 = A + Y1
Y3 = B + Y1
Y 4 = Y 2 + Y3
Y = Y4
(
)
(
)
Y 2 = A + Y1 = A + A + B + A ⋅ (A + B) = A ⋅(A + B) = AA + AB
Y 2 = AB
Y3 = B + Y1 = B + A + B + B ⋅ (A + B) = B ⋅(A + B) = BA + BB = A B
Y 4 = Y 2 + y3 = (AB + A B)
Y = Y 4 = Y 2 + Y3 = Y 2 + Y 3
Y = AB + A B
Experimental Procedure
1. A NOT gate is rigged as shown in Figure-2 using 7400 NAND gate.
2. Pin-14 is connected to +5 volt and Pin-7 to common.
3. Input is set to 0 levels on logic levels and output is monitored on the logic
monitor. The result is tabulated in Table-1. Next input is set to 1 level or logic
high on logic monitor and output is recorded in Table-1.
Table-1
7400
7402
A
Y
A
Y
1
0
1
0
0
1
0
1
NOT Truth Table
4. An AND gate is constructed as shown in Figure-3 using 7400. For different input
levels A&B output is noted on a logic monitor and tabulated in Table-2.
Table-2
A
0
1
7400
B
0
0
Y
0
0
A
0
1
7402
B
0
0
Y
0
0
Experiments with Digital ICs
34
Laboratory Experiments Series
0
1
1
1
0
0
1
1
1
1
AND Truth Table
0
1
5. Now OR gate is constructed as shown in Figure-4 and its truth table is
represented in Table-3
Table-3
A
0
1
0
1
7400
B
0
0
1
1
7402
Y
A
B
0
0
0
1
1
0
1
0
1
1
1
1
OR Truth Table
Y
0
1
1
1
6. XOR gate in now constructed using NAND gate and for different inputs output is
monitored and recorded in Table-4.
A
0
1
0
1
Table-4
7400
7402
B
Y
A
B
0
0
0
0
0
1
1
0
1
1
0
1
1
0
1
1
XOR Truth Table
Y
0
1
1
0
7. Experiment of constructing AND, OR, NOT, & XOR is repeated with 7402 NOR
gate and its truth table is compared with the one obtained using NAND gate.
Results
1. The basic logic gates AND, OR, NOT, XOR are constructed using NAND and NOR
gates and their truth tables are compared.
2. Hence NAND & NOR are universal gates.
References
[1]
LS/S/TTL Logic Data Book, National Semi Conductor, 1989,P2-3, 2-5
Experiments with Digital ICs
Laboratory Experiments Series
35
Chapter -2
Arithmetic Logic Unit
Experiments with Digital ICs
36
Laboratory Experiments Series
Experiment-7
HALF, FULL AND BINARY ADDERS
Abstract
Using 7483 binary adder IC, addition of two bits (Half Adder), addition of three
bits (Full Adder) and 4-bit binary numbers are added and function tables are
verified. Response of binary adder is also studied with 1 KHz and 2 KHz square
wave signals. The SUM and CARRY outputs are recorded from CRO.
2.1 Introduction
Electronic circuits now perform the fundamental arithmetic operations. Half Adder and Full
Adder are the building blocks of arithmetic process. In digital system these operations are
performed in the binary or in the hexadecimal form using these building blocks. A single IC
7483 performs addition and Subtraction operations. This contains half and full adder building
blocks. The binary addition and subtraction are based on the six truths listed in Table-2.1.
Table-2.1
Addition
Subtraction
0+0 =0
0-0 = 0
0+1 =1
1-0 =1
1+0 =1
1-1 =0
1+1 =10
10-1 =1
1+1 +1 =11
Fundamental truths governing binary addition and subtraction
2.2 Half Adder (HA)
Half adder is logic circuit that adds 2-bits. It consists of two outputs called SUM and
CARRY. By observing the function Table-2.1, it is clear that the SUM is XOR operation and
CARRY is an AND operation. Hence the Boolean equations governing the half addition are
given by
SUM = A ⊕ B
…1
CARRY = AB.
…2
Table-2.2 summarizes the half addition.
Table-2.2
Experiments with Digital ICs
37
Laboratory Experiments Series
Inputs
Outputs
A
B
SUM
CARRY
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Half Adder truth Table
2.3 Full Adder (FA)
A full adder is a logic circuit that adds three bits and it contains two outputs the SUM and
CARRY. By observing Table-2.1, it is clear that the output SUM is performed XOR gate and
output CARRY is obtained by ANDing. Hence the Boolean equations governing the Full
addition is given by
SUM = A ⊕ B ⊕ C
CARRY = AB+AC+BC
…3
…4
Table-2.3 summarizes the sequence of Full addition
Table-2.3
A
0
0
1
1
0
0
1
1
Inputs
Outputs
B
C
SUM
CARRY
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
Truth Table for Full Adder
By constructing HA and FA circuits using gates can verify these arithmetic binary operations.
However, performing HA and FA operations using logic gates are only of academic
importance rather than of any practical application. Dedicated ICs are now available which
finds extensive practical applications [1].
2.4 Binary Adder
A binary adder is a logic circuit that adds two binary numbers. Each of these consists of Full
Adder logic circuits. There are two output terminals called the SUM and CARRY as before.
Binary adders can add 4-bit numbers at a time; hence there are 8-inputs. The binary number
A consists of 4-bits and binary number B consists of 4-bits. Hence the binary SUM consists
of 4-bits. The CARRY is a one-bit output as shown in Figure-2.1. Such 4-bit binary adders
can be cascaded to obtain 8-bit or 16-bit binary additions. The third input C to the first FA in
binary adder is called input carry and denoted as Cin. The final carry from the fourth FA of
binary adder is called carry out and denoted as Cout. In between the first and the fourth FA,
Experiments with Digital ICs
38
Laboratory Experiments Series
the carry flows from first FA to second FA and so on. Hence the flow of CARRY is in the
form of ripple. Such a binary adder is also called as RIPPLE CARRY ADDER.
4 -bit bin ary Inp ut - B
B3 B2 B1 B0
Output Carry
Cout
4 -bit bin ary In put - A
A3A2A1A0
Binary
Adder
Input Carry
Cin
SUM
S3S2S1S0
Figure-2.1: 4-bit Binary Adder
2.5 IC 7483 - Binary Adder-Subtractor
IC 7483 is a TTL 4-bit binary adder [2] that is used extensively in digital circuit design.
Figure-2.2 shows the pin diagram of IC 7483. It consists of four full adders FA1, FA2, FA3,
and FA4. Each of these full adders consists of three inputs and two outputs. Using this IC,
HA, FA and Binary additions can be performed. Binary subtraction also can be performed
using this IC with additional circuitry. Binary subtraction will be published as a separate
experiment in future issues of LE.
Vcc
4-bit Binary
Input-A
4-bit Binary
Input-B
Input
Carry- Cin
5
10
8 A1
3 A2
1 A3
A4
11
7 B1
4 B2
16 B3
B4
13
C0
GND
9
S1 6
S2 2
S3 15
S4
C4
14
SUM
Output
Carry- Cout
12
Figure-2.2: Pin diagram of 74LS83 4-bit Barry Adder-Subtractor IC
2.6 HA using 7483
To obtain half adder, IC 7483 is tied as shown in Figure-2.3. Any one of the four FAs can be
used to perform this operation. Since HA adds only two bits, the input CARRY is grounded
permanently. The output CARRY is taken from S2 and SUM is taken as S1. In Figure-2.3 the
first FA is tied to perform half addition operation. A1 and B1 are taken as two binary bits. In
general, any among the four FAs can be used to perform half addition operation.
Experiments with Digital ICs
39
Laboratory Experiments Series
+5V
5
A1
Input-A
B1
Input-B
Cin
10
S1
9
11
S2
6
13
12
SUM
CARRY
7483
GND
Figure-2.3: Half Adder using IC 7483
2.7 FA using 7483
Including input carry Cin as the third bit, 3-bit addition is obtained. Figure-2. 4 gives full
adder circuit using IC 7483.
5
A1
Input-A
B1
Input-B
Input carry
Cin
+5V
10
9
11
6
13
12
S1
S2
SUM
CARRY
7483
GND
Figure-2.4: Full Adder Using IC 7483
2.8 HA, FA and BA with AC signal
We rarely come across with arithmetic operations based on static signals in practice. In
digital circuit design, arithmetic operations are performed on pulses (ac signal). Using 1 KHz
and 2 KHz rectangular pulses one can generate the 00,01,10,11 sequence of input that can be
used as inputs to the adders. The outputs SUM and CARRY are rectangular pulses obeying
the fundamental addition and subtraction truths listed in Table-2.1. In one cycle of the lowest
frequency, there can be four input states for A and B, as shown in Figure-2.5. 1 KHz square
wave is input A and 2 KHz square wave is used as input-B. The SUM will be a square wave,
with frequency equal to the lowest frequency among the input. The carry will be a rectangular
pulse with pulse width one-fourth of lowest frequency pulse width.
(SUM)Frequency = Lowest Frequency (1 KHz) = fA-bit
(CARRY)Pulse width =
(CARRY)Pulse width =
1
4 f A−bit
3
4 f A− bit
…5
for Cin= 0
…6
for Cin= 1
…7
Experiments with Digital ICs
40
Laboratory Experiments Series
1-msec
Input-A
0
1
0
1
0
1
0
1
Input-B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SUM
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
CARRY
0.25msec pulse width
Figure-2.5: Binary addition of 1 KHz (Bit-A) and 2 KHz (Bit-B) signals
2.9 Instruments Used
Digital trainer with ZIF socket consisting of 8-HI-LO input switches, 1 KHz and 2 KHz
square waves, logic monitors, 5V power supply, DMM with frequency measurement and dual
trace CRO.
2.10 Experimental Procedure
The experiment consists of four different parts
Part-A, Half Adder
Part-B, Full Adder
Part-C, Binary Adder
Part-D, Full Adder response to ac signal
Part-A, Half Adder
1. The half adder circuit is rigged as shown in Figure-2.3 using 7483 IC. The input CARRY
is grounded and only two bits are added.
2. The two inputs are connected HI-LO switches of the digital trainer and the two outputs
are connected to logic monitors.
3. The two inputs are set to 0 0 and the SUM and CARRY outputs are noted and verified
from the Truth Table-2. This procedure is repeated by setting input as 0 1, 1 0 and 1 1. In
each case CARRY and SUM are verified from the Truth Table-2.2.
Experiments with Digital ICs
Laboratory Experiments Series
41
Part-B, Full Adder
4. The full adder circuit is rigged as shown in Figure-2.4 using 7483 IC. The input CARRY
is Cin is connected to HI-LO switches and the switch is set to LO.
Cin = 0
5. The two inputs are connected HI-LO switches of the digital trainer and the two outputs
are connected to logic monitors.
6. The two inputs are set to 0 0 and the SUM and CARRY outputs are noted and verified by
comparing with the Truth Table-3. This is repeated by setting input as 0 1, 1 0 and 1 1. In
each case CARRY and SUM are verified from the Truth Table-2.3.
7. The input CARRY is now switched to HI.
Cin =1
8. For four different input combinations, the SUM and CARRY are noted from logic
monitors and verified from the Truth Table-2.3.
Part-C, Binary Adder
9. The binary adder circuit is rigged as shown in Figure-2.2 using 7483 IC. The input
CARRY Cin is connected to HI-LO switch and it is set to LO.
Cin= 0
The 4-bit Binary input A is connected to four different HI-LO switches and 4-bit Binary
input-B is also connected to four different HI-LO input switches. Now there are
altogether 9 inputs: Cin, B4, B3, B2 B1, A4, A3, A2, A1. These inputs are set to different values
starting from 0 0000 0000 to 1 1111 1111.
10. The four-bit SUM is monitored on four different logic monitors. The final carry or Cout is
monitored on another logic monitor. For
Cin
B4 B3 B2 B1 A4 A3 A2 A1
0
0 0 0 0
0 0 0 0
The final CARRY or the carry out Cout and
monitor and are recorded in Table-4.
SUM = S4 S3 S2 S1
Experiments with Digital ICs
are noted from logic
42
Laboratory Experiments Series
Cout S4 S3 S2 S1
0
0 0 0 0
11. This procedure is repeated for different input combinations as under:
Cin
B4 B3 B2 B1 A4 A3 A2 A1
0
0 0 0 1
0 0 0 1
The CARRY-SUM is recorded as in Table-2.4.
Cout S4 S3 S2 S1
0
0 0 1 0
12. In Table-2.4 the decimal equivalents of inputs and outputs are also recorded and verified
with their corresponding binary value.
Table-2.4
Inputs
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
0
0
1
1
1
1
Deci
mal
Equ.
B-bit
0
1
10
14
15
15
15
15
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
1
2
11
15
16
16
16
Input Input B -Bit
Carry
Cin
Outputs
Inputs
B4 B3 B2 B1
Input A -Bit
A4 A3 A2 A1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
Deci
mal
Equ.
A-bit
0
1
4
4
4
8
14
15
0
0
0
1
1
1
1
1
4-bit SUM Decimal
Equ.
Output
S4 S3 S2 S1
bits
0 0 0 0
0
0 0 1 0
2
1 1 1 0
14
0 0 1 0
18
0 0 1 1
19
0 1 1 1
23
1 1 0 1
29
1 1 1 0
30
0
0
0
1
1
1
1
0
0
1
0
0
1
1
Output
Carry
Cout
0 0 0 0
0
0 0 0 1
1
0 1 0 0
4
0 1 0 0
4
0 1 0 0
4
1 0 0 0
8
1 1 1 1
15
Verification of Binary Addition
0
0
1
0
1
0
1
13. Experiment is repeated for Cin =1. From the Table-2.4 it is verified that
Cin + B4 B3 B2 B1 + A4 A3 A2 A1 = Cout S4 S3 S2 S1
Experiments with Digital ICs
0
1
1
1
0
0
1
0
1
1
1
0
0
1
1
3
15
19
20
24
31
43
Laboratory Experiments Series
0 + 1 1 1 1
+ 1 1 1
0 + 15
+ 15
1 = 1
1 1 1 0
= 16 +8 +4 +2 +0 = 30
This verifies the binary addition Cin+B+A= CoutS.
Part-D, Full Adder response to ac signal
14. The full adder circuit is rigged, as shown in Figure-2.4. Input-A is fed with 1 KHz square
wave and input-B is fed from 2 KHz square from the digital trainer. The SUM output (S1)
is connected to Channel-1 of the CRO and Carry output (S2) is connected to channel-2 of
the CRO. The exact frequencies of the two input signals are noted using frequency
counter
fA = 1.02KHz
fB = 2.04KHz
15. The SUM output on Channel-1 and the CARRY output on Channel-2 of the CRO are
recorded as shown in Figure-2.6 (b) and verified with Figure-2.5. Figure-2.6 (a) shows
the Inputs A and B.
16. The pulse width of the CARRY wave form and frequency of the SUM waveforms are
recorded from CRO
For Cin = 0
CARRYPulsewidth = 0.25msec
SUMFrequency
= 1KHz
For Cin = 1
CARRYPulsewidth = 0.75msec
SUMFrequency
= 1KHz
The pulse width and frequency observed are verified with the equations 5 and 6.
In puts
Outp uts Cin= 0
Outputs Cin=1
A1
B1
(a)
SUM
SUM
CA RR Y
CA RRY
(b)
(c)
Figure-2.6, a) Inputs A=1KHz, B=2KHz b) Outputs Cin= 0, c) Outputs Cin=1
Experiments with Digital ICs
44
Laboratory Experiments Series
2.11 Results
The results obtained are tabulated in Table-2.5
Table-2.5
Parameter
Experimental
Theoretical
Carry pulse width (m sec) Cin=0
0.25
0.25msec
Carry pulse width (m sec) Cin=1
0.75
0.75msec
Sum frequency (KHz)
1
1
Carry output (operation)
AND
AND
Sum output (operation)
XOR
XOR
Experimental Results
2.12 Discussion
Using binary adder IC 7483, half, full and binary adder circuits are constructed and truth
tables are verified. Response of the full adder circuit to square wave is also verified and the
observed pulse width and frequency are compared with the theoretical values. Similar
response of the binary adder can be obtained with three input signals with frequency f, f/2
and f/4.
References
[1]
Dr A P Malvino and Jerald A Brown, Digital Computer Electronics, 3 rd Edition, Page79.
[2]
Texas Instruments, TTL Logic Data Book 1988, Page-2-257.
Experiments with Digital ICs
45
Laboratory Experiments Series
Experiment-8
HALF, FULL AND BINARY
SUBTRACTOR
Abstract
Using 7483 binary adders IC, two-bit subtraction (Half Subtraction), three-bit
subtraction (Full Subtraction) and 4-bit binary subtraction are performed and
subtraction truth tables are verified.
3.1 Introduction
Arithmetic addition and subtraction are now performed by integrated circuits that form the
backbone of arithmetic logic units in the computers. Various types of addition and subtraction
techniques are developed. Among them the fundamental process of addition and substation
are performed by single Adder- Subtractor ICs.
The process of addition is explained in experiment 156 published in LE [1]. In the present
experiment Half Subtractor (HS), Full Subtractor (FS) and Binary Subtractor (BS) circuits are
studied using 7483 adder-subtractor IC. The binary subtraction is based on the four truths
listed in Table-3.1.
Table-3.1
Subtraction
Truth
0-0 = 0
1-0 =1
1-1 = 0
10-1 =1
Fundamental truths governing binary subtraction
3.2 Binary Odometer
A binary odometer is shown in Figure-3.1 [2]. In this odometer the negative binary numbers
are represented by their 2’s complement form and positive binary numbers are represented in
sign magnitude form. Hence if A is a binary number then its 2’s complement represents –A.
Therefore
A+ 2’s complement of A = A + A΄= A + (-A) = A-A=0
Where
…1
A is a binary string
A΄ is its 2’s complement
1000
1001
1010
1011
1100
1101
1110
1111
0000
-8
-7
-6
-5
-4
-3
-2
-1
0
0001
0010
0011
0100
0101
0110
0111
1000
+1
+2
+3
+4
+5
+6
+7
+8
Experiments with Digital ICs
46
Laboratory Experiments Series
Figure-3.1: Digital binary odometer
Adding 1 to its 1’s complement obtains 2’s complement of a number. If A is a binary number
then its
1’s complement = A
2’s complement A΄ = A +1
…2
In the odometer shown in Figure-1, if A= 0100 (decimal 4)
A = 1011
A΄= A +1 = 1100 which represents -4 on the odometer line.
In digital computers subtraction is based on these odometer facts. During the process of
subtraction the number to be subtracted Y minuend is converted in to its 2’s complement
form and added to the subtrahend X. Hence a same IC that performs addition also can be used
to obtain subtraction with additional circuitry.
3.3 Half Subtractor (HS)
HS is logic circuits that subtract a minuend Y-bit from a subtrahend X-bit. It consists of two
outputs called DIFFERENCE and BORROW. The subtraction depends on the magnitude of
the subtrahend and the minuend. If the subtrahend is greater than the minuend
X≥Y, then
0-0=0
1-0=1
1-1=0
And if the subtrahend is smaller than minuend then
X<Y
Or in this case to subtract 0 from 1 (0-1) needs to borrow from the next immediate position.
In the decimal subtraction 10 is browed from the next stage. Similarly in the binary
subtraction 2 is borrowed from the next stage such that
2-1 =1
Based on these truths a complete HS truth table is presented in Table-3.2.
Comparing the outputs in Table-3.2 with the half adder truth table it is observed that the
DIFFERENCE output is the same as the SUM output hence the difference output is written as
Table-3.2
Inputs
Outputs
X
Y
Borrow Difference
Experiments with Digital ICs
47
Laboratory Experiments Series
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
Half Subtractor truth Table
Difference (D) = X ⊕ Y
…3
The borrow is given by
Borrow (B) = X Y
…4
The half subtractor equation is given by
D = X-Y
…5
3.4 Full Subtractor (FS)
A FS consists of three inputs namely two minuends Y and Z, one of which (Z) is a borrow
from the previous stage and a subtrahend X. The output of the FS consist the DIFFERENCE
and BORROW.
Table-3.3
X
0
0
0
0
1
1
1
1
Inputs
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
Outputs
DIFFERENCE BORROW
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
Full Subtractor Truth Table
DIFFERENCE (D) = X ⊕ Y ⊕ Z
BORROW (B) = XY + XZ + YZ
…6
…7
The full subtraction equation is given by
D =X-Y-Z
…8
These arithmetic binary operations can be verified by constructing HS and FS circuits using
7483 Full adder-subtractor IC [3].
3.5 Binary Subtraction
Experiments with Digital ICs
48
Laboratory Experiments Series
A 4-bit binary Subtractor is logic circuits that subtract a 4-bit minuend (Y1Y2Y3Y4) from a 4bit subtrahend (X1X2X3X4). The output consists of four-bit difference and single bit borrow
as shown in Figure-2. Such 4-bit binary Subtractor can be cascaded to obtain 8-bit or 16-bit
binary subtractions.
4 -bit binary In put - Y
Y3 Y2 Y1 Y0
Borrow
to next
stage
4 -bit bin ary In put - X
X3 X2 X1 X0
Borrow
from
previous
satge
Binary
Adder
DIFFERENCE
D3 D2 D1 D0
Figure-3.2: 4-bit Binary Subtractor
3.6 IC 7483 - Binary Adder-Subtractor
IC 7483 is a TTL 4-bit binary adder-subtractor which is used extensively in digital circuit
design. Figure-3.3 shows the pin diagram of IC 7483. It consists of four full adders FA1,
FA2, FA3, and FA4. Each of these full adders consists of three inputs and two outputs. Using
this IC, half, full, binary addition-subtraction can be performed.
Vcc
4-bit Binary
Input-A
4-bit Binary
Input-B
Input
Carry- Cin
5
10
8 A1
3 A2
1 A3
A4
11
7 B1
4 B2
16 B3
B4
13
C0
GND
9
S1 6
S2 2
S3 15
S4
C4
14
SUM
Output
Carry- Cout
12
Figure-3.3: Pin diagram of 74LS83 4-bit Barry Adder-Subtractor IC
3.7 HS using 7483
To obtain half subtractor, IC 7483 is tied as shown in Figure-3.4. Any one of the four FAs
can be used to perform this operation. Half subtraction requires only two bits. Hence the
input borrow is not used (NC). The output BORROW is taken from S2 and DIFFERENCE is
taken as S1.
Experiments with Digital ICs
49
Laboratory Experiments Series
5
+5V
10
X
Inputs
1
Y
3
2
11
7486
+5V
9
7483
6
DIFFERENCE
7404
1
Outputs
2
BORROW
74LS86 and 74LS04- Pin 14 to +5V
Pin-7 to GND. 7483 Pin-13 NC.
12
Figure-3.4: Half Subtractor using IC 7483
3.8 FS using 7483
Including input Borrow Z as the third bit, 3-bit subtraction is obtained. Figure- 3.5 shows a
full subtractor circuit using IC 7483.
5
10
X
Inputs
Y
1
+5V
2
Z
+5V
3
11
9
1
7483
2
7404
Outputs
4
7486
13
6
12
DIFFERENCE
5
6
BORROW
7486
74LS86 and 74LS04- Pin 14 to +5V
Pin-7 to GND.
Figure-3.5: Full Subtractor Using IC 7483
3.9 Binary Subtraction
If X and Y are two binary numbers, their DIFFERENCE is obtained by adding X to Y's 2’s
complement.
X-Y = X+ Y΄
…9
To generate the complements a controlled inverter is used as shown in Figure-3.6. The Y-bits
are passed through a controlled inverter formed by XOR gates. The controlled inverters
produce 1’s complement if SUB line is HIGH. Further it adds “1” to the inverted output
producing 2’s complement of Y bits. After this conversion the X and Y΄ bits are added by
the full adder-subtractor IC 7483.
When the SUB line is LOW the Y bits are passed without inversion and 7483 adds the two
bits. This is addition process. Hence the circuit in Figure-6 acts both as adder as well as
subtractor.
Experiments with Digital ICs
50
Laboratory Experiments Series
+5V
5
X0
10
8
X1
X2
3
1
X3
7486
7483
1
Y0
3
2
4
Y1
5
9
Y2
10
12
Y3
11
6
7
8
4
11
13
D0
6
D1
2
D2
15
D3
14
1
2
B
7404
16
13
SUB
9
12
7404 and 7486 Pin-15 to +5V,
Pin-7 to GND
+5V
Figure-3.6: 4-bit binary Subtractor Using IC 7483
3.10 Instruments Used
Digital IC Applications Expt Setup DIC105 KamalJeeth make consisting of 12-bit memory,
logic monitors and 5V power supply.
3.11 Experimental Procedure
The experiment consists of three different parts
Part-A, Half Subtractor
Part-B, Full Subtractor
Part-C, Binary Subtractor
Part-A: Half Subtractor
17. The half subtractor circuit is rigged as shown in Figure-3.4 using 7483 IC.
18. The two inputs X and Y are connected to HI-LO switches of the digital trainer and the
two outputs are connected to logic monitors.
19. Inputs X=0 and Y=0 are set on input logic switches and the DIFFERENCE and
BORROW outputs are monitored on logic monitors. For X=0 and Y=0
Experiments with Digital ICs
Laboratory Experiments Series
51
DIFFERENCE D = 0 and BORROW B = 0 is obtained. This is continued for 01, 10 and
11 inputs as shown in Table-3.3.
Part-B: Full Subtractor
20. The full subtractor circuit is rigged as shown in Figure-3.5 using 7483 IC. The input
BORROW is connected to HI-LO switches and the switch is set to LO.
Z=0
Entry
Condition
1
2
3
4
5
6
7
8
X=Y
X<Y
X>Y
X=Y
X=Y
X<Y
X>Y
X=Y
Table-3.4
Inputs
Outputs
X
B
Y
Z
D
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
Full adder input and outputs
Comments
For Z=0
Output B is
inverted
21. The two inputs X and Y are connected to HI-LO switches of the digital trainer and the
two outputs D and B are connected to logic monitors.
22. The two inputs are set to 0 0 and the DIFFERENCE = 0 and BORROW = 0 are noted and
recorded in Table-4. Borrow is inverted in this case.
23. Trial is repeated for X= 0 and Y=1. In this case D =1 and B =1 is obtained. B is inverted
in this case.
0-1 cannot be subtracted directly. Hence a Borrow is obtained from the next stage that
makes B=1. This borrowing adds 2 to X and X becomes 0 + 2 = 2. Hence the
DIFFERENCE output D = X-Y-Z = 2-1-0 =1 or D =1 as shown in Table-4.
For X=0, Y=0 and Z=1 the difference equation
D =X-Y-Z= 0-0-1 to subtract 1 from 0 we need to get a borrow from the next stage hence
B =1. This adds 2 to X which makes X= 0+ 2 = 2 and the D = 2-0-1=1 or D=1 and B=1 in
this case. This is 5th entry in Table-3.4.
For X=0, Y=1, Z=1 the subtraction equation
D = 0-1-1. In this case also we need to bring Borrow from the next stage that makes B=1
and adds 2 to X. The subtraction equation now becomes:
D= 2-1-1=0 or D=0 and B=1. This is 6th entry in Table-3.4.
Experiments with Digital ICs
52
Laboratory Experiments Series
Finally for X=1, Y=1 and Z=1
D=1-1-1=0-1 to subtract 1 from 0 a Borrow is needed hence B=1. This adds 2 to X
making
D=3-1-1=3-2=1
Note
These fundamental circuits are of theoretical importance rather than any practical
application as such. In practice it is the binary subtraction that is used which needs Z=1
for subtraction. Hence one need not correct the FS circuit by introducing an inverter
for Z=0 case.
Part-C, Binary Subtractor
Case-1: X=Y
The binary adder-subtractor circuit is rigged as shown in Figure-3.6 using 7483 IC. The
SUB line is connected to logic HI to perform subtraction. The X-bits are connected to 4bit memory cells (Or four HI-LO switches). The Y-bits are also connected to another 4bit memory cells of the digital trainer. The four outputs are connected to four logic
monitors of the digital trainer and final Borrow (Output Borrow) is connected 5 th logic
monitor on the digital trainer so that the output becomes
Subtractor Output = B
D3 D2 D1 D0
24. By pressing the control switch of the memory cells the 4-bit inputs X and Y are set to
equal values
X= X3 X2 X1 X0 =1010
Y= Y3 Y2 Y1 Y0 =1010
Outputs displayed on logic monitors are also noted.
Subtractor Output = B
=0
D3 D2 D1 D0
0
0 0 0
This is the first entry in Table-3.5. Experiment is repeated for a few equal values of X and
Y.
25. The X-inputs is set to 1111 (=15 in decimal) and Y inputs are set any value less than 15
and the outputs are noted in Table-3.5 as entries 2,3and 4. The subtraction is
straightforward in this case.
Case-3: X<Y
When X input is greater than Y input the output difference is negative hence it is in the 2’s
complement form.
Experiments with Digital ICs
53
Laboratory Experiments Series
Table-3.5
Entry Condition
Input-X
Input-Y
Outputs
X3
X2
X1
X0
Y3
Y2
Y1
Y0
B
D3
D2
D1
D0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
0
1
1
0
0
1
0
0
1
4
1
1
1
1
0
0
1
1
0
1
1
0
0
5
0
1
1
0
0
0
1
1
1
1
1
1
1
6
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X=Y
2
3
7
X>Y
X<Y
8
Binary subtractor outputs
Case-2: X>Y
26. The X-inputs are fixed at 0110 (6 in decimal) and Y-inputs = 0111 are set greater than 6.
In each case the five bit outputs are noted in Table-3.5. The subtractor output is given by
X = 0110 = 6 Y = 0111 = 7 X-Y = -1
Subtractor Output = B
=1
D3 D2 D1 D0
1 1 1 1
Output = 1 1111
1’s complement of the output = 0 0000
2’s complement of the output = 0 0001 = 1 or answer is -1.
By taking 2’s complement of the observed output the subtraction result is obtained.
27. Trial is repeated for different combinations of input and corresponding outputs are
recorded in Table-3.5.
For inputs X =0000, Y= 0001 the output obtained is1 1 1 1 1 which is equivalent to-1
because 1111, 1’s complement =00000, 2’s complement = 00001 =1, or the answer is -1.
3.12 Results
When X>Y, irrespective of Z (Z=don’t care) borrow B=0 or borrow is not required for
subtraction.
Experiments with Digital ICs
54
Laboratory Experiments Series
When X=Y
and
Z=0
B=0
When X=Y
and
Z=1
B=1
When X<Y irrespective of Z (Z=X) borrow B=1 or borrow is required for subtraction.
When B=1 it adds 2 to X.
The subtraction is given by the equation D = X-Y-Z is verified in all the cases. Positive
binary numbers are denoted by sign-magnitude form and negative numbers are represented
by 2’s complement form in arithmetic process in digital computers. By remembering above
facts one can verify the subtractor outputs.
References
[1]
Dr Jeethendra Kumar P K and Uma Prasad, Half, Full and Binary Adder, Lab
Experiments, Vo-6, No-3, Page-200.
[2]
Dr A P Malvino and Jerald A Brown, Digital Computer Electronics, 3 rd Edition, Page79.
[3]
Texas Instruments, TTL Logic Data Book 1988, Page-2-257.
Experiments with Digital ICs
55
Laboratory Experiments Series
Experiment-9
LOGIC SIGNATURE
OF A FULL ADDER
Abstract
Logic signature of a full-adder is obtained using 74LS183 and f, f/2, f/4 frequency
signals. Using full adder IC, 4-bit binary adder is constructed and the binary
addition is verified.
7.1
Introduction
A logic signature of a digital IC is the waveform representation of its truth table. It is
obtained on CRO by using control signals. For two input logic gates the four possible inputs
are 00, 01, 10 and 11. These four inputs can be generated using f and f/2 square waves [1].
For a three input gates we require three rectangular pulses namely f, f/2 and f/4 to display its
logic signature. A full adder performs mathematical operations. It consists of three inputs as
shown in Figure-7.1. These three inputs are fed with f, f/2 and f/4 pulses to get logic
signature. It is also called as timing diagram.
SUM
A
B
A
B
HA
Ci
SUM
FA
Co
Carry
Figure-7.1: Half adder and Full adder
In the half adder, shown in Figure-7.1, the outputs SUM and CARRY are given by
CARRY= AB
SUM = A ⊕ B
…1
…2
In a full adder A and B are two bits and Ci is the input carry and CO is the output carry. The
full adder equation is given by
CARRY = ABCi + ACi +BCi
SUM = A ⊕ B ⊕ C i
…3
…4
The SUM and CARRY outputs are easy to implement using logic gates. Dedicated chips are
also available in the TTL and CMOS family as full adder ICs. 74LS183 is one such full-adder
IC. Figure-7.2 gives the pin diagram of 74LS183. It is a dual full adder with input and out put
carries. The carries are used for cascading purpose. These ICs perform binary and BCD
additions.
Experiments with Digital ICs
56
Laboratory Experiments Series
Vcc 2A
2B
2Ci 2Co NC S2
1
3
4
74LS183
A
B
CI
13
12
11
A
B
CI
S
CO
S
CO
6
5
8
10
74LS183
1A
NC 1B
1Ci 1Co S1
GND
Figure-7.2: Pin diagram of 74LS183
The binary addition is based on four postulates as shown in Table-7.1.
Input
A
0+0
0+1
1+0
1+1
Table-7.1
Output
Comments
B
SUM CARRY
0
0
Sum zero carry zero
1
0
Sum one carry zero
1
0
Sum one carry zero
0
1
Sum zero carry one
Basic postulates of binary addition
TTL IC 74LS183 is a dual full adder [2] used for high-speed Wallance-Tree summing
networks. The circuit utilizes high-speed, high fan out, TTL logic, and compatible with both
DTL and TTL families. It can be cascaded to get full adder or substractor [3] of any length.
Figure-3 shows a 4-bit binary adder obtained using two 74LS183 ICs. In the circuit in Figure7.3, the final carry output is the MSB of the adder. The sum is given by
Sum = ∑ = S4 S3 S2 S1 S0
B3
12
A3
2Ci
11
13
…5
B2
A2
3
1
1Ci
4
B1
12
A1
2Ci
11
13
Bo
3
74LS183
10
8
S4 S3
1Co 5
6
S2
Ao
1Ci
4
1
74LS183
2Co
10 8
S1
1Co
5
6
So
Figure-7.3, 4-bit Binary Adder
The function table of LS183 is shown in Table-7.2. From the function table the timing
diagram is obtained as shown in Figuire-7.5. Three square wave signals of different
frequencies are used to obtain the logic signatures. IC 555 generates [4] the control signal
required to view the logic signature on the CRO. Figure-7.5 shows the complete circuit
diagram of the control signals. LS107 JK FF divides the square wave frequencies.
Experiments with Digital ICs
57
Laboratory Experiments Series
Table-7.2
Input B Input A
SUM
Output Carry Co
1
1
1
1
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
1
0
0
0
0
0
Logic Table of 74LS183 full adder
Input Carry Ci
1
1
1
1
0
0
0
0
Inputs
Ci
f/4
B
f
A
f/2
SUM
Outputs
Carry
Figure-7.4, Timing diagram or the logic signature of LS183 full adder
+5V
4
10K
8
13 4
7
1
10 11 8
10K
2,6
10n
12
5
9
3
74LS107
555
4148
4148
3
14
7
5
0.01
1
f
f/2
f/4
Figure-7.5, Various control signals for logic signal display on CRO
7.2
Instruments Used
Experiments with Digital ICs
58
Laboratory Experiments Series
Digital IC trainer containing 5V power supply, Logic monitors, HI-LO switches, Breadboard
and dual trace CRO. DMM containing frequency measurements.
7.3
Components Used
ICs 74LS183, 555, 74LS107, Resistors 10K, capacitors 0.01µF, 10nF, diodes 4148.
7.4
Experimental Procedure
The experiment consists of two parts namely
Part-A, Determination of logic signature
Part-B, 4-bit addition
Part-A, Determination of Logic Signature
1. Rigging circuit as shown in Figure-7.5 control signals are generated.
2. The frequencies of the control signals are noted using frequency counter (DMM)
f = 5.8KHz,
f/2= 2.9KHz, f/4 = 1.45KHz
The frequencies are accurately divided.
3. The control signals are fed to one part of the dual full adder as shown in Figure-7.6
+5V
2.9KHz
5.8KHz
1.45KHz
A
B
Ci
1
3
4
1/2-74LS183
14
6
SUM
5
Co
Channel-A
Chaneel-B
7
Figure-7.6: Circuit connections for logic signature display on CRO
The control signals are monitored one compared to other. Finally, the carry is monitored on
CRO channel-B and the sum is monitored on CRO channel-A. The CRO waveform is
recorded as shown in Figure-7.7. The waveforms obtained are compared with waveforms
generated from the function Table-7.2 and shown in Figure-7.4. It was observed that both the
waves are identical.
Experiments with Digital ICs
59
Laboratory Experiments Series
4. The controls signals are now removed and the inputs A B Ci are connected to the HI-lO
switches and the outputs are monitored on logic monitors. For different combinations of
input listed in Table-7.2, the outputs are observed and compared with Table-7.2. This
verifies functional table of the full adder.
Figure-7.7, Logic signature of full adder
Part-B, 4-bit addition
5. 4-bit full adder circuit is rigged as shown in Figure-7.3. The inputs Ci is set to logic LO.
And input bits B3 B2 B1 B0 and A3 A2 A1A0 are connected to HI-LO switches. The outputs
sum and carry are connected to the logic monitors. For different input bits, the output is
monitored and recorded in Table-7.3.
6. Trial is repeated for different input combinations in case of Ci =1. In each case the sum,
S4 S3 S2 S1 S0 is recoded in Table-7.3 that verifies binary addition.
Table-7.3
A3 A2 A1A0
Ci
B3 B2 B1 B0
0
0
0
0
0
0000
0001
0100
1000
1000
0
1
4
8
8
0000
0100
0010
0010
1000
1
1
1
1
1
0000
0001
0100
1000
1000
0
1
4
8
8
0000
0100
0010
0010
1000
S4 S3 S2 S1 S0
Total
0
4
2
2
8
00000
00101
00110
01010
10000
0
5
6
10
16
0
4
2
2
8
00001
00110
00111
01011
10001
0
6
7
11
17
4-Bit addition function table
7.5
Results
Experiments with Digital ICs
60
Laboratory Experiments Series
1. The full adder 74LS 183-logic signature is obtained using control signals. The
waveform obtained (Figure-7.7) is identical to the waveform generated (Figure-7.4)
from function table (Table-7.2).
2. Two ICs are cascaded to get 4-bit binary adder and the binary additions are verified.
The final carry is the MSB of the sum.
7.6
Discussion
TTL IC 74LS183 is a dual full adder which can be cascaded to get any binary and BCD
additions. It also can be used to obtain subtraction using suitable controlled inverters. These
applications will be published in the future volumes of LE.
The sweep technique used to get logic signature can be applied to any logic gate and similar
logic signature of the gates can be obtained.
References
[1]
Sumalatha et al, Logic Function Table Displayer, LE Vol-1, No-1, Nov-2001, Page26.
[2]
TTL Logic, Standard TTL, Schottky, Low power Schottky Data Book, Texas
Instruments, 1988, Page-2-256.
[3]
Malvino A P, Brown J A, digital Computer Electronics, 3 rd Edn, 1997, Page-86.
[4]
Dr S R Sawant, LE, Vol-2, No-1, June-2002, Page-29
Experiments with Digital ICs
Laboratory Experiments Series
Chapter-3
Flip-Flops
Experiments with Digital ICs
61
62
Laboratory Experiments Series
Experiment-10
RS AND D FLIP-FLOPS USING GATES
Abstract
The Reset-Set (RS) and D Flip-Flops (FFs) are constructed using universal gates
7400 and 7402. Their truth tables are studied and the FFs are clocked to understand
the process of data storage and data retension. After the experiment the student
should be in a position to differentiate RS and D FFs, its possible applications, and
the importance of CLK control terminal in FFs.
Introduction
Flip-Flops are memory elements of digital computer. These memory units store binary bits. A
FF has two stable states. It remains in one of its stable state until power is on or until it is
changed, hence FF store digital data. To control the bits stored control the bits stored control
signals are added. Two such control signals R & S are added to get a FF known as RS FF.
The RS or the Reset-Set FF is the simplest form of memory elements. FF can be constructed
using discrete components gates or FF ICs are also available. A RS FF constructed using
gates is shown in Figure-1. A high R reset (Q=0) the FF and a high S sets (Q=1) it.
Figure-1: RS FF using Universal Gates
When both control signals R & S are zero there won’t be change in the outputs states of the
FF. It continues in its last state. A high control signal on R&S will force the memory element
to set or reset and this condition is known as race and in this state the output is unpredictable.
It can be 0 in some trials and can be 1 in some other trials. The RS FF action is summarized
in Table-1 for both the above circuits.
R
0
0
1
1
S
0
1
0
1
Table-1
Q
Output states
NC
Last state
1
Set
0
Reset
*
Race(unpredictable)
RS Truth table
To co-ordinate the overall action of FF a square wave called clock (CLK) is sent to FF. This
signal prevents the FF from changing the states until the right time. Clocked FFs are shown in
Figure-2. It is possible to store the FF in order to store information ( set it or reset it) at any
time and hold the information for any desired period of time by the clock. In the Figure-2 a
high CLK ENABLES the FF and low CLK DISABLE the FF as shown in the Truth Table-2.
Figure-2: Clocked RS Flip-Flop
Experiments with Digital ICs
Laboratory Experiments Series
CLK
0
0
0
0
1
1
1
1
63
Table-2
R
S
Q
Description
0
0
0
1
0
0
Disable
0
1
0
Not Operative
1
1
0
0
0
NC
Last state
1
0
0
Reset
0
1
1
Set
1
1
*
Race
Clocked RS FF Truth Table
(Note: with CLK=0, Q may be either 0 or 1 depending on the last state of the FF)
D Flip-Flop
RS FF is susceptible to a race condition. This can be avoided by the use of a inverter as
shown in Figure-3. This inverter guarantees that R&S be never the same. Therefore it is
impossible to set up a race condition in this FF. And the new FF is known as D FF.
Figure-3: Clocked D FF
The clock will enable or disable the FF as in the previous case. The D truth table is given in
Table-3
CLK
0
0
1
1
Table-3
D
Q
0
NC
1
NC
0
0
1
1
D Truth Table
Description
Previous state
Reset
Set
A low deactivate the FF or in other words FF stores or remembers, when CLK is high D
controls the output. A high D sets the FF, while a low D reset it.
Experimental Procedure
1. A clocked R-S FF circuit is rigged as shown in Figure-3
2. Pin-14 of 7400 is connected to +5V and pin-7 GND
3. The Q output is monitored on a logic monitor
4. CLK is connected to logic LO
Experiments with Digital ICs
64
Laboratory Experiments Series
5. For different combinations of R&S Q is noted and tabulated in Table-4
6. Now CLK is taken to logic high and for different input conditions of R&S Q
noted in Table-4
7. Experiment is repeated with 7402, and the corresponding readings are noted in
Table-4
8. A D FF circuit is now rigged as shown in Figure-3. Pin-14 is connected to +5V
and pin-7 to GND
9. With clock high for different value of D output Q is monitored on a logic monitor
and recorded in Table-5.
Table-4
CLK
0
0
0
0
1
1
1
1
NAND
R
S
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
Q
0
0
0
0
0
0
1
*
CLK
0
0
0
0
1
1
1
1
NOR
R
0
0
0
0
0
1
0
1
S
1
1
1
1
0
0
1
1
Q
0
0
0
0
0
1
0
*
Table-5
NAND
CLK
D
1
0
1
1
0
0
0
1
Q
CLK
0
1
1
1
NC
0
NC
0
D Truth Table
NOR
D
0
1
0
1
Q
0
1
NC
NC
10. Now the clock is taken to low and for D=), 1 the output is noted and tabulated in
Table-5.
11. Experiment is repeated with 7402 and the corresponding outputs are recorded in
Table-5
Results
1. A RS FF is enabled (activated) when CLK is high. And it is disabled when CLK is
low.
Experiments with Digital ICs
Laboratory Experiments Series
65
2. With high clock, FF can be Reset with high R and low S.
3. With high clock, FF can be set with high S and low R.
4. With R=S=1 the FF output is unpredictable and hence should be avoided.
5. A D FF can be set with high D and reset with low D. This takes place when CLK
is high. A low CLK disables the FF.
References
[1]
JD Ryder, Electronic Fundamentals and Applications, Prentice-Hall, 1978, P-428
[2]
AP Malvino & DP Leach, Digital Principles and Applications, Tata McGraw Hill
Fourth Edition, 1991, P-260.
Experiments with Digital ICs
66
Laboratory Experiments Series
Experiment-11
D & JK FLIP-FLOPS USING ICs
Abstract
Characteristics of dual D FF 7474 and dual JK FF 7476 are studied. Toggling in
JK FF, its frequency division and the role of preset and clear inputs on FF are
studied.
Introduction
Logic gates are decision making elements of digital computer. Flip-Flops are memory
elements. FF has two stable states. It remains in one of its stable state until external trigger
changes it. It remains in its new state even after the removal of the triggering signal and
hence it retains the data or it stores the data.
There are three basic types of flip-flops can be constructed using logic gates. Ready made FF
ICs are now available in the market. A FF consists of two input terminals known as data
inputs and two output terminals (Q and Q ). In addition to these terminals FF has a clock
(CLK) terminal, a preset and a clear terminal.
Computers use thousands of such FFs. To co-ordinate the overall action, a square wave called
the clock (CLK) is sent to each flip-flops. This signal prevents the flip-flops from changing
states until right time. There are two types of clocking. Level clocking (positive level
clocking and negative level clocking) is the simplest way of controlling FFs. More efficient
and high speed clocking is known as Edge triggering. In this case FF will be active only at a
unique instant of clocking pulse. In edge triggering also there are two types namely positive
edge triggering and negative edge triggering.
D Flip-Flop
This one input FF is a modification of RS FF. In D FF racing avoided by the use a inverter
between R & S control inputs. 7474 is a TTL dual positive edge triggered FF with preset and
clear terminals. Figure-1 shows pin configurations of 7474.
Figure-1: Pin configurations of 7474
The FF accepts data at D input on the positive going edge of clock pulse. A low logic on the
preset or clear inputs Set or Reset the FF irrespective of the logic on the D input.
JK Flip-Flop
7476 is a dual Master-Slave JK FF with clear and preset inputs. During the positive pulse of
the clock. J&K inputs are transferred to the master. On the negative transition of the clock,
the data from the master is transferred to the salve. A low logic on the preset or clear inputs
set or reset the output. Figure-2 shows pin configuration of7476.
Figure-2: Pin Configuration of 7476
Experiments with Digital ICs
Laboratory Experiments Series
67
Experimental Procedure
1. Pin-14 of 7474 is connected to +5V and pin-7 to GND. Out of the two FFs one is
selected.
2. With preset PR1 (Pin-4) low and clear CLR1(Pin-1) high output Q1 (Pin-5) is
monitored on a logic monitor. The output state is compared with truth table-1.
This is the SET state or the FF.
3. Now preset PR1 is held high and clear CLR1 is held low, Q1 output is noted. This
is the RESET state of the FF
4. With PR1 and CLR1 both low, the output is found to be unstable. This is observed
by repeated trials.
5. Now PR1 and CLR1 both taken to high. A clock signal of 1KHz frequency is
introduced at the clock input CLK1 (Pin-3) and D1(Pin-2) is also held high. The
output is observed on a oscilloscope with respect to the clock. The output is traced
as shown below. In this state D1 control the output.
Figure-3: Timing diagram of 7474
6. D1 is taken low and Q1 is traced with respect to clock as shown in Figure-3. In
this state D1 control the outputs.
7. The experiment is repeated with 7476. Pin-5 of 7476 is connected to +5V and Pin13 to GND. Out pf the two FFs one selected.
8. Preset PR1 (Pin-2) is held low and clear CLR1 (Pin-3) is held high, the output Q1
(Pin-15) is monitored on the logic monitor. This is the SET state of the FF.
9. With preset PR1 high, clear CLR1 low Q1 is again noted and compared with the
truth table given in Table-2. This is the RESET state of the FF.
10. Experiment is repeated as per the Table-2 for various combinations of J, K, CLK1.
11. To observe toggling J&K are held high with both CLR1 and PR1 high. The two
outputs Q1 (Pin-15) and Q 1 (Pin-14) are monitored. A 1Hz clock is connected to
the clock input CLK1 (Pin – 1). The monitors going on and off repeatedly indicate
the toggle.
12. Clock frequency is now increased to 1KHz. And both the monitors going on is
noted. This is still the toggle state. The action is so fast the LEDs appears to be on
Experiments with Digital ICs
68
Laboratory Experiments Series
always. Instead of monitoring Q1 and Q1 on logic monitors, the outputs are
connected to a oscilloscope and output wave form is traced with respect to the
clock as shown in figure-4
Figure-4: Timing Diagram of 7476
From the timing diagram the division in the frequency is noted. Secondly when Q1 is set
(high) Q 1 is reset (low). This set and reset is continuous with the clock demonstrating the
toggle.
Results
1. The D & JK FFs are SET with a high clear and low preset, and RESET with a low
clear and high preset. In the SET or RESET state the clock or the control inputs
(D in case of D FF and J, K in JK FF) doesn’t have any effect on the Q outputs.
2. 7474, D FF is a edge triggered FF and 7476, JK FF is a pulse triggered FF.
3. The toggle in JK FF is an indication of the arrival of a clock pulse at the clock
input. Therefore, it could be used for counting applications. Further, the output
frequency is half the clock frequency hence it act like or frequency divider.
4. There is a state in FFs when the output is found to be unstable. This is obtained for
clear and preset both low. This condition has to be avoided when using FFs.
References
[1]
LS/S/TTL Logic Data Book, National Semi-Conductor, 1989, Page-4-75, 4-81.
Experiments with Digital ICs
Laboratory Experiments Series
69
Experiment-12
MAGNITUDE COMPARATOR
Abstract
Comparators are decision-making devices in memory related applications. In this
paper function tables of 4-bit and 3-bit magnitude comparator are verified using
74LS85 TTL IC.
Introduction
A magnitude comparator compares two binary numbers or BCD numbers. It consists of two
four-bit inputs and three output terminals. TTL 74LS85 is a 4-bit magnitude comparator
widely used in industrial applications. These comparators can be cascaded to get higher bit
comparators [1]. An analog comparator consists only one output terminal [2] whereas digital
comparators consist of three out terminals.
74LS85 Magnitude Comparator
B3
A
1
16
Vcc
Bin
A3
A = Bin
B2
A
Bin
A B
out
A=B out
A Bout
GND
A2
7485
A1
B1
A0
8
9
B0
Figure-1: Pin diagram of 74LS85
Figure-1 shows pin diagram of TTL 4-bit magnitude comparator IC 74LS85. It can compare
two 4-bit binary or BCD numbers. One among the three outputs that is high indicates the
result of comparison. For example the Logic HI output on A=B output terminal indicates that
both the input numbers are equal. If the A>B output is HI indicating that Number A is bigger
than number B. Similarly if A<B output is at HI state indicating that the number A is less
than number B. In this manner the two 4-bit numbers are compared. Pins 2,3,4 are input pins
used during cascading. Pins 5,6,7 are output terminals. Using these ICs two 24-bit numbers
can be compared [1]. It can also compare less than 4-bit numbers. For a 3-bit comparator, the
MSB bits B3 and A3 are grounded. For two-bit comparator B3 B2 A3 A2 bits are grounded. In
normal 4-bit comparator operation pins 2&4 are grounded and pin-3 is connected to VCC.
Instruments Used
Experiments with Digital ICs
70
Laboratory Experiments Series
Digital trainer contains solderless bread board, 5V power supply, logic inputs (HI-LO
switches) and logic monitors. The Digital Trainer DIC-201 KamalJeeth make used in this
experiment is shown in Figure-2.
Figure-2: Digital Trainer DIC-201
Components Used
IC 74LS85, resistors 180 Ohms, LEDs
Experimental Procedure
1. 4-bit binary comparator circuit is rigged as shown in Figure-3. Pin 16 of the IC is
connected +5V supply and pin-8 is grounded.
2. The 4-bit inputs are connected to 8-HI-LO switches of the digital trainer.
3. The three outputs are connected to three LEDs as shown in Figure-3. Or it can be directly
connected to logic monitors of the digital trainer.
Experiments with Digital ICs
71
Laboratory Experiments Series
+5V
16
A3
15
4-bit
A2
input-A
A1
To HI-LO switches
A0
13
12
7
10
6
74LS85
B3
1
4-bit
B2
Input-B
B1
To HI-LO switches
B0
5
A
B
A=B
A
B
14
11
180
9
180
180
8
Figure-3: Magnitude comparator circuit
Table-1
A3
1
1
1
1
1
1
0
1
1
1
1
A2
0
1
1
0
0
0
0
0
1
1
1
A-bits
A1
0
0
1
0
0
0
0
0
0
1
1
B-bits
A0 Dec.
B3
B2
B1
B0
Dec.
0
8
0
1
0
0
6
0
12
0
1
0
0
6
0
14
0
1
0
0
6
0
8
1
1
0
0
12
0
8
1
1
1
0
14
0
8
1
1
1
1
15
0
0
0
0
0
0
0
0
8
1
0
0
0
8
0
12
1
1
0
0
12
0
14
1
1
1
0
14
1
15
1
1
1
1
15
Function table of 4-bit comparator 74LS85
4. Inputs are set on HI-LO switches as
A3A2A1A0 =1 0 0 0 = 8 (in decimal) and
B3B2B1B0 = 0 1 0 0 = 6
5. The three output states indicated by the LEDs are noted in table-1.
Output A<B = 0
Output A>B = 1
Experiments with Digital ICs
Outputs
A<B A=B A>B
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
72
Laboratory Experiments Series
Output A=B = 0
In the three outputs A>B = 1 which indicates that 4-bit number A is greater than 4-bit
number B or in other words 8>6.
16
14
A=B
A>B
12
A-bits
10
8
6
A<B
4
2
0
0
2
4
6
8
10
12
14
16
B-bits
Figure-4: Bit comparison
6. Trial is repeated for different values of A and B. In each case the three outputs are noted
in Table-1.
A3
0
0
0
0
0
0
0
0
0
0
0
A2
0
1
1
0
0
0
0
0
1
1
1
A-bits
A1
0
0
1
0
0
0
0
0
0
1
1
Table-2
B-bits
A0 Dec.
B3
B2
B1
B0
Dec.
0
0
0
1
0
0
4
0
4
0
1
0
0
4
0
6
0
1
0
0
4
0
0
0
1
0
0
4
0
0
0
1
1
0
6
0
0
0
1
1
1
7
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
4
0
1
0
0
4
0
6
0
1
1
0
6
1
7
0
1
1
1
7
Function table of 3-bit comparator 74LS85
Outputs
A<B A=B A>B
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
7. A graph is drawn taking A-bits on Y-axis and B-bits on X- axis as shown in Figure-4. The
straight line belongs to A=B. The area above the straight line belongs to A>B output and
area below the straight line belongs to A<B output.
Experiments with Digital ICs
Laboratory Experiments Series
73
8. The voltage corresponding to HI State output and LO state outputs are also noted using a
DMM. It is observed that the HI state and LO state voltages remained the same for all
three states of the outputs.
HI state output = 3.12V
LO state output = 0.12V
9. Experiment is repeated for 3-bit comparator by grounding inputs A3 and B3 throughout
the trial. The readings obtained are tabulated in Table-2.
Results
The results obtained are tabulated in Table-3.
Table-3
Input Conditions
Output States
A=B
A<B
A>B
1
0
0
A3A2A1A0 < B3B2B1B0
A3A2A1A0 = B3B2B1B0
0
1
0
0
0
1
A3A2A1A0 > B3B2B1B0
Experimental results
Discussion
The straight line in Figure-3 represents the three output states of the magnitude comparator.
The straight line A=B is not a thin line because it is from digital output. One bit (195mV)
resolution is present between output states.
References
[1]
Texas Instruments, TTL Logic Data Book, 1988, Page-2-263.
[2]
Dr Jeethendra Kumar P K, Positive and Negative Peak Detector, Lab Experiments,
Vol-7, No-4, Page-255.
Experiments with Digital ICs
74
Laboratory Experiments Series
Chapter -4
Registers and
Counters
Experiments with Digital ICs
Laboratory Experiments Series
75
Experiment-13
GRAY CODE GENERATOR
Abstract
A parallel binary to Gray and Gray to binary code generator is studied using
74LS193/92 binary up-down counter and 74LS86 XOR gates. The timing
diagrams are recorded and the conversion is verified.
6.1
Introduction
Gray code is one of frequently used code similar to binary, BCD and 8421. It makes use of
binary number 0 and 1. The humming distance between two consecutive binary numbers is
one. Hence, Gray code is a binary sequence in which only one bit changes per humming
distance. Frank Gray invented this and named after him. Originally, the code was known as
cyclic-permuted code. The need for different code other than binary became necessary during
the vacuum tube era. Digital logic circuits were constructed using relays and vacuum tubes
during that era. These electromechanical circuits developed large noise and power
requirements especially when the digit is changing from HI bit to LO bit (1111 to 0000, here
four bits change their status at once), the back emf from the relay created huge noise. Using
gray code, any increment or decrement changed only one bit, regardless of the size of the
number. Gray code was a boon at that time. The codes were patented in 1953 in the name of
Frank Gray for Bell Labs [1]. At present Gray, code is used for encoding shaft position data
from machines such as computer-controlled lathes [2]. An N bit Gary code generator also can
produce (N-1) different frequencies, hence used for frequency division.
If B3 B2 B1 B0 is 4-bit binary, number then the equivalent Gray code G3 G2 G1 G0 is given by
G3 = B3
G2 = B3 ⊕ B2
G1= B2 ⊕ B1
G0= B1 ⊕ B0
…1
…2
…3
…4
Equations 1 to 4 show the relationship between binary and Gray code. These mathematical
equalities can be implemented electronically using XOR gates. Such a circuit that converts
binary code in to Gray code is called binary-to-Gray code converter.
Gray code G0 or the LSB starts with one 0 followed by two 1s and two 0s,
G1 or the second LSB starts with two 0s followed by four 1s and four 0s,
G2 or the third LSB starts with four 0s followed by eight 1s and eight 0s,
G3 or the fourth LSB starts with eight 0s followed by sixteen 1s and sixteen 0s.
In general nth LSB of a Gray code starts with 2n-1 0s followed by 2n 1s and 2n 0s. Using this
definition one can write Gray code of any width. Based on this definition the Gray codes for
first 16 binary states (4-bit) are listed in Table-6.1.
Table-6.1
Experiments with Digital ICs
76
Laboratory Experiments Series
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary Code
Gray Code
B3 B2 B1 B0
G3 G2 G1 G0
0000
0000
0001
0001
0010
0011
0011
0010
0100
0110
0101
0111
0110
0101
0111
0100
1000
1100
1001
1101
1010
1111
1011
1110
1100
1010
1101
1011
1110
1001
1111
1000
The first 16 Gray codes
The reverse process of converting Gray code to binary code is governed by following
equations.
MSB
B3
G3
1
B2
3
G2
6
G1
8
G0
2
7486
4
B1
5
7486
9
LSB
B0
10
7486
Figure-6.1, Four-bit parallel binary to Gray code converter
B3 = G3
…5
B2 = G2 ⊕ G3
…6
B1= G1 ⊕ B2 = G1 ⊕ G2 ⊕ G3
…7
B0= G0 ⊕ B1 = G0 ⊕ G1 ⊕ G2 ⊕ G3
…8
Based on these equations (1 to 8) the binary to Gray and Gray to binary converter circuits are
shown in Figures-6.1 and 6.2 respectively.
Experiments with Digital ICs
77
Laboratory Experiments Series
MSB
G3
B3
1
3
B2
6
B1
8
B0
2
G2
7486
4
5
G1
7486
9
LSB
10
G0
7486
Figure-6.2, Four-bit parallel Gray to binary code converter
6.2
Gray Code Generator
+5V
16
11
Load
7
QD
B3
QC
B2
G3
1
74LS193/92
6
3
G2
6
G1
8
G0
2
7486
CLK
5
4
2
QB
B1
5
CLR
7486
14
8
3
9 10 1 15
D C B A
QA
9
B0
10
7486
Figure6.-3, Four bit Gray code generator
Gray code generator converts a clock signal in to Gray code signal. Such a generator consists
of Gray code converter and a binary counter as shown in Figure-6.3. The clock signal which
has to be converted in to Gray code signal is connected to clock input (CLK) of 74LS193
binary up-down counter [3]. The Load terminal (Pin-11) of the counter IC is tied to +5V and
the clear terminal CLR (Pin-14) is tied to ground. The preset input terminals DCBA (Pins
10,9,1,15) are also grounded. The Gray to binary code generator circuit is shown in Figure6.4.
Experiments with Digital ICs
78
Laboratory Experiments Series
+5V
11
Load
16
7
QD
G3
QC
G2
B3
1
6
74LS193/92
CLK
3
B2
6
B1
8
B0
2
7486
4
5
QB
2
G1
5
7486
CLR
9
3
9 10 1 15
D C B A
8
14
QA
G0
10
7486
Figure-6.4, Gray to binary code generator
B0
B1
B2
B3
G0
G1
G2
G3
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1 1
1
1
1 1
0
0 0
0
0
0
1
1
1
1
1
1
1
1
1
0 0
Figure-6.5, 4-Bit Gray code generated using table-1
The Gray code generated using the Table-6.1 is shown in Figure-6.5. A similar timing
diagram can be generated for any bit-width.
Experiments with Digital ICs
Laboratory Experiments Series
79
The outputs of the binary counter generate 16 logic states listed in Table-6.1; these binary bits
are inputs to the Gray code converter. The output of the Gray code generator is rectangular
pulses with three different frequencies. Frequency of B1 equal to G0, B2 equal to G1, B3 equal
to G2. However, there is 90, 180 and 360 degrees phase difference among them respectively.
G3 is 720-degree phase difference with B3 and its frequency is half of G2.
6.3
Instruments Used
Digital trainer containing 5V regulated power supply, logic monitors, 1KHz clock and dual
trace CRO.
6.4
Components Used
ICs 74LS193, 74LS86
6.5
Experimental Procedure
Part-A, Binary to Gray code generator
1 Binary to Gray code generator circuit is rigged as shown in Figure-6.3. The clock input of
the binary up-down counter is fed with 1KHz clock signal.
2 The binary counter output B0 is monitored on CRO channel-B in compared to Clock
signal on Channel-A of the CRO. The waveform is recorded.
3 Similarly binary counter output B1 is monitored compared to B0, B2 is monitored
compared to B1, B3is monitored compared to B2 and the wave forms are recorded as
shown in Figure-6.6.
4 The counter outputs shown in Figure-6.6 generate 16-bit input to the Gray code converter.
This is similar to 16 different binary inputs shown in Table-6.1.
Figure-6.6, 74LS193 output waveforms
Left top B0, bottom B1 right top B2, bottom B3
The Gray code outputs G0 and G1 are monitored on channel-A and channel-B of the CRO
and the waveforms are recorded. Similarly, G2 G3 is monitored one compared to other.
The waveforms recorded are shown in Figure-6.7.
Experiments with Digital ICs
80
Laboratory Experiments Series
1. The waveforms observed matched with the waveform shown in Figure-6.5, indicating
perfectness in the conversion.
Figure-6.7, Gray code generator output waveforms
Left topG1, bottomG0, right top G3, bottom G2.
Part-B, Gray to binary code generator
2. The Gray to binary code generator circuit is rigged as shown in Figure-6.4.
Table-6.2
Binary to Gray code
Gray to binary code
Decimal
converter
converter
Binary
Gray
Gray
Binary
0
0000
0000
0000
0000
1
0001
0001
0001
0001
2
0010
0011
0010
0011
3
0011
0010
0011
0010
4
0100
0110
0100
0111
5
0101
0111
0101
0110
6
0110
0101
0110
0100
7
0111
0100
0111
0101
8
1000
1100
1000
1111
9
1001
1101
1001
1110
10
1010
1111
1010
1100
11
1011
1110
1011
1101
12
1100
1010
1100
1000
13
1101
1011
1101
1001
14
1110
1001
1110
1011
15
1111
1000
1111
1010
Gray to binary and binary Gray code conversion
3. The binary counter input is fed with 1-KHz clock signal and the output of the Gray to
binary code generator output is monitored on CRO screen. The outputs B0 and B1 are
compared and recorded. Similarly, outputs B2 and B3 are compared. The outputs observed
are shown in Figure-6.8.
4. The output waveforms obtained are verified by feeding HI-LO inputs. Gray to binary and
binary to gray code converter as shown in Figures-6. 1 and 6.2. The inputs are fed from
HI-LO switches and the output is monitored on logic monitors. The outputs recorded are
tabulated in Table-6.2.
Experiments with Digital ICs
81
Laboratory Experiments Series
Figure-6.8: Gray to binary code generator output waveforms
Left topB1, bottomB0, right top B3, bottom B2.
G0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
G1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
G2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
B0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
B1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
B2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Figure-6.9, Gray to binary converter output waveforms
5. The waveforms generated from Table-6.2, for Gray to binary converter is shown in
Figure-6.9. It is seen that the waveforms generated matched with Figure-6.8, indicating
perfect conversion.
6.6
Results
Binary to Gray and Gray to binary code generator functioning is verified. The output
waveforms agreed with the predicted waveform as per conversion table (Table-6.1). With
1KHz, clock input three different frequencies are obtained at the output of the generator.
These frequencies are 62.5Hz, 125Hz and 250Hz.
6.7
Discussion
Binary to Gray code conversion was important invention during the vacuum tube technology.
At present it is used in heavy duty machines controlled by computer were power is an
important considerations such as CMC machine. As such, it is not used in regulator digital
Experiments with Digital ICs
82
Laboratory Experiments Series
design. Instead of feeding clock signal any digital can be fed and the corresponding Gray,
code can be obtained. This is exactly done in machines.
References
[1]
Gray code from FOLDOC, http://nist.gov/dads/HTML/graycode.html
[2]
Douglas V Hall, Microprocessors and interfacing, 2nd Edn, Page-3.
[3]
T Aswathnarayana Rao, Synchronous 4-bit up-down counter, LE Vol-3, No-2, June2003, Page-103.
Experiments with Digital ICs
Laboratory Experiments Series
83
Experiment-14
SYNCHRONOUS 4-BIT UP-DOWN
COUNTER
Abstract
In a 4-bit synchronous up-down counter 74LS193, forward and reverse counting
of input pulse is studied. The counter is tested for preset input in both the
directions. The functioning of Load, CLR control pins are verified and two such
counter ICs are joined to form a 8-bit cascaded counter. The forward and reverse
counting is verified. The output waveforms are recorded by applying a square
wave signal.
8.1
Introduction
SN 74LS192 and 74LS193 are monolithic circuits capable of counting input pulse in both the
directions. A control signal called Up makes the counter to count from a pre determined value
and count Down signal makes it to count in the downward direction from the pre determined
value. LS 192 is BCD counter and LS193 is binary counter. Synchronous operation is
provided by having all the flip-flops (FFs) clocked simultaneously so that the outputs change
coincidently with each other when so instructed by the steering logic.
The outputs of the four master-slave FFs are trigged by a low-to-high level transition of either
count (clock) input. The direction of counting is determined by which count input is pulsed
while the other count input is high.
All the four counters are fully programmable that is each output may be present to either level
by entering the desired data at the data inputs while the load input is low. The output will
change to agree with the data inputs independently of the count pulses. This feature allows
the counters to be used as modulo-N dividers by simply modifying the count length with the
preset inputs.
A clear input has been provided which forces all outputs to the low level when a high level is
applied. The clear function is independent of the count and load inputs. The clear, count, and
load inputs are buffered to lower the drive requirements. This reduces the number of clock
drivers etc, required for long words. These counters are designed to cascade without the need
of external circuitry. Both borrow and carry outputs are available for cascading. The borrow
output produce a pulse equal in width to the count down input when the counter under flows.
Similarly, the carry output produces a pulse equal in width to the count-up input when an
over flow condition exists. The counters can be then be easily cascaded by feeding the
borrow and carry outputs to the countdown and count-up inputs respectively of the
succeeding counter [1]. The maximum frequency of the count signal is 32MHz. In addition,
the maximum power dissipation by the counter is 95mW. Figure-8.1 shows the pin diagrams
of LS192 and LS193 counters.
Experiments with Digital ICs
84
8.2
Laboratory Experiments Series
Input
DCBA are binary input to the counter which can be loaded at the output of the counter by
taking the load terminal to Logic LO when the Load terminal comes back to HI the counter
starts counting from the loaded value and continues to count up to 1111 (15) and resets to
0000 at the arrival of 16th clock pulse. This is very useful input predetermined value. It finds
extensive applications in stop clock applications to start system at a predetermined time or
shut down the system at a predetermined time.
B
1
17
Vcc
QB
2
16
A
QA
3
14
CLR
Down
4
13
BO/
Up
5
12
CO/
QC
6
11
LOAD/
QD
7
10
C
8
9
D
GND
74LS192/193
15
1
10
9
5
4
11
14
A
B
C
D
QA
QB
QC
QD
UP
DN
LOAD
CLR
CO
BO
3
2
6
7
12
13
74LS193/192
Figure-8.1 Pin diagram of 74LS192/193 Synchronous counter
8.3
Clock input UP and DOWN
These two terminals are clock inputs to the counter. A square wave input or a mono pulse at
this input initiates the counting. When Up is inputted with clock signal the counters start
counting in the upward direction in the increasing order. When the down terminal is inputted
with clock signal the counter starts counting downward in decreasing manner. With input
load at DCBA terminals, the counting starts from the loaded input value.
8.4
Output QD Q CQ B QA
BCD outputs are available at the output terminals QD QC QB QA, which directly drive BCD
display.
8.5
LOAD
The load terminal is active low. When load terminal is taken to logic LO the input set on the
input terminals DCBA is loaded and appears at the output terminals. When load terminal is
taken back to HI the counter is ready to count at the arrival of clock pulse.
8.6
Clear (CLR)
Experiments with Digital ICs
Laboratory Experiments Series
85
Clear is also active low control signal. A logic HI at the clear input clears the counter and the
output becomes 0000. When clear terminal is taken back to LO the counter is ready to count
from the beginning.
8.7
Borrow and carry (BO and CO)
BO is borrow input and CO is carry input. Both these are used during cascading of
LS193/192. BO is active low and is connected to DOWN input and CO is connected UP
input.
8.8
Instruments Used
Digital trainer DIC201 with 5V power supply, logic monitors, HI-LO switches, monopulse
and 1KHz clock signal, breadboard and dual trace CRO.
8.9
Components Used
IC 74LS193, 74LS04
8.10 Experimental Procedure
The experiment consists of three parts
Part-A, Down counting
Part-B, Up counting
Part-C, Cascading counters
Part-A, Down counting
1. The circuit is rigged as shown in Figure-8.2 using 74LS193 IC and 74LS04.
2. The input DCBA are connected HI-LO switches and DCBA is set to 0000. The counter is
cleared by taking CLR control to Logic HI (5V) and brought back to Logic LO. Now the
counter is cleared off its memory.
3. The Load is taken to Logic HI, the counter is now ready to count the pulse.
4. First pulse is applied by pressing the monopulse micro switch. The output now reads as
QD QC QB QA = 1111 on the logic monitors.
5. Second pulse is applied and the corresponding output is noted on Table-8.1. Application
of pulse is continued until the 15 plusses and the 16th pulse sets counter back to 1111.
6. The load terminal is held at logic LO and input DCBA=0110 is set on the input HI-LO
switches. When Load is taken to high the input is loaded in to the counter, hence the
counter out put becomes
QD QC QB QA = 0110
Experiments with Digital ICs
86
Laboratory Experiments Series
7. Now mono pulse is applied and the down counting starts from 0110. After the first pulse,
the output becomes 0l01. Further pulses reduce the count by one. The corresponding
outputs obtained are tabulated in Table-8.1.
To Logic Monitors
+5V
Load
Input
+5V
+5V
LOAD
16
Reset
7
6
2
4
74LS193/192
74LS04
Pin 14 +5V
Pin 7 GND
3
11
Count
CLR
QD QC QB QA
Down
14
Count
8
2
1
Mono Pulse
74LS04
10
D
9
1
C
B
To HI-LO
Input
Switches
15
A
Figure-8.2, Down counting circuit diagram
Pulse
0
1
2
3
15
16
0
1
2
3
6
7
Table-8.1
Load
DCBA
QD QC QB QA
0
0000
0000
1
0000
1111
1
0000
1110
1
0000
1101
1
0000
0000
1
0000
1111
0
0110
0110
1
0110
0101
1
0110
0100
1
0110
0011
1
0110
0000
1
0110
1111
Pulse down counting
8.11 Output waveforms
The clock input is replaced by 1KHz square wave signal instead of monopulse. The counter
starts counting down ward. However, the entire monitor LED glows, you will not be able to
see the change in the states because of high frequency. Using a CRO the output can be now
recorded one by one compared to previous.
8. The monopulse is replaced by 1KHz clock signal. The clock signal is monitored on
channel-A of the CRO, one among the four outputs is monitored on channel-B at time,
and the waveforms are recorded as shown in Figure-8.3. After sketching one of the
Experiments with Digital ICs
Laboratory Experiments Series
87
outputs the next output, waveform is monitored and the waveforms are recoded for all the
four outputs. It is seen from the waveform the frequency of the output is given by
f ox =
1
2x
…2
f CLK
Where x = 1,2,3,4 and fCLK is the clock frequency
Clock 1KHz
QA 500Hz
QB 250Hz
QC 125Hz
QD 62.5Hz
Figure-8.3, Output waveforms
Part-B, Up counting
Pulse
0
1
2
3
15
16
0
1
2
3
7
8
Table-8.2
Load
DCBA
QD QC QB QA
0
0000
0000
1
0000
0001
1
0000
0010
1
0000
0011
1
0000
1111
1
0000
0000
0
1000
1000
1
1000
1001
1
1000
1010
1
1000
1011
1
1000
1111
1
1000
0000
Pulse up counting
9. The experiment is continued by connecting the clock to Up input. Clock terminal is
connected to monopulse, load is taken to LO, and input DCBA is set to 0000. When load
comes back to HI the counter is ready for counting. The first pulse is applied and the
output QD QC QB QA = 0001 is noted in Table-8.2.
10. Input is now set to 1000 and load is taken to LO. This loads the input and the output now
becomes QD QC QB QA = 1000. Load is taken back to HI and pulse is applied. The output
Experiments with Digital ICs
88
Laboratory Experiments Series
is incremented by one and process continues with the application of pulses. The output
observed is recorded in Table-8.2.
Part-C, Cascading counters
11. The circuit is rigged as shown in Figure-8.4 with two LS193 ICs. This becomes 8-bit updown counter.
Count
+5V
Load Input
To Logic Monitors
+5V
QH QG QF
16
7
6
2
+5V
11
3
4
74LS193/192
5
8
10
H
9
G
1
15
F
E
To HI-LO
Input
Switches
To Logic Monitors
SW SPDT
QE
11
DOWN BO
UP
14
CO
16
QD QC QB QA
7
6
2
74LS04
Pin 14 +5V
Pin 7 GND
3
13
2
4
74LS193/192
12
Mono Pulse
74LS04
8
14
1
Down
10
D
Clear +5V
Count
9
C
1
15
B
A
To HI-LO
Input
Switches
SW SPDT
Figure-8.4, Cascaded 8-bit up-down counter
12. Mono pulse is fed through the inverter to Down input. Pin 14 CLR is taken to logic LO
and when CLR returns to HI the counter is ready to count and the output becomes 1111
1111.
Table-8.3
Pulse
Load
HGFE DCBA Q H QG QF QE QD QC QB QA
0
0
0000 0000
1111 1111
1
1
0000 0000
1111 1110
2
1
0000 0000
1111 1101
255
1
0000 0000
0000 0001
256
1
0000 0000
1111 1111
0
0
1100 0011
1100 0011
0
1
1100 0011
1100 0011
1
1
1100 0011
1100 0010
2
1
1100 0011
1100 0001
3
1
1100 0011
1100 0000
8-bit cascaded down counting
13. The inputs 0000 0000 (HGFE DCBA) is set on HI-LO switches. And LOAD (Pin 11) is
taken to HI. First monopulse is applied by pressing monopulse micro switch. The output
now reads
1111 1110.
Experiments with Digital ICs
Laboratory Experiments Series
89
14. Application of monopulse is continued and the corresponding output is noted in Table8.3.
15. After reaching 255th pulse, the counter resets at the 256th pulse to 1111 1111. Now the
LOAD signal is set to LO and input is set to 1100 0011 on the HI-LO input switches.
LOAD is taken back to HI and output now reads 1100 0011.
16. Monopulse is applied and corresponding out put is noted in Table-8.3.
17. Feeding monopulses to UP input is continued and the outputs are recorded in Table-8.3.
8.12 Results
1. The 4-bit up down counter is reset with HI CLR signal and when CLR comes to LO the
counter is ready to count.
2. The preset inputs are loaded to the counter, by taking LOAD to HI and when LOAD
comes back to LO counting starts from the loaded input value.
3. When clock pulses are fed, to UP input the counter starts counting towards the upper side
and when the clock pulses are fed to DOWN input counter starts counting down.
8.13 Discussion
Fundamental principles of counter operation are studied in this experiment. Cascading the
counter to count more number of bits is verified. In actual practice instead of DC, inputs AC
inputs are used. In this experiment by feeding time varying signal to the inputs the counting
process is verified.
References
[1]
Texas Instruments, TTL logic Standard TTL, Schottky, Low power Schottky Data
Book,1988, Page 2-633
Experiments with Digital ICs
90
Laboratory Experiments Series
Experiment-15
BOOLEAN FUNCTION GENERATOR
Abstract
A Boolean function generator circuit is constructed using a multiplexer and an
analog to digital converter. The output pulses are recorded and output voltage is
estimated from the output pulse waveform.
9.1
Introductions
A Boolean function generator [1,2] is logic circuit which converters 0-5Volt dc signal in to a
pulse waveform. For a given voltage range there is a definite number of logics states each of
that is represented by a pulse waveform. A Boolean pulse generator consists of a analog to
digital converter (ADC) [3] and a multiplexer (MUX). The input is the continuously variable
dc voltage is fed to ADC and the output of the ADC drives the MUX. The MUX output is a
serial output and it is called Boolean function. Such function generator is useful in digital lab
for data communication experiments.
9.2
TTL Multiplexer-74LS151
A multiplexer is a data selector. It has many inputs and one output terminal. TTL series
74LS151 is a eight-to-one data selector with eight input lines and one output line with its
compliment. Figure-1 shows pin diagrams of LS151 [2]. In Figure-9.1 terminals D7 – D0 are
the eight input lines and Y is the out with its compliment W. ABC are the control signals
which guides the MUX to select any one input line from the eight inputs. ABC varies from
000 to 111. There are an eight logic state between 000 to 111 each of this state represents an
address to the MUX. Depending on this address corresponding input is steered to the
output.G is the strobe control,
Vcc
4
3
2
1
15
14
13
12
11
10
9
7
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
G
16
W
Y
6
5
8
74151
GND
Figure-9.1, MUX74LS151 Pin diagram
and it is active low. When strobe is high the MUX is inactive. Table-9.1 shows the functional
table of MUX. With low strobe, input is steered to the output. ABC decides which input is to
be connected to the output.
Experiments with Digital ICs
Laboratory Experiments Series
Table-9.1
B
C
Y
G
X
X
1
0
0
0
0
D0
0
1
0
D1
1
0
0
D2
1
1
0
D3
0
0
0
D4
0
1
0
D5
1
0
0
D6
1
1
0
D7
Function Table LS151
A
X
0
0
0
0
1
1
1
1
91
W
1
D0
D1
D2
D3
D4
D5
D6
D7
The output voltage of the Boolean function generator is given by
Y= G [(CBA) D0 + (CB A) D1 + (C BA) D2 + (C B A) D3 + (CBA) D4 + (CB
A)
D5 + (C B A) D6 + (C B A) D7]
W = Y
9.3
Control Signals ABC
Two bits A and B have four different states 00,01,10 and 11. Using HI-LO switches it is
possible select any one state out of the four different states. The same thing is also done by
two square wave signals of frequency 1KHz and 2KHz [3]. In general a rectangular pulse of
frequency f and f/2 generate four different states of the 2 bits. Similarly three bits require f,
f/2 and f/4 frequencies to generate eight different states. ABC is selected as f, f/2, f/4
respectively. The fundamental frequency f is termed as clock. In this experiment f is selected
around 5KHz. Any frequency in the range 1 to 10KHz is suitable for this purpose. Further
clock frequency need not be very accurate because it is divided exactly to its half and onequarter value by flip flop ICs. The division is very accurate. Figure 2 shows three rectangular
pulses generating eight different states. ABC acts like steering signal or the address line to the
MUX. To read the content of the input, MUX takes only four clock cycles. Hence within
four-clock pulse cycle all the eight inputs are steered to the output of the MUX. Hence the
output of the MUX look like a pulse train. If the inputs to the MUX is D7…. D0 equals
11011001 the output looks as shown in Figure-3. For 8-bit input there are 256 different states
hence there are 256 different pulse trains similar to the one shown in Figure 3. Hence it is
called Boolean function generator. To get 256 different waveforms the input to the MUX is
fed from ADC [4].
Experiments with Digital ICs
92
Laboratory Experiments Series
The control signals are generated using a 555 IC and divided using JK flip flop 74LS107 as
shown in Figure-9.4. The frequency of the rectangular pulse generated by the 555 IC is given
by [5]. The first half of FF divide A in two half resulting in B, C is half B and G/ (G ) is half
of C.
T
5.57KHz A
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2.78KHz B
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1.39KHz C
690Hz
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
G/
Figure-9.2: Various control signals generating 8 different logic states
D0
1
D7
0
0
1
1
1
1
1
Figure-9.3: A Boolean function waveform
+5V
10K
7
10
8
1
4
10K
4148
4
3
555
13 14
LS107
12
3
11
1
8
4
LS107
9
5
13
14
LS107
12
3
4148
2,6
A
1
5
7
B
C
7
G
0.01uF
0.01uF
Figure-9.4: Various control signals
f =
1.44
C(R A + R B )
…1
Experiments with Digital ICs
Laboratory Experiments Series
9.4
93
Instruments Used
DC regulated power supply 5V/1A,digital multimeter and CRO.
9.5
Components Used
IC 555, 74LS107, 74LS151, ADC0804. Resistors 10K, Capacitors 0.1µF, 0.01µF, 150pF,
diodes 4148 and 10K 10 turn 3296 type trim pot and solderless bread board.
9.6
Experimental Procedures
The experiment consists of three different parts.
Part –A: Generation of control signals ABC and G
Part –B: Response of MUX
Part –C: Boolean Function Generation
Part –A: Generation of control signals ABC and  G
1
To generate controls signal the circuit is rigged as shown in Figure-9.4. The Signals
are observed on CRO and its frequency is noted. The fundamental signal A is called
the clock. The various signals are sketched using graph sheet as shown in Figure-9.2
A – 5.57KHz
B – 2.78KHz
C- 1.39KHz
G - 696 Hz
Part –B: Response of MUX
2
The circuit is rigged as shown in Figure-9.5. The control signals are connected to the
MUX. The strobe signal G is monitored on CRO channel A. The output Y of the
MUX is monitored on CRO channel-B.
3
Input D0 … D7 is set by connecting few inputs to GND and few to VCC. The input set
is
10011011
Connecting D0 D3 D4 D6 D7 to +5V and D1 D2 D5 to GND does this.
4
The output Y and W are recorded in compared G . In the CRO D0 appears first on the
left-hand side of the screen.
5
Trial is repeated by setting different inputs and the corresponding outputs are verified
on CRO screen.
Experiments with Digital ICs
94
Laboratory Experiments Series
G
7
+5V
16
GND
8
C
B
A
9
10
11
Y
5
74LS151
12 13 14 15 1
2
3
D7
6
4
W
D0
Figure-9.5: MUX producing sequence of pulses
C
B
A
9
10
11
G
G
7
+5V
16
GND
8
12 13 14 15 1
2
3
6
4
PD0
11 12 13 14 15 16 17 18
+5V
DAC 0804
Vin
6
W
D0
PD7
TP1
10K
3296 Type
Y
74LS151
D7
SF 3
5
20
1 2
5
7
19
10K
4
8 10
150pF
+5V
Figure-6 Boolean Function Generator
Part –C: Boolean Function Generation
1. To get Boolean function generator an ADC added as shown in Figure-9.6. A 10-turn 3296
type trim pot is selected to vary the input to the ADC0804.
2. The input Vin to the ADC is set around 1 volts by adjusting the trimpot PT1. The output
of the MUX is monitored on Channel-B and channel-A A of the CRO is connected to G .
Experiments with Digital ICs
Laboratory Experiments Series
95
The output noted is recorded as shown in Figure-9.7. From the pulse position on CRO the
input dc voltage producing the pulse train is calculated using equation.
Vo = R [27D7 +26D6 +25D5 +24D4 +23D3 +22D2 +21D1 +D7]
…2
Where R =19.53 mV is the resolution of ADC 0804. The readings obtained are tabulated
in Table-9.2. The pulse sequence on the CRO screen in Figure –9.7 is read as 001000110
the input dc voltage corresponding to this pulse waveform is
Vo = 19.53 [128x0 +64x0 +32x1 +16x0 +8x0 +4x1 +2x1 +0] mV = 0.742volts.
8. Experiment is repeated by setting different input and from the resulting pulse train input
producing it is calculated. Table-9.2 shows few such calculations. The values calculated
tallies with actual dc voltage measured using DMM.
Figure-9.7 A pulse sequence
Table-9.2
Pulse Sequence Estimated Output(V)
Vin(V)
0.75
01100100
0.742
4.50
00010111
4.53
0.45
00011000
0.468
4.04
11010011
3.96
5.00
11111111
4.99
Voltage estimated from pulse sequence
9.7
Results
1. Boolean function generator converts dc input voltages into pulse train just like a VCO
generating waveform. Pulse is generated with LO G . When the input is zero volts there is
no pulse output and when the input is 5V the pulses waveform appears like G (inversion
of G .
Experiments with Digital ICs
96
Laboratory Experiments Series
2. In the CRO pulse train on the left corresponds LSB. It reads as D0 D1 D2 … D7. The
estimated input coincides with the actual input voltage.
9.8
Discussion
Boolean pulse generator or sequence generator or digital signal generator produces pulse
train. It is a very useful instrument for digital electronics lab. Instrument finds applications in
digital communication and data communication experiments.
References
1. Malvino A P, Brown J A, Digital computer electronics, 3rd Edition, 1995, Tata McGrawHill, Page 58.
2. Texas Instruments, TTL logic standard TTL, Schottky, Low Power Schottky, Page-2-457.
1988.
3. Dr Jeethendra Kumar P K, De Morgan’s Theorem, LE Vol-2, N0-1, June 2002, Page-47.
4. Uma Prasad B K, Analog to digital conversion using ADC0804, LE vol-2, No-1, June
2002, Pasge-48.
5. Dr S R Sawant, Wide range duty cycle variation in 555 astable multivibrator, LE Vol-2,
No-1, June 2002, Page 29.
Experiments with Digital ICs
Laboratory Experiments Series
97
Experiment-16
SEQUENTIAL LOGIC
MACHINE
Abstract
Basic counting sequence of 10-output sequential logic circuit is studied using
CD4017 decade counter IC. The output waveforms are recorded and function of
RST is studied in obtaining different mod-N counting. Two ICs are cascaded to
get mod-20 counter.
20.1 Introduction
A counter is a sequential logic machine, the output of which depends on the past and current
input values. Flip-flops are the fundamental building blocks of a counter. The D and JK flipflops are used in the construction of counter circuits. In such a counter, each of these flipflops contains Preset (PR) and Clear (CLR) terminals. The counter output can be preset
(Q=1) or cleared (Q=0) using these control terminals. Such counters are called asynchronous
counters. Asynchronous counters are slow. A synchronous counter waits for a clock edge
(either positive going or negative going) to change its state. Such counters does not have
preset terminal only clear terminal is provided. Synchronous counters are faster. It is widely
used counters in electronic circuits. Counters constructed using flip-flop ICs are
asynchronous counters and counter ICs are synchronous counters.
20.2 Family of digital counters
The LS and CD family of ICs are frequently used in electronics circuit design. Among them
the LS series, LS90, LS160, LS190 and CD 4000 series, ICs such as 4017 and 4022 are
frequently used. Table-1 lists the various counter ICs.
Important operational aspect of a counter is the clock signal. Clock signal becomes the
control input to the counter and instructs the counter to change its state. A bad clock will
make counter behave poorly. Hence, clock signal has to be perfect square wave. It is better to
pass the clock through an Schmitt trigger and get it signal conditioned before feeding to the
counter [1]. A counter is called good if it satisfies the following basic requirements.
1. Feasibility of making Mod-N counter (N=2,3,4,5,6…)
2. Cascading options
If the counter IC fulfills these basic requirements then it is a very good counter. For example,
LS90 is a divide by 2 (Mod-2), divide by 5 (Mod-5) and divide by 10 (Mod-10) counter.
Experiments with Digital ICs
98
Laboratory Experiments Series
CD4017 has 10 output terminals hence one can get Mod-N (N=2,3,4,5,6,7,8,9,10) counting
sequences hence 4017 is better compared to LS90. Both the ICs can be easily cascaded to get
higher bit counting.
Table-20.1
Family
74LS90
74LS192
74LS160
74LS190
74LS290
74LS390
74LS490
74LS590
74LS592
74LS690
CD4017
CD4022
Part No
LS90
LS192, LS193
LS160, LS163
LS190, LS193
LS290, LS293
LS390, LS393
LS490
LS590, LS591
LS592, LS593
LS690,
LS691, LS693
4017
4022
Description
TTL decade counter
TTL 4-bit ripple counter
TTL 4-bit synchronous counter
TTL synchronous up-down counter
TTL decade 4-bit binary counter
TTL dual 4-bit decade counter
TTL 4-bit decade counter
TTL 8-bit binary with output registers
TTL 8-bit binary with input registers
TTL Synchronous counters with out put
registers and multiplexed 3 stage output
CMOS Counter with 10 output terminals
CMOS divide by 8 counter with 8 output
terminals
CMOS presentable up/down counter with
binary or BCD decade outputs
CMOS decade counter with 7 segment
display outputs
Dual Up counter with BCD outputs
Various counter ICs
CD4029
4029
CD4033
4033
CD4518
4518
When we require a large bit counting two or three counter ICs are cascaded. In such cases
clock for the second IC is taken from the MSB output of first IC. In the case of 4017, a
separate terminal is provided for cascading purpose. This pin provides required clock (fin /10)
signal for the next stage.
Another important factor that decide the goodness of counter performance is the up down
counting process and counting from the predetermined value. ICs 74190/193 are up-down
presetable counters [2]. These counters are called advanced counters. In general, TTL
counters are slower compared to CMOS counters. In this experiment the basic operations of
4017CMOS counter is studied.
20.3 CD4017 CMOS Counter/divider with 10 decoded outputs
CD4017 is a 16-pin IC quite different from other counter ICs. Out of the 16 pins two are used
for supply, 10 output terminals; the remaining four form the control terminals. Lesser the
control terminal easier is the usage. Hence, it is one of the easy to use IC. The four control
terminals are
1. Reset (RST)
Experiments with Digital ICs
Laboratory Experiments Series
99
2. Clock (CLK)
3. Clock enable (ENA or CE)
4. Carry out (CO)
Figure-20.1 shows pin diagram of CD4017.
14
13
15
CLK
ENA
RST
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
3
2
4
7
10
1
5
6
9
11
12
Figure-20.1: CD4017 pin diagram
The counter counts on the positive edge of the clock signal applied to the CLK input,
provided the clock enable (ENA or CE) is low. A high on any of the output terminals indicate
the count. For example, if only Q7 is high then the counter is counted 8 clock edges. If Q3
only is high then the counter has counted only 4 clock edges. At the 10th clock edge the
counter reset and repeats counting. Like wise it can count from 0 to 9 or it is decade counting.
The counting is similar to ring counting hence it is also a ring counter.
The carry out terminal CO provides a rectangular clock for cascading purpose. This clock
frequency is fin/10. If the input clock frequency is 1MHz then 100KHz square wave appear at
pin CO.
20.4 MOD-N counter
Any modulo N counting with N = 2 to 9 can be obtained by connecting respective output pin
to the RST control pin. For example to get Mod-7 counter Q7 output pin is connected to RST
(pin 15). To get Mod-3 counting pin Q3 is connected to RST.
20.5 Instruments Used
Digital IC trainer containing 5 or 15-volt power supply, logic monitors, clock signals, CRO.
20.6 Components Used
CD4017 IC
20.7 Experimental Procedure
The experiment is divided in to three parts
Part A- Decade counting
Experiments with Digital ICs
100
Laboratory Experiments Series
Part B –Mod-N counting
Part C- Cascading counter ICs
Part A- Decade counting
1. The circuit is rigged as shown in Figure-2.
+5V
16
CLK
3
14
Q0
2
4
+5V
Reset
RST
7
15
Outputs
to logic
monitors
10
1
Count
NC
CO
CE
CD4017
12
5
6
9
13
11
8
Q9
Figure-20.2: decade or ring counter circuit using CD4017
2. The RST terminal is connected to Logic-HI and the counter resets to
Q9 , Q8, … Q0 = 0, 0, …0
3. RST is brought back to Logic –LO and the first monopulse is applied to the clock input.
The changes in the output states are noted in Table-2.
4. Trial is repeated by applying monopulses one at a time and the outputs are recorded in
Table-2. The process of pulse counting is similar to ring counting. Hence, the counter can
also be called as ring counter.
5. To record the output waveforms, the monopulse connected to the CLK input is replaced
by 1KHz square wave and the input clock is monitored on CRO channel-A. At a time one
output among Q9 , Q8, … Q0 is monitored on CRO channel-B in compared to input clock.
The waveforms are recorded as shown in Figure-3. Transition taking place at the positive
going edge is verified from Figure-3.
6. With 1KHz clock input the output at C0 pin is monitored and its frequency is noted.
fCLK = 1Khz =1msec
Experiments with Digital ICs
101
Laboratory Experiments Series
fCO = 100Hz = 10msec
Table-20.2
Monopulse (CLK)
Output (Q9, Q8, … Q0)
RST is held HI counter is reset
00 00000000
RST is held LO counter ready for counting
00 00000000
First monopulse is applied
00 00000001
Second monopulse is applied
00 00000010
Third monopulse is applied
00 00000100
Fourth monopulse is applied
00 00001000
Fifth monopulse is applied
00 00010000
Sixth monopulse is applied
00 00100000
Seventh monopulse is applied
00 01000000
Eighth monopulse is applied
00 10000000
Ninth monopulse is applied
01 00000000
Tenth monopulse is applied
10 00000000
Eleventh monopulse is applied
00 00000000
Counting sequence of Cd4017
1
2
3
4
5
6
7
8
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Figure-20.3: Output waveforms of the counter
Experiments with Digital ICs
9
10
102
Laboratory Experiments Series
Part B –Mod-N counting
7. To get Mod-5 counter the circuit is rigged as shown in Figure-4. The RST pin is
connected to output Q5. By applying monopulses, the counting is observed as recorded in
Table-3.
8. Experiment is repeated for different mode counting by connecting respective output to the
RST pin.
Table-3
Monopulse
Output (Q9, Q8, … Q0)
-
00000
0000 0
1
00000
0000 1
2
00000
0001 0
3
00000
0010 0
4
00000
0100 0
5
00000
1000 0
6
00000
0000 0
Mode-5 Counting
+5V
16
RST
3
15
Q0
2
4
CLK
7
14
10
Q5
1
NC
CO
CE
CD4017
12
5
Outputs
to logic
monitors
6
9
13
11
8
Q9
Figure-20.4: Mod-5 Counter
Part C- Cascading counter ICs
Experiments with Digital ICs
103
Laboratory Experiments Series
9. Two 4017 ICs are cascaded to form Mod-20 counter as shown in Figure-5. The CLK
input of second counter is fed from CO of the first counter. This acts like clock to the
second counter IC.
+5V
+5V
16
RST
3
15
14
Outputs
to logic
monitors
CO
CE
12
CLK
CO
9
13
11
8
4
7
14
Outputs
to logic
monitors
10
1
5
6
Q0
2
IC1
10
CD4017
3
15
4
7
1
NC
RST
2
IC2
CLK
16
Q10
CE
CD4017
12
6
9
13
Q19
5
11
8
Q9
Figure-20.5: Cascaded Mod-20 Counter
20.8 Results
1. The counting sequence shown in Table-2 is similar to ring counting hence it is called a
decade/ring counter.
2. Counter counts when count enable CE is low.
3. Mod-2 to 9 counting is obtained by connecting respective Q output to reset RST pin. In
Figure-4, Mod-5 counter is shown.
4. The frequency of CO output is fCLK/10.
20.9 Discussions
CD4017 is a wonderful counter because of its 10 outputs using which ten systems or gadget
can be activated or deactivated. Disconnecting respective outputs can perform deactivation of
the output from the load to which it is connected. Secondly cascading is extremely easy and
more reliable because of the terminal CO. As soon you feed the clock at CLK input there
exists clock at CO, which makes the cascading easy. Minimum numbers of control pins
further make the designer’s job easy.
Experiments with Digital ICs
104
Laboratory Experiments Series
References
[1]
Dr D Sudhakar Rao, Schmitt trigger using comparator, Lab Experiments, Vol-4, No1, March-2004, Page-30.
[2]
T Aswathnarayana Rao, Synchronous 4-bit Up-down counter, LE Vol-3, No-2, June2003, Page 103.
Experiments with Digital ICs
105
Laboratory Experiments Series
Experiment-17
SHIFT REGISTERS
Abstract
The TTL 4-bit parallel shift register 7495 is tied to perform left and right shift
operations with serial and parallel data. The arithmetic operations resulting from
the left and right shift operations are illustrated.
Introduction
A register is a group of memory elements that work together as a unit. The simplest register
stores binary and others modify the stored data shifting it left or right. It is also used for
arithmetic operations. Shifting the data stored in a shift register to the right is equivalent to
divide by 2 and shifting the data to the right is equivalent to multiply by 2. TTL IC 7495 is a
universal 4-bit shift register containing four RS FFs and other functional blocks. Figure-1
shows pin configurations of 7495.
Figure-1: Pin Configuration of 7495
In Figure-1 serial input the serial data input terminal, and parallel data are loaded at A, B, C,
D inputs. Mode control MC directs the register load or shift the data. CLK1 & CLK2 are the
clock inputs for left and right operations.
Left Shift Operation
1. 7495 is connected as shown in Figure-2 to perform left shift operation. The serial
data Din=1 is loaded at Pin-2.
2. Mode control MC (Pin-6) is held low. Now the register is ready to load serial data
at the arrival of clock.
CLK1
1
2
3
4
Pulse
5
6
7
8
Table-1
MC
Din
QD
QC
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
0
0
0
Left Shift Truth Table
Experiments with Digital ICs
QB
0
0
1
1
1
1
1
0
0
0
QA
0
1
1
1
1
1
0
0
0
0
106
Laboratory Experiments Series
3. A clock signal (manually operated) is connected CLK2 (Pin-8). And one clock
pulse is passed. This loads the serial data at QA. The Q outputs are monitored on
logic monitors. The second clock pulse shifted QA to QB. This process of shifting
is continued at the arrival of next clock pulse. The readings are tabulated in Table1 of Din=1 and Din=0.
Right Shift Operation
4. 7495 is reconnected as shown in Figure-3 to perform right shift operation.
Figure-3: Right Shift Operation
5. Now the serial data Din is fed at D input (Pin-5).
6. Mode control MC held high and D is set to logic high. Clock is applied at CLK1.
The first clock pulse applied. This loads the serial data at QD. Successive clock
shifts the data to the right as shown in Table-2.
CLK1
1
2
3
4
Pulse
5
6
7
8
MC
1
1
1
1
1
1
1
1
1
1
Table-2
Din
QD
QC
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
Right Shift Truth Table
QB
0
0
0
1
1
1
1
1
0
0
QA
0
0
0
0
1
1
0
1
1
0
7. From Table-1, it is noted that shifting to left is equivalent multiply by 2. And from
Table-2 shift right is equivalent divide by 2.
Parallel Loading and Shifting
8. Figure-4 shows circuit connection for parallel loading and shifting.
Figure-4: Parallel Data Loading & Shifting
9. The 4-bit data ABCD-1110 are loaded at parallel data inputs. And clock is
connected to CLK1 Mode control to 1. This loads ABCD and displayed at the
outputs. When MC is taken back to 0 the data is ready for left shift operation. The
successive clock pulses shifts data left as shown in Table-3.
Data
A
1
B
1
C
1
D
0
Experiments with Digital ICs
Laboratory Experiments Series
107
Table-3
MC QD
QC
QB
QA
1
1
1
1
0
1
0
1
1
0
0
2
0
1
0
0
0
3
0
0
0
0
0
Parallel Loading & Left Shift Truth Table
CLK2
Results
1. 7495 accepts serial data at serial input and 4-bit parallel data at its parallel data
input.
2. Serial input can be shifted left or right by controlling clock and mode control
signals. Pulse on CLK2 and low MC perform left shift operation on serial data.
This is also equivalent to multiplication by 2 – arithmetic operation. Pulse CLK2
and a high MC shifts the data to the right and the operation is equivalent to divide
by 2.
3. 4-bit parallel data can be loaded at ABCD and a low MC and pulse on CLK2
perform left shift of parallel data. A high MC and pulse on CLK2 perform to right
shift of parallel data.
Reference
[1]
LS/S/TTL Data Book, National Semiconductor, 1989, Page 4-101.
Experiments with Digital ICs
108
Laboratory Experiments Series
Experiment-18
RIPPLE COUNTER
Abstract
Using two dual JK master slave flip flop a 4- bit forward and reverse ripple
counters are constructed. The counters is modified to count 0 to 10 (Mod-10) and
0 to 5 (Mod-5). The various output waveforms of the FFs are studied on a
oscilloscope at high clock frequency, and frequency division is illustrated. Once
doing this experiment the students must be in a position to construct counters with
any modules.
Introduction
A counter is a register capable of counting the number of pulses that arrive at its clock input.
In a JK FF with J=K=1, the FF toggle once per clock. This toggling is made use here in the
counting applications. The JK FF 7476 is provided with SET and RESET terminals plus
complimentary outputs Q and Q. This makes it possible to construct forward (Up) and or
reverse (Down) counter. In figure-1 pin configurates of 7476 is shown.
Figure-1: Pin Configuration of7476
Figure-2: Forward Ripple Counter
Figure-3: Reverse Ripple Counter
In Figure -2 two 7476 s are tried to form a 4-bit up counter.
When CLR goes low it resets the output. Therefore the Q outputs
Q = Q3 Q2 Q1 Q0 = 0 0 0 0
When CLR returns to high the counter is ready to count. The FF on the right and (LSB) first
receive a clock pulse and toggle. Then the output becomes.
Q=0001
The remaining FFs toggle less often became they receive their clock pulse from the preceding
FF. When Q0 goes from 1 to 0 it sends a clock pulse to Q1 FF, hence the second FF toggle
resulting in a output.
Q=0010
Now the first FF has toggled twice and second FF once. This process continue until
Experiments with Digital ICs
Laboratory Experiments Series
109
Q = 1111
Now the counter can be reset with low CLR.
In this process of binary counting the carry moves through FFs like a ripple on water. In other
words, Q0 FF must toggle before Q1FF, which in turn must toggle before Q2 FF and hence
forth. Here each FF act like a wheel of a binary odometer. Whenever it resets to 0, it sends a
carry to the next higher FF making it equivalent to a binary odometer.
To get reverse counter the FFs are tied as shown in Figure-3. The set terminal is made use for
setting Q= 1111 t o start with. And preceding FF clock inputs are driven by Q instead of Q.
The process of counting is similar to up counter.
MOD-10 COUNTER
The FFs can be programmed to SET or RESET after a desired count. The above binary
counter counts from 0 to 15 with 16 states.
Figure-4: Mod-10 Counter
Figure-5: Mod-5 Counter
Hence it is Mod-16 counter. A Mod-10 counter counts from 0 to 9 and resets at the 10th clock
pulse. Similary Mod-5 counter counts from 0 to 4 and resets at 5th clock pulse. Figure -4 & 5
shows Mod-10 and Mod-5 counter tied over 7476.
In Figure-4 & 5 the counter can be reset with low CLR or low Y. Intially CLR taken low and
counters reset. When CLR goes back to high counter is ready to go. The Y output
Y = Q 3 Q1
is high for first nine states from 0 0 0 0 to 1 0 0 1. Therefore, nothing serious happens when
the counter is counting from 0 to 9. However, on the 10th clock pulse the Q output.
Q= Q3 Q2 Q1 Q0 = 1 0 1 0
Which means that Q3 & Q1 are high. Almost immediately Y goes low forcing the counter to
reset to
Q=0000
Y then goes high and the counter is ready to start again. In case of Mod-5 counter shown in
Figure -5
Y = Q2 Q0
Experiments with Digital ICs
110
Laboratory Experiments Series
When the counter is counting from 0 0 0 0 to 0 1 0 0, Y is high. At the instant of 5th clock
pulse the output becomes
Q=0101
This takes both Q2 Q0 high, hence Y = 0 and the counter is reset to
Q=0000
Again the counter starts as before.
Experimental Procedure
A.
Forward Ripple counter
1. A forward ripple counter is rigged as shown in Figure -2. Pin-5 is connected to +5 V
and pin-13 to GND of both the ICs
2. Q0 Q1 Q2 & Q3 are connected to logic monitors
3. A mono pulse is connected to the clock input (Pin- 1)
4. CLR is taken low and all the FFs reset
In this state clock pulses doesn’t have any effect on FF
5. CLR is taken to high and the first clock pulse is applied by pressing the mono pulse
Microswitch
6. The output Q3 Q2 Q1 Q0 = 0001 is noted and recorded in Table -1
7. Experiment is repeated by sending more pulses and the outputs are recorded in
Table-1
CLK
0
1
1
1
1
1
1
1
1
1
1
1
1
CLK
X
1
2
3
4
5
6
7
8
9
10
11
12
Table-1
Q2
Q3
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
Experiments with Digital ICs
Laboratory Experiments Series
1
1
1
0
13
14
15
X
1
1
1
0
1
1
1
0
0
1
1
0
111
1
0
1
0
8. Instead of mono pulse a 1KHz clock is connected to clock input (Pin -1). The first FF
output Q0 is connected to oscilloscope and compared with the clock signal. The
oscilloscope traces are noted. Next Q1 Q2 & Q3 are also compared with clock and
recorded as shown timing diagram.
Figure -6: Timing Diagram of forward Counting
B.
Reverse Counter
1. A reverse counter is constructed as shown in Figure -3. Pin- 5 is connected +5V and
pin -13 to GND both of the ICs.
2. The Q outputs Q3 Q2 Q1 Q0 are maintained on logic monitor.
3. A mono pulse is connected to clock input.
4. PRE is taken low. This SETS the Q outputs to Q = 1111. Then PRE taken back to
high and the counter is ready to count down.
5. First mono pulse is applied by pressing mono pulse switch. The decrement in the out
put is noted and recorded in Table-2.
CLK
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
CLK
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
X
Table-2
Q2
Q1
Q3
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
Down Counting
Q0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Experiments with Digital ICs
112
Laboratory Experiments Series
6. Instead of mono pulse 1KHz clock signal is fed to clock input and Q outputs are
monitored on oscilloscope one by one with respect to clock signal. The wave forms
are recorded in timing diagram below.
Figure-7: Timing diagram of count down
C. Mod -10 Counter
1. A mod -10 counter is connected as shown in Figure -4 pin -5 of 7476s are connected
to +5V and 13 to GND. Pin -14 of 7400 and 7408 are connected to +5V and pin -7 to
GND.
2. The Q outputs are monitored on logic monitors
3. A mono pulse is connected to clock input.
4. The counter is reset taking CLR low
5. CLR is bought back to high and first pulse is applied. The output is noted and
recorded in Table -3. Resetting of the counter at the arrival of 10th pulse is noted.
CLK
0
1
1
1
1
1
1
1
1
1
1
Y
1
1
1
1
1
1
1
1
1
1
0
Table-3
CLK
Q3
Q2
Q1
X
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
1
7
0
1
1
8
1
0
0
9
1
0
0
10
0
0
0
Decade Counter Truth Table
Q0
0
1
0
1
0
1
0
1
0
1
0
D. Mod -5 Counter
1. A mod -5 counter is constructed as shown in Figure -5 and experiments are repeated
as in previous case. The counting sequence is presented in Truth Table -4.
Results
1. A forward and a reverse ripple counter is constructed using JK flip flop. This Mod -16
counter is modified to count from 0 to 10 or 0-5. This is done by providing a reset
pulse obtained by NANDing selective Q outputs.
Experiments with Digital ICs
Laboratory Experiments Series
113
2. Other modules counter can be constructed by suitably selecting reset pulse.
3. The frequency divisions of ripple counter is noted for forward and reverse counter.
References
1. LS/S/TTL logic Data Book. National Semi conductor, 1989, P 4-81.
2. Digital Computer Electronics, 2nd Ed., AP Matrino, TMH Edition, 1983, P-112.
Experiments with Digital ICs
114
Laboratory Experiments Series
Chapter-5
Multiplexers and
Demultiplexers
Experiments with Digital ICs
115
Laboratory Experiments Series
Experiment-19
DECODER
Abstract
The basic line selection function of a3to 8-line decoder is studied using 74LS138
TTL IC. The function of enable control in the line selection process is verified.
4.1 Introduction
A decoder [1] is a logic circuit, which identifies each combination of input and sets an output
corresponding to each of these input combinations. Figure-4.1 shows 2-to-4 decoder. It has
two input lines A and B and four output lines. The two inputs can assume four output
combinations 00,01,10,11. The output lines 0,1,2,3 identify each of these combinations
respectively. If the input is 10 the output line 2 goes HI and all other output lines remains at
LO. Table-4.1 summarizes the line selection process. Decoders can be constructed either
using universal gates or ready-made ICs are also available.
A
INPUT
3
2-to-4
2
DECODER 1
B
OUTPUT
0
Figure –4.1: 2-to-4 Decoder Logic symbol
4.2 74LS138
The TTL IC 74LS138 is a 3-to-8-line decoder widely used for high performance memory and
data routing applications. This 16 pin TTL IC has three input lines S0S1S2 and eight output
lines Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7. And it is controlled by three control signals G1, G 2A and
G 2B. The signals G1 are active HI and G 2A and G 2B are active LO. Figure-4.2 shows pin
configurations of LS138 [2].
Table-4.1
Input
A
0
0
1
1
Output
B
0
1
2
0
1
0
0
1
0
1
0
0
0
0
1
1
0
0
0
Function Table 2-to-4 Decoder
Experiments with Digital ICs
3
0
0
0
1
116
Laboratory Experiments Series
Two active low ( G 2A and G 2B) and one active HI (G1) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one inverter. An enable input can be
used as data input for de-multiplexing applications [23].
1
2
3
A
B
C
6
4
5
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2A
G2B
15
14
13
12
11
10
9
7
74LS138
Figure-4.2: Pin diagram of 74LSD138
4.3 Apparatus Used
Digital IC trainer DIC 201 KamalJeeth make Consisting of 5V power supply, Logic
monitors, HI-LO memory input switches and HI-LO toggle switches and breadboard.
4.4 Components Used
IC74138
4.5 Experimental Procedure
1. Using LS138 decoder circuit is rigged as shown in Figure-4.3. Pin 16 is connected +5V
and Pin 8 is connected to GND.
+5V
3
Inputs
2
1
G2A
S2
16
S1
7
Y7
S0
9
Y6
10
Y5
11
Y4
74LS138 12
Y3
13
Y2
14
Y1
15
Y0
4
5
Outputs
6
G2B
8
G1
Enable
Disable
Figure-4.3: Decoder Circuit diagram
Experiments with Digital ICs
+5V
117
Laboratory Experiments Series
2. Input S0, S1, S2 is connected memory cells and Outputs are monitored on the logic
monitor LEDs.
3. The control signal G1 is connected HI-LO toggle switch and it is set to HI position.
4. The output is noted for various combinations of S2S1S0 starting from 000 to 111 and the
corresponding outputs are noted and recorded in Table-4.2.
Table-4.2
S2
0
0
0
0
1
1
1
1
Input
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Output
Y7
Y6
Y5
Y4
Y3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
Function Table LS138 Decoders
Y2
1
1
0
1
1
1
1
1
Y1
1
0
1
1
1
1
1
1
Y0
0
1
1
1
1
1
1
1
5. With G1 set to LO the output is noted for various combinations. There is no change
noticed in the output (remains 11111111) hence the decoder is disabled.
4.6 Results
The TTL MSI IC 74LS138 is a 3-to-8-line decoder is enabled with HI G1 and disabled with
LO G1. The output of the 74LS138 is active low.
References
1. Microprocessor Architecture Programming Applications, Goankar, Wiley Eastern
Limited p-46, 1992.
2. TTL Logic Data Book Texas Instruments p2-45, 1988.
Experiments with Digital ICs
118
Laboratory Experiments Series
Experiment-20
DIGITAL GAIN CONTROL
FOR OPAMP
Abstract
Using CD4051B 8-channel multiplexer demultiplexer IC, Opamp feedback
resistance is switched and digital gain control is provided. Function of an 8-pole,
1- way digital switch is demonstrated in this experiment.
17.1 Introduction
Among the linear integrated circuits, Opamp is one of the widely used IC in electronic circuit
design. It has replaced most of the transistor-based circuits. Wide varieties of Opamp
applications [1] are published in various textbooks and literature. One of simplest
applications of an Opamp is the inverting and non-inverting amplifier. In these amplifiers
changing the feed back ratio varies gain. While constructing instruments using Opamps, such
gain variations are done with a help of a rotary switch as shown in Figure-17.1. These manual
and bulk switches are now replaced by electronic switches.
+12V
7
3
Vin
2
6
Vout
4
-12V
+
Rfs
S1
S2
Ri
S3
S4
S5
S6
S7
S8
Figure-17.1: Gain selection using rotary switch
An analog multiplexer is used in this experiment to select gain automatically. The digital
input to the multiplexer connects various feed back resistors across pin-2 and pin-6 of the
Opamp in the feedback loop.
Experiments with Digital ICs
119
Laboratory Experiments Series
17.2 4051B 8-Channel Analog Multiplexer/Demultiplexer
A multiplexer performs the function of many-into-one and demultiplexer performs the
function of one-into-many [2]. CMOS multiplexer CD 4051B is a digitally controlled analog
bi-directional switch that can be used as a rotary switch. These switches have a common
INHIBIT control terminal which disable all the switches to their OFF state when held in HI
state. CD 4051B is an 8-channel multiplexer or it can be used as 8 independent switches. In
the B series of ICs, the input leakage current is 100nA that means there is no loss of power in
the OFF state [3]. Figure-17.2 shows the pin diagram of 4051B. Manual switching from S1 to
S8 will connect the feedback resistors one by one to the feedback loop.
In/outputs
8
7
16
0
VSS VEE VDD
13
1
14
2
15
3
12
4
1
5
5
6
2
7
4
INH
6
3
Out/input
CD4051B
11 10 9
A B C
Figure-17.2: Pin diagram of CD4051B
The voltage gain of the non-inverting amplifier is given by,
V0 = (1 +
RF
)Vi
RI
…1
By using S1
V0 = 1 +
R F1
Vi , etc.
RI
…2
The manual switches S1….. S8 are replaced by electronic switches in Figure-17.3. Table17.1 lists various resistor selections and respective amplifier gain.
17.3 Control Signals to Analog Switch
To generate the control signal ABC, circuit shown in Figure-4 is used. One can also use 3
high-low switches to set ABC inputs. However with memory cell shown in Figure-4, only
one micro switch controls ABC. The LED’s LD1, LD2, LD3 will display the ABC status.
Experiments with Digital ICs
120
Laboratory Experiments Series
0.1
+12V
7
Vin
3
+
2
-
6
Vout
LF356
4
-12V
0.1
8
Rfs
Ri
10K
100K
150K
10K
GND
220K
390K
470K
560K
1M
-5V
+5V
7
16
13
14
15
12
3
1
5
2
4
6
CD4051B
11 10 9
A B C
Figure-17.3: Digital gain control for non-inverting amplifier
Table-17.1
Control Signal
C B A
0 0 0
Gain Voltage
2
Comments
R F is connected
1
0
0
1
11
0
1
0
16
R F2 is connected
R F is connected
0
1
1
23
R F4 is connected
1
0
0
34
R F5 is connected
1
0
1
48
1
1
0
57
R F6 is connected
R F is connected
1
1
1
101
3
7
R F8 is connected
Amplifier gain and control inputs
17.4 Apparatus Used
±5V, ± 12V RPS, Function Generator and CRO.
17.5 Components Used
IC CD4051B, LF356, 74LS107, 555,Microswitch (PMS1), Resistors 220Ω, 10K, 33K,
47K,56K,100K, 470K, Capacitors 0.01µF,1µF
17.6 Experimental Procedure
Part A: Generation of ABC control signals
Part B: Opamp gain variation
Experiments with Digital ICs
121
Laboratory Experiments Series
+5V
8
1
9
3
2
Micro
switch
Trigger
8
10
555
3
6
5
6
5
7
470K
7400 pin-14 to +5V
pin-7 to GND
4
4
2
7400
Mono-Pulse
7400
0.01
1uF
1
+5V
1/2- LS107 1
3
9
1/2- LS107
11
6
12
2
8
5
4
10
1
12
1/2- LS107
2
4
10
13
1
3
5
7404
B
LD2
74LS107 Pin-7 GND
7404 Pin-14 to +5V
pin-7 to GND
A
2
4
6
C
LD3
CLK
LD1
Figure-17.4: Control signal for the analog switch
Part A: Generation of ABC control signals
1. The circuit is rigged as shown in Figure – 17.4
2. By pressing the micro-switch the monopulse generated at the pin-3 is monitored on CRO
3. The clock signals at the FF ICs are also observed on CRO by pressing the micro-switch.
4. As the micro-switch is pressed the counting will increase as indicated by three LEDs. The
counter can be reset by taking the reset terminal to active low.
5. The ABC control inputs are now connected to the CD4051B and control signal ABC is
set to 000. For this control signal resistor R Fi = 10K is connected across pin-2 and pin-6
of LF 356. This provides a gain of 2.
Part B: Opamp non-inverting amplifier gain variation
6. The input to the non-inverting amplifier is set about 50mV and frequency is set to 10
kHz. The output of the non-inverting amplifier is monitored on the CRO and output is
noted and gain is calculated for CBA =000
Experiments with Digital ICs
122
Av =
Laboratory Experiments Series
V0
0 .1
=
= 1.92
V1 52mV
C
B A
Table-17.2
Output (V)
Gain
0 0 0
0.10
1.92
0 0 1
0.60
11.50
0 1 0
0.84
16.15
0 1 1
1.20
23.07
1 0 0
2.10
40.38
1 0 1
2.60
50.00
1 1 0
3.00
57.69
1 1 1
5.10
98.07
Output voltage and gain at 10 KHz frequency. Input 52mV
7. Experiment is repeated by setting CBA = 001 and so on. In each case output voltage is
measured and gain is calculated and presented in Table-2.
Results
The results obtained are tabulated in Table-17.3.
Table-17.3
Control Signal
Non-inverting Voltage Gain
C B A
Theoretical
Experimental
0 0 0
2
1.9
0 0 1
11
11.5
0 1 0
16
16.15
0 1 1
23
23.07
1 0 0
40
40.38
1 0 1
48
50.00
1 1 0
57
57.69
1 1 1
101
98.07
Experimental Results
17.8 Discussion
In this experiment use of analog switch is demonstrated by varying the gain of the Opamp in
non-inverting mode. The switching mechanism acts like 1-pole, 8-way rotary switch. Since
the input current drawn by these analog switches is very low there is no effect on Opamp
gain. The experimental and theoretical gains are found to agree within ±5% in all the eight
cases. To conduct the experiment one need not rigg the circuit in Figure-17.4. One can as
well use HI-LO switches of digital trainer or else the switches can be selected manually.
References
[1] National semiconductor corporation, Linear Application Hand Book, P-79
[2] Dr. Jeethendra Kumar P.K, Analog Multiplexer LE Vol- 4, No-4, Dec 2004, P- 273
[3] CMOS logic selection guide 1994, Harris, PP-. 5-9.
Experiments with Digital ICs
Laboratory Experiments Series
Chapter-6
Digital to Analog
Converters
Experiments with Digital ICs
123
124
Laboratory Experiments Series
Experiment-21
DIGITAL TO ANALOG CONVERSION
Abstract
Using 8-bit digital to analog converter IC DAC0808, resolution, accuracy, fullscale error, offset error, linearity error are determined. The transfer characteristic
of the DAC is displayed on CRO screen.
18.1 Introduction
Digital-to-analog conversion (DAC) is a process in which a signal having two definite states
(0 and 1) are converted in to a signal having theoretically infinite number of states (analog).
Present day computers, communications and electronic industries are based on digital
technology. In such a system, DACs are used frequently. DAC can be obtained in two
different ways [1].
Weighted resistor method
R-2R ladder method
RF
R
2
3
R
D0
Vo
7
D1
2R
6
+
2R
-12V
4
D2
2R
-
D3
+12V
2R
R
2R
Figure-18.1: DAC circuit using R-2R ladder network.
In both these methods, an Opamp is used as active device. In the weighted resistor, method
different values of resistors are used to get DAC. Depending on the bit width, the number and
value of resistors will increase. In practice, it is very difficult get different values of
precession resistors. Hence, this method has only theoretical importance. In the second
method only two different values of resistors are involved hence getting them is a not a
problem. Figure-18.1 shows a R-2R network DAC circuit.
Experiments with Digital ICs
125
Laboratory Experiments Series
The D inputs to the DAC are either 0 or 1. Such a discrete component DAC is not used in
practice. Instead, monolithic integrated circuits based on R-2R networks are available in form
of ICs. A DAC is specified by its bit capacity, which indicates the number of inputs. DACs
with 8 or 16 bit capacity are frequently used in electronic circuits. DAC0808 is an 8-bit
converter IC [2].
18.2 DAC0808
Figure-2 shows pin configurations of DAC0808IC. It is available two dip packages with
0.20% accuracy. It requires a spilt power supply for energization. Wide supply voltage range
from ± 5 volts to ± 15volts can be used. However, best results are obtained with +5V and –
15V combination.
DAC0808
Vcc
1
16
Vref+
2
Vref-
3
compensation
DAC0808
LSB
NC
1
16
Compo
15
GND
2
15
Vref-
14
VEE
3
14
Vref+
Io
4
13
4
13
VCC
NC
5
12
MSB-A8
5
12
A1
GND
6
11
A7
6
11
A2
VEE
7
10
A6
7
10
A3
Io
8
9
A5
8
9
A4
Wide DIP package
MSB
Standard regular 16 pin package
Top view
Top view
Figure-18.2: Pin configurations of DAC0808 IC
There are 19 parameters defined [3] to specify and speak the merits and demerits of a DAC.
Among them, few important parameters are defined and estimated experimentally here.
18.3 Resolution
Resolution describes the smallest standard incremental change in the output voltage of a
DAC. It is defined as the amount of output voltage change for a consecutive code change.
For example, an 8-bit DAC can resolve 1-part in 28 states (1-part in 256 states) or 0.39% of
full scale. If the full-scale voltage is 10 volts then the resolution is
R=
10V
2
8
=
10V
= 0.039V = 39mV = 0.39% of full-scale voltage.
256
This refers to 1-LSB or one-step height of the DAC output. The resolution of a DAC is
connected with IC design. It is nothing to do with its performance. Another parameter called
accuracy is defined to specify the performance of the DAC IC.
18.4 Accuracy
Experiments with Digital ICs
126
Laboratory Experiments Series
It is the difference between the actual output voltage and the full-scale weighted equivalent of
the binary output code. As the bit size, increase in weighted difference increase. However, the
difference per bit remains the same.
V
− VExpt
Accuracy = 100% − Thet
x100
VThet
…1
Where VThet is the weighted or the value of input bits.
VExpt is the experimental value of output voltage
For example an 8-bit DAC with 10V reference voltage, for input bits 1111 1111, the actual
output measured is 9.9 volts. The full-scale weighted equivalent of the binary out put is 10
volts.
D = 10V-9.9V =0.1V
A = 10V-0.1V = 9.9V = 99%
The conversion is 99% accurate. Accuracy varies with bit width. Maximum difference is ±1
LSB.
18.5 Full-scale error
Full-scale error is the actual difference between output voltage and its equivalent weighted
value at the MSB. In the above calculations, 0.1V difference is obtained at the MSB hence
full-scale error is 0.1V.
18.6 Offset error
Some negative voltage
due offset error
0
Figure-18.3: Transfer curve and offset error.
Offset error is the output voltage of a DAC with zero code input. The internal difference
amplifier of the Opamp usually causes offset error. This can be eliminated by offset
adjustment pot. The results of offset can be viewed on the transfer curve on CRO as shown in
Figure-3. On the other hand, it is the output voltage measured with 0000 0000 input.
Experiments with Digital ICs
127
Laboratory Experiments Series
18.7 Linearity
The transfer curve of DAC on equal X and Y-axis has 45º slope. However, some times the
slope varies slightly. This is due to various error factors. A percentage variation in the slope
is called non-linearity. In addition, linearity is defined as
L = 100 − N
…2
Where L is linearity in %
N is non-linearity
Figure-4 shows non-linearity effect. For example if the slope of the transfer curves are 50º
instead of 45º, then
50 − 45 5
=
= 0.111 = 11.1%
45
45
Or the linearity is
Non linearity =
L= 100-11.1= 89.9%
Slight variations
in the slope of
transfer curve
due to lnon-linearity error
Figure-4, Transfer curve with its slope
18.8 Monotonicity
Non-monotonicity
in the curve
Figure-18.5: Transfer curve with non-monotonicity
Figure-5 shows the non-monotonicity in the transfer curve. The steps of the transfer curve
increase monotonically then the monotonicity is 100%. If it does not increase monotonically
then non-monotonicity results as shown in the Figure-5. Monotonicity is measured in terms
of LSB. The allowable value of non-monotonicity is ±½LSB.
Experiments with Digital ICs
128
Laboratory Experiments Series
18.9 Slew rate
Slew rate is an inherent limitation of the output amplifier of a DAC, which limits the rate of
change of output voltage from 0.2 to several volts/µs. Delay in reaching final value of DAC
output voltage is the sum of slew time and setting time as shown in Figure-6.
Delay in reaching
final state
Settling time
Figure-18.6: Settling time and delay time resulting in slewing of the transfer curve
Slew rate SR = Settling time delay + delay in reaching final stage
The settling time delay is much smaller than delay in reaching final stage hence
SR = delay in reaching final stage
If I0 is the output current the
SR =
dI o
dt
…3
If RL is load resistance connected to the output terminal and Vo is the output voltage
measured then slew arte is given by
SR =
dI o
dVo
=
dt
R L dt
…4
dVo
Is measurable from CRO hence slew rate can be determined.
dt
18.10 DAC Circuit
Figure-7 shows DAC0808 IC connected perform DAC. A8…A1 is an 8-bit input terminal. Pin
4 is the out pin connected to the Opamp. C is the compensation capacitor. The reference
voltage is set by trim pot TP. LF 356 Opamp is used as current to voltage converter. The out
put current of the DAC is given by
A
A
A
A
A
A
A 
A
I O = I REF  1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 
4
8
16 32 64 128 256 
 2
Experiments with Digital ICs
…5
129
Laboratory Experiments Series
Where IO is the output current of the DAC
IREF is the reference current
A1…A8 is input bits
The reference current is given by
I REF =
VREF
R REF
Substituting for IREF we get
IO =
VREF  A1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 
+
+
+
+
+
+
+
R REF  2
4
8
16 32 64 128 256 
MSB
A8
REF=100K
IREF
+15V
+5V
10.00V Vref
13
5
6
10K TP
14
15
7
8
5.6K
2
RF=100K
1
9 DAC0808
10
RI=10K
2
3
16
0.1
6
Vo
LF356
7
3
+
Io
-
4
11
12
4
LSB A1
-15V
+15V
-15V
Figure-18.7: DAC circuit
The Opamp out put is given by
V0 =RF I0
VO =
R F VREF  A1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 
+
+
+
+
+
+
+
R REF  2
4
8
16 32 64 128 256 
Selecting resistance RF =RREF = 100K the output can be written as
A
A
A
A
A
A
A 
A
VO = VREF  1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 
4
8
16 32 64 128 256 
 2
Experiments with Digital ICs
…6
130
Laboratory Experiments Series
18.11 Instruments Used
Digital trainer containing split power supplies with ±5V/0.4A and ±15V/0.4A, logic
monitors, clock signal and HI-LO switches, dual trace CRO, Digital dc voltmeter 2V/20V
dual range and DMM.
18.12 Components Used
DAC0808, 74LS193,Opamp LF 356, resistor 100K, 10K and 5K, capacitors 0.1µF
18.13 Experimental Procedure
The experiment consists of three different parts
Part A, Verification of DAC equation
Part B, Display of transfer curve
Part C, Determination of slew rate
Part A, Verification of DAC equation
1. The circuit rigged as in Figure-7 on breadboard of the digital trainer. The supply voltages
verified by measuring it with a DMM.
2. The eight input terminals are connected to HI-LO switches on the digital trainer. And
digital dc voltmeter is connected to Opamp output. The input bits are set to
A8 A7 A6 A5 A4 A3 A2 A1 = 0000 0000
The output voltage is noted in the dc voltmeter and recorded in Table-1. This voltage for
0000 0000 input is the offset error
Vo offset =0.007V = 7mV
3. The reference voltage is now set to exactly 10.00 by varying trim pot TP. This sets the
full-scale output voltage.
4. Now the input is set to 0000 0001 using HI-LO switch and the output is noted. Trial is
repeated for different inputs and the corresponding output voltage is noted in Table-1.
The output voltage noted for 0000 1000 input is –312mV tallied with the output voltage
calculated using DAC equation.
1
0
0
0 
0 0 0 0
VO = 10.00 + + + +
+
+
+
= 0.3125 V=312.5mV
 2 4 8 16 32 64 128 256 
5. Trial is repeated till the final input 1111 1111. In each case, output voltage is noted and
theoretical output is calculated using DAC equation and presented in Table-1. The final
output noted is
10.00 volts. Hence the resolution is
Experiments with Digital ICs
131
Laboratory Experiments Series
R=
10.00
28
=
10.00
= 39.06mV
256
6. Experiment is repeated for 5.00 volts reference. In this case the resolution obtained is
19.55mV
Table-18.1
Input Bits
Decimal
Output Voltage
Difference
Accuracy
A8 A7 A6 A5 A4 A3 A2 A1
(V)
%
Expt (V) Thet (V)
0
0000 0000
0.0007
0.0
0.0007
Offset error
1
0000 0001
0.0391
0.0390
0.0001
99.74
2
0000 0010
0.0778
0.0781
0.0003
99.61
4
0000 0100
0.1562
0.1562
0.0000
100.00
8
0000 1000
0.3125
0.3125
0.0000
100.00
16
0001 0000
0.625
0.6250
0.0000
100.00
32
0010 0000
1.248
1.2500
0.0002
99.84
64
0100 0000
2.498
2.5000
0.0002
99.99
128
1000 0000
5.00
5.0000
0.0000
100.00
256
1111 1111
10.00
10.000
0.0000
100.00
Table-18.1: Output voltage variation with input bits.
Expt
Thet
Output (V)
10
5
0
0
50
100
150
200
250
300
Input bits (decimal)
Figure-18.8: Transfer curve of the DAC
Accuracy is calculated using equation-1
V
− VExpt
0.0390 − 0.0391
Accuracy = 100% − Thet
x100 = 99.74% for 0000
x100 = 100% −
VThet
0.0390
0001
input. It is observed that the conversion 100% accurate in all trials. A transfer curve is drawn
taking input bits along X-axis and output voltage along Y-axis. The graph is shown in Figure8.
It is seen from the graph that both the experimental and theoretical curves coinciding
indicating 100% accuracy in the conversion. The slope of the straight line gives linearity.
Experiments with Digital ICs
132
Laboratory Experiments Series
Slope = 45˚
45 − 45 0
=
= 0%
45
45
L = 100-0=100%
Non linearity =
Part B, Display of transfer curve
7. To display the DAC curve on CRO. The input bits are fed from a counter so that there is
continuous change in the input bits. The 8-bit DAC converted in to 4-bit DAC by
grounding the four upper MSB bits as shown in Figure-9. The 4-bit binary counter
74LS193 [4] is connected four lower bits of DAC. The counting is initiated by a 1KHz
clock signal from the digital trainer.
CLOCK 1KHz
8
14
2
6
2
3
11
12
-15V
4
Io
RI=10K
2
3
1 15
16
0.1
6
Vo
LF356
7
3
10 9
RF=100K
4
74LS193
5.6K
1
9 DAC0808
10
7
5
15
+
560 Ohms
14
7
8
16
10K TP
-
11
10.00V Vref
13
5
6
+5V
REF=100K
IREF
+15V
+5V
+15V
-15V
Figure-18.9, Binary counter feeding the DAC
Figure-18.10: Transfer characteristics curve of DAC0808
(4-bit input from binary counter. The curve showed 89.9% linearity)
8. The output is monitored on CRO channel B. The transfer curve obtained is shown in
Figure-10. The sixteen-step stair case generator as seen from the figure is having linearity
distortion. The four output waveforms from the counter IC not always has equal
Experiments with Digital ICs
133
Laboratory Experiments Series
amplitude hence slight linearity distortion is seen in the curve. The slope of the transfer
curve is measured using a protractor it is found to equal to 50˚.
9. No non-monotonicity is observed in transfer curve. Hence monotonicity is100%
Part C, Determination of Slew rate
10. To determine the slew rate DAC is connected as shown in Figure-11. The reference input
is fed with 1KHz clock signal. The output at pin-4 is monitored on CRO screen. A
distorted square wave appeared on the output. Figure-12 shows reference input and output
signal. The slewing time and peak-to-peak voltage are noted.
+5V
2V
VREF
0V
1K-TP2
A8
13
5
6
14
15
7
8
5.6K
2
1
9 DAC0808
10
A1
4
11
12
3
16
0.1
0
To CRO
Slewing time
-15V
Figure-18.11: DAC0808 circuit connection for slew rate determination
Figure-18.12: Reference input and slewed output
Peak to peak out put voltage = 3 volts
Slewing time
= 200µA
dV
3V
SR =
=
= 0.015V / µs
dt 200µs
Experiments with Digital ICs
134
Laboratory Experiments Series
18.14 Results
The results obtained are tabulated in Table-18.2.
Parameters
Resolution
Accuracy
Full scale error
Offset error
Linearity
Monotonicity
Slew rate
Table-18.2
Experimental
39.10mV
99.59% (-1LSB)
0.32mV (-1LSB)
0.4mV
100%
Not observed
0.015V/µs
Standard
39.04mV
±1LSB
±1LSB
±½LSB
99.98%
±½LSB
0.2 to few
hundred V/ µs [3]
DAC0808 Characteristics experimental results
18.15 Discussions
The characteristic parameters obtained by experiment are in very good agreement with the
DAC0808 standard values as per the manufacturers data. This indicates that the IC is well
optimized with minimum deviation in its parameters. In order to observe large values for
these parameters one need to perform the experiments using Opamp and discrete component
R-2R network. The experiment introduces a method of determining various parameters
associated with DAC/ADC in general and DAC in particular. By varying the reference
voltage the full scale, voltage can be set to desired value.
References
[1]
A P Malvino and Jerald A Brown, Digital computer electronics, 3rd edition, Page 483.
[2]
National Semiconductor, National data acquisition data book, Page 3-15.
[3]
Jim Sherwin, National Semiconductor, Application Note-156, Linear applications
handbook, Page-413.
[4]
T Aswathnarayana Rao, Synchronous 4-bit up-down counter, LE Vol-3, N0-2, June2002, Page-103.
Experiments with Digital ICs
135
Laboratory Experiments Series
Experiment-22
DIGITAL TO ANALOG
CONVERSION USING R-2R NETWORK
AND OPAMP
Abstract
Using R-2R network and Opamp digital to analog conversion is performed.
The characteristic parameters such as resolution, accuracy, full-scale error,
offset error, linearity, monotonicity and slew rate distortions are determined.
The transfer characteristic of the DAC is displayed on CRO screen. The
number of steps in the staircase is controlled by suitably programming the
counter input to the DAC.
19.1 Introduction
Digital-to-analog conversion (DAC) is a process in which a signal having two definite states
(0 and 1) are converted in to a signal having theoretically infinite number of states (analog).
The fundamental building block of DAC IC is the Opamp based R-2R network shown in
Figure-1.
24K 2R
12K
-15V
R
4
C
R=RF=12K
24K 2R
2
3
12K
Vo
LF356
+15V
12K
LSB A
R
6
7
B
24K 2R
+
D
-
MSB
R
24K 2R
2R 24K
Figure-19.1: DAC circuit using R-2R ladder network.
Present day computers, communications and electronic industries are based on digital
technology. In such a system, DACs are used frequently. DAC can be obtained in two
different ways [1].
Weighted resistor method
R-2R ladder method
Experiments with Digital ICs
136
Laboratory Experiments Series
In both these methods, an Opamp is used as active device. In the weighted resistor, method
different value of resistors are used to get digital to analog conversion. Depending on the bit
width, the number and value of the resistors increase. In practice, it is very difficult to get
different values of precession resistors. Hence, this method has only theoretical importance.
In the second method only two different values of resistors are involved hence getting them is
a not a problem.
The DCBA inputs to the DAC are either 0 or 1. For TTL IC the HI state input is 5V and LO
state input is 0V. This need not be the case always. CMOS DAC ICs have 10V as HI state
and 0V as LO state. Therefore, in general Vref denotes the HI state input to the DAC.
A discrete component DAC is important in lab experiments to study the characteristic of the
conversion. In practice, monolithic integrated circuits based on R-2R networks are used in
electronic circuits. A DAC IC is specified by its bit capacity, The DAC shown in Figure-1 is
a 4-bit wide converter.
19.2 DAC characteristic parameters
Various parameters connected with the process of digital to analog conversion refer to both
the weighted resistor and R-2R network hence it applies to both the types of conversion. The
output voltage of the DAC as shown in Figure-1 is given by
V R D C B A
Vo = − ref F  + + + 
2 R 1 2 4 8
Where
…1
Vref is the reference voltage or the HI state digital input
RF is the forward feedback resistor
R is the one of the ladder resistor
DCBA are input digital bits.
For R=RF the equation is rewritten as
V D C B A
Vo = − ref  + + + 
2 1 2 4 8
…2
The width of the input bit can be in multiples of 4 such as 4,8,12,16 etc. However, one can
have any width within the practical limit of Opamp supply voltage.
19.3 Resolution
Resolution describes the smallest standard incremental change in the output voltage of a
DAC. It is defined as the amount of output voltage change for a consecutive code change.
R=
Vo (full)
…3
2n − 1
Experiments with Digital ICs
137
Laboratory Experiments Series
For example, a 4-bit DAC can resolve 1-part in 16 states or 6.6% of full scale. If the fullscale voltage is 5 volts then the resolution is
R=
5V
24 − 1
=
5V
= 0.333V = 333mV = 6.6% of full-scale voltage.
15
This refers to 1-LSB or one-step height of the DAC output. The resolution of a DAC is
connected with number of input bits. It is nothing to do with its performance. Another
parameter called accuracy is defined to specify the performance of the digital to analog
converter.
19.4 Accuracy
It is the difference between the actual output voltage and the full-scale weighted equivalent of
the binary output code. As the bit size, increases the weighted difference also increase.
However, the difference per bit remains the same.
V
~ VExpt
Accuracy = 100% − Thet
x100 %
VThet
…4
Where VThet is the theoretical output voltage.
VExpt is the experimental value of output voltage
For example in a 4-bit DAC with 5V reference voltage, for input bits 1111, the actual output
measured is 4.9 volts. The full-scale weighted equivalent of the binary output is 5.0 volts.
D = 5V - 4.9V = 0.1V
A = 5V - 0.1V = 4.9V = 98%
The conversion is 98% accurate. Accuracy may vary with bit width. Maximum difference is
±1 LSB.
19.5 Full-scale error
Full-scale error is the actual difference between output voltage and its equivalent weighted
value at the MSB. In the above calculations, 0.1V difference is obtained at the MSB hence
full-scale error is 0.1V.
19.6 Offset error
Offset error is the output voltage of a DAC with zero (DCBA=0000) code input. The outputoffset voltage of the Opamp usually causes offset error. This can be eliminated by offset
adjustment pot. The results of offset can be viewed on the transfer curve on CRO as shown in
Figure-2. On the other hand, it is the output voltage measured with 0000 input.
Experiments with Digital ICs
138
Laboratory Experiments Series
Some negative voltage
due offset error
0
Figure-19.2: Transfer curve and offset error.
19.7 Linearity
The transfer curve of DAC on equal X and Y-axis has 45º slope. However, some times the
slope varies slightly. This is due to the tolerance of R-2R resistor network and Opamp
parameters. A percentage variation in the slope is called non-linearity. In addition, linearity is
defined as
L = 100 − N
…5
Where L is linearity in %
N is non-linearity
Figure-3 shows non-linearity effect. For example if the slope of the transfer curves are 50º
instead of 45º, then
50 − 45 5
=
= 0.111 = 11.1%
45
45
Or the linearity is
Non linearity =
L= 100-11.1= 89.9%
Slight variations
in the slope of
transfer curve
due to lnon-linearity error
Figure-19.3: Transfer curve with its slope
19.8 Monotonicity
Figure-4 shows the non-monotonicity in the transfer curve. The steps of the transfer curve
increase monotonically then the monotonicity is 100%. If it does not increase monotonically
then non-monotonicity results as shown in the Figure-4. Monotonicity is measured in terms
of LSB. The allowable value of non-monotonicity is ±½LSB.
Experiments with Digital ICs
139
Laboratory Experiments Series
Non-monotonicity
in the curve
Figure-19.4: Transfer curve with non-monotonicity
19.9 Slew rate
Slew rate is an inherent limitation of the output Opamp of the DAC, which limits the rate of
change of output voltage from 0.2 to several volts/µs. Delay in reaching final value of DAC
output voltage is the sum of slew time and setting time as shown in Figure-5.
Delay in reaching
final state
Settling time
Figure-19.5: Settling time and delay time resulting in slewing of the transfer curve
Slew rate SR = Settling time delay + delay in reaching final stage
The settling time delay is much smaller than delay in reaching final stage hence
SR = delay in reaching final stage. If I0 is the output current then
SR =
dI o
dt
…6
If RL is load resistance connected to the output terminal and Vo is the output voltage
measured then slew rate is given by
SR =
dI o
dVo
=
dt
R L dt
…7
dVo
Is measurable from CRO hence slew rate can be determined.
dt
19.20 Instruments Used
Experiments with Digital ICs
140
Laboratory Experiments Series
Digital trainer containing ±15V and 5V power supplies, HI-LO switches, logic monitors,
clock signal and breadboard. Digital dc voltmeter 0.2V/2V/20V multi range and dual trace
CRO.
19.21 Components Used
Opamp LF356, binary counter 74LS93, resistors 12K and 24K.
19.22 Experimental Procedure
1. The reference input to the DAC (logic HI state input) is measured from HI input using
digital dc voltmeter
HI input = 5.01V = Vref
LO input = 0V
2. DAC circuit is rigged as shown in Figure-1. All the four inputs DCBA are connected to
LO state and the output voltage is measured using dc voltmeter. This voltage is the output
offset error.
VO(off) = -7.2mV
This offset error can be nullified using offset adjustment terminal of the Opamp and a
trim pot [2].
3. The input DCBA is now set to 1111 and the output is measured. This is the full-scale
output voltage
Vo(full) = -4.71V
Resolution is calculated using equation-3.
R=
Vo (full)
n
2 −1
=
4.71
4
2 −1
=
4.71
= 0.314V
15
4. For different input bits varying from 0000 to 1111 the corresponding output, voltage is
measured and tabulated in Table-1. Theoretical value of output voltage is calculated using
equation-1. For 1010 input the output voltage is given by
V D C B A
5.01 1 0 1 0 
Vo = − ref  + + +  = −
+ + +
= −2.50x1.25 = −3.125V
2 1 2 4 8
2 1 2 4 8 
The value calculated agreed very well with experimental value -3.131V, indicating the
perfectness in the conversion.
Accuracy is calculated using equation-4 at MSB (1111).
Experiments with Digital ICs
Laboratory Experiments Series
141
V
~ VExpt
Accuracy = 100% − Thet
x100 %
VThet
= 100% -
4.687 ~ 4.71
x100 = 99.5%
4.687
Full-scale error is calculated at DCBA=1111. It is the difference between theoretical
output and experimental output
Full scale error = VThet − VExpt = 4.687-4.71=0.023V. This 23millivolt full error is
<½LSB
Table-19.1
Decimal Binary Output Voltage (V)
LSB
Input
(Thet)
Thet
Expt
0
0000
-0.000
-0.0072
1
0001
-0.312
-0.312
0.310
2
0010
-0.625
-0.626
0.316
3
0011
-0.937
-0.931
0.313
4
0100
-1.250
-1.264
0.312
5
0101
-1.562
-1.569
0.314
6
0110
-1.875
-1.883
0.313
7
0111
-2.187
-2.187
0.317
8
1000
-2.500
-2.513
0.315
9
1001
-2.812
-2.817
0.315
10
1010
-3.125
-3.131
0.313
11
1011
-3.437
-3.467
0.314
12
1100
-3.750
-3.780
0.314
13
1101
-4.060
-4.080
0.314
14
1110
-4.375
-4.400
0.312
15
1111
-4.687
-4.710
0.313
Average LSB = 0.3136
Input bits and DAC output voltages
5. A transfer characteristic curve is plotted taking input bits along X-axis and DAC output
voltage along Y-axis. The curve is shown in Figure-6. From the curve the slope of the
straight lines are calculated.
Slope of Experimental curve = 0.3136 = LSBExpt
Slope of Theoretical curve = 0.3125 = LSBThet
The slope of the straight lines gives the LSB of conversion.
Difference in the slopes = 0.0011 = 0.352%
∴
Non linearity N = 0.352%
∴
Linearity L = 100-0.352 = 99.64% <½LSB.
Experiments with Digital ICs
142
Laboratory Experiments Series
Thet
Expt
0
DAC Output (V)
-1
0
5
10
15
20
-2
-3
-4
-5
Input Bits
Figure-19.6: Transfer characteristics of DAC
Part-B, Display of Characteristic Curve on CRO
6. Feeding DAC inputs with time varying clock signals from a binary counter the transfer
characteristic curve is viewed on a CRO. The 74LS93 binary counter is used as shown in
Figure-7. By connecting the DAC output to CRO channel-B, the transfer curve is
observed.1 KHz Clock signal is fed from the digital trainer. The counter produce QA =
500Hz, QB = 250Hz, Qc = 125Hz, QD = 62.5Hz signals. These signal generate 0000-1111
sequence of inputs continuously [3]
+5V
QD
D
24K 2R
11
C
24K 2R
2
3
14
12K
9
QB
B
24K 2R
12
Vo
LF356
+15V
12K
3 10
R
6
7
74LS93
2
4
QC
8
-15V
R
+
12K
1KHz
Clock
5VPP
R=RF=12K
-
5
QA
A
R
24K 2R
1
2R 24K
Figure-19.7: Binary counter feeding the DAC
7. The output of the Opamp is connected to CRO channel-B and the staircase waveform is
observed as shown in Figure-8. The peak-to-peak amplitude of the staircase is measured
by switching the time/div knob of the CRO to the external position.
Experiments with Digital ICs
Laboratory Experiments Series
143
Figure-19.8 (a), Fifteen step staircase waveform (b) Peak-to-peak amplitude
8. The CRO channel-B is switched to GND- position and the centerline is coincided with the
CRO centerline. When the channel is switched back to DC position, the transfer curve
appears on the screen. The first step is now shifted just below the centerline as shown in
Figure-.9, the shift is measured on Y-axis. This is the offset error.
Offset error = -8mV. This agreed well with the -7.2 obtained in part-A.
Figure-19.9: Offset error causing shift in the start of staircase waveform
9. The peak-to-peak value of the staircase waveform is measured by turning the time/div
knob of the CRO to the external position as shown in Figure-8 (b). The total number of
steps in the staircase waveform is also noted.
Peak to peak output = 3.5V
Number of steps = 15
∴ Resolution Rac = 0.233V
This is one-step height. This can be verified by reconnecting the circuit as shown in
Figure-9 The three upper bits BCD = 000 are set LO by disconnecting them from counter
and grounding them. The LSB (A input of the DAC) of the DAC is fed with QA that can
have only two states hence produce a single step staircase (square wave) as shown in
Figure-11. The peak-to-peak amplitude of the square wave is the LSB for ac signal.
Experiments with Digital ICs
144
Laboratory Experiments Series
+5V
QD
D
24K 2R
QC
C
24K 2R
2
3
14
12K
9
QB
B
24K 2R
12
LF356
+15V
12K
3 10
R
6
7
74LS93
2
4
8
-15V
R
+
12K
1KHz
Clock
5VPP
R=RF=12K
11
-
5
QA
A
R
24K 2R
1
2R 24K
Figure-19.10: Circuit producing single step staircase or a square wave
Figure-19.11: Single step staircase or a square wave
Peak-to peak output 230mV
Three step and seven step staircase waveforms
Figure-12(a), Three step staircase (QA= A,QB=B, QC = 0, QD= 0)
Figure-12(b), Seven step staircase (QA= A,QB=B, QC = C, QD= 0)
Table-19.2
Input
Output (V)
No of Steps
Step height Rac
A=QA, B=C=D=0
0.230
1
0.230
A=QA, B=QB, C=D=0
0.700
3
0.233
A=QA, B=QB,, C=QC D=0
1.700
7
0.242
A=QA, B=QB,, C=QC D=QD
3.500
15
0.233
Average Rac =0.2345V
Different inputs to the DAC and resolution to ac signal
(Step numbers are counted vertically)
Experiments with Digital ICs
Laboratory Experiments Series
145
10. By reconnecting QB to B input and QC to C input three step and seven step staircase
waveforms are obtained. In each case, the step height is calculated by noting peak-to-peak
amplitude of the staircase and number of steps. The readings obtained are tabulated in
Table-2
19.23 Slew rate
11. The staircase waveform is observed on a smaller time scale as shown in Figure-13. There
is no measurable slew rate distortion observed in the waveform
Figure- 19.13: Extended 15 step staircase waveform without slew rate distortion
19.24 Monotonicity
12. The perfect 15 step staircase waveform observed as shown in Figure-8(a) doesn’t show
any discontinuity in the staircase wave which indicate zero monotonicity.
19.25 Results
The results obtained are tabulated in Table-19.3.
Table-19.3
Parameters
Expt
Resolution (dc) V/bit 0.314
Resolution (ac) V/bit 0.234
Accuracy (%)
99.5
Full scale error
23mV
Offset error
-7.2mV
Linearity (%)
99.64
Slew rate
Not observed
Monotonicity
Not observed
Experimental results
Thet
0.312
0.233
±1LSB
±1LSB
±½LSB
99.85
±½LSB
19.26 Discussions
Basic functioning of the DAC and the various characteristic parameters associated with the
DAC are studied in this experiment. The various characteristics parameters obtained are in
very good agreement with the theoretical value indicating the perfectness in the conversion.
Using DAC with HI-LO input the transfer characteristic curve obtained matched with the
theoretical curve. The transfer curve is displayed on a CRO using binary counter that
Experiments with Digital ICs
146
Laboratory Experiments Series
generate 0000 to 1111 sequence of inputs. Programming the counter output as indicated in
Table-2 suitably controls the numbers of steps. The resolution obtained in ac case (0.230) is
lower than the dc case because the full-scale output in ac itself is 3.5V in compared to 4.7V in
case of dc. In practice Opamp and R-2R based DAC is not used in electronic circuit
applications. However, all the DAC ICs are based on R-2R network. Hence, it is the
fundamental building block of DAC IC.
References
[1]
K V Acharya, Digital to analog conversion, LE Vol-3, No-4, Dec-2003, Page-329.
[2]
Jeethendra Kumar P K, Universal offset balancing techniques, LE Vol-3, No-4, Dec2003, Page-348.
[3]
Jeethendra Kumar P K, Boolean function generator, LE Vol-2, No-2, Sept-2002,
Page-47
Experiments with Digital ICs
Laboratory Experiments Series
Chapter-7
Data
Communications
Experiments with Digital ICs
147
148
Laboratory Experiments Series
Experiment-23
AMPLITUDE SHIFT KEYING
Abstract
Multiplication of a carrier with a pulse sequence is studied in amplitude shift
keying (ASK) using analog switch. The ASK signal is demodulated using Norton’s
amplifier. The modulated and demodulated signals are observed on CRO.
10.1 Introductions
Data communication began with the use of public switching telephone network to carry voice
signals. The band of frequencies these voice signals occupy is between 300Hz to 3400Hz. A
train of rectangular plusses has its frequency below the lower limit (300Hz). If these pulses
are asked to carry by the telephone line then, these pulses will be of very highly distorted
shape. Hence it is difficult to send unmodified train of pulse through telephone line. Pulses
are modified and asked to carry by the telephone line. The process of modification is called
as Modulation and at the receiving end signal is DEMoulated (MODEM) to obtain back the
original signal. An instrument called MODEM does the entire process.
At the transmitting end modem converts digital pulses in to voice and transmits through
telephone line. At the receiving end the modem converts the voice in to digital pulses. This
process of transmission of signal is called as data transmission or data communication. There
are three basic types of modulations in data communications, namely
1. Amplitude shift keying (ASK) modulation and demodulation.
2. Phase shift keying (PSK) modulation and demodulation
3. Frequency shift keying (FSK) modulation and demodulation.
10.2 Amplitude Shift Keying
ON
OFF
OFF
ON
ON
No-Signal
Signal
OFF
ON
ON
N-S
Signal Signal
OFF
N-S
Signal Signal
Figure-10.1: ASK modulated signal
A binary pulse train is represented by ON-OFF sequence. During the ON time a sinewave
carrier signal (f c) is allowed to pass and during the OFF time no signal is allowed to pass.
Hence the resulting pulse train consists of sine wave signal followed by no signal as shown in
the Figure-10.1. This is called ASK modulated signal. If fc is the carrier and P (t) is the pulse
Experiments with Digital ICs
Laboratory Experiments Series
149
train then the multiplication these two results in ASK [1]. The resulting ASK signal is
represented by
A (t) = P (t) Cos (2πfct)
…1
To get ASK modulated signal the carrier and the pulse train is multiplied as per Equation 1.
This is done in general by an analog switch that switches ON passing the carrier when there
is HI state and switches OFF not allowing the carrier to pass when there is LO state in the
pulse train. This process results in ASK modulated signal. The carrier (1.8KHz) is taken from
an audio oscillator and signal to be transmitted is converted in to Boolean function and
multiplied by the carrier. The analog switch used in the present experiment consists four
independent JFET SPST switches as shown in Figure-10.2. It is available in 16-pin DIP
package from National Semiconductor or Harris [2,3].
3
S
D
G
1
Q1
2
4
8
6
Q2
7
5
9
11
Q3
10
12
16
14
Q4
13
15
AH5012/IH5012
Figure-10.2: Analog SPST switch AH/IH 5012 pin diagram
The JFET switches are operated in the current mode hence placed generally in series with
other elements. The drain of each JFET is held near the ground potential by the diode. The IC
acts like a one pole –4 way rotary switch. Figure –10.3 shows analog switch tied to form
ASK modulator. The Opamp is used as inverting amplifier with closed loop voltage gain
given by
A V ( CL ) =
Where
R 2 + rDS ( on ) 2
…2
R1 + rDS ( on )1
rDS(on)1 is the drain-source resistance of JFET Q1
Experiments with Digital ICs
150
Laboratory Experiments Series
rDS(on)2 is the drain-source resistance of JFET Q2
Q2
1/4-5012
D
S
8
6
G
+15V
Q1 1/4-5012
3
1
3
R1
10K
2
R2
6
+
2
-
10K
4
Sine Carrier
1.8KHz
7
ASK
Output
LF356
7
1
4
-15V
0
Modulating
Pulse
Figure-10.3: ASK modulator circuit
In general the drain-source resistances are nearly equal and selecting R1 = R2, the closed loop
gain is taken as unity.
The carrier sine wave is fed through R1 and the pluses are fed at the gate as shown in Figure10.3. ASK demodulation is the reverse process of getting back the pulse waveform. This is
done in different ways. In this experiment demodulation is obtained using a Norton’s
amplifier [4].
10.3 Norton’s Amplifier
+5V
10uF
ASK
Input
1
+
14
14
1
6
7
LM3900
LS04
2
Demodulated
ASK
7
10K
Figure-10.4: ASK Demodulator circuit
10.4 Instruments Used
Norton’s amplifier is class of Opamps designed for single supply applications. Norton’s
amplifier makes use of current feedback instead of voltage feedback. It is used to perform all
the basic applications of Opamp and it is used as a special amplifier with specific application
which
Experiments with Digital ICs
Laboratory Experiments Series
151
are not possible with Opamp. One such application is the present ASK demodulator circuit.
Figure-10.4 shows ASK demodulator circuit. The circuit appears very simple. An inverter is
added to reshape the demodulated output in to perfect rectangular pulse.
Digital signal generators, regulated power supply 5V/1A, split power supply ±15V/0.5A, sine
wave oscillator 10-100KHz, Dual trace CRO.
10.5 Experimental Procedures
The experiment is divided in to two parts
Part A:
Part B:
ASK modulation
ASK demodulation
Part A:
ASK modulation
1. The circuit is rigged as shown in Figure-10.3. A sine wave oscillator is connected as
carrier signal. Its amplitude is set to 10VPP and frequency is set 1.8KHz.
2. The digital signal generator is connected to JFET gate and the pulse train is monitored
on CRO channel-B. It is the modulating pulse.
3. The output of the Opamp is monitored on Channel-A of the CRO in comparison with
the modulating signal.
4. The ASK modulated signal is observed as shown in Figure-10.5.
5. The ASK modulated signal is observed for all input pulse train. The carrier frequency
is also varied up to 100KHz to observe the functioning of the circuit. It is found that
without any changes in the circuit ASK modulated signal is obtained with carrier
frequency up to 100KHz.
Figure-10.5: ASK modulated signal
(Upper modulating signal, lower ASK modulated signal)
10.6 ASK demodulation
Experiments with Digital ICs
152
Laboratory Experiments Series
6. The demodulator circuit is rigged as shown in Figure-10.4. The ASK modulated signal is
fed to the input of the Norton’s amplifier. And the output is observed on CRO channel-A
in comparison with the modulating pulse train. The output observed is shown in Figure10.6
Figure-10.6 ASK demodulated signal
(Upper one demodulated, lower modulating signal)
10.7 Results
ASK modulated and demodulated circuits are tested and their waveforms are recorded. Clearcut waveform with sharp cuttings at the falling and rising edge of the pulse is observed. It is
also observed that carrier frequency up to 100KHz is acceptable by the circuit. The
demodulation is made simpler by Norton’s amplifier.
10.8 Discussion
The process of ASK modulation and demodulation is studied. The circuit presented is the
first time for both ASK modulation and demodulation. The experiment requires a digital
signal generator to set the modulating signal. In the absence of which a rectangular pulse
generated by a 555 is also can be used. KamalJeeth make digital function generator is
available.
References
1
http:www.cs.ucl.ac.uk/staff/s.bhatti/DS/.noto1/node//.html
2
National Semiconductor, National Data Acquisition Data Book, Analog Switch &
multiplexer Page 8-13.
3
RCA Component Data Catalog 1987, Page 8-65.
4
National Semiconductor, National Operational Amplifier Data Book, 1995 Edition
page- 1-432.
Experiments with Digital ICs
153
Laboratory Experiments Series
Experiment-24
PSK MODULATION AND
DEMODULATION
Abstract
Phase shift keying (PSK) modulation is studied using a JFET SPST switch. And
demodulation is obtained using PLL. The modulated signal is passed through 100
meters twisted wire and the characteristic parameters of PSK namely bias
distortion and jitter are determined.
11.1 Introduction
Phase shift keying (PSK) is one of the most popular data communication techniques through
which digital data is transmitted through telephone lines. Figure-11.1 illustrates a PSK
modulated signal by 101100111-pulse sequence. PSK encodes two distinct signals of same
frequency with 180-degree phase difference between the two. The Logic HI is represented by
flead, phase lead signal and flag, phase lag signal, represents Logic LO. A modem [1] performs
PSK modulation and demodulation. The modulated signal is passed through telephone lines.
Therefore the lead and lag signal frequency should be within the bandwidth of telephone line
(3.1KHz). The spacing between the lead and lag frequencies depend on the demodulation
techniques used [2].
1
0
1
1
0
0
1
1
1
Figure-11.1: PSK modulated signal
In this experiment a sine wave of 880Hz is selected as carrier and 180-degree phase shift is
obtained using an Opamp shown in Figure-11.2. Different techniques are used to demodulate
PSK. The popular analog scheme is the phase locked loop (PLL).
The demodulation process results in several degradations to the originally transmitted data.
Bias distortion, out put jitter are the two parameters, which decide the quality of the
demodulation circuits.
Figure-11.3 shows a 0101 sequence of input transmitted via PSK and demodulated signal.
The demodulated signal is found to have more than 50% duty cycle in the pulse sequence at
certain time.
Experiments with Digital ICs
154
Laboratory Experiments Series
10K-R2
-15V
4
!0K-R1
2
Sine input
3
+
lag
0.1
f
-
f
lead
6
LF356
7
0.1
+15V
Figure-11.2: The lead and lag carrier signals
1
0
1
0
T1RX
TORX
1
0
Bias Distorsion
Resulting in variation
in the duty cycle
Figure-11.3: Bias distortion resulting variation of duty cycle
This is the result of distortion that had resulted in duty cycle variation in the demodulated
output. Such a distortion is called bias distortion. And it is given by
Bd =
0.5T1RX
x100%
T1TX + TORX
Where
…1
T1RX is high state time of the receiving (demodulated) pulse
T1TX is high state time of the transmitted pulse
TORX is low state time of the demodulated pulse
TOTX is low state time of the transmitted pulse
Bias distortion is represented in % in general. The smaller the value of bias distortion better is
the demodulated circuit. The second figure of merit of the PSK demodulation is the jitter.
Jitter is illustrated in Figure-11.4. This is similar to phase variation in sine wave form.
However, the phase difference is not continuous here. It is the discrete phase difference
occurring due to mismatch in the timings of the falling and trailing edges of the pulse
waveform. The jitter is defined as
Experiments with Digital ICs
155
Laboratory Experiments Series
Tb
1
0
1
Mismatch
Tmin
0
Mismatch
1
0
Mismatch
Matching
Tmax
Figure-11.4: Jitter in the demodulated signal
J=
Tmax i Tmin
x100%
Tb
Where
…2
Tmaxi is maximum time delay between the transmitted and receiving pulse
Tmin is minimum time delay between transmitted and receiving pulse
Tb is the half period of the transmitting pulse called time frame bit.
When Tmaxi = Tmin jitter is zero indicating that the received signal is jitter free. Smaller value
of J, better is the receiving signal or more perfect is the PSK demodulation.
11.2 PSK Modulation
PSK modulation is obtained using a JFET analog switch. The quad JFET analog switch
IC5011/5012 pin diagram is shown in Figure-11.5 [3]. The lead and lag carrier signals
produced by Wien Bridge oscillator [4]. Y and W are the ADC outputs [5], which control the
JFET switch.
Y= W
…3
The JFET switch is ON when its gate is at logic HI (+5V), the switch is OFF when the gate is
at logic LO (0V). When the modulating signal is fed to the gate the lead and lag signals are
passed from the source to the drain during high state of the pulse sequence. During the low
state of the pulse sequence the switch is of. Consider a HI state appearing at the gate of Q1
JFET in Figure-11.6, then the W input to the Q2 JFET is LO hence Q2 switch is off. Q1
switch that is closed now passes the lead frequency to the Opamp hence Opamp output has
lead frequency signal. Alternatively, if Logic LO appears on the gate of Q1 JFET then Q1 is
off. Simultaneously Q2 is ON this passes the lag frequency to Opamp or the Opamp out put
now contains lag frequency. In this manner the lead and lag frequencies are passed through
the analog switch to obtain PSK modulated signal. Figure-11.6 shows PSK modulator circuit.
The Opamp is tied in the inverting amplifier mode. The closed loop voltage gain of the
Opamp is given by
Experiments with Digital ICs
156
A V ( CL ) =
Where
Laboratory Experiments Series
R 2 + rDS ( ON )3
…4
R 1 + rDS ( ON )1, 2
rDS(ON)3 is the drain-source resistance of Q3 FET
rDS(ON)1,2 is the drain source resistance of the conducting FET (Q1 or Q2)
The drain-source resistance [7] of the JFET is of the order of 100 Ohms and in the integrated
form these resistance of individual JFET are almost equal, hence one can write
rDS(ON)1 = rDS(ON)2 = rDS(ON)3 = rDS(ON)4 = rDS(ON)5
…5
Thus closed loop gain reduces to
AV(CL) = - 1 for R1 = R2
3
S
1
D
G
Q1
2
4
8
6
Q2
7
5
9
11
Q3
10
12
16
14
Q4
15
13
AH5012/IH5012
Figure-11.5: JFET analog switch
Q3
8
6
-15V
7
IC- 5011/5012
R2
1
2
3
2
10K
10K
TP
14
W
6
LF356
7
4
R1
10K
+
3
Q1
-
10K
4
R1
16
Q2
+15V
15
13
IC- 5011/5012
Y
Figure-11.5: PSK Modulator Circuit
Experiments with Digital ICs
PSK Output
Laboratory Experiments Series
157
11.3 PSK Demodulation
PSK demodulation or decoding is done with 565 PLL IC as shown in Figure-11.7 [7]. Since
the input is single, ended pin-3 of 565 is grounded and the PSK modulated signal is fed to the
input pin-2. The demodulated output appears at pin-7.
+15V
10
PSK Input
2
3
4
565
5
7
1
Demodulated
Output
-15V
Figure-11.7: FSK Demodulator Circuit
11.4 Instruments Used
Split power supplies ±15, dual trace CRO, and Digital Signal Generator (DSG), frequency
counter.
11.5 Components Used
IC 5011/5012, IC 565, LF 356, Resistors 10K, 51K, 510K, 100K, 18K, Capacitors, 0.1,
0.047µA, 4400pF. Trim pot 10K 3296 types. Solderless breadboards.
11.6 Experimental Procedure
The experiment consists of two parts.
Part-A; PSK modulation
Part-B; PSK demodulation
Part A; PSK modulation
1. The PSK modulator circuit is rigged as shown in Figure-6 and carrier is obtained as
shown in Figure-11.2. Frequency of the carrier is noted using frequency counter.
Flead = flag = 880 Hz
2. The Y and W outputs of the DSG are connected to the two analog switches. These are
modulating signals. The output of PSK is monitored on CRO channel-2 in comparison
Experiments with Digital ICs
158
Laboratory Experiments Series
with modulating signal Y. The output noted is shown in Figure-11.8. The trim pot TP
is adjusted so that amplitude is uniform in the PSK signal.
Figure-11.8: Input modulating signal and PSK modulated signal
(Digital photograph is taken with 880 Hz signal )
3. The waveform observed coincided with the pulse waveform indicating perfect ness in
the modulation process and no distortion is observed.
4. Trial is repeated by varying the wave from in the DSG. In each case FSK waveform is
coincided with the pulse waveform to see the perfect ness of modulation.
Part-B; PSK demodulation
5. The PSK demodulator circuit is rigged as shown in Figure-11.7 using 565 IC. The
PSK modulated signal is fed to the demodulator at PSK input terminal. Output of the
demodulator is observed on CRO channel-2 in comparison with the PSK signal as
shown in Figure-11.9(a) and modulating signal Y as in Figure-11.9(b).
(a)
(b)
Figure-11.9(a): PSK modulated and demodulated signal
11.9(b): PSK demodulated with modulating signal
6. The PSK modulated signal is passed through 100meters twisted wire before getting it
demodulated by 565. After passing the signal through the twisted wire, it demodulated
to see the difference in demodulated signal. Photograph in Fogure-11.10 shows the
demodulated signal in compared to Y. Distortions are seen in the waveforms.
Experiments with Digital ICs
Laboratory Experiments Series
159
Figure-11.10, PSK demodulated signal after passing through 100 meters twisted wire
( Bottom modulating signal Y, Top PSK demodulated signal)
11.7 Determination of Bias Distortion
7. The modulating signals Y and W are now replaced by 0101-sequence square wave Y′
and W′ from the DSG. The modulating and demodulated signals observed on CRO as
shown in Figure-9. From the CRO waveform following time period is noted.
T1RX = 0.6msec
T1TX = 0.5msec
TORX = 0.2msec
TOTX = 0.6msec
Bias distortion is given by
Bd =
=
0.5T1RX
x100%
T1TX + TORX
0 .5 x 0 .6
0 .3
x100% =
= 43%
0.5 + 0.2
0.7
11.8 Determination of jitter
From wave form in Figure-11.9, the following time period are recorded
Tmaxi = 0
Tmin = 0
Tb = 0.4msec.
Jitter J is given by
J=
Tmax i − Tmin
0 .0
=0
x100% =
0 .4
Tb
11.9 Results
Experiments with Digital ICs
160
Laboratory Experiments Series
PSK modulation is obtained using analog switch and PSK demodulation is obtained using
565 PLL IC. The modulated and demodulated waveforms are recorded. From the CRO
waveform, bias distortion and jitter are calculated.
Bd = 57%
J=0
11.10 Discussion
A perfect PSK modulated signal is obtained using JFET analog switch 5012. Demodulation is
obtained for modulated signal varying from 00000000 to 11111111. Demodulation of PSK is
obtained using 565 PLL IC.
The modulated signal is passed through 100 meters of twisted wire and when demodulated,
clear-cut distortions are observed in demodulated signal as shown in Figure-11.10. This
indicates that the modulated signal has to be conditioned before sending through telephone
line. This also gave an idea of the distortion parameters discussed above. The jitter and bias
distortion observed are within the limits of experimental error.
References
1. Jeethendra Kumar P K, ASK modulation and demodulation, Lab Experiments, Vol-2, N02, Sept-2002, Page 42.
2. Modem Basics, EXAR data book, 1987, Page 3-2.
3. National Data Acquisition data book, 1995, Page 8-9.
4. Jeethendra Kumar P K, Wien Bridge Sine-wave Oscillator, Lab Experiments, Vol-2, N02, Sept-2002, Page-54.
5. Uma Prasad B K, Analog to digital conversion using ADC0804, Lab Experiments, Vol-2,
N0-1, June-2002, Page-48.
6. J Anil Kumar, JFET Characteristics, Lab Experiments, Vol-1, N0-1, Nov-2001, Page-32.
7. Malvino A P, Electronic Principles, 1989, Pare 707.
Experiments with Digital ICs
161
Laboratory Experiments Series
Experiment-25
FSK MODULATION AND
DEMODULATION
Abstract
Frequency shift keying (FSK) modulation is studied using a JFET SPST switch.
And demodulation is obtained using PLL. The characteristic parameters of FSK
namely bias distortion and jitter are determined and compared with the theoretical
values.
12.1 Introduction
Frequency shift keying (FSK) and phase shift keying (PSK) are the most popular data
communication techniques through which digital data is transmitted through telephone lines.
Figure-12.1 illustrates a FSK modulated signal by 0101 sequence. FSK encodes two distinct
frequency signals called mark and space. Mark is the high frequency signal represents logic
HI and space is the low frequency signal represents logic LO. A modem [1] perform FSK
modulation and demodulation. The modulated signals are passed through telephone lines.
Therefore the mark and space frequencies should be within the bandwidth of telephone line
(3.1KHz). The spacing between the mark and space frequencies depends on the demodulation
techniques used [2].
1
Mark
0
Space
1
Mark
0
Space
1
Mark
0
Space
Figure-12.1: FSK modulated signal
In this experiment a sine wave of 1KHz and 1.2KHz are used as space and mark frequencies
respectively. Different techniques are used to demodulate FSK. The popular analog scheme is
the phase locked loop (PLL) or using narrow band filter and envelope detectors [3]. In PLL
type of demodulator, the PLL locks to the incoming FSK frequencies and produce two
different DC voltages at the phase detector output. The voltages are then reshaped to obtain 0
and 1.
The demodulation process results in several degradations to the originally transmitted data.
Bias distortion, out put jitter are the two parameters that decide the quality of the
demodulation circuits.
Figure-12.2 shows a 0101 sequence of input transmitted via FSK and demodulated signal.
The demodulated signal is found to have more than 50% duty cycle in the pulse sequence at
certain time.
Experiments with Digital ICs
162
Laboratory Experiments Series
1
0
1
0
1
T1RX
TORX
0
Bias Distorsion
Resulting in variation
in the duty cycle
Figure-12.2: Bias distortion resulting variation of duty cycle
This is the result of distortion that had resulted in duty cycle variation in the demodulated
output. Such a distortion is called Bias distortion. And it is given by
Bd =
0.5T1RX
x100%
T1TX + TORX
Where
…1
T1RX is high state time of the receiving (demodulated) pulse
T1TX is high state time of the transmitted pulse
TORX is low state time of the demodulated pulse
TOTX is low state time of the transmitted pulse
Bias distortion is represented in % in general. The smaller the value of bias distortion better is
the demodulated circuit. The second figure of merit of the FSK demodulation is the jitter.
Jitter is illustrated in Figure-12.3. This is similar to phase variation in sine wave form.
However, the phase difference is not continuous here. It is the discrete phase difference
occurring due to mismatch in the timings of the falling and trailing edges of the pulse
waveform. The jitter is defined as
Tb
1
0
1
Mismatch
Tmin
0
Mismatch
1
0
Mismatch
Matching
Tmax
Figure-12.3: Jitter in the demodulated signal
J=
Tmax i Tmin
x100%
Tb
Where
…2
Tmaxi is maximum time delay between the transmitted and receiving pulse
Experiments with Digital ICs
163
Laboratory Experiments Series
Tmin is minimum time delay between transmitted and receiving pulse
Tb is the half period of the transmitting pulse called time frame bit.
When Tmaxi = Tmin jitter is zero indicating that the received signal is jitter free. Smaller value
of J, better is the receiving signal or more perfect is the FSK demodulation.
12.2 FSK Modulation
FSK modulation is obtained using a JFET analog switch. The quad JFET analog switch
IC5011/5012 pin diagram is shown in Figure-12.4 [4]. The input mark and space signals
produced by Wien Bridge oscillator [5]. Y and W are the ADC outputs [6], which control the
JFET switch.
Y= W
…3
The JFET switch is ON when its gate is at logic HI (+5V), the switch is OFF when the gate is
at logic LO (0V). When the modulating signal is fed to the gate the mark and space signals
are passed from the source to the drain during high state of the pulse sequence. During the
low state of the pulse sequence the switch is of. Consider a HI state appearing at the gate of
Q1 JFET in Figure-12.5, then the W input to the Q2 JFET is LO hence Q2 switch is off. Q1
switch that is closed now passes the mark frequency to the Opamp hence Opamp output has
mark frequency signal. Alternatively, if Logic LO appears on the gate of Q1 JFET then Q1 is
off. Simultaneously Q2 is ON this passes the space frequency to Opamp or the Opamp out
put now contains space frequency. In this manner the space and mark frequencies are passed
through the analog switch to obtain FSK modulated signal. Figure-12.5 shows FSK
modulator circuit. The Opamp is tied in the inverting amplifier mode. The closed loop
voltage gain of the Opamp is given by
A V ( CL ) =
Where
R 2 + rDS ( ON )3
…4
R 1 + rDS ( ON )1, 2
rDS(ON)3 is the drain-source resistance of Q3 FET
rDS(ON)1,2 is the drain source resistance of the conducting FET (Q1 or Q2)
The drain-source resistance [7] of the JFET is of the order of 100 Ohms and in the integrated
form these resistance of individual JFET are almost equal, hence one can write
rDS(ON)1 = rDS(ON)2 = rDS(ON)3 = rDS(ON)4 = rDS(ON)5
Thus closed loop gain reduces to
AV(CL) = - 1 for R1 = R2
Experiments with Digital ICs
…5
164
Laboratory Experiments Series
S
3
D
G
1
Q1
2
4
8
6
Q2
7
5
9
11
Q3
10
12
16
14
Q4
15
13
AH5012/IH5012
Figure-12.4: JFET analog switch
IC-5011/5012
8D
Q3
S6
G7
-15V
IC-5011/5012
1
2
2
3
+
Q1
-
3
4
R1-10K
Mark-1.2KHz
+15V
14 Q2 16
Space-1.0KHz
LF356
0.1
W
R1-10K
6
7
4
IC-5011/5012
15
13
Y
Figure-12.5: FSK Modulator Circuit
Experiments with Digital ICs
R2-10K
0.1
FSK
Output
165
Laboratory Experiments Series
12.3 FSK Demodulation
FSK demodulation or decoding is done with XR2211 FSK demodulator/tone decoder IC.
There are various ways one can demodulate FSK. In the discreet method [3] the modulated
signal is passed through two narrow band filter circuits centered at mark and space
frequencies. The output of the filter is fed to an envelope detector. The output of the envelope
detector is the required demodulated output.
Table-12.1
FSK Band
Component Value
300 Baud
CO=0.039µF, CF=0.005µF,
fmark = 1270Hz
C1=0.01µF,RO= 18K, R1=100K
fspace = 1070Hz
200 Baud
CO=0.022µF, CF=0.005µF,
fmark = 2225Hz
C1=0.0047µF,RO= 18K, R1=200K
fspace = 2025Hz
1000 Baud
CO=0.027µF, CF=0.0022µF,
fmark = 2200Hz
C1=0.01µF,RO= 18K, R1=30K
fspace = 1200Hz
FSK demodulator component values for three different bands
XR2211 is a PLL especially designed for data communication applications [2]. It is well
suited for FSK modem applications. It can accept input signal as low as 2mV to 3 Volts with
frequency as high as 300KHz. Figure-6 shows XR 2211 tied to form FSK decoder. The
resistance RO and CO set the PLL center frequency and R1 sets the bandwidth. C1 sets loop
filter time constant and loop damping
+5V
0.1
FSK
Input
1
2
7
74LS04
51K
1
2
3
4
0.1
510K
13
XR2211
CF 0.0047
CO 0.039
100K
14
4
Demodulated
Output
8
11
C1 0.01
10 12
R1 100K
0.1
RO 15K TP1-1K
Figure-12.6: FSK Demodulator Circuit
Experiments with Digital ICs
166
Laboratory Experiments Series
factor. CFRF form one-pole post-detection filter for the FSK comparator to facilitate rapid
feedback between output logic states. Table-1 lists various component values for three
different FSK band used in modem.
12.4 Instruments Used
Split power supplies ±15, 5V-power supply, dual trace CRO, and Digital Signal Generator
(DSG), frequency counter.
12.5 Components Used
IC 5011/5012, IC XR2211, LF 356, LS00, Resistors 10K, 51K, 510K, 100K, 18K,
Capacitors, 0.1, 0.047µA, 4400pF. Trimpot 10K 3296 type. Solderless bread board.
12.6 Experimental Procedure
The experiment consists of two parts.
Part-A; FSK modulation
Part-B; FSK demodulation
Part-A; FSK modulation
8. The FSK modulator circuit is rigged as shown in Figure-12.5. Frequencies of the mark
and space signals are noted from the output of digital signal generator using frequency
counter.
fmark = 1.285
fspace = 1.012
9. The Y and W output of the DSG is connected to the two analog switches. These are
modulating signals. The output of FSK modulator is monitored on CRO channel-2 in
comparison with modulating signal Y. The output noted is shown in Figure-12.7.
Figure-12.7: Input modulating signal (Top Y) and FSK signal
(Digital photograph is taken with 1KHz and 3KHz signal for easy identification)
Experiments with Digital ICs
Laboratory Experiments Series
167
10. The waveform observed coincided with the pulse waveform indicating perfectness in the
modulation process and no distortion is observed.
11. Trial is repeated by varying the wave from in the DSG. In each case FSK waveform is
coincided with the pulse waveform to see the perfectness of modulation.
Part-B; FSK demodulation
12. The FSK demodulator circuit is rigged as shown in Figure-12.6 using XR2211 IC. The
FSK modulated signal is fed to the demodulator at FSK input terminal. Output of the
demodulator is observed on CRO channel-2 in comparison with the FSK signal as shown
in Figure-12.8.
Figure-12.8: FSK modulated and demodulated signal
13. The trimpot TP1 is adjusted to get faithful reproduction of the demodulated signal.
Figure-12.8 shows FSK demodulated signal and modulating signal Y.
Figure-12.9: FSK demodulated (upper) and modulating signal Y
12.7 Determination of Bias Distortion
14. The modulating signals Y and W are now replaced by 0101-sequence square wave Y′ and
W′ from the DSG. The modulating and demodulated signals observed on CRO as shown
in Figure-12.9. From the CRO waveform following time period is noted.
Experiments with Digital ICs
168
Laboratory Experiments Series
T1RX = 0.8msec
T1TX = 0.5msec
TORX = 0.2msec
TOTX = 0.5msec
Bias distortion is given by
Bd =
=
0.5T1RX
x100%
T1TX + TORX
0.5 x 0.8
0.4
x100% =
= 57%
0 .5 + 0 .2
0.7
Determination of jitter
15. From wave form in Figure-12.9, the following time period are recorded
Tmaxi = 0
Tmin = 0
Tb = 0.5msec.
Jitter J is given by
J=
Tmax i Tmin
0 .0
x100%
=0
Tb
0.5
12.8. Results
FSK modulation is obtained using analog switch and FSK demodulation is obtained using
2211 PLL IC. The modulated and demodulated waveforms are recorded. From the CRO
waveform bias distortion and jitter are determined.
Bd = 57%
J=0
12.9 Discussion
1. A perfect FSK modulated signal is obtained using JFET analog switch 5012. Modulated
signals have sharp changeovers as shown in Figure-12.7. Demodulation is obtained for
modulated signal varying from 00000000 to 11111111. With 00000000 modulating signal
zero volt dc line is obtained and with 11111111 modulating signal square waveform is
obtained.
Experiments with Digital ICs
Laboratory Experiments Series
169
2. Demodulation of FSK is obtained using 2211 PLL IC. This particular IC is optimized for
modem applications. The component values listed in Table-12.1 and Figure-12.6 are to
be very accurate for proper operation of the demodulator.
3. The jitter observed is zero. However, time delay is observed between modulating and
demodulated output as shown in Figure-12.9. For better determination of these
parameters, The modulated signal may be passed through 100 meters twisted wire before
getting it demodulated by the PLL. We have not done this in this part.
References
8. Jeethendra Kumar P K, ASK modulation and demodulation, Lab Experiments, Vol-2, N02, Sept-2002, Page 42.
9. Modem Basics, EXAR data book, 1987, Page 3-2.
10. Gabriel M Rebeiz, EECS Dept, The University of Michigan, Educatorscorner.com
Experiments.
11. National Data Acquisition data book, 1995, Page 8-9.
12. Jeethendra Kumar P K, Wien Bridge Sine-wave Oscillator, Lab Experiments, Vol-2, N02, Sept-2002, Page-54.
13. Uma Prasad B K, Analog to digital conversion using ADC0804, Lab Experiments, Vol-2,
N0-1, June-2002, Page-48.
14. J Anil Kumar, JFET Characteristics, Lab Experiments, Vol-1, N0-1, Nov-2001, Page-32.
Experiments with Digital ICs
170
Laboratory Experiments Series
Experiment-26
DPSK MODULATION AND
DEMODULATION
Abstract
Differential Phase Shift Keying (DPSK) is studied using JFET- SPST switch and
demodulation is obtained using PLL. The characteristic parameters such as bias
distortion and jitter are determined.
13.1 Introduction
DPSK is a common form of phase modulation conveys data by changing the phase of carrier
wave. In Phase Shift Keying (PSK) [1], within one pulse width of logic high state or logic
low state only one cycle of the carrier is imposed. This sometimes confuses because, at the
falling edges of the modulating pulse, the modulated output will have same carrier voltages
for logic Lo and Logic HI as shown in Figure-13.1. To avoid this confusion, in DPSK, in one
pulse widths of the high or low state of the modulating signal one and half carrier is
superimposed. By this modification, for high state logic the carrier appears like a letter M and
for low state logic the carrier appears like W in the modulated signal. Figure-1 shows both
PSK and DPSK modulated signal by pulse train.
1
0
1
0
1
1
1
1
0
1
0
Digital Modulating
Signal 10101111010
DPSK Modulated
Signal
m
w
m
w
m
m
m
m
w
m
w
PSK Modulated
Signal
Figure-13.1: DPSK and PSK modulated signals
This experiment requires two 180 degree out of phase carriers and a modulating signal. Sine
wave from a oscillator is selected as carrier signal. The modulating signal is taped from a
Digital Signal Generator (DSG) that converts DC voltage in to 8-bit pulse train [2]. These 8bit pulse trains are taken as modulating signals. In actual practice modulating signal is digital
form of data. Sine wave is selected as carrier and 180 degree phase shift is obtained using
Opamp as shown in Figure-13.2. Demodulation of DPSK signal is obtained using a Phase
Locked Loop (PLL) circuit.
Experiments with Digital ICs
171
Laboratory Experiments Series
10K-R2
-15V
4
!0K-R1
2
Sine input
3
+
lag
0.1
f
-
f
lead
6
LF356
7
0.1
+15V
Figure-13.2: Generation of two carrier signals
The demodulation process results in few degradation of original transmitted signals. Bias
distortion, output jitter are the two parameters, which decide the quality of the demodulation
circuit. Figure-3 shows pulse sequence 101010 of input transmitted via DPSK and
demodulated signal. The demodulated signal is found to have more than 50% duty cycle in
the pulse sequence at certain time. This results in duty cycle variation in the demodulated
output. Such a distortion is called bias distortion and it is given by,
1
0
1
T1RX
0
1
0
TORX
Bias Distorsion
Resulting in variation
in the duty cycle
Figure-13.3: Bias distortion resulting in the variation of duty cycle
Bd =
0.5T1RX
x100%
T1TX + TORX
Where
…1
T1RX is high state time of the receiving (demodulated) pulse
T1TX is high state time of the transmitted pulse
TORX is low state time of the demodulated pulse
TOTX is low state time of the transmitted pulse
Experiments with Digital ICs
172
Laboratory Experiments Series
Tb
1
0
1
Mismatch
Tmin
0
Mismatch
1
0
Mismatch
Matching
Tmax
Figure-13.4: Jitter resulting in the mismatch of leading and training edges
Bias distortion is represented in % in general. The smaller the value of bias distortion better is
the demodulated circuit. The second figure of merit of the DPSK demodulation is the jitter.
Jitter is illustrated in the Figure-13.4. This is similar to phase difference in sine waveform. It
is the discrete phase difference occurring due to mismatch in the timing of the falling and
trailing edges of pulse waveform. The jitter is defined as
J=
Tmax i Tmin
x100%
Tb
Where
…2
Tmaxi is maximum time delay between the transmitted and receiving pulse
Tmin is minimum time delay between transmitted and receiving pulse
Tb is the half period of the transmitting pulse called time frame bit.
When, Tmax = Tmin jitter is zero indicating that the received signal is free from Jitter, smaller
the J value better is the receiving signal or more perfect is the DPSK demodulation.
13.3 DPSK Modulation
DPSK modulation is obtained using a JFET analog switch. The quad JFET analog switch [3]
IC 5012 pin diagram is shown in the Figure-13.5. The carrier signal is taken from the
function generator and is passed through a inverting amplifier as shown in Figure-13.2, these
two carrier lead and lag signals are input to the two switches. Y and W are the ADC output
which control the JFET switch
Y=W
…3
JFET switch is ON when its gate is at logic HIGH (+5V); the switch is OFF when the gate
terminal of the JFET is at logic LOW (0V). When the modulating signal is fed to the gate the
lead-lag signals are passed from source to the drain during high state pulse sequence. During
low state of pulse sequence the switch is OFF. Consider a high state of Q1 JFET in Figure13.6, then the W input to the Q2 JFET is low hence Q2 switch is OFF. Q1 switch that is
closed now passes the lead frequency to the Opamp hence Opamp output has lead frequency
signal.
Alternatively, if logic LOW appears on the gate Q1 JFET then Q1 is OFF. Simultaneously
Q2 is ON this passes the lag frequency to Opamp or Opamp output now contains lag
frequency. In this manner the lead and lag frequencies are passed through the analog switch
Experiments with Digital ICs
173
Laboratory Experiments Series
to obtain DPSK modulated signal. Figure-13.6 shows DPSK modulator circuit. The Opamp is
tied in the inverting amplifier mode. The closed loop voltage gain of the Opamp is given by
…4
R I + rDs(on)1,2
rDS (on) 3 is the drain- source resistance of Q3 FET
rDS (on) 1,2 is drain-resistance of the conducting FET(Q1 or Q2)
S
3
D
G
1
Q1
2
4
8
6
Q2
7
5
9
11
Q3
10
12
16
14
Q4
15
13
AH5012/IH5012
Figure-13.5: Analog switch pin configurations
Q3
8
6
-15V
IC- 5011/5012
10K
3
Q1
R2
1
2
3
2
10K
10K
TP
14
W
6
LF356
7
4
R1
10K
4
R1
16
Q2
+15V
15
13
IC- 5011/5012
7
+
Where
R F + rDS(on) 3
-
A V(CL) =
Y
Figure-13.6: DPSK Modulator circuit
Experiments with Digital ICs
PSK Output
174
Laboratory Experiments Series
The drain source resistance is of the order of 100Ω which is very small compared to RF and
RI hence the closed loop gain is decided by the resistors RF and RI.
13.4 DPSK Demodulation
DPSK demodulation is obtained using PLL IC 565 [3, 4, 5]. DPSK modulated signal is given
as input to PLL as shown in the Figure-13.7. Demodulation doesn’t require free running
oscillations of PLL. Free running frequency may further modulate the demodulated signal.
Hence pins 8 & 9 are left free.
A capacitor C is connected between pin-7 and supply point to form a low pass filter with
internal resistance of 3.6K. The capacitor C should be large enough to eliminate variations in
the demodulated output voltage and filter the carrier signal. The cutoff frequency of low pass
filter is made equal to carrier frequency. Hence the C value is given by
C=
1
2 πRf H
…5
+15V
1K
10K
3nF
C
+5V
-15V
5
14
6
741
Demodulated
output
1
7414
2
7
7
3
4
3
+
565
2
-
2
7
10K
4
DPSK
Modulated
Signal
10
+15V
1
-15V
Figure-13.7: DPSK demodulator circuit
13.5 Instruments Used
Split power supply ± 15V, dual trace CRO and Digital Signal Generator which consists of Y
and W signals. Y and W are the ADC outputs which is used as modulating signals. It is eight
bit pulse train controlled by SET PULSE knob of DSG. The output of ADC is indicated by
eight LEDs. Hence one can set input from 00000000 to 11111111 just by adjusting the SET
PULSE knob. Figure-8 shows DSG used in this experiment.
13.6 Components Used
IC5012, LF356, 10K resistors, IC741, 2nF Capacitors, Trim pot 10K-3296 type, Solder less
Breadboard
.
13.7 Experimental Procedure
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175
Laboratory Experiments Series
The experiment consists of two parts.
PART A; DPSK Modulation.
PART B; DPSK Demodulation.
Figure-13.8: Digital Signal Generator Used in this experiment
Part –A, DPSK Modulation
1. The modulating signal Y from the DSG is connected to the CRO and Pulse sequence
1000 0000 is set by adjusting the SET PULSE Knob of the DSG. The width of the
pulse is noted as shown in Figure-13.9(a).
Pulse width = 80µsec.
(a)
(b)
Figure-13.9: (a) Pulse width of the modulating signal, (b) The two carrier signals
Within this 80µsec pulse width, one and half cycle sine wave (carrier) is modulated.
Hence the frequency of the carrier is set as
fcarrier =
80
= 53.3 µsec = 18.7 KHz
1.5
Hence carrier frequency is set to 18.7 KHz by adjusting frequency dial of the function
generator. The amplitude is set to above 4V (PP). Two carrier signals are as shown in
the Figure-13.9(b).
Experiments with Digital ICs
176
Laboratory Experiments Series
2. The DPSK modulator circuit is rigged as shown in the Figure-13.6. The Y and W,
outputs of DSG are now connected to the two analog switches. And two carrier
signals are also fed to the analog switches.
3. The modulated output signal is monitored on CRO screen. The carrier frequency is
slightly adjusted so that during high state of the modulating signal, modulated signal
appears like letter M and during low state of the modulating signal, it appears like
letter W. The output observed is shown in the Figure-13.10 with respect to the
modulating signal. The waveform observed is coincided with the pulse waveform
indicating the perfectness in the modulation process and no distortion is observed.
Figure-13.10, DPSK modulated signal compared to modulating signal Y
3.
Trial is repeated by varying the waveform by adjusting SET PULSE knob of DSG.
Part B; DPSK Demodulation
4. DPSK demodulator circuit is rigged as shown in Figure-13.7 using PLL 565. The
output from DPSK modulator circuit is connected to DPSK input terminal.
(a)
(b)
Figure-13.11: (a) Bottom PLL output, Top Opamp output, (b) Demodulated output
from ST in compared to modulating signal Y=10101010.
5. To remove the carrier from modulated signal a low pass filter capacitor is selected as
Experiments with Digital ICs
Laboratory Experiments Series
C=
177
1
1
=
= 2 nF
2 πRf H 2 π 3.6 Kx18.7 K
6. The output of the demodulator is observed on CRO channel-2 in comparison with the
modulating signal Y on channel-1.
7. An Inverting amplifier and Schmitt Trigger (ST) [6] circuits are added to get proper
demodulated output without which there may be slight distortion as shown in the Figure13.11(a). Figure-13.11 (b) shows the demodulated signal coming out from the ST. The
final demodulated signal appears at the ST output.
13.8
Determination of Bias Distortion
9. Modulating signal Y is now placed in 10101010 sequences (which appear like square
wave) by adjusting the SET PULSE knob of the DSG. The modulating and
demodulated signals are observed on CRO. From the CRO waveform following time
period is noted.
TIRX = 100µs
TITX = 80µs
TORX = 80ms
TOTX = 80µs
Bias distortion is calculated using equation-1,
Bd =
13.9
0.5 T1 RX
0.5 x 100 µsec
x 100% =
= 0.31 = 31%
T1TX + T0 Rx
80 µsec+ 80 µsec
Determination of Jitter
10. From waveform in Figure-13.11(b), the following time period are noted
Tmax = 15µs
Tmin = 10µs
Tb = 80µs
J=
13.10
Tmaxi − Tmin
15 µsec− 10 µsec
x 100% =
= 0.065 = 6.5%
Tb
80 µsec
Results
DPSK modulation is obtained using analog switch and DPSK demodulation is obtained using
PLL IC 565. The modulated and demodulated waveforms are recorded. From the CRO
waveform bias distortion and jitter are calculated.
Bd = 31%
J = 6.5%
Experiments with Digital ICs
178
13.10
Laboratory Experiments Series
Discussions
The experiment can be repeated for AC input signal from microphone controlling the ADC.
Further the DPSK signal can be transmitted using simple transistor or MOSFET transmitter.
The response of DPSK for AC signal [voice] will be published in future LE.
References
1. Dr. Jeethendra Kumar P.K, PSK Modulation and Demodulation, Lab Experiments,
Vol-2, No-3, March 2003, P-48.
2. Dr. Jeethendra Kumar P.K, Boolean Function Generator, Lab Experiments, Vol-2,
No-2, Sept 2002, P- 47.
3. Linear Applications, Hand book, National Semiconductor Corporation, AN-46, AN146.
4. A P Malvino, Electronic Principles, Third Edition, P-703.
5. Ramakanth A Gayakwad, Opamp And Linear Integrated Circuits, Second Edition, P399.
6. CMOS LOGIC Selection Guide -1994, P-1-15.
Experiments with Digital ICs
Laboratory Experiments Series
179
Experiment-27
PULSE CODE MODULATION &
DEMODULATION
Abstract
Pulse code modulation and demodulation is studied using codec ICs ADC0804
and DAC0808. The demodulated waveform is compared with input waveform. The
demodulated waveform is observed for different sampling frequencies.
14.1 Introduction
Pulse code modulation (PCM) is a digital scheme [1] of transmitting analog (continuous) data
such as voice, music, image etc. PCM is the basis of pulse modulation or digital modulation.
Sampling process results in PCM. In this process the analog signal is sampled (measured) at a
fixed rate called sampling rate. The process is also known as quantization. Figure-14.1 shows
the process of quantization. Quantization takes place during the falling edge of the sampling
signal. At the instant of falling edge the instantaneous value of the ac signal is coded and
transmitted. For example at the instant A in Figure-1, quantized value 0110 (corresponds to
6th quantized level) is transmitted. At the instant of second falling edge 0111 is transmitted,
and at the instant of the third falling edge 0110 is transmitted and process continues.
A continuous sine wave is converted in to a train of pulses. This conversion is an
approximation because certain portion of the input sine wave is lost during quantization.
Comparing 8 level quantization and 13 level quantization, as the number of the quantization
level increase less and less information is lost. Hence A 256 level or 8-bit quantization has
almost negligible loss.
ADC performs quantization [2] it is also called coder. The ADC requires a sampling signal
SF to its write (WR) input. The analog input is sampled as per SF. This process of sampling
and coding an analog signal is called pulse code modulation. The PCM signal is received at
the receiving end and digital signals are reconstructed to obtain original analog signal.
Almost the reverse processes takes place at the receiving end this reconstruction of the
original signal is called PCM demodulation and it is done by a digital to analog converter
(DAC). The output of demodulator is analog signal and its magnitude is given by [1]
A1
Vo = VREF [ ----- +
Where
A2
A3
---- + ---- + …
2
22
23
An
+ ---]
…1
2
n
VREF is the reference voltage to the DAC
An is the Input bits
Using Equation-1 output voltage is calculated.
Experiments with Digital ICs
180
Laboratory Experiments Series
A
Analog
Input
Sampling
Signal
7
6
Falling Edges
Actual
Input
5
0111
8 Quantized Levels
4
Digitised
Input
3
2
0001
1
0
0000
13
13 Quantized Levels
More
Accurate
digitization
0
Figure-14.1: Basic Process of PCM; Analog input, Sampling signal,
8 quantized levels, 13 quantized levels.
Figure –14.2 shows a PCM modulator-demodulator circuit. To drive input sine wave an
Opamp buffer is used. Input is fed to the ADC along with dc to clamp the dc level. With this
the lower level of the sine input ≈0 (-0.5 volts to be very exact). At the output of the DAC
again Opamp drive is used to reconstruct the analog signal.
14.2 Instruments Used
Digital communications experimental setup DCT301, consisting of ADC 0804, DAC0808,
sampling frequency 4KHz, Regulated power supply 5V, ±15V, and 10K-10-turn trimpot.
Sine wave oscillator 0-200KHz, CRO and DMM.
14.3 Components used
ADC0804 (20pin IC), DAC0808 (16pin IC) LF 356, LM 741. Resistors 150K, 10K, 100Ω,
4.7M and 5.6K. Capacitors 150pF, 0.01µF.
Experiments with Digital ICs
181
Laboratory Experiments Series
14.4 Experimental Procedure
The PCM modulator demodulator circuit is rigged as shown in Figure-14.2. Supply
voltages to 0804, 0808, LF356, LM741 is checked with the DMM. And verified with
value printed in Figure-14.2.
+5V
-15V
+15V
+5V
0.1
150K
4
2
1
3
7
Vi
100
6
+
10K
20
-15V
-
-15V
10.00V
3
16
6
2VPP
741
ADC0804
+15V
3
19
150pF
4
7
1
2
8
12
11
13
10
14
9
15
8
16
7
17
6
18
10
5
14
TP1
10K
4.7M
4.7M
DAC0808
-15V
4
150K
2
3
7
10K
12
Vref
4
2
Sampling
Frequency
4KHz
11
13
2
15
6
+
10K
-
1
LF356
+15V
5.6K
Figure-14.2: PCM Modulator demodulator circuit
2. The clock signal to the ADC is observed at pin 19 of 0804 using CRO. 100KHz clock
signal is observed
Figure-14.3: PCM demodulated output and input waveform
3. 4KHz, 5VPP Sampling signal is connected to ADC at pin 3.
4. The reference voltage to the DAC is set 10.00 exactly using DMM and adjusting trimpot
TP1.
Experiments with Digital ICs
Vo
182
Laboratory Experiments Series
5. The output Vo is observed on CRO channel-B in comparison with the input. The
demodulated out put is observed. The output is shown in Figure-14.3.
6. Trial is repeated by varying sample signal frequency to 3KHz, 2KHz, 1KHz and 500Hz.
The corresponding demodulated signal is observed in comparison with in put signal.
7. Best-demodulated signal is obtained for 4KHz. And below 3KHz sampling frequency the
demodulation is not good.
14.5 Results
PCM modulation and demodulation is studied using 0804 ADC and 0808 DAC ICs. The
demodulated waveform is shown in Figure-3. Best-demodulated output is obtained for 4KHz
sampling frequency.
14.6 Discussion
PCM modulated signal is not observed in the above experiment on CRO. In order to observe
PCM output a MUX is required. The MUX is connected to ADC and MUX output is serial
data, which can be observed on CRO. Addition of MUX and observation of pulse code
modulated signal will be discussed in a separate experiment in the December volume of LE.
References
1
http:// www. Tpub.com/neets/book12/491.htm
2
National semiconductor, National Data Acquisition Data Book, Definitions terms A/D
converters Page2-4, 1995.
Experiments with Digital ICs
Laboratory Experiments Series
183
Experiment-28
PULSE WIDTH MODULATOR
Abstract
Pulse width variation with control voltage is studied in a pulse width modulator
(PWM) based on dual timer NE556. T he PWM is used to drive a 12-volt bulb
using mosfet. Power variation with control voltage is recorded. The PWM
waveform is recorded.
15.1
Introduction
Pulse width modulator generates pulse train having varying pulse width. Such pulse train
used for controlling power in electrical appliances and speed of a dc motor. PWM is not used
for communication purpose. However, the PWM signal also can be demodulated.
Demodulation is the process in which varying pulse is converted into varying voltage by an
integrator. PWM based power supplies are frequently used. The Switch mode power supply
(SMPs) based on PWM is used in PCS. For such applications, dedicated ICs are available.
XR494, 495 are PWM ICs. A dual timer also can be used to produce PWM. NE 556,
XR2556, are dual timers that can also be used to generator PWM signals.
Figure-15.1 shows base diagram of NE556 dual timer [1]. It contains two independent timer
sections. The common between two timers is the power terminal. Each timer section is
equivalent to a 555-timer section with control, trigger, threshold, reset, output and supply
terminals [2]. Each output terminal is capable of sourcing 100mA current and operates over
wide range of voltage 2.5V to 15V.
15.2
Output Pins (5&9)
The output logic level is normally LO state and goes to HI state during timing cycle. Each
output terminals are totem pole capable of sourcing 100mA current.
15.3
Trigger Pins (6&8)
The timing cycle is initiated by lowering the dc level at the trigger pin below (2/3) VCC
15.4
Control Pins (3&11)
The timing cycle or frequency of oscillation can be controlled or modulated by applying a dc
control voltage to these pins. This terminal indirectly biased at (2/3) VCC. The control signal
for frequency modulation or pulse width modulation is applied to these terminals. When not
used these pins are dc grounded through 0.01µF capacitor.
15.5
Discharge Pins (1&13)
Experiments with Digital ICs
184
Laboratory Experiments Series
These terminals correspond to collector of the discharging capacitor. During charging cycle,
this terminal behaves as an open circuit, during discharge it becomes low impedance path
ground.
15.6
Reset Pins (4&10)
The timing cycle can be interrupted by grounding the reset terminal. When the reset signal is
applied, the output goes low and remains in that state while the reset set voltage is applied.
When the reset signal is removed, the output remains low until re-triggered. When not used
the reset terminal is connected to VCC to avoid any false triggering.
15.7
Basic Operations
The timer can be operated in the monostable and astable mode. In the monostable, it uses one
resistor (R) and one capacitor (C) similar to 555[2]. In the monostable mode R and C decide
the ON time or the pulse width. Applying dc voltages to the control input also further
increase the ON time. R and C decide the minimum pulse width. The minimum pulse width is
given by
TW=1.1RC
…1
In the stable, mode two resistors RA and RB and C1 decide the frequency. Addition of one
more resistance gives rise to duty cycle. The frequency of oscillation and duty cycle is given
by
f =
1.44
C1 (R A + 2 R B )
…2
D=
RB
R A + 2R B
…3
To get a square wave RA<<RB is selected.
Discharge
Threshold
Control
Reset
Output
Trigger
GND
1
2
14
13
3
12
NE556 11
4
10
5
Vcc
6
7
Output
9
8
Discharge
Threshold
Control
Reset
Trigger
Figure-15.1: Pin diagram of NE556 dual timer
To get PWM output one half of the 556 is used as monostable and other half is used as a
stable mode. The astable output is inputted to the trigger input of monostable. The
Experiments with Digital ICs
Laboratory Experiments Series
185
modulating signal is fed to control input. Figure-15.2 shows PWM circuit. While designing
PWM the following frequency, relations are followed.
1. First, decide the frequency fm of the modulating signal.
2. The astable frequency (fT) for triggering monostable is selected such that fT>10 fm
3. The minimum pulse width TW is taken >TT/2 where
TT =
1
fT
…4
The pulse width modulator is used to drive a power mosfet connected 12Volt auto lamp. The
average power variation is recorded in this experiment.
15.8
Instruments used
Regulated power supplies 5V/0.4A, decade capacitor box, dual trace CRO 20MHz, and
digital dc voltmeter 0-20V and DMM with frequency measurements and regulated battery
eliminator 1.2 to 12V/1A.
15.9
Components Used
IC NE556, Capacitors 0.01µF, 0.033µF, 0.047µF, 70kpF, resistor 10K, 6.8K, 560Ω.
15.10 Experimental Procedures
The experiments consists of five different parts
Part-A, Astable clock frequency variation with capacitor C1
Part-B, Monostable pulse width variation with capacitor C
Part-C, Variation of pulse width with control at input (pin-3)
Part-D, Sine wave pulse width modulation
Part-E, Light intensity control using PWM.
Part – A, Astable clock frequency variation with capacitor C 1
1. Using second half of the dual timer a astable multivibrator circuit is rigged as shown
in Figure-15.2 with C1 replaced by a decade capacitor box. The capacitance in box is
set to 10KpF. The potentiometer POT-1 is set to its maximum value so that pin-3 is at
+5V.
2. The output at pin-9 is monitored on CRO channel-B. The peak-to-peak amplitude and
frequency of the square wave is noted. The reading obtained is tabulated in Table15.1.
V0=5V, fT=10KHz
3. Trial is repeated by changing C1 in suitable steps and the corresponding frequency of
the square output is noted. In Table-15.1.
Experiments with Digital ICs
186
Laboratory Experiments Series
+5V
10K
RL
PWM
Output
10K
R
4
5
10K
RL
10
2
1
13
C
70pF
1/2 556
1/2 556
3
6
RA
560
9
+5V
10K
POT-1
14
RB
6.8K
12
8
7
11
C1
0.033uF
0.01uF
Figure-15.2: Pulse width modulator circuit
Table-15.1
Clock Frequency fT
C(KpF)
Pulse width TW (msec)
(KHz)
Expt
Thet
Expt
Thet
10
10.00
10.16
60
0.28
0.257
20
4.97
5.08
70
0.32
0.300
30
3.36
3.38
80
0.36
0.343
40
2.52
2.54
90
0.40
0.386
50
2.03
2.03
100
0.44
0.429
60
1.68
1.69
200
0.92
0.858
70
1.45
1.45
300
1.30
1.287
80
1.27
1.27
400
1.80
1.711
90
1.12
1.12
500
2.20
2.145
100
1.01
1.01
600
2.80
2.574
Astable RA=560Ω,RB=6.8KΩ
Monostable R = 3.9KΩ,fT=2.14KHz
Frequency of the square wave generated by monostable and pulse width obtained in the
monostable operation
C1(KpF)
Part-B, Monostable pulse width variation with capacitor C
4. Using the second part of the dual timer monostable multivibrator circuit is rigged as
shown in Figure-2. The trigger input pin-6 of the monostable fed by astble output
from pin-9 of astble multivibrator. The trigger frequency is noted.
f T = 2.14KHz (R A = 560Ω, R B = 6.8Kand C1 = 0.033µF)
5. The capacitor C in the DCB is set to 60KpF and by varying C the width variation is
noted. With C=60KpF the pulse width in noted from the CRO screen. The pulse width
obtained is recorded in Table-15.1.
Experiments with Digital ICs
187
Laboratory Experiments Series
6. Varying C in the box in suitable steps and the corresponding pulse width in noted in
Table-15.1 repeats trial.
Part-C, Variation of pulse width with control voltage at control input
7. In this part of the experiment both C = 70KpF and C1=0.033µF is fixed. The clock
frequency and pulse width is noted
f T = 1.6KHz, t W = 0.70m sec
8. The control voltage to pin is slowly reduced by adjusting the POT-1. The variation in
the pulse width is noted. Using digital voltmeter control voltage is measured. The
readings obtained are tabulated in Table-2. Figure-3 shows pulse width variation with
control input.
9. Trial is repeated by varying control voltage up to 1 volt. Finally, the trim pot is
disconnected from the control input and pulse width is noted.
Table-15.2
VCon(V)
TW(µsec)
5.0
820
4.5
700
4.0
520
3.5
420
3.0
320
2.5
250
2.0
180
0.9
125
Open
60
Pulse width variation with control voltage
900
Pulse Width (Micro sec)
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
Control Voltage (V)
Figure-3, Pulse width variations with control voltage
(RA=1K, RB=10K, C1=0.033µF, R=6.8K, C=50KpF)
Experiments with Digital ICs
6
188
Laboratory Experiments Series
10. The POT-1 connected to the control input-3 is removed in its place a sine wave
oscillator is connected. It is the modulating signal. The frequency of the modulating
signal is set to 200Hz. The modulating signal is monitored on channel-A of the CRO.
The amplitude of the modulating signal is slowly varied until the PWM signal is
appears on CRO channel-B as shown in Figure-15.4.
Figure-15.4, Pulse width modulation of sine wave
(a) fm=200Hz, fT=2.14KHz(b)fm=250Hz,fT=2.14KHz.
11. Trial is repeated for different frequency modulating signal. Figure 4(b) shows PWM
signal obtained for 250Hz sine wave modulating signal.
Part-E, Light intensity control using PWM.
12V/3A
12V
Auto lamp
D
2
4
PWM
Signal
IRF540
1
3
G
IRF
540
S
GDS
Figure-15.5: PWM is used to vary light intensity
The PWM signal produced is bused to control light intensity of 12V auto lamp. Power Mosfet
IRF540 is used as driver. The PWM signal is fed to the gate of the Mosfet and the load bulb
is included in the drain circuit as shown in figure-5. By varying the control voltage intensity
found to vary. The power across the load varied from 14watt to 30watt for pulse width
variation from 60µsec to 820µ second.
15.11
Results
For a given value R and C pulse width varied more than a decade from 60µsec to 820µ
second as shown in Table-15.2. The pulse width variation with the control voltage non-linear
as shown in Figure-3
15.12
Discussion
The dual timer produced PWM signal. It is observed that pulse width of the monostable
section depends on two parameters
1. The R and C time constant
2. The control voltage at pin-3
Experiments with Digital ICs
Laboratory Experiments Series
189
R and C decide the minimum pulse width. Control voltage varies pulse width above this
minimum value. The pulse width variation is exponential as shown in Figure-3. PWM signal
obtained for sine wave is shown in Figure-4. The signal can be demodulated and one can get
back the original signal using an integrator combination
References
[1]
EXAR data book, Exar corporation, page 5-131, 5-141.
[2]
Robert F coughin and Frederick F Driscoll, Operational amplifier and linear integrated
circuits, 3rd Edn, Page-333.
Experiments with Digital ICs
190
Laboratory Experiments Series
Experiment-29
TIME DIVISION MULTIPLEXING
Abstract
Time slot is studied in Time Division Multiplexer (TDM) circuit using CD4052
analog multiplexer. In a given time slot three different sets of input signals are fed
to four different channels of the multiplexer and output waveforms are recorded.
Using dc voltage, amplitude variation of TDM signal is also studied.
16.1 Introduction
Time division multiplexing (TDM) is widely used multiplexing technique is digital
communication. Fiber optics cables use TDM for transmission of multiple signals, so the
extensive use of fiber optics has increased the use of TDM worldwide. Time division
multiplex access (TDMA) is used in third generation (3G) mobile communication, which
allocates unique time slot for each user. This gives access to many users within same channel
without interfacing one another. Global system for mobile communications (GSM) makes use
of TDMA and now it has become the standard technology for mobile communication [1].
A given period is divided in to equal parts and each part of time is allotted to particular user
in TDM. TDM allows many signals to be placed on a single high bandwidth channel. For
example, a single mode fiber optics cable containing 75,200Mbits/sed wave –guide can
transmit bits of information.
75x200x106 =15Gbits/sec.
A telephone connection requires 3400Hz bandwidth, it is sampled at the rate of 8000bits/sec,
and each sample is pulse code modulated by 8-bits/sec. Then
8x8000 =64000bits/sec
must be transmitted for each telephone conversation. The capacity of the TDM is given by
15 x109
= 2,34,375
64000
Two lakh thirty four thousand telephone conversations could be carried over a single optical
cable. This is amazing and it is the strength of TDM.
TDM is a form of digital modulation the demodulation of which is also very simple.
Nyquist’s sampling theorem is always be the fundamental consideration in TDM, which says
the signal to be transmitted through TDM shoul have sampling rate more than twice the
highest frequency of the signal. For telephone conversation the highest frequency is 3400Hz,
twice of which is 6800 sample/sec. in practice, 8000samples/sec is the standard sampling
rate, which is slightly above the Nyquist’s limit. TDM is used in three important practical
applications namely,
Experiments with Digital ICs
191
Laboratory Experiments Series
1. Optical fiber telephone line
2. Mobile communications
3. Data acquisition in instrumentation
+5V
14
1
14
1
CLK
4
3
2
10K
7
16
B9
3
4
A 10
12
1
Cha-4 11
3
4
fin
V3
Cha-2 14
V2
Cha-1 12
V1
10K
5
6
7
8
10K
POT
10K
Cha-3 15
2
1/2- LS107
7
7400
V4
10K
6
5
7400
13
10K
CD4052
10K
Figure –16.1: TDM Circuit
In data acquisition it is used to acquire data from different sensors and pass through a
common channel for analysis. A multiplexer out put is TDM signal. There are two types of
multiplexer namely the digital multiplexer and the analog multiplexer Digital multiplexer
respond to HI-LO inputs whereas an analog multiplexer responds to any voltage level and
wave shape. Figure-16.1 shows TDM circuit tied using analog multiplexer 4052. Figure-16.2
shows pin diagram of dual multiplexer 4052. CD4052 is a dual 4-channel CMOS multiplexer
(MUX). In this experiment, only one part of the MUX is used. The JK flip flop 74LS107 is
used to divide the clock frequency by 2. The two control signals A and B generate
00,01,10,11 sequences of inputs at the control input of the MUX.
12
14
15
11
1
5
2
4
6
10
9
X0
X1
X2
X3
X
Y
13
3
Y0
Y1
Y2
Y3
INH
A
B
4052
Figure-16.2: Pin diagrams of CD4052 dual MUX
In the TDM circuit shown in Figure-1, the four input channels are fed from a voltages
divider. Therefore, at different channels the voltage is different. These voltages V1, V2, V3,
V4 are passed to MUX out put during different interval o time. During the period 0-t1
seconds, 00 (AB) appears on the control input, this connects the channel-1 to the output
terminal 13, hence the input at the channel-1 is transmitted to the output of the MUX and
MUX output becomes V1.
Experiments with Digital ICs
192
Laboratory Experiments Series
During the period t1-t2, 01 appears on the control input, this connects the channel-2 to the
output terminal 13, hence the input at the channel-2 is transmitted to the output of the MUX
and MUX output becomes V2.
During the period t2-t3, 10appears on control input, this connects the channel the channel -3 to
the output terminals 13, hence the input at the channel -3 is transmitted to the output of the
MUX and MUX output becomes V3,
During the period t3-t4, 11 appears on the control input, this connects the channel-4 to the
terminal 13, hence the input at the channel -4 is transmitted to the output of the MUX and
MUX out put becomes V4. During one full cycle of the clock (A) period all the four channels
are connected to the outputq` of MUX for 1/4th of the clock period. Hence, the output of
MUX will be different voltage levels at different interval or it is a staircase waveform as
shown in figure –16.3.
0
1
2 3
4
5 6
7 8
B
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
0
t1 t2 t3 t4 t5 t6 t7 t8
4V
Vo
4V
3V
3V
2V
1V
2V
1V
0V
Figure-16.3: TDM output for dc inputs
In telephone applications instead of dc voltage at the different cannel inputs different
subscriber will speak. Each subscriber will be connected to common transmission line once
per clock period for time of 1/4th of clock period. Alternatively, the speakers will be
connected and disconnected from the common transmission line. This Processes of
connecting and disconnecting takes place at very fast rate so that the speaker will not
experience it. That is the beauty of multiplexing.
In this experiment, we have used three sets of inputs for multiplexing namely
1. DC input through voltage divider network.
2. AC voltage through voltage divider network
3. sine, square, triangle and dc, four different wave forms
Experiments with Digital ICs
Laboratory Experiments Series
193
The TDM output is recorded for all these three sets of inputs.
If fin is the frequency of the clock input (control signal A) to the TDM the time slot is given
by
Ts =
1
2 fin
The Time slot appears as step width in the output waveform shown in figure –16.3. Hence,
step width of the stair case waveform.
T w = Ts
If V1, V2, V3,V4 are the inputs to the four different channels, then the step height of the
staircase wave form is given by
Vs =Vn where n=1,2,3,4 is inputs to different channels.
16.2 Instruments used
Regulated power supply 5V/1A, split power supply ±12V/0.4A, dual trace CRO 20MHz,
function generator 1Hz -200KHz and DMM.
16.3 Components used
ICs 4052, 74LS107, 74LS00, 8038 resistors 10K, capacitors 0.1µF, pot 10K carbon metal
shaft.
16.4 Experimental Procedure
The experiment consists of three parts
Part –A, TDM response to dc input
Part –B, TDM response ac input
Part-c, TDM response to mixed input
PART-A, TDM response to dc input
1. The TDM circuit is rigged as shown in figure-16.1.
2. A function generator is connected to the CLK input of the TDM and square wave
amplitude is set to 5Vand frequency 1KHz. The clock signal is monitored on CRO channelA. The inverses are required to get TTL input.
3.The control signal B from the JK flip flop is also monitored on CRO channel-B and the
frequencies of the two control signals to the MUX is noted. The control signals are shown in
figure-16.4.
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Frequency of the control signal A= 1000Hz
Frequency of the control signal B= 500Hz
Figure-16.4: Control A (top) and control signal B (bottom)
4. The pot is set to its maximum position and the voltages at four input channels are measured
using DMM. The Voltages V1,V2,V3,V4 measured are recorded in Table-16.1.
5. The output at pin13 of the MUX is monitored on CRO channel –B in comparison with
control signal –A (CLK). The output obtained is shown in figure-16.5.
Figure-16.5: TDM response for DC signal
6. The height of the each step is measured on CRO scale and the width of the step is
measured and recorded in Table-16.1.
7. Trial is repeated by varying the input to the voltage divider by varying pot. The voltages
V1, V2, V3, V4 again measured and recorder in Table-16.1.
8. To confirm the signal selection by the MUX, pin-11 of the MUX is connected from the
voltage divider. This disconnection removes the highest step in staircase. Like other channels
are disconnected one by one and signal is confirm by disappearance of step in the staircase
output. By removing all the four channels, CRO showed zero dc level.
9. By varying frequencies of the input square wave, time slot is determined in each case and
presented in Table-16.2
Table-16.1
In put of different channels
Step Height
V1(V) V2(V)
V3(V)
V4V) Step-1 Step-2 Step-3
1.00
2.00
3.01
4.03
1.10
2.10
3.20
0.80
1.59
2.39
3.20
0.90
1.80
2.50
0.61
1.22
1.84
2.45
0.60
1.35
1.90
0.50
1.00
1.50
2.00
0.50
1.10
1.60
0.30
0.61
0.92
1.23
0.28
0.34
0.90
0.00
0.00
0.00
0.00
0.00
0.00
0.00
TDM signal step height variation with input voltage
Table-16.2
Input Clock
Clock period
Time slot
Step width
frequency (fin)
Tin
TiS
TW
1
1msec
500µsec
500µsec
2
500µsec
250µsec
250µsec
3
333µsec
166µsec
180µsec
4
250µsec
125µsec
130µsec
5
200µsec
100µsec
105µsec
Time slot variation with input clock period
Part –B, TDM response to ac input
Experiments with Digital ICs
Step-4
4.20
3.40
2.50
2.10
1.25
0.00
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Laboratory Experiments Series
+12V
TP1
4.7K
6
4.7K
10K
4
5
9
7
3
10K
8038
8
Square 4.5V
10
12
2
TP2
Triangle 4.5V
20K
11
TP3
0.1uF
82K
20K
Sine 4.5V
-12V
Figure-16.6: Function generator 8038 producing sine, square and triangular outputs
10. The Potentiometer top terminal connected to the +5V supply is disconnected and instead
of DC voltage a sine wave form generated by 8038 is fed to the pot as shown in figure –16.6.
with 4.5V sine input to the potentiometer the TDM output is monitored as shown in figure16.7 (a). Figure16.7 (b) shows TDM output for square input fed to pot input. The Period of
the input sine (160µsec) is kept well below the clock period (500µsec).
Figure –16.7: TDM outputs (a) for sine input (b) to square input
Part C, TDM response to mixed input
11. Four different inputs are selected similar to four different telephone line for this part of
the experiment. The outputs shown in Figure-16.7 and the fourth input is taken as dc voltage.
These four inputs are connected to four different channels of the TDM.
Channel-1 sine wave, 3KHz, 4.5V
Channel-2 Dc input 3.5V
Channel -3square input 3KHz, 4.5V
Channel-4 Triangular input 3KHz, 1.5V
By feeding these, signals TDM output is monitored on CRO channel-A. The output observed
is shown in figure –16.8.
Figure -8, TDM out put for four different inputs
16.5 Results
In a TDM circuit obtained using analog multiplexer CD4052, the time slot (Ts) observed is
found to half input clock period (Tin) in all the trials as shown in Table –16.2. For a dc input
the TDM output is staircase waveform as shown in figure- 16.5, the step width is equal to
time slot.
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16.6 Discussions
A Mux is used to produce TDM output in this experiment. The staircase output of the TDM
is one of best I have come across with provision of varying step height and step width. Such a
waveform is useful in studying three terminal semiconductor devices. In such case, staircase
wave form is used as base or gate drive.
Response of the TDM to four different inputs verifies the concepts multiplexing of telephone
signal and sending it through a common transmission line. One can study a 8-channel TDM
using 4051 CMOS multiplexer.
References
[1] All about the latest mobile technologies, www.rediff.com/netguide/2003/jul/21
mobile.htm
[2] Time –Division Multiplexing, www.engr.sjsu.edu/igarcia/Tech
Experiments with Digital ICs
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Chapter-8
Memories
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198
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Experiment-30
STATIC RAM (SRAM)
Abstract
Using 74LS189 static RAM, 4-bit binary data is stored in 16- different memory
locations. The stored data is read by applying suitable address and control signal.
21.1 Introduction
Random access memory (RAM) is temporary storage device in computer where the operating
system, application programs and data in current use are kept for the easy and quick access of
the processor. Because of its speed, it is easy to read from and write in to RAM, in compared
to other storage devices such as hard disk, floppy disk and CD-ROM. However, the data stays
in RAM only till the computer is on. When the power is off RAM data is lost. Hence, it is a
volatile memory. Nonvolatile RAM (NVRAM) is special kind of RAM that retains data
when the computer is turned off. A battery backup inside the computer makes it non-volatile.
The computer hard disk can become full with data and further it may not accept any data.
Whereas a RAM does not become full, it always accepts data. However, its speed becomes
slow as its capacity is reached.
Based on the structure there are two types of RAM [1] namely
1. Static RAM (SRAM)
2. Dynamic RAM (DRAM)
Based on applications there are numerous RAMs, such as Burst Static RAM (BSRAM), Fast
Page Mode DRAM (PPMDRAM), Enhanced DRAM (SDRAM), Extended Data Output
RAM or DRAM (EDO RAM, EDO DRAM), Synchronous DRAM (SDRAM) [2] etc. Table1 lists the merits and demerits of two type RAMs. Both these RAMs are used in computer
depending upon the application. The name RAM is called random access because any storage
location can be accessed directly.
Features
Simplicity
Speed
Cost
Size
Table-20.1
SRAM
DRAM
Does not require refresh circuit to retain Requires refresh circuitry to
data
retain the data
Faster
Slow
Expensive
Cheap
Big
Small
Comparison of SRAM and DRAM
21.2 74LS189 SRAM
74LS189 SRAM is simplest and cheapest RAM available and selected for this experiment. It
is a group of addressable registers. After placing address on the address line, one can read the
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data from or write the data in to the RAM. It is a read-write memory. Core RAM was the
earlier magnetic version and SRAM and DRAM are its semiconductor versions.
Commercially available RAMs have three state outputs. Because of this, one can connect,
disconnect and float the output with suitable control signals from the data bus. Figure-1
shows a typical RAM, and Table-2 gives the basic functions of a RAM.
Address
WE
Data
Input
Di
Data
Output
SRAM
Do
CE
Figure-21.1: Basic RAM structure
CE
0
0
1
Table-21.2
Operation
Write
Read
Hold
Basic RAM operations
WE
0
1
X
Output
Floating
Connected
Floating
Vcc
A2
A1
A0
D0
D0
D1
D1
16
15
14
13
12
11
10
9
74LS189
1
2
3
A3
CE
WE
4
5
6
7
8
D3
D3
D2
D2
GND
Figure-21.2: Pin configurations of 74LS189
The address bits select memory locations and the control signals CE and WE select write,
read or do nothing operations. The output is bubbled input
Dout = Din
…1
74LS189 is a 64-bit SRAM organized in 16 bit words of 4-bit each [3]. Figure-2 shows pin
configurations of 74LS189. A3 A2 A1 A0 are the four address lines, D3 D2 D1 D0 are four
input lines and D3 D 2 D1 D0 are the four output lines. To program the chip a set of address
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and data are applied to the respective lines and WE taken to LO. This loads the data and
WE taken back to HI data is stored in the respective memory location.
21.3 Instruments Used
Digital trainer with 5V power supply, logic monitors and HI-LO switches.
21.4 Components Used
IC 74LS189
21.5 Experimental Procedure
Address
A3 A2 A1 A0
1 15 14 13
Input Data
Set on HI-LO
Switches
D0
12
D1
10
D2
6
D3
4
11
D0
9
D1
7
D2
74LS189
5
Outputs
to logic
monitors
(LEDs)
D3
WE
16
8
2
3
+5V HI= READ
LO= WRITE
CE
+5V
Figure-21.3: Circuit connections for read write operation
1. The circuit is rigged as shown in Figure-3 on the digital trainer. The control signal CE is
held LO.
2. WE is set to HI on HI-LO switch
3. 4-bit address and 4-bit data are also set on HI-LO switches
Address = A3 A2 A1 A0 = 0 0 0 0
Data = D3 D2 D1 D0 = 0 0 1 0
4. WE is taken back to LO. This loads the data 0 0 1 0 in memory location 0 0 0 0. The data
and address is tabulated in Table-3.
5. Trial is repeated by incrementing the address to 0 0 0 1 and corresponding data to be
stored is set to 0 1 1 0.
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201
6. This process of addressing and storing the data is continued until all the memory locations
are addressed from 0000 to 1111.
Address
A3 A2 A1 A0
Table-21.3
Input
D3 D2 D1 D0
Output
D3 D 2 D1 D0
0000
0010
1101
0001
0110
1001
0010
0100
1011
0011
0101
1010
0100
0101
1010
0101
1001
0110
0110
1011
0100
0111
1001
0110
1000
1101
0010
1001
1111
0000
1010
0000
1111
1011
0001
1110
1100
0101
1010
1101
1101
0010
1110
0101
1010
1111
0010
1101
Data stored at various memory locations
21.6 Reading stored data
7. To read the data from the memory location 1100, address line is set to 1100 and WE is
set to LO on HI-LO switch. The content of the memory location 1100 is displayed on the
output lines connected to the logic monitors.
Address =1100
Output = 1010 which indicate stored data as 0101
Which tally with data in Table-3.
8. Similarly by applying corresponding address and taking WE is to HI stored data can be
read on the monitor as inversion.
21.7 Results
In 74LS189 4-bit SRAM, data addresses are set with LO WE and when WE is taken to HI
the data is stored at the location. This is the write operation
With WE is HI address is applied to the SRAM and when WE is taken back to LO the logic
monitors display-stored data as the inverse of the input. When CE is held HI the outputs are
floated or the IC is disabled.
21.8 Discussion
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Fundamental function of SRAM is studied in this experiment by writing binary data in to 16
different memory locations. The stored data is read by applying address and control signal.
Two 74LS189 can be connected in parallel to get 8-bit data storage. In such cases, the address
lines to both the ICs are the same [1].
With WE is HI, address and data are applied, and when WE goes LO the logic monitors
where the outputs are connected goes off irrespective of the input. This indicates the
functioning of the IC. When WE is HI again the monitors should indicate inverse of the input
stored.
References
[1]
A P Malvino and J A Brown, Digital computer electronics, Page-133.
[2]
Fast Guide to RAM-a Whatis.com definition
[3]
A P Malvino and D P Leach, Digital principles and Applications, Page-396.
Experiments with Digital ICs
Laboratory Experiments Series
Chapter-9
Microprocessors
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Experiment-31
DISPLAY OF NAME USING 8085
MICROPROCESSOR KIT
Abstract
Using seven segment LED displays of the 8085-microprocessor kit a program is
written to display ones name. The possible letters and its codes are worked out.
Introductions
Microprocessor is the brain of a computer. But it can not be compared with the human brain.
Human brain is much much more than a microprocessor or a computer. One may surprise if I
say that 70% of the world best brains are of Indians! However, Indians brains are sparingly
used. Hence it is always fresh and demanded one in the world. A microprocessor is a central
processing unit (CPU). It is available in the integrated circuit (IC) form. Among the
microprocessor 8085 IC is most familiar and it is the last 8-bit microprocessor manufactured
by Intel Semiconductor Corporation.
To understand the functioning of a microprocessor (µP), its architecture is studied first.
Architecture give the details of various functional blocks of the µP and their control signals
and conditions. Once you understand these functional blocks and control signals, it is easy to
use the µP in the circuit. To get use out of the µP it has to be programmed. Programming is a
set of instructions to µP, which tells what to do. These sets of instructions are called software.
Without the software the µP is a dead brain. Microprocessor can not understand English.
Therefore a separate language is developed to make the µP understand the instructions. This
language is called machine language or assembly language. Further to feed the machine
language to the µP keys are required. The alphanumeric keyboards can not understand
machine language. Hence a special type of code and keyboards are developed to feed the data
to the µP. This code is called opcode. Therefore one need to connect the English instructions
in to machine language and machine language in to opcode. Therefore to use the µP or to
design circuit with µP one need to study the instructions and its opcode first. The opcode is
different for different processor. Among them the instructions of 8085 are the simplest and
the most familiar one.
Inside 8085 µP there are 10 separate registers namely register A, B, C, D, E, H, L, PSW, and
PC and register SP. Among these register A is also called accumulator. Accumulator is just
like a drama stage where things come, go and perform. Here the processes of addition,
subtraction etc takes place and the results of these operation remains there or can be transfer
to other registers or to some memory locations.
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The µP trainer kit consists of address field and data field. For example the address field is
contains four 7-segment displays to indicate the memory location. And the data field contains
two 7-segment displays to indicate the content of the memory location. Totally there are six
7-segment displays. Using these 6 displays it is possible to write a program to display 6-letter
word or name. In this experiment a program is written to display ones name and the codes of
the letters to be displayed are worked out.
7-Segment LED Display
A common anode seven segment display is shown in Figure-1. The seven segments of the
display are named as a, b, c, d, e, f, g and dp. Each of these segment will glow when the
corresponding segment terminal is connected 0 volt or logic LO. The decimal point indicator
dp makes it totally 8-segment display. For examples by grounding segment a, d, e, f and g to
logic LO we get letter E as shown in Figure-1. To get letter E segments b, c and h are held HI
(+5V). This can be written as an equation in Table-1. Similarly one can work out and
generate code for possible alphabetic letters. Theses 8-bit code is in the binary form.
Microprocessor work on hexadecimal numbers. Hence these binary codes are converted in to
hexadecimal codes.
g f
a
a b
+5V
f
b
g
e d
c dp
e
+5V
Front View
c
d
dp
Figure-1, Common anode display and its pin configurations
Table-1
Segment
dp
a
b
c
d
e
f
g
Logic Status HI
LO
HI
HI
LO
LO
LO
LO
Code
0
1
1
0
0
0
0
1
8-bit Code for letter “E”
Letter E is represented by 1011 0000 these 8-bit code is split in to four upper bit and four
lower bit. The four lower 1011 bits are equivalent to 11 in decimal and B in hex decimal. The
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four upper bits 0000 are equivalent 0 in both decimal and hexadecimal. Hence the code for E
is now written as BO. Similar conversions are done for all possible letters and presented in
Table-2.
1011= B, 0000 = 0 or 1011 0000 = B 0
Not all the alphabet letters are possible to display using seven-segment display. Letters such
as M, N, Q, K, V, W, X and Z are not possible. To display the name AJEYA.P the codes are
Table-2
Letter
Code
Letter
Code
Letter
Code
Letter
Code
Letter
Code
A
88
E
86
I
F9
P
8C
U
C1
b
83
F
8E
J
F1
r
AF
Y
99
C
C6
G
90
L
C7
S
92
-
BF
d
A1
H
89
O
C0
t
87
.
7F
Letters and their codes
Table-3
A
J
E
Y
A.
P
88
F1
86
99
08
8C
Here the code for A is 88 but for A. it is 08 (the decimal dp should glow to indicate.) Is
worked using Table-2.
Programming the µP Kit
To write a program to display alphanumeric one need to know how exactly the displays are
connected to the µP trainer kit. A programmable keyboard display controller IC 8279 [1]
controls the keyboard and the display in the trainer kit.
8279-Programmable keyboard display controller
8279 is a programmable display and keyboard controller used in the trainer kit. It scans and
encodes up to 64-key keyboard and controls 16-digit numerical display [2]. An internal 16x8
RAM called display RAM controls the 7-segment display. Display RAM stores the codes of
the letters to be displayed. The codes are loaded at certain memory locations. One by one
these codes are transferred to the accumulator from which it is transferred to the display
RAM.
Experiments with Digital ICs
Laboratory Experiments Series
207
To perform these transfers two instructions called control address is made use. D1 is the
control word address of 8279 and D0 is the data address. The control word pattern used for
writing in the display RAM is given by
100 AI AAAA
Where
…1
100(H) is the write command to the display RAM
AI is the command to increment or decrement the address bit in the display
RAM. AI=1 increments and AI=0 decrements the address bit. If AI=1, then
address specified by the RAM will be incremented after each write operation.
AAAA is the address bits, which point to the RAM address.
The control word in the equation now reads as
100 1 0111
9
…2
7
This is the control word to display alphanumeric. Here AI =1 and AAAA= 0111 the last four
bits is taken as 7 so as to remember the IC number 8279. During this auto increment mode is
set and display RAM is made to point the 7th location of the display RAM. The letter
corresponding to that location is displayed. In all the interactions the same memory location
(0111) is used to write in to the display RAM.
Algorithm
Algorithm is the logical set of functions given as instructions to the microprocessor to
perform. The microprocessor performs these instructions. Once name to be displayed is
selected (the sweetest word that one think is his name) one can start writing the program. We
have selected name AJEYA.P the codes of this name are stored at memory location F900
called memory location MAD. Microprocessor is asked to read these codes. The total number
of letters to be displayed (N) is also given to the microprocessor as instruction.
•
Move immediately the total number (N=06) of 7-segment displays in the µP Kit to
register C. Register C now loads number 06.
•
Load register HL with the codes of the six letters to be displayed, with the first letter code
starting at specified memory location called MAD .HL registers loads the codes of the
word to be displayed from the memory location starting at MAD=F900
Experiments with Digital ICs
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Laboratory Experiments Series
•
Move the control word of 8279 (equation 2, 1001 0111) to the register B. Register B is
loaded with control word 97.
•
Move the contents of the register B in to the register A or the accumulator. The data from
register B is transferred to register A.
•
Output the content of A through port D1. Control word is now sent to the display RAM to
receive data.
•
Move the contents of the HL register pair to accumulator so as to perform next operation.
The first letter (A=88) code is moved to the register A.
•
Out the contents of the accumulator through the port D0. The content (A=88) is moved to
the display RAM to active the segments of the display and letter A is displayed.
•
Increment the content of the HL pair. This loads second letter code from the memory
location F903, code corresponds to letter J.
•
Decrement the contents of the register B. Control word is decrement by one (96).
•
Decrement the contents of the register C. Program counter is decrement from 6 to 5
•
Jumps to step 4 if there is no zero from the previous step else go to the next step.
•
Stop.
Experimental Procedure
1. The microprocessor kit is connected to the power supply and supply is switched on. The
sign on message ISU-85 appears on the monitor.
2. The code data (Table-3) is stored at the memory location starting at F900 by pressing
SUB.MEM key as shown in Table-4. This loads all the codes of the letter to be displayed.
3. The program is now loaded at a memory location starting at F800. The contents and the
operations performed by the µP are listed in Table-5.
Table-4
SUB MEM.
.
F900
F900
NEXT
F900.
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88
F900.88
NEXT
F901
F1
F901.F1
NEXT
F903
86
F903.86
NEXT
F904
99
F904.99
NEXT
F905
08
F905.08
NEXT
F906
8C
F906.8C
NEXT
F907
RESET
ISU-85
Table-5
Label
Address
Mnemonics
Opcode
Register Contents
A
Start
LOOP1
4
B
C
HL
F800
MVI C,N
OE,06
06
F802
LXI H,MAD
21,00,F9
06
F900
F805
MVI B,97
06,97
97
06
F900
F807
MOV A,B
78
97
97
06
F900
F808
OUT, D1
D3,D1
97
97
06
F900
F80A
MOV A,M
7E
88
97
06
F900
F80B
OUT, D0
D3,D0
88
98
06
F900
F80D
INX H
23
88
98
06
F901
F80E
DCR,B
05
88
97
06
F901
F810
JNZ, LOOP1
C2,07,F
8
88
98
06
F901
F813
STOP
76
88
98
06
F901
After feeding the data and program, to see the results the microprocessor is executed
as follows
RESET
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GO TO F800
EXEC.
By pressing these keys the name AJEYA. P is displayed as shown in Figure-2
Figure-2, The name AJEYA.P is displayed on the monitor
Results
1.
A program is written by understanding the process of the 7-segment display connection to
8279-keyboard display controller.
2.
The codes of the possible letter are generated and listed in Table-1. Letters W, X, Y, V, Z,
Q, R are not possible to display.
Discussions
1.
Ones name is the sweetest word for him. Hence displaying his name is the best word for
this experiment. This program gives an idea that how the big big advertising sign boards
near the city bus stand or railway station work displaying series of words.
References
1. 1 Ramesh S Goanker, Microprocessor Architecture, Programming and Applications with
8085, 4th Ed, Page-436.
2. http://www.csee.umbc.edu/~plusquel/310/slides/8086_IO3.html
Experiments with Digital ICs
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211
Experiment-32
DIGITAL STOP CLOCK
USING MICROPROCESSOR KIT
Abstract
A classic experiment that converts an 8085 microprocessor kit in to digital stop
clock is presented here. It is programmed to count railway time (24- hours’ clock),
regular time (12-hour clock) and further it is programmed to start or stop at
prescribed time.
Introduction
Microprocessors since its invention revolutionized human life in various ways. It has been
taught to students at various levels starting from the post graduate level to polytechnic levels.
Now it is the time to experiment it at the plus-two level.
The 8085 microprocessor kit stood firm in the electronic curriculum because of its wide
applicability, easy to understand and easy to program capability. It is both malleable and
ductile microprocessor. The latter versions (8086) did not become as popular as 8085 in
educational curriculum. Many experiments based on 8085 are presented in various text books
and journals. However, this particular experiment is a classic experiment that can not be
forgotten. The accuracy of counting time using microprocessor kits depend on the
propagation delays due to various ICs involved in the process of counting. For laboratory
practical purposes it is an accurate time counting machine which can be used for process
control and display applications.
Programming the 8085 µP kit
To write a program to set stop clock one need to know how exactly the displays are
connected to the µP trainer kit. A programmable keyboard display controller IC 8279
controls the Keyboard and the display in the trainer kit.
The software uses the monitor routines DELAY, UPDDT, UPDAD to provide Hour, Minutes
and Seconds display in the address and data fields.
UPDAD: Updad is used in the keyboard and serial modes to update the address field display
using the current address stored at locations FFF7h and FFF8h.
UPDDT: Upddt is used in the keyboard and serial modes to update the data field using the
current data at location FFF9h.
DELAY: The procedure used to design a specific delay by loading an appropriate number
into one of the register. A register is loaded with number depending on the time delay
required and then the register is decremented until it reaches zero by setting up a loop with a
conditional jump instruction. The loop causes the delay depending upon the clock period of
the system. To count in one second, 0.5 µsec delay is provided.
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Algorithm
1. Initialize the register B, which is used to set the Seconds.
2. Initialize the HL register pair. Register L is used to set the Minutes and
H is used to set the Hours.
3. Move the content of register B into the Accumulator.
4. Push the content of register pair BC onto the stack.
5. Push the content of register pair HL onto the stack.
6. Push PSW onto the stack.
7. Store the content of HL register pair in memory location FFF7h.
8. Call the UPDAD instruction which has been already stored in the
address 06BC in the system permanently.
9. Pop off the stack to the PSW.
10. Push the PSW onto the stack.
11. Store the content of accumulator in the memory location FFF9.
12. Call the UPDAD instruction which has been already stored in the
memory address 06D3 permanently.
13. Push the HL pair onto the stack.
14. For specific delay load the appropriate number into the H register.
15. Call the delay program in step (40).
16. If register H is not zero jump to step (14).
17. Pop off the stack to the HL pair.
18. Pop off the stack to the PSW.
19. Pop off the stack to the HL pair.
20. Add immediately the number 01 with the content of accumulator and
the result is in accumulator.
21. Adjust the content of accumulator to its BCD number.
To set seconds
22. Compare the content of accumulator with a number 60.
23. Jump to the step (5) if there is no zero resulted due to step (22). Else
follow the next step.
24. Pop off stack to the BC register pair.
25. Move the content of register L into the accumulator.
26. Add immediately the number 01 with the content of accumulator and
the result is in the accumulator.
27. Adjust the content of accumulator to its BCD number.
28. Move the content of accumulator to its BCD number.
To sets a minutes
29. Compare the content of accumulator with the number 60.
30. Jump to the step (3) if there is no zero resulted due to step (29). Else
follow the next steps.
31. Initialize the accumulator.
32. Initialize the register L.
33. Move the content of register H into the accumulator.
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Laboratory Experiments Series
213
34. Add immediately the number 61 with the content of accumulator and
the result is in accumulator.
35. Adjust the content of accumulator to its BCD number.
36. Move the content of accumulator into register H.
To set hours
37. Compare the content of accumulator with the number 24.
38. Jump to step (3) if there is no zero resulted due to the step (7). Else
follow the next step.
39. Jump to step (1).
40. Load the DE register pair with number FFFF. (FFFF is one part of delay
count to give exact one second delay).
41. Call the delay subroutine in the address 04BE permanently.
42. Load the DE register pair with number F000 (F000 is other part of delay
count to give exact 1 sec delay).
43. Call the delay subroutine in the address 04BE permanently.
Program Description
The program to count from 00-59 and reset to 00 at 60th count with a one second delay
between counts is listed below. At the instant of 60th count, the counter resets itself to zero
and the sequence of counting repeats. This is true for seconds and minutes counting. To count
time in hours, 12 hour (conventional time) the resetting is done at the instant of 12th count
and for the 24 hours clock (railway time) the resetting is done at the instant of 24th counts.
•
To set 12 Hours clock the number 24 is replaced by 12 in step 37 (at the
memory location F741).
•
To start the clock at certain prescribed time such as 10hours, 30minutes and 30
Seconds the respective hours, minutes and seconds counts are changed (at the
memory location F701 for Seconds, F703 for Minutes, F704 for hour).
To set the time delay the default delay which is at address 04BE is used. This provides a
delay – returns to calling routine after input argument is counted down to zero. INPUT: D, E
16 bit quantity for loop count.
In this case, using one loop (DE register pair) we can provide a time delay one second
maximum. To provide more than 1second delay, the delay routine is called, using another
loop (register H).
For example to set 5 seconds delay for counting,
The register H is loaded with number 05h (at the memory location F719). Register H is
decremented until it reaches zero by setting up a loop with a conditional jump instruction.
Within this loop there is another loop which contains DE register pair. A register pair DE is
loaded with number FFFF (at the memory location F749) and F000 (in memory location
F74F). This loop provides 1 second delay. Register H LOOP calls the DE register pair LOOP,
5 times (register H is loaded with count 05h) and 5 second Delay is obtained.
Experiments with Digital ICs
214
Laboratory Experiments Series
Experimental Procedure
The microprocessor kit SDA8085 is powered and following program is entered starting at the
memory location F700.
Press
Keys
RESET
Sub. Mem
F700
NEXT
Display
-sda 85
.
F700
Enter the Opcode in the program
Program
Label
Start
Loop2
Loop1
Loop4
Address
F700
F702
F705
F706
F707
F708
F709
F70C
F70F
F710
F711
F714
F717
F718
F71A
F71D
F71E
F721
F722
F723
F724
F726
F727
F729
F72C
F72D
F72E
F730
F731
F732
F734
Mnemonics
MVI B,00
LXIH 00,00
MOV A,B
PUSH B
PUSH H
PUSH PSW
SHLD FFF7
CALL UPDAD
POP PSW
PUSH PSW
STA FFF9
CALL UPDDT
PUSH H
MVI H,01h
CALL loop3
DCR H
JNZ loop4
POP H
POPPSW
POP H
ADI 01h
DAA
CPI, 60
JNZ loop1
POP B
MOV A,L
ADI , 01h
DAA
MOV L,A
CPI ,60
JNZ loop2
Experiments with Digital ICs
Opcode
06,00
21,00,00
78
C5
E5
F5
22,F7,FF
CD,BC,06
F1
F5
32,F9,FF
CD,D3,06
E5
26,05
CD,48,F7
25
C2,1A,F7
E1
F1
E1
C6,01
27
FE,60
C2,07,F7
C1
7D
C6,01
27
6F
FE,60
C2,05,F7
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Laboratory Experiments Series
Loop3
F737
MVI A,00
F739
MVI L,00
F73B
MOV A,H
F73C
ADI 01h
F73E
DAA
F73F
MOV H,A
F740
CPI 24
F742
JNZ loop1
F745
JMP start
F748
LXID FF,FF
F74B
CALL delay
F74E
LXID F0,00
F751
CALL delay
F754
RET
Program for counting time
3E,00
2E,00
7C
C6,01
27
67
FE,24
C2,07,F7
C3.00,F7
11,FF,FF
CD,BE.04
11,00,F0
CD,BE,04
C9
Figure-1: Twenty four hour railway clock: starting time 10hrs 20minutes 30secs
When the program is executed, the OUTPUT is seen on the six seven segment displays of the
kit. Figure-1 shows a 24-hour clock started at 10 hours 20 minutes and 30 seconds.
Note
To stop the clock at a particular time permanently, the RET (F754) is replaced by
HALT instruction.
In case of conditional return instruction the sequence return to the main program if
the condition is met. Otherwise the sequence in the subroutine is continued.
Therefore we replace RET instruction by HALT instruction.
Results
1. A program is written by understanding the Delay and Counting process.
2. The clock can be made to count time in 12-hours mode or 24 hours mode by
changing entry at memory location F741.
3. To start the clock at a predetermined time the entry at the memory location
F701 for seconds, F703 for minutes, F704 for hours can be altered.
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Laboratory Experiments Series
References
[1]
Ramesh S Gaonkar, Microprocessor Architecture, Programming and Application with
8085, 4th Ed, Page-251.
[2]
A P Malvino and D P Leach, Digital Principles and Application 4th Ed, Page-327.
Experiments with Digital ICs