Journal of Electrical and Control Engineering
JECE
Series Compensation with Negative Inductance:
Stability Analysis and Applications
JoséAntenor Pomilio1, Leonardo de Araújo Silva2, AndréAugusto Ferreira3
School of Electrical and Computer Engineering, University of Campinas1,2
Electrical Energy Department, Federal University of Juiz de Fora 3
Brazil
antenor@fee.unicamp.br;2leonardodearaujo@gmail.com; 3andre.ferreira@ufjf.edu.br
1
Abstract - This paper presents the use of synthesized negative
inductances, connected in series with an electrical network for
improving the power quality by mitigating disturbances as
voltage drop. The negative impedance synthesis is based on
Direct Reactance Synthesis method, in which the voltage
produced by a power inverter is proportional to the derivative
of the current. Any VSI voltage source converter can be used
to implement the proposed control strategy. In order to
validate the proposed method, experimental results have been
obtained with a cascaded multilevel inverter that is more
suitable for high power applications. Results were also
obtained with a PWM inverter. The paper also presents the
system dynamic modelling and its stability analysis.
filter order and on its components but also on the impedance
of the grid in which the device (VAPAR, DSR or BVI) is
connected to. Hence, as far as series compensation of
transmission or distribution lines are considered, at least a
second order filter must be used. For this reason, the BVI
(Bootstrap Variable Inductance) control strategy [10] seems
to be less feasible for series compensation purposes.
In order to produce a negative inductor, the terminal
current of the VAPAR is controlled to track the reference
given by (1), in which, 𝐿𝑛𝑒𝑔 , is the value of the negative
inductance that is intended to be synthesized. In this case, if
a voltage source converter is concerned, a closed loop
feedback control algorithm must be implemented.
Keywords - Series Compensation; Negative Inductance; Non
Natural Impedance; Multilevel Inverter
I.
𝑖𝑡∗ 𝑡 =
INTRODUCTION
1
𝐿𝑛𝑒𝑔
𝑣𝑡 𝑡 𝑑𝑡.
(1)
it
The self-inductance of transmission lines, among other
effects, limits the maximum power that can be transferred
through power grid busses.
vc
V DC
Traditionally, banks of capacitors have been connected
in series with long transmission lines in order decrease its
impedance and increase transmission power capability.
Unfortunately these capacitors may cause resonances
requiring countermeasures to avoid electrical oscillations, or
even generator-turbine shaft failure [1]-[2].
VSI Converter
vt
Low Pass Filter
it
ic
I DC
The self-inductance also impacts the voltage regulation
of distribution line endings, which may not be properly
compensated by step voltage regulators, especially if there
are cyclical or short term variable loads.
vt
CSI Converter
Low Pass Filter
Fig. 1 VAPAR or DRS schematic circuits.
This work discusses a method to synthesize non-natural
impedances. This method is based on DRS (Direct
Reactance Syntheses) strategy [11] that consists on realizing
the control of the device’s terminals voltage instead of the
current. Hence, the voltage terminal reference is given by:
Controlled variable artificial negative inductances,
which can be artificially synthesized with power converters,
could solve these problems better than classical approach
methods. Series [3]-[4], or shunt compensation [5]-[6] can
be applied, depending on the disturbance nature. Hence,
some control strategies to produce artificial negative
inductance, as the VAPAR [7]-[9], the BVI [10] and the
DRS [11] have been proposed.
𝑣𝑡∗ 𝑡 = 𝐿𝑛𝑒𝑔
𝑑𝑖 𝑡 𝑡
𝑑𝑡
(2)
Equations (1) and (2) define essentially the same
relationship between the terminal variables, 𝑖𝑡 and 𝑣𝑡 .
However, they lead to very different control strategy
approaches. Generally, the derivative operation is avoided
due to fact that high frequency noise is amplified. This
disadvantage can be overcome with software filters.
Nevertheless, choosing equation (2) is a better alternative if
series applications are concerned, because it makes possible
to set up a very stable open loop control strategy, as
The VAPAR (Variable Active Passive Reactance) and
the DRS can be implemented by using voltage or current
source converters, as show in Figure 1. In order to avoid the
flow to the grid of the high frequency switching components
produced by the converter, a low pass filter must be used at
the converter output.
The effectiveness of the filtering depends not only on the
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King Scientific Publishing
22
Journal of Electrical and Control Engineering
JECE
Comparing both terms of the transfer function it can be
noticed that for 𝐿𝑆 ≫ 𝐿𝑓 and 𝑅𝑆 ≫ 𝑅𝐿𝑓 the gain regarding
𝑉𝐶 𝑠 is higher than to 𝑉𝐴𝐵 𝑠 . Hence, the device’s
terminal voltage, 𝑣𝑡 , depends more on 𝑣𝐶 than on 𝑣𝐴𝐵 . This
means that the converter may be capable of rejecting
disturbances caused by 𝑣𝐴𝐵 without significant increase of
its output voltage 𝑣𝐶 .
presented at sections II, III and IV.
For real application purposes, it is desirable that a
control strategy of the DC voltages of the inverter be
established, because it makes possible to substitute the DC
voltage sources by controlled voltage capacitors. This may
reduce implementation cost and makes the compensation
device less cumbersome. In section V this possibility is
discussed as well as the impact of this procedure on the
equivalent synthesized impedance. Experimental results are
presented in sections VI and VII.
II.
Considering typical values of 𝑅𝑆 and 𝐿𝑆 and the use of
high quality factor filter components, it is expected that 𝑅𝑆
and 𝑅𝐿𝑓 effect is dominant in the low frequency range,
below synchronous frequency, while 𝐿𝑆 and 𝐿𝑓 determine
the high frequency response, around synchronous and above.
This issue is important because it allows that an open-loop
control strategy of 𝑣𝑡 be established and, additionally,
defines some design tips to achieve efficient design in terms
of the converter requirements.
SERIES COMPENSATION STRATEGY
This section describes the realization of the proposed
DRS method. Figure 2 represents a simple radial system in
which the transmission line is represented by an inductance,
𝐿𝑆 , and a resistance, 𝑅𝑆 . A power electronic converter
synthesizes in its terminals a virtual negative inductance,
𝐿𝑛𝑒𝑔 , that compensates part of the line reactance.
In spite of being possible to set up an open-loop control
strategy, it is necessary to introduce damping in order to
avoid the excitation of the system modes during transient
disturbances. A state space feedback algorithm [12], as
shown in figure 3, can perform such damping effect. The
algorithm feedbacks the states through a vector of gains 𝐤,
given by (8), and through feedforward gain 𝑘𝑔 , which is
necessary to make the open loop gain between 𝑣𝑡∗ and 𝑣𝑡 , at
the fundamental frequency, be equal to 1.
vt
A
jLS
RS
it
RLf
Generator
RCf
Cf
iCf
vCf
B
10 o
iLf
Lf
𝐤 = 𝑘𝑖𝐿𝑓
vc
𝑘𝑖𝐿𝑠
𝑘𝑣𝐶𝑓
(8)
v AB t 
jLneg
vt * t 
kg
+
vc t 
-
B
+
x
+

x
C
it t 
vt t 
VDC
A
Fig. 2. Series Compensation of a Radial Transmission System
This circuit determines a two-input two-output plant that
can be modelled in state space form:
Fig. 3. State space feedback diagram.
𝐱=𝐀∙𝐱+𝐁∙𝐮
𝐲=𝐂∙𝐱
(3)
− 𝑅𝐿𝑓 + 𝑅𝐶𝑓 /𝐿𝑓
𝑅𝐶𝑓 /𝐿𝑓
𝑅𝐶𝑓 /𝐿𝑆
1/𝐶𝑓
− 𝑅𝑆 + 𝑅𝐶𝑓 /𝐿𝑆
1/𝐶𝑓
𝐀=
−1/𝐿𝑓
𝐁∙𝐮=
0
𝐲=
0
−1/𝐿𝑆
0
𝑖𝑡
= 𝐂 ∙ 𝐱 = −𝑅
𝑣𝑡
𝐶𝑓
0
0
1
𝑅𝐶𝑓
k
State feedback can be used to force the eigenvalues to
the left region, improving the damping characteristic. The
transfer function zeroes are not affected by the state space
feedback, hence it may be possible to cancel some of them.
1/𝐿𝑓
𝑇
−1/𝐿𝑆 ,
0
(4)
𝑣𝐶
𝑣𝐴𝐵 ,
(5)
𝑖𝐿𝑓
𝑖𝐿𝑠
𝑣𝐶𝑓
(6)
0
1
This procedure guarantees that the terminal voltage, 𝑣𝑡 ,
asymptotically tracks the reference 𝑣𝑡∗ . Although, as far as
𝑣𝑡 is expected to be essentially sinusoidal, the poles should
be placed in a frequency that is much higher than the
fundamental one.
The high frequency gain produced by the derivative
operation of equation (2) can be limited by adding poles
[13] as illustrated in figure 4. A drawback of doing this is
the introduction of a delay that leads to a phase
displacement on the reference voltage and that depends on
the frequency that the poles are inserted. The delay is small
if the poles are inserted in a high frequency. However, as
high is this frequency, as poor is the filtering action
introduced by the poles.
The transfer functions from the inputs, 𝑣𝐴𝐵 and 𝑣𝐶 , to
the output 𝑣𝑡 are given by:
𝑉𝑡 𝑠 =
𝑠 2 𝐿𝑆 𝑅𝐶𝑓 𝐶𝑓 +𝑠 𝐿𝑆 +𝑅𝑆 𝑅𝐶𝑓 𝐶𝑓 +𝑅𝑆
𝜆 𝑠
𝑠 2 𝐿𝑓 𝑅𝐶𝑓 𝐶𝑓 +𝑠 𝐿𝑓 +𝑅𝐿𝑓 𝑅𝐶𝑓 𝐶𝑓 +𝑅𝐿𝑓
𝜆 𝑠
. 𝑉𝐶 𝑠 +
. 𝑉𝐴𝐵 𝑠
(7)
𝜆 𝑠 is the system characteristic polynomial.
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King Scientific Publishing
23
Journal of Electrical and Control Engineering
Lneg p 2 s vt * t 
s  p 2
JECE
v AB t 
kg
+
vc t 
-
B
+
x
+

x
C
complex plane. However, this would require high gains that
might not be feasible for practical implementations.
it t 
vt t 
One of the zeroes of the transfer function (17) is closed
to the origin and, due to this, one of the system poles can be
placed closed to it, without dynamic degradation. The other
system poles can be placed at a frequency 10 times higher
than the maximum frequency that the device is supposed to
behave as a negative inductance.
derivator
A
k
Fig. 4. DRS implementation with State Space feedback.
If the reference voltage to be synthesized by the DRS is
essentially sinusoidal, the feedforward open loop gain, 𝑘𝑔 ,
must be calculated to make the gain of the transfer functions
between 𝑣𝑡 and 𝑣𝑡∗ unitary at the fundamental frequency:
III. THE EQUIVALENT SYNTHETIZED IMPEDANCE
An expression for the equivalent synthesized impedance
by the DRS can be determined. From the schematic diagram
of figure 2, it can be noticed that this impedance is given by:
𝑍𝑆𝐷𝑅 𝑠 =
𝑉𝑡 𝑠
𝐼𝑡 𝑠
=
1+𝑠𝑅 𝑐𝑓 𝐶𝑓
𝑠𝐶𝑓
∙
𝐼𝐶𝑓 𝑠
𝐼𝑡 𝑠
= 𝑍𝐶𝑓 𝑠 ∙
𝐼𝐶𝑓 (𝑠)
𝐼𝑡 (𝑠)
𝑉𝑡 (𝑠)
𝑉𝑡∗ (𝑠)
(9)
(11)
(12)
From figure 4:
𝑉𝑡∗ 𝑠 = 𝑠𝑝1 𝑝2 𝐿𝑛𝑒𝑔 𝐼𝑡 𝑠 / 𝑠 + 𝑝1 𝑠 + 𝑝2
𝑉𝐶 𝑠 = 𝑘𝑔 𝑉𝑡∗ 𝑠 + 𝐤. 𝐗(𝑠)
𝑘 𝑣𝐶𝑓
𝑠𝐶𝑓
𝐼𝐶𝑓 𝑠 = 𝑍𝐿𝑓 + 𝑘𝑖𝐿𝑓 𝐼𝐿𝑓 𝑠 +
(14)
𝑠𝑘 𝑔 𝐿𝑛𝑒𝑔 𝑝 1 𝑝 2
𝑠+𝑝 1 𝑠+𝑝 2
𝑘𝑖𝐿𝑠 𝐼𝑡 𝑠
+
𝑠𝐿𝑛𝑒𝑔 𝑘 𝑔 𝑝 1 𝑝 2 + 𝑍𝐿𝑓 +𝑘 𝑖𝐿𝑓 +𝑘 𝑖𝐿𝑠
𝑠+𝑝 1 𝑠+𝑝 2 𝑠𝐶𝑓
𝑠𝐶𝑓 𝑍𝐿𝑓 +𝑍𝐶𝑓 +𝑘 𝑖𝐿𝑓 −𝑘 𝑣𝐶𝑓 𝑠+𝑝 1 𝑠+𝑝 2
TABLE I
Output filter
𝐼𝑡 𝑠
Series
Inductor
(16)
Control Gains
Finally, substituting (16) in (9) the expression for the
DRS impedance is found:
𝑍𝐷𝑅𝑆 𝑠 =
𝐿𝑓
0 0
𝑇
=
𝑠=𝑗 2𝜋60
(18)
(15)
Substituting (10) in (15) and isolating𝐼𝐶𝑓 :
𝐼𝐶𝑓 𝑠 =
1
The control diagram of figure 4 has 5 poles. Two of
them can be directly located with equation (4), and the three
other poles can be located by choosing proper values of
control gains, using standard state space theory. One of
these poles can be located to cancel the zero that is close to
the imaginary axis, which is helpful to ensure lower control
gains. The system parameters and control gains are shown
in Table 1.
(13)
If (13) and (14) are substituted in (11) the following
expression can be found:
𝑍𝐶𝑓 −
−
In order to verify the feasibility of the proposed method
for practical system, a low power prototype of the circuit
shown in figure 2 has been built in laboratory. The electric
parameters of the filter ( 𝐿𝑓 , 𝑅𝐿𝑓 , 𝐶𝑓 , 𝑅𝐶𝑓 ) and the series
impedance (𝑅𝑆 , 𝐿𝑆 ,) are shown in Table I. They have the
same order of magnitude of real parameters of a high
voltage long transmission line.
Where,
𝑍𝐿𝑓 𝑠 = 𝑅𝐿𝑓 + 𝑠𝐿𝑓 .
−1
1
(10)
𝑍𝐶𝑓 𝑠 𝐼𝐶𝑓 𝑠 = 𝑍𝐿𝑓 𝑠 𝐼𝐿𝑓 𝑠 + 𝑉𝐶 𝑠 .
=
𝑘𝑔 −𝑅𝑐𝑓 𝑅𝑐𝑓 1 𝑠𝐈 − 𝐀 − 𝐤𝐱
From that circuit we can also obtain the following
expressions:
𝐼𝐿𝑓 𝑠 = 𝐼𝑡 𝑠 − 𝐼𝐶𝑓 𝑠 ,
𝑠=𝑗 2𝜋60
System poles
𝑠𝐿𝑛𝑒𝑔 𝑘 𝑔 𝑝 1 𝑝 2 + 𝑍𝐿𝑓 +𝑘 𝑖𝐿𝑓 +𝑘 𝑖𝐿𝑠 𝑠+𝑝 1 𝑠+𝑝 2 1+𝑠𝑅 𝐶𝑓 𝐶𝑓
𝑠𝐶𝑓 𝑍𝐿𝑓 +𝑍𝐶𝑓 +𝑘 𝑖𝐿𝑓 −𝑘 𝑣𝐶𝑓 𝑠+𝑝 1 𝑠+𝑝 2
(17)
Controller
Expression (17) indicates that the impedance depends on
the state feedback gains, on the derivative poles, on the
resistances and on the filtering elements. However it doesn’t
depend on the line impedance, neither on 𝑣𝐴𝐵 . In other
words, it doesn’t depend on the parameters of the system
that the DRS is connected to.
DC/CA
Converter
Voltage
Source (vAB)
IV. CONTROL SETUP AND STABILITY ANALYSIS
Theoretically, state space feedback can allocate system
poles anywhere in complex plane and the best results would
be achieved if these poles were placed far left in the
SYSTEM PARAMETERS
Lf = 3,24 mH, RLf = 1,0, powder iron core;
Cf = 344F, RCf = 0,096, (Polyester)
LS = 449mH, RS= 17,98, (Laminated iron core)
Kg = 2,79
k = [ -22,056 22,926 1,791]
𝑝1,2 = −2𝜋800∠ ± 45𝑜
𝑝3,4 = −2𝜋800∠ ± 30𝑜
𝑝5 = −50
Texas Instruments DSP - TMS320F2812
Switching frequency: 12kHz
Control frequency 24kHz
Discretization method: Bilinear
Three series connected H-bridge International Rectifier
modules (IRAMX16UP60A) (Multilevel Asymmetric
Cascaded single phase converter)
DC voltages: (99V: 33V: 19.8V) *
Total DC voltage: 𝑉𝐷𝐶 = 151.8𝑉
*
unless otherwise specified.
DC capacitances: 2.82mF (electrolytic)
Programmable voltage and frequency power source California Instruments (4500 iL)
Figure 5 shows the representation of the equivalent
impedance of an ideal negative inductor and the synthesized
impedance obtained with DRS method for this set of
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King Scientific Publishing
24
Journal of Electrical and Control Engineering
JECE
parameters. The synthesized impedance approaches the
reference impedance for low frequencies. As the frequency
rises, magnitude and phase errors impedance become
greater. At the fundamental frequency, 60 Hz for example,
the magnitude still is very close to the magnitude reference,
although the phase is no longer so close. The difference is
due to the position of the poles that have been introduced to
the derivative operation and the not canceled complex poles
of the transfer function (18). If operation at higher
frequencies is concerned, those poles must be moved left in
the complex plane. An alternative is to decrease the
damping rate of the complex poles of equation (13) and
(18), or use just one pole for equation (13). For series
compensation application, in which low frequency behavior
is concerned, the control bandwidth does not need to be
high. Hence, the chosen set of control parameters may lead
to satisfactory results.
substitution of the DC voltage source by controlled voltage
capacitors. Ideally, if it were possible to synthesize an ideal
negative inductance, there would be no active power
transfer between the DRS device and the power line source.
However, for practical situations, it is necessary to absorbs
active power from line in order to compensate the converter
losses. Additionally, the phase of the synthesized
impedance, which is not equal to -90ºfor all frequencies,
cause some impact on the active power flow between the
converter and the line.
Taken into account that the voltage and current
waveforms in transmission systems are essentially
sinusoidal, the active power flow is strongly dependent on
the impedance phase at the fundamental frequency. From
figure 5, it can be noticed that this phase is smaller than
-90º, which means that the DRS device must provide active
power to the system.
4
Magnitude ()
10
The phase difference can be corrected by adding to the
reference voltage, 𝑣𝑡∗ , a signal that is proportional to the
terminal current, 𝑖𝑡 , as shown in figure 7. This technique is
known as resistive load synthesis, because the
proportionality ratio, which is determined by the DC
controller, 𝑅𝑐𝑜𝑚𝑝 , has a resistive behavior [14].
3
10
2
10
1
10
0
10 1
10
2
3
10
4
10
10
0
If multilevel DC/AC converters are concerned, the
proposed DC phase correction strategy can be used to
control the total DC voltage. However it is also necessary to
implement a strategy to equalize each DC voltage source of
the multilevel converter that depends on the multilevel
topology.
Phase (º)
-90
-180
-270
-360
Ideal Negative Inductance
Synthesized Impedance
-450 1
10
2
3
10
4
10
10
Frequency (Hz)
The proposed DC control method affects the synthesized
impedance and a new expression for it can be found.
Assuming that losses are negligible and the terminal voltage
and current are sinusoidal, the steady state value of 𝑅𝑐𝑜𝑚𝑝 is
the real part of expression (17) at the fundamental frequency.
The low pass filter is supposed to eliminate the 120 Hz
oscillation of 𝑉𝐷𝐶 . Due to this, 𝑅𝑐𝑜𝑚𝑝 can be assumed to be
constant over a line cycle and the expression for the
converter voltage becomes:
Fig. 5. Magnitude and Phase Diagram of the Synthesized Impedance.
Stability analysis of the DRS device with different
negative inductance reference values or with different
system parameters can be tested using classical control
theory. Figure 6, for example, shows the system poles
location if negative inductance reference value varies from 0
to 100% of series line inductance.
1
x 10
4
400
0.259
0.8
0.259
0.383
7e+003
0.5
0.5
300
300
250
0.707
6e+003
0.793
5e+003
Imaginary Axis
150
3e+003
0.966
2e+003
0.991
100
100
0.966
𝑍𝐷𝑅𝑆 𝑠 =
0
1e+003
0.991
2e+003
0.966
0.991
-100
50
0.966
150
4e+003
0.866
0.793
-0.6
5e+003
2
(20)
-200
200
0.793
(21)
0.707
6e+003
0.707
0.609
0.5
7e+003
0.383
-0.8
0.259
250
-6000
-4000
-2000
0
*
 VCC t 
0.609
-300
300
0.5
0.131 8e+003
0.383
0.259
-1
-10000 -8000
𝑠𝐶𝑓 𝑍𝐿𝑓 + 𝑍𝐶𝑓 + 𝑘𝑖𝐿𝑓 −𝑘𝑣𝐶𝑓 𝑠 + 𝑝
𝑤 𝑠 = 𝑍𝐿𝑓 + 𝑘𝑖𝐿𝑓 + 𝑘𝑖𝐿𝑠 + 𝑘𝑔 𝑅𝑐𝑜𝑚𝑝 (𝑠 + 𝑝)2
0.924
0.866
1 + 𝑠𝑅𝐶𝑓 𝐶𝑓
100
3e+003
0.924
𝑠𝐿𝑛𝑒𝑔 𝑘𝑔 𝑝2 + 𝑤 𝑠
50
0.991
1e+003
0
-0.4
200
0.866
0.924
0.924
-0.2
200
4e+003
(19)
Consequently, the new expression for the synthesized
impedance is:
0.707
0.793
0.866
0.4
0.2
𝑉𝐶 𝑠 = 𝑘𝑔 𝑉𝑡∗ 𝑠 + 𝐤 ∙ 𝐗 𝑠 + 𝑅𝐶𝑜𝑚𝑝 𝑘𝑔 𝐼𝑡 𝑠
350
0.609
0.609
0.6
0.131
0.383
0.131 8e+003
-400
-400
-300
Real Axis
-200
-100
0.131
VCC t 
350
0
Real Axis
Lneg p1 p 2 s
s  p1 s  p2 
Fig. 6. System poles location if negative inductance reference value
varies from 0 to 100% of series line inductance.
+
-
PI
x
LPF
vt * t 
Rcomp
kg
+
+
-
vC t 
B
x

x
C
it t 
vt t 
derivador
v AB t 
V.
+
+
DC VOLTAGE CONTROL
A
k
An important issue for practical implementation is the
control of the DC voltages, because it makes possible the
Fig. 7. DRS implementation with state space feedback and DC voltage
control strategy.
it t 
Lneg p1 p 2 s
vt * t 
x
vC t 
x
kg
+
C
+
B

+
vt t 
s  p1 s  p2 
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King
Scientific Publishing
derivador
25
v AB t 
A
k
Journal of Electrical and Control Engineering
JECE
Figure 8 shows the synthesized impedance behavior (20)
in the frequency domain, considering the DC voltage control.
At the fundamental frequency the phase is -90º. The result is
valid if the terminal voltage and current are essentially
sinusoids. Due to the converter and filter losses, it is
expected that the required value of 𝑅𝑐𝑜𝑚𝑝 rises.
Consequently, for practical implementation, the magnitude
and phase graphics may move slightly up, especially in the
low frequency range.
harmonics. The spectrum is in compliance with IEEE-519
standards, even if the more restrictive limits are considered.
vt
it
vC
4
Magnitude ()
10
iLf
3
10
2
10
1
10
0
10 1
10
2
3
10
10
4
10
Fig. 9. Experimental result – Line frequency = 60 Hz, 𝑣𝐴𝐵 = 175 Vrms,
𝐿𝑛𝑒𝑔 = -0.16 H. Voltage (50 V/div.), Current (1 A/div.), time (5 ms/div.).
0
Phase (º)
-90
-180
-270
-360
-450 1
10
Ideal Negative Inductance
DRS without VDC Control
DRS with VDC Control
vt
2
3
10
10
it
4
10
Frequency (Hz)
Fig. 8. Magnitude and Phase diagrams of the synthesized impedance
considering the DC control strategy.
vC
iLf
VI. EXPERIMENTAL RESULTS
Figure 9 shows steady-state experimental results using a
single-phase multilevel asymmetric cascaded inverter [15][17]. The converter is implemented with 3 series connected
single-phase H-bridge modules whose DC voltages follow
the ratio (1.2 : 2 : 6) [18]. The DC voltage equalization
between different cells can be obtained by using the control
strategy presented in [19].
Fig. 10. Experimental result – Line frequency = 100 Hz, 𝑣𝐴𝐵 = 175 Vrms,
𝐿𝑛𝑒𝑔 = -0.16 H. Voltage (50 V/div.), Current (1 A/div.), time (2 ms/div.).
vt
At the top of the figure are displayed the terminal
voltage, 𝑣𝑡 , and current of the synthesized negative
inductance, 𝑖𝑡 . At the bottom, are shown the unfiltered
converter output voltage, vC, and current iLf. The synthesized
negative inductance value, 𝐿𝑛𝑒𝑔 = –0.16 H (equivalent to
35% of the series impedance). The test has been made with
𝑣𝐴𝐵 = 175 Vrms. The terminal voltage waveform slight
distortion is due to the saturation of the magnetic core of the
inductor that represents the series inductance 𝐿𝑆 .
it
vC
iLf
Fig. 11. Experimental result – Line frequency = 100 Hz, 𝑣𝐴𝐵 = 175 Vrms,
𝐿𝑛𝑒𝑔 = -0.16 H. Voltage (50 V/div), Current (1 A/div), time (2 ms/div.).
Current (0.5 A/div.).
In order to demonstrate this, another experimental test
has been made with higher line frequency. Figure 10 shows
the steady state result for 100 Hz, which is high enough to
guarantee that the magnetic core does not saturate, so
voltage and current distortion are negligible.
Figure 11 shows the same experimental result of figure
10 obtained with PWM inverter, instead of multilevel
converter. Both results are equivalent, except for the
switching noise in the current that is much higher in the
PWM solution.
Figure 12 shows the terminal current spectrum. The
harmonic distortion is quite low; with amplitudes of odd
harmonics components bellow 48 dB (  0.4%) of the
fundamental, and bellow 70 dB (  0.03%) for the even
Fig. 12. Experimental result – Terminal current spectrum with multilevel
converter. (𝑣𝐴𝐵 = 175 Vrms, 100 Hz, 𝐿𝑛𝑒𝑔 = - 0.16 H). Horizontal (250
Hz/div.), Vertical (20 dB/div.).
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King Scientific Publishing
26
Journal of Electrical and Control Engineering
JECE
Figure 13 shows the transient response to a step
variation of the reference inductance from –0.08 H to –0.16
H. Figure 14 shows the transient response to a step variation
of the 𝑣𝐴𝐵 voltage from 117 Vrms to 175 Vrms (50% increase).
During both transients it can be noticed a small DC
component on the terminal current, it, that exponentially
vanishes few cycles after the transient beginning. This sort
of transient is typically related to first order RL circuits.
Another important issue to be considered is the fact that
there are no voltage or current oscillations due to filter
resonances. This certainly would not happen if capacitors
were used for series compensation or if plant poles were not
correctly positioned in complex plane.
it
low power prototype. The voltage drop shown in the figure
is 7% of the nominal voltage of load A.
Infinite
Busbar
B
Load A
Load B
Fig. 15.Schematic circuit diagram used to emulate voltage fluctuations due
to load variations.
vt
vc
iLf
Fig. 13.Experimental Result – Transient response of inductance reference
variation, 𝐿𝑛𝑒𝑔 , from –0.08 H to –0.16 H. Voltage (50 V/div.), Current (1
A/div.).
it
Fig. 16. Voltage at load A without compensation (at the top, 133 V/div.)
and line current (1 A/div.).
A controlled variable negative inductance in series with
the distribution line could reduce or even eliminated such
load voltage drop at the PCC, as shown in Figure 17.
vt
Several methods can be used to determine the required
value of negative inductance to compensate the voltage drop
at the grid and, hence, stabilize the voltage at load A. It is
possible, for example, to measure the voltage A, compare it
to a desired value, and use the voltage error and the
compensator determines the value of the negative
inductance.
vc
iLf
An alternative that produces faster dynamic response is
to determine the inductance directly from the current, which
is possible if load and system parameters are known.
Fig. 14. Experimental Result - Transient response of line voltage 𝑣𝐴𝐵
variation, from 117 Vrms to 175 Vrms. (50 % increase). Voltage (50
V/div.), Current (1 A/div.).
Figure 18 shows the control diagram implemented, in
which it makes the calculation of the peak current according
to (22) and uses this value to adjust the reference negative
inductance value, (23). This equation was obtained
empirically and is valid for the particular parameters of this
circuit. Note that, unlike other strategies of compensation of
voltage drop, the proposed strategy does not require an
active power supply at the DC side of the converter.
The experimental results presented so far confirms the
feasibility of the DRS method to synthesize negative
inductances.
VII.
A
MITIGATION OF VOLTAGE DROP
Another possible application of negative inductances,
besides series compensation of transmission lines, could the
mitigation of voltage fluctuations. The circuit of Figure 15
illustrates a simple case that illustrates how the problem
could occur. The circuit has two loads connected to the
same grid bar, the Point of Common Coupling (PCC). The
switching of load B causes voltage variations on load A,
such as those of the Figure 16 that has been obtained using a
In order to verify the operation of the proposed system,
an experimental low power prototype has been implemented
in laboratory.
Figure 19 shows experimental results of the circuit of
Figure17. When the load current increases, the negative
inductance reference value is also increased, thus
compensating the voltage drop. In spite of the sudden
JECE Vol. 4 No. 2, 2014 PP. 22-29 © American V-King Scientific Publishing
27
Journal of Electrical and Control Engineering
JECE
current variation the load voltage is reestablished smoothly
and faster than half a cycle.
2
𝐼𝑝𝑖𝑐𝑜 =
𝑖
3 𝑡𝑎
𝐿𝑛𝑒𝑔 = −𝐿𝑆 +
1
1
3
3
2
− 𝑖𝑡𝑏 − 𝑖𝑡𝑐
3
𝑖𝑡𝑏 +
3
3
𝑖𝑡𝑐
2
0,27
(23)
C
jLneg
LS
There are different approaches for producing such
negative inductance behavior. This paper has used the
Direct Reactance Synthesis, which, essentially, solves the
inductance
equation.
For
the
control
strategy
implementation the method requires only voltage and
current measurements to produce a negative or positive
reference inductance behavior. It has been shown that the
produced inductance does not depend on the parameters of
the system where the DRS device is connected (line
impedance and equivalent voltage, 𝑣𝐴𝐵 ), despite the openloop control configuration.
(22)
𝐼𝑝𝑖𝑐𝑜
VC
Infinite
Busba
r
3
+
overall line inductance, permitting the power flow control,
the voltage regulation, etc.
VC
VC
C
C
Asymmetric
H-bridge
Multilevel
Converter
RS
The realization of this device was verified with PWM
and with multilevel inverters. For high power applications,
the multilevel topology seems to be more attractive since it
allows reaching higher output voltage and can minimize the
switching frequency noise. Results have shown that the
proposed DRS realization method for negative inductance
synthesis reach good performance. The device produces
clean voltage and current waveforms in its terminals and
exhibits satisfactory dynamic performance during transients.
Experimental results have shown that the state feedback
eliminates possible oscillations due to interaction of the
filtering capacitance with inductive elements.
PC
C
A
Load
A
Load
B
Fig. 17. Schematic circuit diagram used to test the applicability of variable
negative inductance to mitigate voltage variations.
 vDC t 

vDC*
PI
+
-
R COMP
x
t 
derivator
p1 p 2 s
s  p1 s  p2 
ia
ib
ic
Eq.(25)
I peak
f(Ipico)
L neg
x
*
vt t 
kg
+
+
-
vC t 
B
+
x
+

it t 
x
C
vt t 
ACKNOWLEDGMENTS
A
Plant
The authors would like to thank the Brazilian agencies
FAPESP (Fundação de Amparo à Pesquisa do Estado de
São Paulo), CNPq and CAPES by the financial support,
Texas Instruments by providing DSP starter kit used to
implement the control strategy, and Bevian by the
International Rectifier integrated inverter modules.
k
Fig. 18. Control diagram of variable negative inductance applied to
mitigate voltage fluctuations.
it
The authors also would like to thank Ricardo Q.
Machado, Fernando P. Marafão, Giuliano Sperandio, Fellipe
Garcia and Edson Vendrusculo.
(1A/div)
Lneg
(-8mH/div)
-104mH
-62mH
REFERENCES
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Subcommittee, “Reader's guide to subsynchronous
resonance”, IEEE Transactions on Power Systems, Vol.
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(133V/div)
vC
(133V/div)
iC
(1A/div)
Fig. 19.From top to bottom: total load current; negative inductance
reference value; load voltage; inverter output voltage; Inverter output
current.
VIII.
CONCLUSION
Series compensation of electrical feeders is necessary in
many situations. The use of power converters in this
application allows implementing compensation strategies as
the synthesis of negative inductance which reduces the
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Journal of Electrical and Control Engineering
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Volume: 1 , 3-6 Aug. 1997, pp. 355 - 360
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JoséAntenor Pomilio is electrical engineer
(1983), Master (1986) and Ph.D. (1991) in
Electrical Engineering from University of
Campinas - UNICAMP. From 1988 to 1991
he was head of the Power Electronics of the
Brazilian
Synchrotron
Laboratory.
Conducted post-doctoral internships at the
University of Padova (1993/1994) and the
Third University of Rome (2003), both in
Italy. He was president of the Brazilian Association of Power
Electronics - SOBRAEP and member of various boards of this
entity. He was member of the administrative committee of the
IEEE Power Electronics Society for 4 years. He is associate editor
ofIEEE Transactions on Power Electronics, andAdvances in Power
Electronics (Hindawi Publ. Co.). He is professor at the School of
Electrical and Computer Engineering at UNICAMP, where he
worked since 1984.
Leonardo de Araújo Silvawas born in 1976
in Iporá, atthe state of Goiás, Brazil.He
graduated in electrical engineeringin 1998 at
the Federal University of Goiás – UFG and
obtained the MSc. and DSc. degreesat the
State University of Campinas – UNICAMP,
at the state of São Paulo, Brazil, in 2000 and
2007.From 2008 to 2010 he worked for the
Brazilian oil company, Petrobras, and since
2010 he works at the Brazilian Electricity
Regulatory Agency - ANEEL.
André Augusto Ferreira received the
Electrical Engineering degree from the
Federal University of Juiz de Fora (UFJF),
Juiz de Fora, in 2000, and M.E. and Ph.D.
degrees in Electral Engineering from
University of Campinas (UNICAMP),
Campinas, in 2002, and 2007, respectively.He
joined Federal University of Pampa
(UNIPAMPA), Alegrete, Brasil, in 2008.
Since 2009 he has been with the Electrical Engineering
Department at Federal University of Juiz de Fora, Juiz de Fora,
Brasil, where he teaches Power Electronics, Electric Machines,
Dynamic Control, Digital Logic Circuits, Energy and Electricity,
Electrical Installation, and Industrial Automation.His main areas of
research interest are electric vehicles, solar photovoltaic energy,
power quality, power electronics, and their control systems.He is
member of Brazilian Society of Power Electronics (SOBRAEP)
and he is also registered professional in the Brazilian Council of
Engineering (CREA/COFEA).
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