ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts
P. Paramahans1,*, S. Gupta2, R. K. Mishra1, N. Agarwal1, A. Nainani2, Y. Huang2, M.C. Abraham2, S. Kapadia2, U. Ganguly1, S. Lodha1
1
CEN, Department of EE, Indian Institute of Technology Bombay, 400076 India, 2Applied Materials Inc, Santa Clara, USA, 94085 *paramahans@iitb.ac.in
Abstract
We propose ZnO as an attractive interfacial layer (IL) option for
n-type metal-IL-semiconductor (MIS) contacts because of (i) good
conduction band alignment between ZnO and Si/Ge/SiC, (ii) high
n-type doping possible in ZnO, and, (iii) low Fermi-level pinning
factor for metal/ZnO contacts. Device simulations suggest better
scalability for MIS contacts versus silicides/germanides for future
FinFET technologies. Contact diode measurements on
Ti/n+-ZnO/n-Ge and Ti/n+-ZnO/n-Si devices show nearly 1000X
increase in current densities due to the presence of an n+-ZnO IL. In
comparison to alternate IL options such as Al2O3 and TiO2, n+-ZnO
gives significantly higher current densities on n-Ge as demonstrated
through device simulations and experimental data. Specific contact
resistivity of (0.8-1.5)x10-6 Ω cm2 is demonstrated through four-probe
measurements on circular TLM devices fabricated on n+-Ge (1x1019
cm-3) epi layers using n+-ZnO IL.
Introduction
Contact resistance has emerged as a significant bottleneck for device
scaling for logic technology node. Specifically, future contact
solutions need to address the challenges arising due to dimensional
scaling of the contact and source/drain (S/D) regions as well as new
materials being evaluated as replacements for Si, such as Ge channel
[1] and SiC S/D [2]. Low-resistance n-type contacts are more difficult
to realize, especially for Ge, due to low dopant activation and
Fermi-level pinning (FLP) near the valence band resulting in a large
potential barrier (~0.55eV) at metal/n-Ge interface [3].
In this work we first show, that for future FinFET transistor structures
metal-interfacial layer-semiconductor (MIS) contact technology is a
more scalable option versus current silicide technology. Secondly, we
demonstrate through experimental data aided by device simulations,
that ZnO is a suitable candidate for the interfacial layer to realize
low-resistance n-type S/D contacts due to good conduction band
alignment between ZnO and Si/Ge and high n-type doping possible in
ZnO. We have evaluated the performance of ZnO MIS contacts by
varying all three variables, viz. the semiconductor (Si, Ge), the IL
(n+-ZnO vs Al2O3 and TiO2) and the metal with varying
work-function (Ti, Al, Au).
Simulation study of MIS versus silicide contact technologies
The total resistance possible with silicidation and MIS S/D contact
schemes has been compared as FinFET widths are scaled from 15 nm
to 5 nm (Fig 1(a) & (b)). Fig 1(a) depicts the case of a silicided S/D
where the silicides on the two sides of the fin merge for scaled fin
widths (10 nm and less). The contact resistance increases sharply for
scaled silicided fins due to decrease in contact area between silicon
and silicide. On the other hand, IL layer of MIS contacts does not
consume silicon and the current spreads well (Fig 1(a)). Fig. 1(b)
estimates the total contact resistance of silicided and MIS S/D
assuming contact resistivity of 10-8 Ω cm2 for both cases. The
advantage offered with the MIS becomes significant when the
silicides merge (15 and 12 nm fin width), and as the contact hole
shrinks wherein MIS contacts offer significantly lower total resistance
for 15nm node and beyond. Further, if the thin IL (typically ~2nm)
can itself act as a diffusion barrier layer for contact plug metal,
significant lowering of the contact plug resistance can be achieved
through the elimination high resistivity Ti/TiN contact liner/barrier.
MIS contacts: Experiments and Simulations
Fig 2(a) shows energy band line-ups with a nearly negligible (<0.1
eV) conduction band offset for ZnO with respect to the various n-type
S/D materials- Si, Ge and SiC. Fig 2(b) shows the measured Schottky
barrier height (Φb) versus metal work-function (Φm) for Si, Ge and
ZnO. In comparison to Si and Ge [3], ZnO exhibits less FLP, thereby
978-1-4673-0847-2/12/$31.00 ©2012 IEEE
allowing a wider choice of metals to tune contact resistivity. Al2O3
and TiO2 have been recently tried as IL to unpin the Fermi-level on
n-Ge[4][5]. Fig 3 shows simulated contact tunnel barriers and
normalized current densities for Al2O3, TiO2 and n+-ZnO ILs on n-Ge.
n+-ZnO exhibits the highest current density because the high doping at
the metal/n+-ZnO interface and the negligible conduction band offset
at the n+-ZnO/n-Ge interface result in the thinnest and smallest tunnel
barrier.
Fig 4(a) shows the process flow for forming Ti/n+-ZnO/n-Ge contacts
for diode study. Ge wafers (1x1017 cm-3) were first processed through
organic cleans (acetone and 2-propanol) followed by a cyclic 2% HF
+ DI water clean to remove native oxides. Thin films of crystalline
ZnO (0.7, 1.5, 2.0 nm) were deposited using RF sputtering. XRD
confirmed the presence of crystalline, c-axis oriented ZnO (0002).
Hall measurements indicate that the as-deposited ZnO films are
low-doped (1x1017 cm-3). UV-Vis spectroscopy gave an optical band
gap of 3.1 eV for the ZnO films. Metal contacts were formed using
Ti/Au e-beam evaporation and backside metallization was done using
Al. A PDA was carried in N2 ambient. As reported previously[7], the
annealing process results in the formation of a highly doped (n+) ZnO
layer at the Ti/ZnO interface due to accumulation of oxygen vacancies
that act as donors in ZnO.
Fig 5 shows the J-V characteristics of Ti/n+-ZnO/n-Ge and
Ti/n+-ZnO/n-Si contacts. The presence of n+-ZnO IL gives a
significant increase in current density (~1000X) and converts the
contacts from rectifying to Ohmic. n-Ge exhibits larger improvement
than n-Si likely due to stronger FLP on Ge as shown in Fig 2(b).
Ti/Al2O3/n-Ge and Ti/TiO2/n-Ge contacts were also fabricated to
compare the performance of n+-ZnO versus Al2O3 and TiO2. Fig 6
compares the maximum current densities obtained for all three ILs
and Fig 6(a) shows the dependence of the current density on the IL
thickness. n+-ZnO shows the maximum current density at a given IL
thickness(Fig 6(c)), corroborating the simulation results in Fig 3(d).
The current density is nearly independent of ZnO thickness since the
tunneling barrier is fixed by the high doping of the ZnO film and not
by its thickness (Fig 6(b)). The formation of n+-ZnO at the metal/ZnO
interface is only possible for metals, such as Ti and Al, that have a
lower enthalpy for formation of metal-oxide versus ZnO[7]. Fig 7
shows the increase in current density post anneal for Ti and Al contact
metals, unlike Au that does not form oxygen vacancies (donors) in the
ZnO layer. This reinforces the requirement of a heavily doped n+
interfacial layer for formation of low-resistance contacts.
Circular TLM devices fabricated on 100 nm thick n+-Ge (1x1019
cm-3) epi layers yielded specific contact resistivity(ρc) of nearly
(0.8-1.5) x10-6 Ω cm2 which is matched to the best reported values on
n+-Ge [8].A doping of 1x1020 for n- Ge(Fig. 8) is expected to give
ITRS specified (ρc) of 1x10-8 Ω cm2.
Conclusions
In summary, we have successfully demonstrated the feasibility of
forming low resistance n-type contacts on future source-drain
materials using an n+-ZnO IL through comprehensive experiments
and simulations that evaluate the effect of varying the semiconductor,
the IL layer and the metals on contact performance.
References
[1]Chui et al., IEDM 2003, [2] K.W Ang et al., IEDM, 2004,[3] T.Nishimura
et al. , APL. 91, 123123 (2007), [4] J.Y.Lin et al. , APL 98, 092113 (2011),
[5]Wang et al., APL 93, 202105 (2008),[6] ZnO:Materials & Devices Hadis
Morkoç, Wiley Pub., [7] H.Kim et al. ECS Journ. 148(3) G114-G117, 2001.[8]
K. Martens et al. APL 98, 013504, 2011[9] Varaharamyan et al. Solid St.39
1996
2012 Symposium on VLSI Technology Digest of Technical Papers
83
Gate
Source Metal
Source Metal
d
h
w
Contact Area
AMIS = wd+2hd
Asilicide = wh
w
d
h
Horizontal
Cut
w
MIS S/D
Gat
Fully Silicided S/D
w
MIS gives area advantage
over fully silicided S/D
d
(a)
d
Total Contact Resistance (ohms)
Drain Metal
Drain Metal
160
Fin Extension Resistance
Silicide Contact Resistance
MIS Contact Resistance
120
(b)
Contact Metal
80
40
Silicide Contact
0
5
6
8
10 12
Fin Width (nm)
TiN (barrier)
Ti (Liner)
Silicide
IL
Silicon
15
(c)
MIS Contact
0.90
Energy (eV)
Barrier (eV)
0.75
-5
Ge
Si
-6
-7
-8
SiC
(a)
-9
Large Tunneling
Barrier
S=0.09
0.70
S=0.2
ZnO (c)
0.65
0.60
S=0.03
0.55
TiO2
ZnO
Al2O3
0.1eV
0.50
0.45
(b)
4.0
Tunneling Barrier
Reduces further by
heavy doped ZnO
S: Pinning Factor
4.4 4.8 5.2 5.6
Workfunction (eV)
Metal
2nm IL
Ge Cond. Band
Fig 2. (a) Band alignment of ZnO with conduction band of
Si, Ge and SiC, (b) Barrier Vs Metal Workfunction from
[3], [6] showing less Fermi Level Pinning by ZnO
Germanium
10
0.1
(a)
0.01
1E-3
1E-4
1E-5
-0.5
Control
0.7nm ZnO
1.5nm ZnO
2nm ZnO
0.0
Voltage (V)
0.01
~1000 X
improvement
1E-3
(b)
1E-4
10
0.0
Voltage (V)
2
J (A/cm )
2
J (A/cm )
0.1
0.01
1E-3
1E-4
1E-5
-0.5
PreAnneal
PostAnneal
1
1
Ti, WF = 4.33eV
Al, WF = 4.08eV
Au, WF = 5.1eV
0.0
Voltage (V)
0.5
0.1
0.01
1E-3
1E-4
1E-3
(a)
1E-4
1E-5
1E-6
O3
O3
Al 2 TiO 2 ZnO ZnO TiO 2 Al 2
V = - 0.1V
0.1
0.5
Ti
Al
Au
Metal Stack
ZnO(-0.1V)
1
Tunneling Barrier remains same
for all ZnO thickness
(a)
2
3
4
Thickness of IL (nm)
5
1E-5
1E-6
This work
-2
0
2
4
6
Ge/ZnO Interface Distance (nm)
100
10
0.4 eV
0.5 eV
~10X improvement in ρC
1nm ZnO
2nm ZnO
3nm ZnO
-4
Φ Β=0.3 eV
Without IL [8]
Metal
Ge C Band
(b)
Fig 6.(a) Current density for Al2O3, TiO2 and
ZnO as IL at -0.1V. Thickness independence
in case of ZnO relaxes process window.
1E-4
1E-7
1E-9
1E19
1E-5
-0.5
1E20
-3
~10X improvement
0.01
1E-3
ITRS Specification
~10X
improvement
1
0.1
1E-4
1E-8
ZnO
Fig 4. (a) Process Flow for making
ohmic contacts on n-Ge (b) TEM
of Ti/ZnO/Ge interface
Doping(cm )
Fig 7. (a) J-V for metals (Ti, Al, Au) on n-Ge with ZnO as IL
for
showing unpinning of Fermi level, (b) Bar graph comparing Fig 8. Specific Contact Resistivity Vs Doping
20
-3
pre & post anneal current densities at -0.1V explaining the Ge simulated using [8] . A doping of 1x10 cm
-8
2
possibility of heavy doped ZnO with Ti and Al only
can achieve ITRS specified ρc of 1x10 Ω-cm
978-1-4673-0847-2/12/$31.00 ©2012 IEEE
Ge
Al2O3(-0.1V)
TiO2(-0.1V)
(b)
Ti
V = 0.1V
1
0
Fig 5. J-V for different ZnO thickness on (a) n-Ge
17
-3
18
-3
(Doping 10 cm ), (b) n-Si (Doping 10 cm )
10
PDA in N2 forming
high doped ZnO
0.01
~10 X
improvement
0.01
1E-5
0.5
-0.5
100
(d)
10
2
J (A/cm )
improvement
0.1
2
~1000 X
Sp. Contact Resistivity (ohm-cm )
2
1
1
0.1
Fig 3. Band Diagram for (a) Al2O3, (b) TiO2, (c)
ZnO (d) Relative tunneling current at ±0.1V for
2 nm IL and given metal (Al)
Silicon
1
Current Density 'J' (A/cm )
2
Current Density 'J' (A/cm )
100
nGe Substrate
Pre-Clean
ZnO+Ti/Au Diode
formation+ Back Al
Tunnel
Barrier
Reduces
Energy
0.80
1.7 eV
2
-4
0.06 eV
J (A/cm )
0.85
TiO2 (b)
Al2O3 (a)
ZnO
Ge
Si
Relative Tunneling Current
-3
Pd
Au
Pt
-2
Ag
Al
Ti
Fig 1. Comparison of total contact resistance for MIS vs silicide, (a) Illustration depicting the contact area advantage in MIS, (b) Total extrinsic contact
resistance with scaling fin-width, (c) Liner & barrier layers used for contact plug are not required in MIS which improves plug resistance from 80 to 20 Ω.
(c)
Control
0.7nm ZnO
2nm Al2O3
3nm TiO2
0.0
Voltage (V)
0.5
Fig 6. (b) Band diagram explaining no
dependence of current density on ZnO
thickness due its heavy doped nature, (c)
Best obtained J-V for Al2O3, TiO2 and
ZnO with given IL thickness
2012 Symposium on VLSI Technology Digest of Technical Papers
84