ULTRA LOW POWER READ-OUT INTEGRATED CIRCUIT DESIGN
A thesis submitted in partial fulfillment of
the requirements for the degree of
Master of Science in Engineering
By
Jian Chen
B.E., East China Institute of Technology, China, 2006
M.E., Shenzhen University, China, 2009
2012
Wright State University
COPYRIGHT BY
Jian Chen
2012
WRIGHT S TATE UNIVERSITY
GRADUATE SCHOOL
August 15, 2012
I HERBY RECOMMEND THAT THE THESIS PREPARED UNDER MY
SUPERVISON BY Jian Chen ENTITLED Ultra Low Power Read-Out Integrated
Circuit Design ACCEPTED IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF Master of Science in Engineering
Saiyu Ren
Ph.D. Thesis Director
Kefu Xue
Ph.D., Chair
Department of Electrical Engineering
College of Engineering and Computer Science
Committee on
Final Examination
Saiyu Ren, Ph.D.
Raymond E. Siferd, Ph.D.
Henry Chen, Ph.D.
Andrew Hsu, Ph.D.
Dean, Graduate School
ABSTRCT
Jian Chen. M.S.Egr., Department of Electrical Engineering, Wright State University,
2012. Ultra low Power Read-Out Integrated Circuit Design.
Carbon nanotubes (CNTs) are widely studied by the researchers in recent years, as
they have small size, large strength, highly electrical and thermal conductivity. The
single-walled CNT (SWNT) is readily changed in electrical resistance when exposed to
gas, and has significant use in environmental monitoring, agriculture and fishing industry,
chemical industry and even security. A read-out integrated circuit (ROIC) is required to
detect the resistive change.
In this thesis, an ultra-low power, wide dynamic detecting range and small size
CMOS ROIC design is presented. This ROIC can interface wide dynamic range signal up
to more than two orders (100pA-60nA) from deployable sensors using automatic gain
control (AGC) unit. A novel technology of sub-threshold technique is applied in this
design, which can save up to 96% (from 25.2mW to 0.89mW) power consumption
comparing to the circuit operating in super-threshold. To improve the accuracy of
calibrated readout current, compensation factor derived from the analysis of simulation
results is finally added. The proposed circuit also has the capability to output 8 bit digital
signal that can be transmitted wirelessly to the data center for further signal processing.
iv
Table of Contents
1
2
INTRODUCTION ....................................................................................................1
1.1
Background .......................................................................................................1
1.2
Motivation .........................................................................................................3
1.3
Document Organization .....................................................................................4
THEORY OVERVIEW ............................................................................................5
2.1
Carbon nanotubes (CNTs) based sensor .............................................................5
2.2
Operational amplifier .........................................................................................6
2.2.1
Input Common Mode Range (IMRR) .........................................................7
2.2.2
Common Mode Rejection Ratio (CMRR) ................................................. 10
2.2.3
Phase Margin (PM) .................................................................................. 11
2.2.4
Closed loop op-amp gain .......................................................................... 11
2.2.5
Slew Rate (SR) ......................................................................................... 12
2.3
Analog to digital convertor (ADC) .................................................................. 13
2.3.1
Resolution ................................................................................................ 14
2.3.2
Sampling Rate .......................................................................................... 15
2.3.3
Quantization Error .................................................................................... 15
v
3
2.3.4
Integral Non-Linearity (INL) .................................................................... 16
2.3.5
Differential Non-Linearity (DNL) ............................................................ 16
READ-OUT INTEGRATED CIRCUIT DESIGN OPERATING IN
SUBTHRESHOLD........................................................................................................ 17
3.1
Introduction ..................................................................................................... 17
3.2
Implementation of sub-threshold ROIC ........................................................... 17
3.2.1
Sub-threshold technology ......................................................................... 19
3.2.2
Sub-threshold CVC Design ...................................................................... 24
3.2.3
Sub-threshold AGC Design ...................................................................... 33
3.2.4
Calibration Method................................................................................... 38
3.2.5
Optimization applying compensation technology ...................................... 44
3.2.6
8-bit ADC Design..................................................................................... 50
3.3
4
Simulation Results ........................................................................................... 56
3.3.1
Comparison in power consumption........................................................... 56
3.3.2
Evaluation for entire system ..................................................................... 57
CONCLUSION AND FUTURE WORK ................................................................ 61
4.1
Conclusion ...................................................................................................... 61
4.2
Future work ..................................................................................................... 61
vi
5
REFERENCE ......................................................................................................... 62
vii
List of Figures
Fig. 2.1 Single-Wall Nanotube (SWNT) Model ...............................................................6
Fig. 2.2 Two-stage op-amp: (a) Schematic, (b) Block diagram (c) Symbol .......................7
Fig. 2.3 General block diagram of closed-loop Op-amp ................................................. 11
Fig. 2.4 Closed-loop Op-amp ......................................................................................... 12
Fig. 2.5 Slew Rate (SR) ................................................................................................. 13
Fig. 2.6 INL and DNL ................................................................................................... 16
Fig. 3.1 Block diagram of ROIC .................................................................................... 19
Fig. 3.2 Simplified block diagram of ROIC ................................................................... 19
Fig. 3.3 Schematic of Op-amp ....................................................................................... 21
Fig. 3.4 Block diagram of CVC ..................................................................................... 24
Fig. 3.5 Diagram for traditional I-V converter................................................................ 25
Fig. 3.6 Model for Sensor and transistor ........................................................................ 27
Fig. 3.7 I-V Performance Evaluation with Input Current Sweep ..................................... 28
Fig. 3.8 DC level shift and 1st stage amplification of CVC ............................................. 30
Fig. 3.9 Unit Gain Analog Buffer................................................................................... 31
Fig. 3.10 Schematic of 2nd stage amplification ............................................................... 32
Fig. 3.11 Block diagram of sub-threshold AGC ............................................................. 34
Fig. 3.12 Transient analysis for ROIC (
Fig. 3.13 Final analog Output signal (
=0.4V,
=-0.4V).................................... 36
) .................................................................. 38
viii
Fig. 3.14 Block Diagram of ROIC ................................................................................. 39
Fig. 3.15 Comparison between Readout and Input current (
=0.5V,
=-0.5V) ...... 42
Fig. 3.16 Comparison between Readout and Input current (
=0.4V,
=-0.4V) ...... 43
Fig. 3.17 Performance comparison between before-compensation and after-compensation
with power supply (
=0.5V,
=-0.5V).. ................................................................ 49
Fig. 3.18 Performance comparison between before-compensation and after-compensation
with power supply (
=0.4V,
=-0.4V).. ................................................................ 49
Fig. 3.19 Analog to Digital Conversion.......................................................................... 50
Fig. 3.20 Flash Analog to Digital Convertor .................................................................. 51
Fig. 3.21 Schematic of 8-bit flash ADC in sub-threshold ............................................... 53
Fig. 3.22 8-bit flash ADC Transient Analysis ................................................................ 54
Fig. 3.23 The Discrete Fourier Transform (DFT) Analysis for 8-bit flash ADC .............. 55
Fig. 3.24 Schematic of Read-Out Integrate Circuit (ROIC) ............................................ 57
Fig. 3.25 Analog and weighted sum digital output (
=100 Hz) ................................... 58
Fig. 3.26 Comparison between analog and weighted sum digital output (
=100 Hz) .. 58
Fig. 3.27 Analog Outputs and weighted digital outputs with different input frequency: (a)
=100 Hz (b)
=400 Hz (c)
=700 Hz (d)
ix
=1 kHz ......................................... 60
List of Tables
Table 2.1 The number of bits (n) vs number of gradations (N) ....................................... 14
Table 3.1 Comparisons between sub-threshold and super-threshold ............................... 21
Table 3.2 Error percentage vs power supply and gain .................................................... 23
Table 3.3 Performance comparisons in op-amp with different power supply .................. 23
Table 3.4 I-V performance Evaluation with Input Current ............................................. 29
Table 3.5 Results of CVC (
=0.4V,
=-0.4V) ....................................................... 35
Table 3.6 Comparison of input and calibrated current (
=0.5V,
=-0.5V) ............. 41
Table 3.7 Comparison of input and calibrated current (Vdd=0.4V, Vss=-0.4V) .............. 43
Table 3.8 Comparison of input current and calibrated output current after compensation
(
=0.5V,
=-0.5V)................................................................................................ 44
Table 3.9 Comparison of input current and calibrated output current after compensation
(
=0.4V,
=-0.4V)................................................................................................ 46
Table 3.10 Performance comparison between before-compensation and ........................ 48
Table 3.11 Performance comparison between before-compensation and aftercompensation with power supply (
=0.4V,
=-0.4V) ............................................ 48
Table 3.12 Digital Output Codes.................................................................................... 52
Table 3.13 Comparisons in power consumption ............................................................. 56
Table 3.14 Input current (
=100Hz), analog output and digital output ........................ 60
x
Acknowledgement
First of all, I would like to thank my advisor Dr. Saiyu Ren at Wright State
University for her support and meticulous guidance. Her expertise in the field has
motivated me to learn and improve my knowledge. I would also like to thank my
professors for all the support and encouragement they have provided. I am grateful to Dr.
Raymond Siferd and Dr. Henry Chen, who were kind enough to accept the invitation and
serve as the thesis committee members.
I would like to thank George Lee, Muppala Prashanth, Hiremath Vinayashree and
Billman Steven John in the VLSI research group, for their valuable help during my study.
I thank my friends for all the encouragement. I am also grateful to our system
administrator Mike Vanhorn for his timely support, and thankful to the Department of
Electrical Engineering in Wright State University for providing me with all the useful
utilities in my studying.
My special thanks to my wife Chuna Huang for her great patience and going through
so much in supporting my studies. I sincerely thanks to my father for his encouragement
in spiritual during all the time. I am also thankful to my sister and brother for their love
and affection on me. I finally thank all my friends, classmates and relatives who have in
some kind do me a favor during my degree pursuing.
xi
1 INTRODUCTION
1.1 Background
During recent years, researchers are showing great interests on carbon nanotubes
(CNTs) because of their small size, large strength, highly electrical and thermal
conductivity. Consequently, CNTs are implanted as sensing materials in gas, pressure,
strain, chemical and biomedical sensors, known as CNTs sensors [1]. With the readily
changing in electrical resistance of the semiconducting single-walled CNT (SWNT)
based sensors when exposed to gaseous molecules, which makes it has the capability of
detecting small concentration of toxic gas or other kind of gas molecules, and has
significant use in environmental monitoring , agriculture and fishing industry, chemical
industry and even security [2-3].
Considering the accuracy for the signal detecting from sensors, it is important to
design a read-out integrated circuit (ROIC) with high resolution, wide dynamic range,
anti-noise and easy to control to account for process variation in the manufacturing of
CNTs. Most of researchers focused on the methods of detecting the change from CNTs
when exposed to gas. The change can be modeled as resistance change. To detect the
resistance change, two mainly conversion approaches resistance-to-current and
resistance-to-voltage are found in the existed literature.
For the resistance-to-current, the resistance change is first converted to current
change by applying a constant voltage on the CNTs sensor [4-9]. The next step is trying
1
to detect the current. One traditional architecture of detecting the current is converting the
current signal from sensor to voltage using an op-amp, knows as trans-impedance
amplifier (TIA) [10-12], but it should have high performance requirements for this opamp, such as high gain, small offset voltage and very low leakage current, otherwise, it is
hard to detect the weak current signal. Another traditional one is adopting capacitive
trans-impedance amplifier (CTIA) [13-15], also known as resistive-to-time (RTC), it
reduces the noise and show good linearity, but requires long measurement time when
estimate high resistance value [16].
The resistance-to-voltage method is biasing a fixed current source for the chemical
CNTs based sensors [17-20], and then resistance change is converted to voltage change
according to Ohm’s law. The depicted architectures in [17-20] are limited for the
relatively small resistance variations.
2
1.2 Motivation
In energy constrained applications such as read-out integrated circuit design for CNTs
based biomedical, chemical sensors, or other portable devices, where the low power
dissipation is the priority. Ultra-low power circuit design with capability of operating at
low frequency is very desirable in these applications.
According to the existed literature, most ROIC designers for CNTs based sensors are
focused on the methods to increase the measurement accuracy and already obtained some
improvements, but didn’t pay much attention to the power consumption. Considering that
the input range is fixed for an ADC working normally, automatic gain control (AGC) is
needed in ROIC to handle wide sensing range.
Hence, the goal of this thesis is:
▪ Design an ultra-low power ROIC using novel sub-threshold technology
▪ Design an automatic gain control (AGC) circuit to maximize the detecting range
3
1.3 Document Organization
The thesis is organized as follows: Chapter1 introduces the background and
motivation for ROIC design. Chapter 2 briefly discusses the properties of CNTs based
biomedical or chemical sensors and also the analysis of components, such as operational
amplifier, analog to digital conversion. Chapter 3 describes the ROIC design in subthreshold, which includes CVC, AGC and ADC design. It discusses the comparison in
power consumption for ROIC between super-threshold and sub-threshold, and analyze
the comparison between input current from sensor and the calibrated output current.
Compensation technology is applied to improve conversion accuracy. Finally, chapter 4
gives the conclusion and future work.
4
2 THEORY OVERVIEW
2.1 Carbon nanotubes (CNTs) based sensor
Sensors are these devices detecting or measuring physical and chemical quantities
such as gas concentration, temperature, pressure, and etc. In recent years, researchers are
showing great interests on carbon nanotubes (CNTs) because of their small size, large
strength, highly electrical and thermal conductivity, low cost, high specific surface area.
Consequently, CNTs are implanted as sensing materials in gas, pressure, strain, chemical
and biomedical sensors, known as CNTs sensors.
Based on the arrangement of graphene cylinders, CNTs can be categorized by two
types: single-walled nanotubes (SWNTs) and multi-walled nanotubes (MWNTs).
Considering CNTs structures are susceptible to structural instability as they have high
aspect ratio. MWNTs have worse defined shapes of cylinder than SWNTs, and hence
have higher possibilities of structure defects. Consequently, people prefer to use SWNT
in their research. With the easily changing in electrical resistance of the semiconducting
SWNT based sensors when exposed to gaseous molecules, SWNTs has the capability of
detecting even small concentration of toxic or other kind of gas molecules, and has
significant use environmental monitoring , agriculture and fishing industry, chemical
industry and even security. Fig. 2.1 is the model of SWNT.
5
Fig. 2.1 Single-Wall Nanotube (SWNT) Model
As shown in Fig. 2.1, fixed gate or fixed drain to source voltage is applied to the
SWNT sensor to measure the current flowing through it. The basic principle behind gas
detection or any other detections is the change in the electrical properties, such as
resistance, permittivity, resonate frequency and etc when exposed to different gases
(
,
,
) or concentration variation. In this thesis, a chemical CNTs sensor model is
studied. Its resistance is very sensitive to the concentration. To facilitate the detection, the
resistance change can be transferred to current change from sensor applying a fixed
voltage drop from drain-to-source based on the Ohm’s Law (I=V/R). Therefore, the final
task is trying to find an effective approach to detect the current change from sensor.
2.2 Operational amplifier
Operational amplifiers, also known as op-amp, are the most significant part in linear
integrated circuits. Op-amps have different performances based on their topologies. Such
as one stage op-amp has limited gain, cascade op-amp has increased gain but has poor
output swing and two stages op-amp is more complex in architecture but providing high
gain and high output swing. Considering the high gain and high swing needed in this
6
ROIC design, two stages op-amp is selected. Fig. 2.2 shows a two stage op-amp
schematic circuit (a), block diagram (b) and symbol (c).
Fig. 2.2 Two-stage op-amp: (a) Schematic, (b) Block diagram (c) Symbol
As shown in Fig. 2.2(a) typical two stages op-amp includes a differential amplifier
and an inverter amplifier. Differential amplifier provides high gain and reduces noise,
while inverter amplifier provides extra gain and large swing. In the following sections,
some of the design parameters, such as input common mode range (IMRR), common
mode rejection ratio (CMRR), gain, phase Margin (PM), gain etc will be discussed.
2.2.1 Input Common Mode Range (IMRR)
Common mode means connecting inverting terminal and non-inverting terminal
together, then the two input voltage will change in the same direction. To keep all the
transistors working in saturation region, input voltages must be constrained in certain
range [21].
Connecting two input terminal together, it can be obtained,
7
=
(2.1)
To keep transistor M1 saturated, following inequality equation must be satisfied,
≥
−
(2.2)
>
Applying
=
−
, then we obtain,
≤
+
(2.3)
Since
=
−
=
−
(2.4)
Substituting Eq. (2.4) into inequality Eq. (2.3) yields,
≤
−
+
(2.5)
Considering the current through transistor M3 (in saturation region) is,
= 0.5
=
After calculation, then
2
= 0.5
/
−
+
(2.6)
(2.7)
Combine Eq. (2.7) and Inequality Eq. (2.5), we get,
≤
If we keep reducing
− 2
/
−
+
(2.8)
to a certain value, transistor (M5) will be out of saturation.
So, to keep M5 in saturated, the voltage relationship is given by,
8
≥
−
(2.9)
−|
= 0.5
|
(2.10)
Calculate Eq. (2.9), it is easy to get,
≤
=
Similarly, we can get
2
2
/
/
+
(2.11)
+
(2.12)
Substitute Eq. (2.11) into Inequality Eq. (2.9) yields,
≥
2
/
+
−
=
2
/
(2.13)
As described in Fig. 2.2, we have,
=
−
=
And
=
−
(2.14)
−
(2.15)
Hence,
=
+
=
+
+
(2.16)
Similarly,
Combine Eq. (2. 12), Eq. (2. 15) and Inequality Eq. (2.13) yields,
≥
2
/
+ 2
/
+
+
(2.17)
Finally, we obtain the range of input gate voltage for transistor M1,
2
/
+ 2
/
+
+
≤
≤
9
− 2
/
−
+
(2.18)
= 0.5
Where
/
= 0.5
and
/
,
/
are the mobility of
electron and hole respectively. If known the current, size, power supply, then the input
range would be readily obtained.
To simplify the calculation in our design, inequality Eq. (2.18) can be changed into,
+
≤
≤
−
(2.19)
Therefore, the input range of two stages op-amp can be approximately acquired with
just knowing power supply. For example, with 1.8V power supply (
= −0.9 ),
= 0.3,
= 0.9
and
= −0.32, then the input range is from -0.6V to 0.58V. If
reduce the power supply to 0.8 V (
= 0.5 and
= −0.5 ), then the input range
will be decreased to (-0.2 to 0.18).
2.2.2 Common Mode Rejection Ratio (CMRR)
CMRR is the parameter to evaluate the ability for input noise rejection. The equation
is given by,
=
Where
(2.20)
is the differential gain given by different input voltage, and
is common
mode gain provided with same input. Ideally, common mode gain is zero and the CMRR
is infinite according to Eq. (2.20). However the two input voltages are not the same
because of the noise or any other influent factors, such as input variation. Hence, the
smaller
means less distortion from noise, which also means the larger CMRR, the
better for the noise rejection [21].
10
2.2.3 Phase Margin (PM)
Phase margin is the difference between the phases, generally measured in degree,
which is widely used in stability measuring of a system in frequency domain. In system
design, the larger PM (system will be more stable) is preferred, typical PM value is 45°,
but prefer 60 ° for practical design. Recalling the multiple op-amp stage design, the
performances of op-amps are varied due to mutual influence among them.
2.2.4 Closed loop op-amp gain
Closed loop op-amp gain, is the significant parameter in the op-amps design
especially in sub-threshold design. The high gain would increase the performance of the
entire system [21].
Fig. 2.3 General block diagram of closed-loop Op-amp
Fig. 2.3 is the general block diagram of a closed-loop Op-amp, where A(jω) is the
open loop gain and F(jω) is the closed loop gain, the transfer function is given by,
( )
=
If (
) (
( )
(
=
(
)
) (
)
(2.21)
) ≫ 1, then Eq. (2.21) can be simplified as,
=
(
(2. 22)
)
11
Therefore, if open-loop gain is large enough, the closed-loop gain depends on external
feedback circuit.
Fig. 2.4 Closed-loop Op-amp
To better comprehend the concept of closed loop gain, a more specific example is
presented. Fig. 2.4 is the schematic of closed-loop op-amp, where the external circuit
composed by two resistors R1 and R2 in series. As seen in Fig. 2.4,
is negligible as
the input resistance of op-amp is infinite. According to KCL, Eq. (2.23) can be obtained,
=
(2.23)
Applying calculation, then
=−
(2.24)
Where the ratio of R2 and R1 is the feedback gain, which is the reciprocal of (
)
2.2.5 Slew Rate (SR)
Slew rate is the changing rate (response speed) for the output signal in electronic
circuits design. The measured two points are selected at 10% and 90% respectively, as
depicted in Fig. 2.5. Considering some deviations between rising SR and falling SR,
12
usually the average value can be used. However, the best design is to keep
=
For the rising SR
S
=
=
(2.25)
For the falling SR
S
=
=
(2.26)
Finally, the average slew rate is given by Eq. (2.27),
SR=
S
=(
+
−
)(
+
)
(2.27)
Fig. 2.5 Slew Rate (SR)
2.3 Analog to digital convertor (ADC)
Analog to digital convertor is the device that convert continuous signal to discrete
data. In the real world, most things can be higher or lower, louder or quieter, on a sliding
scale, which are characterized by analog signal. However, the analog signal is easily got
lost, distorted and sometimes even impossible to be recovered by the receiver due to the
effects of random noise [22]. Digital signal can reduce noise effectively and it is also easy
to manipulate, compatible with digital systems, such as microprocessor. In terms of
conversion method, ADCs are classified by direct-conversion (flash ADC, pipeline ADC,
13
SAR ADC) and indirect conversion (digital ramp ADC, delta-sigma ADC, counter ramp
ADC). ADCs also have other classifications based on power consumption, operating
speed, resolution, number of bits and even the complexity. Flash ADC is easily to be
implemented and widely used in current integrated circuit design, which is the
architecture used in our ROIC design. To better comprehend the operating principle and
to facilitate the design, some of the important technical standards are illustrated in the
following sections.
2.3.1 Resolution
Resolution, also called Least Significant Bit (LSB) is the minimum change for the
input signal that can be detected by the ADC, and is expressed as Eq. (2.28).
=
=
=
(2.28)
Where n is the number of bits, and FSR is the full scale range. N is the number of
gradations (
= 2 ),
and
are the positive, negative reference voltage
respectively. The number of bits can be characterized the resolution, as listed in Table
2.1.
Table 2.1 The number of bits (n) vs number of gradations (N)
Number of bits (n)
Number of gradations (N)
4
8
12
16
16
256
4096
65536
14
2.3.2 Sampling Rate [23]
Sampling rate defines the number of samples taken from analog signal to make
digital signal in one second, which indicates the speed of ADC. In virtue of Nyquist
Sampling Theorem, to avoid aliasing in frequency domain, the sampling frequency is at
least two times larger than the maximum frequency of the signal, is given by,
≥2
(2.29)
2.3.3 Quantization Error [23]
● Signal-to-Noise-Ratio (SNR)
Signal-to-Noise-Ratio is a measure of comparison between signal and background
noise. It defines the ratio of the signal power to the sum of all other noise power
excluding the first nine largest spur and dc [23].
= 10 log
∑
= 20 log
=
∑
(
)−
,
(
)
(2.30)
● Signal-to-Noise-And-Distortion (SINAD)
SINAD is the ratio of the signal power to sum of the all other noise excluding dc.
= 10 log
(2.31)
∑(
● Effective Number of Bits (ENOB)
ENOB is a measure of the quality for the analog to digital conversion. The
relationship between ENOB and SNR or SINAD is described as below,
=
.
.
15
(2.32)
.
=
(2.33)
.
● Spur-Free Dynamic Range (SFDR)
SFDR is the ratio of the signal power to the largest spur whether harmonically
related or not, which can be expressed by,
(
=
)−
(
)
(2.34)
2.3.4 Integral Non-Linearity (INL) [23]
INL is the maximum difference between the actual and ideal finite resolution
characteristic measured vertically in percent or LSBs, as shown in
Fig. 2.6 INL and DNL
2.3.5 Differential Non-Linearity (DNL) [23]
DNL is a term defining the deviation between adjacent codes measured at each
vertical step in percent or LSBs, which is expressed as below,
=(
Where
− 1)
is the size of the actual vertical step in LSBs
16
(2.35)
3
READ-OUT INTEGRATED CIRCUIT DESIGN OPERATING IN
SUBTHRESHOLD
3.1 Introduction
To detect the resistance change when resistive CNTs sensors are exposed to gas, two
mainly conversion approaches resistance-to-current and resistance-to-voltage are adopted.
Each of approach also has different architectures to implement.
According to the existed literature, most of researchers focused on the architectures to
implement a read-out integrated circuit (ROIC) with high resolution, wide dynamic range,
anti-noise and easy to control to account for process variation in the manufacturing of
CNTs, and already obtained some improvements but didn’t pay much attention to the
power consumption. However, in energy constrained applications such as read-Out
integrated circuit design for CNTs based biomedical, chemical sensors, or other portable
devices, where the low power dissipation is the priority. Therefore, ultra-low power
circuit design with capability of operating at low frequency is very desirable in these
applications. In this thesis, a ROIC for the resistive CNTs based sensors applying subthreshold technology is presented. Meanwhile the ROIC also includes automatic gain
control unit to extend the reading dynamic range.
3.2 Implementation of sub-threshold ROIC
The proposed sub-threshold ROIC includes current to voltage converter (CVC),
automatic gain control (AGC), multiplexer, buffer and analog to digital conversion
17
(ADC), as shown in Fig. 3.1, which can be used to detect the current from the sensor such
as carbon nanotube sensor. This ROIC has wide dynamic current reading range and
extremely low power consumption after applying automatic gain control (AGC) and subthreshold technology. In this circuit, the current flowing to the sensor is transferred to
voltage ( ) after through the transistor M1. M1 is operating in linear region act as an
active resistor. Hence Fig. 3.1 can be simplified as Fig. 3.2. In Fig. 3.2,
resistance of transistor M1,
is the resistance of sensor,
voltage applied on one terminal of sensor, and
fixed, then
is the
is the reference
is the source voltage of M1. If
is
is give by,
=
(3.1)
As shown in Fig. 3.1, after initial I-V conversion,
goes into DC level shifter to
shift DC voltage to zero and multistage amplifiers. Meanwhile AGC determines which
stage’s output is selected to send to next stage. After that a unit gain buffer is added to
drive the ADC. Finally, interfaces ADC to convert analog signal to digital signal for
future digital signal processing. The detail discussions will be given in the following
sections.
In this thesis, all the components are implemented in 180nm CMOS technology. To
compare the difference in power dissipation and other performances, three sets of power
supplies (
=0.5V/
=-0.5V;
=0.4V/
=-0.4V;
18
=0.3V/
=-0.3V) are used.
Fig. 3.1 Block diagram of ROIC
Fig. 3.2 Simplified block diagram of ROIC
3.2.1 Sub-threshold technology
Sub-threshold technology is a terminology that operating transistors in sub-threshold
region by providing gate-to-source voltage lower than threshold voltage (
<
). The
characteristic of transistor working in sub-threshold was studied since 1970s [24]. It is
known that a minority channel is formed When
threshold, or strong inversion. Ideally, when
is larger than
is lower than
, here calls super-
, the channel between
source and drain is off. However, some of the more energetic electrons can still flow
from source to drain due to Boltzmann distribution of electron energies, and a weak
19
current created in the channel, known as leakage current, sub-threshold current, weak
inversion current. Study found that the current is decreasing exponentially when the
gate-to-source voltage is scaling down after below threshold voltage
, and is related to
the thermal voltage, transistor size, sub-threshold slope parameter and etc. The
relationship can be expressed as following two equations [25]:
=
_
=
When
1−
<
(3.2)
, the drain to source current is given by,
=µ
( )
( − 1)
(3.3)
Where the parameters in Eq. (3.2) and (3.3) are defined as:
W
Effective width of the channel
L
Effective length of the channel
n
Sub-threshold slope parameter
V
Thermal voltage ((KT/q) =26 mV at 300K)
µ
C
( )
Carrier mobility for n and p channel device
Gate oxide capacitance per unit area
The incentive of operating the circuit in weak inversion is to be able to exploit the
sub-threshold leakage current as the operating drive current. From equation (3.2), the
sub-threshold current is exponentially related to the gate voltage, which means it will
give an exponential increasing delay. However, the simulation results show that the
reduction in power dissipation (PD) outweighs the increase in delay, it means the power
delay product (PDP) in sub-threshold circuits is less than the one working in strong
20
inversion circuits. As listed in Table 3.1, the comparisons in the delay and PD between
sub-threshold and strong inversion for single inverter, nand2 and nor2 gate, it is found
that their power consumption from sub-threshold region is much less than that from
strong inversion and delay is larger when gates working in sub-threshold region than that
in strong inversion region, but the power delay product in sub-threshold region gained a
lot when comparing to that working in strong inversion region. Therefore, circuits
working in weak inversion have improved performance in the power delay product.
Table 3.1 Comparisons between sub-threshold and super-threshold
for single inverter, nand2 and nor2 gate
Inverter
Nand2
Nor2
Super-threshold
Sub-threshold
Super-threshold
Sub-threshold
Super-threshold
Delay
(s)
5.55p
2.60n
8.93p
3.45n
13.8p
Power
(W)
10.5µ
0.35n
9.39µ
0.35n
13.7µ
PDP
(W.S)
58.28E-18
0.910E-18
83.85E-18
1.208E-18
189.1E-18
Sub-threshold
8.65n
0.46n
3.979E-18
Fig. 3.3 Schematic of Op-amp
21
PDP Ratio of
super- to sub64.1
69.4
47.5
To illustrate sub-threshold technology, a two stage operational amplifier design
process is presented. As shown in Fig. 3.3, the two stage operational amplifier has two
power supply
=0.4V and
= -0.4, and
= -0.1789.
At the beginning, DC analysis is applied to find the
value for
(
) = 0.
The following procedures are used:
Step1: Sweep the biased voltage till get the zero output voltage;
Step2: Record the value of bias voltage when output voltage is zero;
Step3: Measure the dc voltage for all the other nodes at the value of bias voltage
recorded in the second step. All the node DC voltages are marked in Fig. 3.3. According
to the Eq. 3.2, all the transistors in op-amp are working in sub-threshold region. For
example, transistor M5,
=-0.1789-0.4=0.2211V less than
(
=0.38V). Therefore
M5 working in sub-threshold region.
As known, Op-amp is the key component in the CVC design. Consequently, the
performance of Op-amp will affect the design of DC level shifter and multi-stage
amplifiers. For instance, as shown in Fig. 3.8, to shift the median input voltage (
zero in DC level shifter block, appropriate value of
Table 3.2, the deviation between simulated
) to
should be given, as listed in
and calculated
is expressed by
Error%.
%=
_
_
_
22
× 100%
(3.4)
Table 3.2 Error percentage vs power supply and gain
-0.1
-0.06
-0.03
-0.01
0.03
0.06
0.1
(calculate)
-0.4
-0.24
-0.12
-0.04
0.12
0.24
0.4
= 0.9
= −0.9
Gain=51.8dB
Error%
(simulation)
-0.3919
2.025
-0.2351
2.042
-0.1175
2.083
-0.03917
2.075
0.1175
2.083
0.2348
2.167
0.3911
2.225
= 0.5
= −0.5
Gain=52.3dB
Error%
(simulation)
-0.356
11.5
-0.201
16.3
-0.102
15.0
-0.034
15.0
0.105
12.5
0.211
12.1
0.330
17.5
= 0.5
= −0.5
Gain=65.2dB
Error%
(simulation)
-0.398
0.475
-0.239
0.417
-0.119
0.333
-0.039
0.350
0.119
0.333
0.239
0.333
0.398
0.325
It is observed that error% is about 2% with 1.8V power supply and gain of 51.8dB,
while it is up to 17% with 1.0V power supply and gain of 52.3dB. However, the error% is
reduced to 0.5% when increase the gain to 65.2dB and keep 1.0V power supply. Hence,
the gain of sub-threshold should be larger than the one from super-threshold to get
closely error percentage.
Table 3.3 Performance comparisons in op-amp with different power supply
Working region
Super-threshold
Sub-threshold
Sub-threshold
Sub-threshold
(v)
0.9
0.5
0.4
0.3
(v)
-0.9
-0.5
-0.4
-0.3
(v)
-0.2067
-0.2116
-0.1789
-0.1349
Gain
(dB)
51.8
65.15
65.19
63.85
PM
(deg)
108.8
59
61
62
UGB
(MHz)
138.7M
579k
99.3k
20.4k
CMRR
(--)
58.4
1810
1614
1185
PD
(W)
921μ
620n
76.8n
11.4n
SR
(v/uS)
131
0.3
0.05
0.009
Table 3.3 gives the comparison of simulation results for op-amp between superthreshold and sub-threshold, where DC analysis, AC analysis and transient analysis are
applied for the op-amp. First, doing DC analysis is to find the
value for
(
)=
0, second doing AC analysis by sweeping the frequency to measure gain, phase margin
23
(pF)
1
1
1
1
(PM) and unit gain bandwidth (UGB), common mode range ratio (CMRR). Finally, the
slew rate also recorded using transient analysis.
It can be seen from Table 3.3 that the power consumption (PD) is reduced almost
four orders (from 921μW to 11.4nW) when the power supply is decreased from 1.8V to
0.6V. Op-amp also operating in acceptable frequency (UGB=20.4k) even with 0.6V
power supply. So sub-threshold technology is quite attractive for the applications of ultra
low power and low speed.
3.2.2 Sub-threshold CVC Design
As shown in Fig. 3.4, CVC includes two stages. The first stage converts the current
directly into voltage
based on Ohm’s Law. The second stage includes DC shift, 1st
stage amplification and 2nd stage amplification.
Fig. 3.4 Block diagram of CVC
● Stage 1 Design
The basic principle for detecting current signal is the conversion of current to
voltage. Ideally current signal can be treated as current source (
24
see Fig. 3.5) with very
large inner resistance. The principle diagram in which positive terminal connects to the
ground measuring current signal can be seen in Fig. 3.5.
Fig. 3.5 Diagram for traditional I-V converter
The output voltage is proportional to the input current if input impedance and openloop gain are infinite:
=−
(3.5)
Theoretically, relatively large output voltage would be obtained if resistor
enough even though input current signal is pretty weak. For example,
=1
, then
=−
is large
= 10 Ω,
= −1 . However, the totally ideal operational amplifier
does not exist in reality, as the input impedance is not infinite and the increasing in
also limited by the input impedance.
is
Meanwhile, the variation of manufacture
technology and process should also be given a consideration, such as offset voltage
, leakage current
and etc. Actually, considering the leakage current
output voltage of Fig. 3.5 becomes
= −(
−
) , if
is larger than
, the
, then
will not be measured. Additionally, the open-loop gain is not infinite. The characteristic
of relationship between input and output is expressed as following equation:
=−
+
−
25
+
(3.6)
From Eq. (3.6), it can be seen that several conditions should be satisfied if measuring
weak current signal, they are listed as follows:
≫ feedback resistor
◊ Input impedance
◊ Leakage current
≪input current
◊ Small offset voltage
and temperature drift
For using sub-threshold technique, leakage current will no longer be able to be
ignored, and must be considered.
However, in this thesis, the above requirements are not needed as the op-amp is not
included in I-V conversion part. As illustrated in Fig. 3.6, one terminal of the sensor
connects to the ground (
.
and
=0), the other one connects to the drain terminal of transistor
are the gate voltage and source voltage of
conversion, the voltage signal
respectively. After I-V
goes into unit gain buffer to avoid the feedback current
to the sensor and the next application stage which will be discussed later. The active
transistor working in linear region can be treated as a resistor, so the circuit (a) in Fig. 3.6
can be simplified as (b) in Fig. 3.6. Based on the principle of Ohm’s Law (V=IR), and the
current from sensor can be developed by Eq. (3.7),
=
−
(3.7)
The main advantage of this design is the current will flow directly from
to
terminal, no DC current will flow to and from the unit gain buffer due to the inherent
capacitor at the gate terminal of the transistor.
26
Fig. 3.6 Model for Sensor and transistor
Considering the inherent capacitor for gate of transistor, a long settling time is
needed before outputs a steady voltage value for weak current. This will be an issue when
operating in the high speed (MHz, GHz) applications. However, the design of this circuit
is applied in low speed area: biochemical sensing and chemical detecting and etc.
Another obviously advantage of using active resistor can be observed when
considering the process error. As we know, process variation will cause the resulting
resistance to differ from the one expected during the CMOS fabrication process, which
will reduce the accuracy for the subsequent stages. However, with the using of active
transistor
design, , the resistance value can be adjusted through a control voltage
is the gate voltage and . In this
is the source voltage for transistor M1. The
expression to the resistance value of active transistor working in linear region is show in
Eq. 3.8.
=
>
(3.8)
Where
27
<
−
L Length of transistor
W Width of transistor
Voltage from gate to source
A function of electron mobility or hole mobility and oxide thickness.
Fig. 3.7 I-V Performance Evaluation with Input Current Sweep
The circuit in Fig. 3.6 is implemented by using 180nm CMOS technology, where the
sensor is modeled as a varying current source. Fig. 3.7 is the simulation result with
versus current. As seen in Fig. 3.7, an ideal current source is used to test the I-V
conversion circuit with input currents of 0 to 100 nA. The purpose is to adjust the
transistor width to length ration for
that yields a resistance of around 1 MΩ to cover
the potential current range of the sensor. The value used for the control voltage
is also
another important design parameter to ensure the transistor operates in linear region. The
results are shown in Fig. 3.7 and Table 3.4. Note that the voltage drop across the
transistor
is
−
. For a given value of 1MΩ (
28
_
), 1nA of current will
be converted to approximately 1mV. Therefore, it is important to preserve the linear
relationship between the input current and output voltage
. As shown in table 3.4, the
conversion error is given by,
Where
_
_
%=
=(
−
× 100%
_
)/
(3.9)
_
It can be seen that the conversion error is about 5% when the input current below
60nA, so in the following analysis, estimated value of 1 MΩ for
Meanwhile, the variation of
will be used.
can be calibrated to generate data similar to the Table
3.4 after fabrication.
Table 3.4 I-V performance Evaluation with Input Current
(nA)
0
(mV)
(mV)
(mV)
Simulated Resistance
(MΩ)
Conversion
Error %
-400
1
2
3
4
5
6
7
8
9
10
20
30
40
50
60
70
80
90
100
-399
-398
-397.1
-396.1
-395.1
-394.1
-393.1
-392.1
-391.2
-390.2
-380.1
-369.8
-359.2
-348.3
-337.1
-325.5
-313.6
-301.2
-288.6
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
-400
0
1
2
2.9
3.9
4.9
5.9
6.9
7.9
8.8
9.8
19.9
30.2
40.8
51.7
62.9
74.5
86.4
98.8
111.4
0.000
1.000
1.000
0.967
0.975
0.980
0.983
0.986
0.988
0.978
0.980
0.995
1.007
1.020
1.034
1.048
1.064
1.080
1.098
1.114
0.0
0.0
0.0
3.3
2.5
2.0
1.7
1.4
1.2
2.2
2.0
0.5
0.7
2.0
3.4
4.8
6.4
8.0
9.8
11.4
_
29
● Stage 2 Design
In Fig. 3.4, stage 2 design comprises of DC level shift block and 1st stage
amplification, and the 2nd stage amplification. DC shift is used to set the middle value of
to be zero.
Fig. 3.8 is the circuit of combined DC level shift and 1st stage amplification, after DC
level shift, the voltage signal
added by the absolute value of
), meanwhile it is also amplified by
(the median value of
(the gain of first stage amplification) times, the
relationship is expressed as Eq. (3.12).
Fig. 3.8 DC level shift and 1st stage amplification of CVC
Assume it is an ideal op-amp, we obtain
=
(3.10)
Then
= 1+
Set
=
, to get
) .
(3.12)
value, DC level shifter shifts middle value of
means shifting all the values of
because
(3.11)
be zero,
= (1 +
With this
−
by |
| . Note that
= 0 in Fig. 3.6.
30
to zero, which
is a negative number
=(
Thus
−
)
(3.13)
=1+
Where
(3.14)
However, for sub-threshold region, the leakage current to the gate must be
considerate. So Eq. (3.11) is no longer valid. According simulation results, a modification
factor is added in Eq. (3.11)
= 1+
−
(
+ )
Comparing Eq. (3.11) and Eq. (3.15), it is find that
adjusting
(3.15)
would still be zero by
even though the Equation changed.
Fig. 3.9 is the schematic circuit of a unit gain buffer, where the inverting terminal
and output terminal are connected together, is given by,
=
(3.16)
Fig. 3.9 Unit Gain Analog Buffer
Substituting Eq. 3.16 into Eq. 3.11 yields,
= 1+
−
(3.17)
Simplify Eq. (3.17), finally get,
=
(3.18)
31
Hence, unit gain analog buffer is obtained just simply connecting inverting terminal
and output terminal each other. Note that
is the input signal while
is the output
signal.
To provide extra gain for the weak voltage signal, a second stage amplifier is added.
As discussed before, the gain is highly related to the ratio of resistance, see Eq. (3.14).
High gain requires large ratio of
, then the resistance will pretty large and increase the
hardware overhead needed for fabricating on-chip. However, if using multi-stage gain
distribution, the resistor value will be reduced a lot while still satisfy overall gain
required in the second stage. The schematic of second stage amplification depicted in Fig.
3.10 includes three stages of operational amplifiers in non-inverting configuration. Each
stage’s gain is the ratio of resistor they are given by,
Fig. 3.10 Schematic of 2nd stage amplification
_
The entire gain
(
_
,
_
and
_
=
(3.19)
_
=
(3.20)
=
(3.21)
for second stage is the product of smaller gain of three sections
_
, as described in Fig. 3.10), and is given by,
32
=
_
_
(3.22)
_
The Cadence schematic simulation result shows that the gain for the second stage is
approximately 15.822.
3.2.3 Sub-threshold AGC Design
Fig. 3.11 is the block diagram of sub-threshold automatic gain control (AGC). The
AGC circuit is designed to control the system gain and increase the ROIC interfacing
sensor dynamic range. It includes three differential op-amps (Diff_comp), labeled as C1,
C2 and C3, and two multiplexers, where Diff_comp block includes a comparator and a
D type flip flop and Mux block is a 2-to-1 multiplexer, clk is the clock signal into the
Diff_comp. The input voltage signal
is directly coming from the DC shift and first
stage amplification as shown in Fig.1, and its amplitude range is from -160mV to 160mV.
The polarity of
is to be determined by the comparator C1 which is included in
Dif_comp, where non-inverting terminal connecting to the ground. Meanwhile,
also
goes into comparators C2 and C3 to compare with the negative reference voltage (
=-
10mV) and positive reference voltage (
=10mV) repectively. The reference voltage
can be adjusted according to the designing requirements for different applications.
After comparing with the reference voltage
and
, two outputs (S2 and S3)
from comparator C2 and C3 are obtained. One of the outputs S2 or S3 will be picked up
depends on the polarity of
by multiplexer m1. If
. For instance, if
< 0, then S1=1 and S3 will be selected
> 0, then S1=0 and S2 will be selected by multiplexer m1.
33
Fig. 3.11 Block diagram of sub-threshold AGC
Finally, the output of first multiplexer m1 will serve as a control signal for the
second multiplexer m2 to determine which input (
and
) will be selected. Note that
is the output of second stage amplification as shown in Fig. 3.1, where it is amplified
by
more times than
then
. For example, if
larger than 10mV, the control signal S=0,
= . If not, the control signal S=1 and
,
,
= . Hence, the logic relationship of
and S is obtained as follows,
=
(1 − ) +
In the following, the deduction of gain
presented. As mentioned in section 3.2.2,
(3.23)
for the function of
is expressed by
,
,
and
and S will be
. The Eq.
3.13 is rewritten as below,
=(
−
)
(3.24)
After through the 1st stage amplification, the signal will go to the second stage and
amplified by
times more, so we have
=
(
−
)
Substituting Eq. (3.24) and Eq. (3.25) into Eq. (3.23) yields
34
(3.25)
=(
)(
−
(1 − ) +
)
(3.26)
Considering
=
(
−
)
(3.27)
Thus the equivalent gain (the gain after applying AGC) is,
=
(1 − ) +
(3.28)
From Eq. (3.28), it is clearly found that automatic gain control is well implemented.
=
For example, if S=0, then the total gain
=
. The simulation results can be seen in Fig. 3.12 and Table 3.5.
Table 3.5 Results of CVC (
(nA)
60.0
54.1
48.1
42.1
36.1
30.1
24.1
18.1
12.1
6.1
0.1
, else if S=1, then the total gain
(mV)
-236.3
-243.2
-250.1
-256.8
-263.4
-269.8
-276.1
-282.2
-288.2
-294.1
-299.9
(mV)
161
125.8
90.94
56.95
23.77
-8.659
-40.38
-71.44
-101.9
-131.7
-161
(mV)
-197.2
-197.2
-197.2
-197.2
-197.2
-131.6
368.2
399.7
399.7
399.7
399.7
(mV)
161
125.9
91.04
57.07
23.85
-131.6
-40.38
-71.44
-101.9
-131.7
-161
S
0
0
0
0
0
1
0
0
0
0
0
Av1
5.063
5.063
5.063
5.063
5.063
5.063
5.063
5.063
5.063
5.063
5.063
35
=0.4V,
Av2
15.198
15.198
15.198
15.198
15.198
15.198
15.198
15.198
15.198
15.198
15.198
=-0.4V)
Av
5.063
5.063
5.063
5.063
5.063
76.9475
5.063
5.063
5.063
5.063
5.063
(mV)
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
(mV)
400
400
400
400
400
400
400
400
400
400
400
(mV)
-300
-300
-300
-300
-300
-300
-300
-300
-300
-300
-300
Fig. 3.12 Transient analysis for ROIC (
=0.4V,
=-0.4V): (a) is the current from
sensors using PWL current, (b) is the intermediate output of CVC after DC shift & 1st
stage amplification, (c) is the output of CVC after 2nd stage amplification without using
AGC, (d) is the final output of CVC using AGC.
As listed in table 3.5,
100pA to 60nA;
1 is
0
is the current to be detected from sensor ranging from
is the voltage after I-V conversion which are all negative number;
the voltage after 1st stage amplification, which are shifted by median value of
and also amplified by 5.063 times;
2
is the voltage after 2nd stage amplification without
AGC, most of value are out of the input range of ADC;
amplification;
2
is the gain of 2nd stage amplification;
1 is
the gain of 1st stage
is the gain after applying
AGC; S is the control signal from AGC, it is clearly observed that when the signal after
first stage amplification is still low enough, for example,
=-8.658mV (marked red color
in table) within the range of -10mV to 10mV, control signal will be 1 and the
36
will be
amplified by extra 15.158 times. In the last right two columns (
and
) are the input
control terminals to maintain a 1MΩ resistance for the active transistor M1.
median value of
1
and
1
is the
, and is used to determine the adjustment voltage for
DC shift.
Fig. 3.12(a) depicts output current from sensors ranging from 100pA to 60nA. As
illustrated in Fig. 3.12(b), after DC level shift and 1st stage amplification, the current are
converted to voltage signal ranging from -161 mV to 161 mV, which is within the input
range of ADC (-0.2V to 0.2V). Fig. 3.12(c) and (d) show the output voltage without using
AGC and using AGC respectively, it is observed that lots of current signal can’t be
detected without using AGC, as output voltage after 2nd stage amplification reach in
saturation. However, after applying AGC, all the current are well detected and transferred
to voltage signal. If the converted signal ( ) is too weak (for instance, | |=8.658mV,
less than 10mV), then the control signal blue line in Fig. 3.12(d) from AGC change to
high level, and
will be amplified by further stage to reach in -131.6mV. If signal
over 10mV, then control signal will be at low level. Finally,
is
serves as the final analog
output of ROIC.
The results in Fig. 3.12 and Table 3.5 are simulated under 0.8V power supply.
Considering the large improvement in power consumption by reducing the power supply,
can we keep reducing the power supply to
=0.3V,
=0.3V? However, AGC is no
longer operating normally, as depicted in Fig. 3.13, the control signal is always at high
level, nothing related to the value of
coming from the DC shift and first stage
amplification as shown in Fig. 3.1. Hence, some modifications are required to make the
CVC work in the future.
37
Fig. 3.13 Final analog Output signal (
)
As discussed in chapter 2.2.1, the input range of ADC is related to the power supply.
With the power supply scaling down, correspondingly the input range is reducing.
Therefore, to improve the entire performance of ROIC, multi-power supply is
recommended. For example, distributes 0.8V to CVC and 1.0V to ADC.
3.2.4 Calibration Method
To convert voltage back to current, calibration method is applied after read the
voltage output from ROIC. After calibration, it is convenient to use compensation
technology to improve the accuracy of current detecting.
Fig. 3.14 shows the block diagram of Read-Out Integrated Circuit including active
transistor, 1st stage and 2nd stage amplification, AGC, Multiplexer, Buffer and ADC.
38
Fig. 3.14 Block Diagram of ROIC
Where
= the current to be detected from sensor
= the voltage after I-V conversion
= the voltage after 1st stage amplification
= the voltage after 2nd stage amplification
= the gain of 1st stage amplification
= the gain of 2nd stage amplification
= the gain after applying AGC
S = the control signal from AGC
= the analog output signal
= the digital output signal
The voltage drop across active transistor M1 is (
− ), and applying Ohm’s Law,
we obtain
=
−
Reviewing Chapter 3.2.3, the relationship among
=
(1 − ) +
39
(3.29)
,
,
and S is given by,
(3.30)
Since
=
(
−
)
(3.31)
Substituting Eq. (3.30) into Eq. (3.31) yields
=(
)(
−
(1 − ) +
)
(3.32)
Thus we have
−
=
=
(
(
(3.33)
)
+
)
(3.34)
Combining Eq. (3.29) and Eq. (3.34), then get
=
(
)
(
)
+
−
+
−
(3.35)
Finally
=
(
Hence, if given the value of
,
, S,
,
)
and measured result
(3.36)
, then the
current can be readily obtained.
For example,
=5.089,
=15.822, Vs=-400mV. From simulation of DC
analysis using ideal current source ranging from 100pA to 60nA, we get
399.9mV,
=-337.1mV, and also know the value of active transistor
==1MΩ,
then
= 0.5(
) = −368.5
+
(3.37)
From transient analysis, the measured output voltage is 159.5mV and -93.87mV
respectively
Case 1
=60nA,
=
=159.5mV and S=0, then
(
+
)
40
−
=
(
.
(
.
)
.
×
.
×
− 368.5
+ 400
)
(3.38)
+ 400
)
(3.39)
= 62.84nA
Case 1
=-93.87mV and S=1, then
=30nA,
=
=
(
(
)
(
)
+
−
.
.
.
×
.
×
− 368.5
= 30.33nA
Similarly, all the measured output voltage can be converted back to current using
Eq. (3.36). More calculations are tabulated in Table 3.6 and Table 3.7.
Table 3.6 Comparison of input and calibrated current (
(nA)
60.0
54.1
48.1
42.1
36.1
30.1
24.1
18.1
12.1
6.1
0.1
(mV)
159.5
125.9
92.03
58.86
26.34
-93.87
-37.58
-68.76
-99.53
-129.9
-159.8
S
0
0
0
0
0
1
0
0
0
0
0
(mV)
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
-368.5
41
Av
5.089
5.089
5.089
5.089
5.089
80.5182
5.089
5.089
5.089
5.089
5.089
=0.5V,
(nA)
62.8421
56.2396
49.5841
43.0661
36.6759
30.3342
24.1155
17.9885
11.9421
5.97435
0.09894
=-0.5V)
Error
(%)
4.7368
3.9549
3.0855
2.2948
1.5952
0.7779
0.0640
0.6160
1.3047
2.0597
1.0611
Fig. 3.15 Comparison between Readout and Input current (
=0.5V,
=-0.5V)
As seen in Table 3.6, comparison between input current and calibrated current with
1V power supply (
current
=0.5V,
=0.5V), where the input current
, the converted back
, and percentage error are listed. When control signal S=1, automatic gain
control is in effective and changes the gain 5.089 to 80.5182. So the weak voltage signal
amplified by one more stage. In the column (Error%), the maximum error percentage is
4.7%. Fig. 3.15 shows the comparison between input current and converted back current,
it is observed that error percentage is increasing when input current over 36.1nA, and
reach in maximum value when
= 60nA.
Table 3.7 shows the information about input current and calibrated output current with
0.8V power supply (
= 0.4 ,
= −0.4 ). Note that the gain for the 1st stage and
2nd stage has a little bit difference with the gain provided by 1.0V power supply. The
maximum error percentage 6.16% is also increased when served with a lower power
42
supply. Similarly, as depicted in Fig. 3.16, the error percentage is increasing when input
current is over 42.1nA, and get the peak value when
=60nA.
Table 3.7 Comparison of input and calibrated current (V =0.4V, V =-0.4V)
(nA)
60.0
54.1
48.1
42.1
36.1
30.1
24.1
18.1
12.1
6.1
0.1
(mV)
161
125.9
91.04
57.07
23.85
-131.6
-40.38
-71.44
-101.9
-131.7
-161
S
0
0
0
0
0
1
0
0
0
0
0
(mV)
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
-268.1
Av
5.063
5.063
5.063
5.063
5.063
76.9475
5.063
5.063
5.063
5.063
5.063
Fig. 3.16 Comparison between Readout and Input current (
43
(nA)
63.6993
56.7667
49.8814
43.1719
36.6106
30.1897
23.9245
17.7898
11.7736
5.88775
0.10067
=0.4V,
Error
(%)
6.1655
4.9292
3.7036
2.5463
1.4145
0.2981
0.7283
1.7138
2.6976
3.4794
0.6715
=-0.4V)
3.2.5 Optimization applying compensation technology
● Establishment of fitting function for compensation factor
Compensation factor α is derived from the analysis of simulation results, which is
added to the initial calibrated current to reduce the error of current detecting. More details
are discussed in the section.
Table 3.8 Comparison of input current and calibrated output current after compensation
(
(nA)
60
58
56
54
52
50
48
46
44
42
40
38
(mV)
159.5
148
136.6
125.2
113.9
102.7
91.48
80.36
69.3
58.31
47.37
36.49
(nA)
62.84211
60.58233
58.34221
56.10208
53.88161
51.68078
49.47603
47.29092
45.11761
42.95805
40.80831
38.67037
=0.5V,
(
−
)nA
2.84211
2.58233
2.34221
2.10208
1.88161
1.68078
1.47603
1.29092
1.11761
0.95805
0.80831
0.67037
=-0.5V)
Compensation
Factor (nA)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Error%(before
Compensation)
4.736851
4.452301
4.182516
3.892746
3.618476
3.361564
3.075056
2.806351
2.540015
2.281064
2.02078
1.764125
Error%(after
compensation)
0.070184
0.030458
0.103199
0.181328
0.227678
0.238436
0.258278
0.237127
0.187258
0.099889
0.020780
0.185178
To find an appropriate fitting function for compensation factor, more simulation data
are connected. From Fig. 3.15 and Fig. 3.16, we already known that the error percentage
is increasing when input current larger than 36.1nA. As tabulated in Table 3.8, the
comparison of input current and calibrated output current after compensation with
=0.5V,
=0.5V, where the error percentage from 1.76% increases up to 4.73%
while input current varies from 38nA to 60nA. It is observed that all the calibrated
output current is larger than the input one, and difference steadily goes from 0.67 to 2.84.
44
If we give a compensation factor to the calibrated current subtracting
by an
arithmetic progression (as shown in table 3.10, the initial term is 0.6V, the common
difference is 0.2V), then all the error percentage are decreased, especially the maximum
error percentage degrading from 6.16% to 0.25%. Therefore, it is very helpful to reduce
the error using compensation technique.
For convenient, the minimum calibrated output current is expressed by
(62.84nA) when input
(38.67nA) and the maximum output current is written as
current varies from 30nA to 60nA. Similarly, the smallest and largest compensation
factor is seen as
(0.6nA) and
(2.8nA) respectively. Considering the discussion
above, the compensation factor α can be calculated as below,
Compensation factor:
=
+
(
For example, the calibrated current is
−
)
(3.40)
=48nA, substituting all the parameters into
Eq. (3.40) yields,
= 0.6
+
.
.
.
(2.8 − 0.6)
= 1.449
(3.41)
Comparing α calculated by Eq. (3.40) to the one (1.6nA) from Table 3.8, both of
them are pretty close.
Similarly, the same analysis is applied for the comparison of input current and
calibrated output current after compensation with
=0.4V,
=-0.4V, as shown in
Table 3.9, where the error percentage from 1.72% increases up to 6.16% while input
current varies from 38nA to 60nA. It is observed that all the calibrated output current is
45
larger than the input one, and difference steadily goes from 0.65 to 3.70. If we give a
compensation factor to the calibrated current subtracting
by an arithmetic
progression (as shown in table 3.11, the initial term is 0.85V, the common difference is
0.25V), then all the error percentage are decreased, especially the maximum error
percentage degrading from 6.16% to 0.74%.
Table 3.9 Comparison of input current and calibrated output current after compensation
(
(nA)
60
58
56
54
52
50
48
46
44
42
40
38
(mV)
161
149
137
125.2
113.5
101.9
90.37
78.95
67.63
56.39
45.45
34.19
=0.4V,
(
−
)nA
3.69933
3.32919
2.95906
2.62842
2.31754
2.02641
1.7491
1.49352
1.25769
1.03767
0.87689
0.65291
(nA)
63.69933
61.32919
58.95906
56.62842
54.31754
52.02641
49.7491
47.49352
45.25769
43.03767
40.87689
38.65291
=-0.4V)
Compensation
Factor (nA)
3.60
3.35
3.10
2.85
2.60
2.35
2.10
1.85
1.60
1.35
1.10
0.85
Error%(before
Compensation)
6.165547
5.739987
5.284028
4.867448
4.456806
4.052815
3.643961
3.246786
2.858393
2.470632
2.192228
1.718193
Error%(after
compensation)
0.998881
0.739987
0.4626
0.237818
0.033729
0.147185
0.314372
0.448866
0.550698
0.624606
0.307772
0.650228
For convenient, the minimum calibrated output current is expressed by
(38.65nA) and the maximum output current is written as
(63.69nA) when input
current varies from 30nA to 60nA. Similarly, the smallest and largest compensation
factor is seen as
(1.1nA) and
(3.1nA) respectively. In virtue of the discussion
above, same fitting equation with Eq. 3.40 is obtained by only changing some initial
parameters (
,
,
and
). For example, the calibrated current is
=48nA, then the compensation factor will easily be acquired and has the approximately
value for the ideal one.
46
=
+
=1.1
+
(
.
.
.
.
−
)
(3.1 − 1.1)
(3.42)
= 1.847
To sum up, the fitting function for compensation factor can be expressed by Eq.
(3.40). Some initial parameters changes are required if power supply varied.
● Verification
Table 3.10 and Table 3.11 are the comparison in performance between beforecompensation and after-compensation, where
is the initial calibrated output current
calculated by the Eq. 3.36 before compensation, and
after compensation, and
is the calibrated output current
is the compensation factor getting from Eq. 3.40. Note that
is obtained by different power supply, 1.0V in Table 3.10 while 0.8V in Table 3.11.
The performance is evaluated by the error percentage of deviation to input current, which
is given by,
%=
(3.43)
× 100%
To better observe the performance after applying compensation technology, all the
results are drawn in Fig. 3.17 with 1.0V power supply (
3.18 with 0.8V power supply (
=0.4V,
=-0.4V).
47
=0.5V,
=-0.5V) and Fig.
Table 3.10 Performance comparison between before-compensation and
after compensation with power supply (
=0.5V,
=-0.5V)
(nA)
Compensation
Factor (nA)
(nA)(after
compensation)
(nA)(after
compensation)
Error%(before
Compensation)
Error%(after
compensation)
60.0
54.1
48.1
42.1
36.1
30.1
24.1
18.1
12.1
6.10
0.10
2.80
2.08
1.58
1.08
0.00
0.00
0.00
0.00
0.00
0.00
0.00
62.8421
56.2396
49.5841
43.0661
36.6759
30.3342
24.1155
17.9885
11.9421
5.97435
0.09894
60.0421
54.1596
48.0041
41.9861
36.6759
30.3342
24.1155
17.9885
11.9421
5.97435
0.09894
4.7368
3.9549
3.0855
2.2948
1.5952
0.7779
0.0640
0.6160
1.3047
2.0597
1.0611
0.0702
0.1101
0.1994
0.2705
1.5953
0.7780
0.0643
0.6160
1.3049
2.0598
1.0611
Table 3.11 Performance comparison between before-compensation and aftercompensation with power supply (
=0.4V,
=-0.4V)
(nA)
Compensation
Factor (nA)
(nA)(before
compensation)
(nA)(after
compensation)
Error%(before
Compensation)
Error%(after
compensation)
60.0
54.1
48.1
42.1
36.1
30.1
24.1
18.1
12.1
6.10
0.10
3.60
2.55
1.89
1.23
0.00
0.00
0.00
0.00
0.00
0.00
0.00
63.6993
56.7667
49.8814
43.1719
36.6106
30.1897
23.9245
17.7898
11.7736
5.88775
0.10067
60.0993
54.2167
47.9914
41.9419
36.6106
30.1897
23.9245
17.7898
11.7736
5.88775
0.10067
6.1655
4.9292
3.7036
2.5463
1.4145
0.2981
0.7283
1.7138
2.6976
3.4794
0.6715
0.1655
0.2157
0.2258
0.3755
1.5952
0.7779
0.0640
0.6160
1.3047
2.0597
1.0611
48
Fig. 3.17 Performance comparison between before-compensation and after-compensation
with power supply (
=0.5V,
=-0.5V). Red line is the input current, blue line is the
calibrated output current.
Fig. 3.18 Performance comparison between before-compensation and after-compensation
with power supply (
=0.4V,
=-0.4V). Red line is the input current, blue line is the
calibrated output current.
As depicted in Fig. 3.17 and Fig. 3.18, no observable deviation between input current
and calibrated output current after compensation. From Table 3.10 and Table 3.11, it is
49
observed the accuracy is improved a lot when the input current over 36.1nA, additionally,
maximum estimated error percentage decreased from 4.73% to 2.05% with 1V power
supply, and from 6.16% to 2.05% with 0.8 power supply.
3.2.6 8-bit ADC Design
After I-V conversion, the signal will go to computer or other digital devices to do
signal processing. However, analog signal is not recognized by digital devices and is also
easily distorted by the noise.
Consequently, an analog to digital converter is quite
necessarily. As shown in Fig. 3.19, the analog signal is first sampled, quantized to a
digital format of ones and zeros, and finally converted to a workable binary number
format
through
the
encoder.
The
digitized
data
can
then
be
processed,
modulated/demodulated, and transmitted through different signal.
Fig. 3.19 Analog to Digital Conversion
The flash ADC is used to implement analog to digital conversion, as shown in Fig.
3.20. For convenient, a 3 –bit ADC is presented due to the same principle of 3-bit and 8bit ADC. As learnt in CMOS analog integrated circuit design, a N-bit flash ADC consists
of 2 resistors, 2 − 1 comparators, and a 2 − 1 to N encoder. Thus 3-bit flash ADC
requires 8 equal value resistors, 7 comparators and a 7-to-1 encoder [26].
50
Fig. 3.20 Flash Analog to Digital Convertor
The series of equal value resistors forms a voltage divider, which creates seven
reference voltages to sample the analog input. Then the comparators are used to compare
the input analog value with the seven reference voltages at fixed time intervals. Zero
indicates that the current voltage value is less than the reference voltage compared with
and one indicates the opposite. Generally, a clock with a fixed period and 50% duty cycle
is used here for sampling at fixed time intervals. At the end of quantization, a 7-bit
thermometer code composed of zeroes and ones is obtained, and then is converted to a
workable numerical format for post processing.
Table 3.12 is used to convert the 7-bit thermometer code to 3-bit binary number.
The order of bits for thermometer code is from top-to-bottom, or from most to least
significant bits, in Fig. 3.20.
51
Table 3.12 Digital Output Codes
Decimal
0
1
2
3
4
5
6
7
Thermometer
Binary
0000000
0000001
0000011
0000111
0001111
0011111
0111111
1111111
000
001
010
011
100
101
110
111
Considering that all the components in ROIC are implemented in the 180nm CMOS
technology and provided by multiple power supply (0.8V to CVC, and 1.0V to ADC),
which determines the output range of I-V converter (from -0.2V to 0.2V) based on the
principle explained in section 2.2.1.
In this thesis, a 8-bit flash ADC is presented. Its components include comparators,
operational amplifiers, D flip flops, XOR gates, OR gates, resistors, 2-bit flash ADCs, 6bit flash ADCs and multiplexers. The overall schematic of 8-bit flash ADC is shown in
Fig. 3.21. For comparison, two different power supply (
= 0.5 /
= 0.9 /
= −0.9 and
= −0.5 ) are provided. Note that the power supply (1.0V) for ADC
part is larger than the one (0.8V) in I-V conversion part. Given the output range of I-V
converter is from -0.16V to 0.16V, the power supply should be around 1.0V according to
the Eq. 2.19. Therefore a second power supply (
the ADC part.
52
= 0.5 /
= −0.5 ) applied for
Fig. 3.21 Schematic of 8-bit flash ADC in sub-threshold
As shown in Fig. 3.21, 8-bit ADC mainly comprises of four 6-bit ADCs and one 2bit ADC. At first, according to 2-bit ADC, the interval (-0.2V to 0.2V), which includes
the output range of I-V converter (-0.16V to 0.16V) divided by four sections, the outputs
of 2-bit ADC to be served as control signal for the 4-to-1 multiplexer depends on the
input signal
. For example, 0.1 <
≤ 0.2 V, then
=1,
=1, this will
choose one of inputs (D3) of all the six 4-to-1 multiplexers to the next stage. More details
can be found in the following sections.
53
Fig. 3.22 8-bit flash ADC Transient Analysis
The transient analysis of the 8-bit ADC schematic design is shown in Fig. 3.22. The
input frequency here is given at 1.5625 kHz while the clock frequency is 12.5 kHz. The
corresponding period is 80 us, therefore the ADC samples at the falling edge of the clock
pulse as indicated in the Fig. 3.22 at every 80 us. After conversion, the above simulation
results visually demonstrates that the digital signal closely match with the original analog
input signal.
To evaluate the performance of the 8-bit flash ADC, spectral analysis using Discrete
Fourier Transform (DFT) is also presented. Fig. 3.23, is the spectral analysis of 8-bit
flash ADC. Two typical approaches are used in estimate the performance of the ADC
from observing the spectrum of the digital output. Both involve measuring the power of
the primary signal against other peaks in the spectrum. The line has the largest amplitude
is the digitized signal at the frequency of 1.5625 kHz. The first one measures the dB
54
difference between the primary signal and the next highest spur, refers as the signal to
noise and distortion ratio (SINAD). The spurs can be noise due to quantization or
harmonics of the primary signal. As shown in Fig. 3.23, SINAD=56.07dB, which is
approximately equal to 6.02 times the effective number of bits for ADC. Consequently,
after minor calculation, the ENOB is nearly 8. The second one measures the dB
difference between the primary signal and the next highest noise spur (excluding the
harmonics of the primary signal), here calls the spurious free dynamic range (SFDR).
Fig. 3.23 The Discrete Fourier Transform (DFT) Analysis for 8-bit flash ADC
SFDR=76.34dB, which is 9 times the effective number of bits for ADC. Therefore, the
same approximately value for ENOB (8) is obtained. The test here just verifies the ADC
operating normal at the frequency of 1.5625 kHz, it may not the case with higher
sampling frequency, however, note that the sampling frequency is 1.5625 kHz, which is
faster than the required sampling frequency of sensor with slow changing speed.
55
3.3 Simulation Results
3.3.1 Comparison in power consumption
Table 3.13 Comparisons in power consumption
Working region
(v)
-0.9
(v)
-0.35
(kHz)
1
(kHz)
10
Working
Or not
Yes
Power
(W)
4.31m
Current-to
-Voltage
converter
(CVC)
Super-threshold
(v)
0.9
Super-threshold
Sub-threshold
Sub-threshold
Super-threshold
0.5
0.4
0.3
0.9
-0.5
-0.4
-0.3
-0.9
-0.2116
-0.1789
-0.1349
-0.35
1
1
1
1.5625
10
10
10
12.5
Yes
Yes
No
Yes
0.13m
0.53μ
0.21μ
22.1m
8-bit
Flash ADC
Super-threshold
Sub-threshold
CVC
ADC
CVC
ADC
0.5
0.4
0.4
0.5
0.9
0.9
-0.5
-0.4
-0.4
-0.5
-0.9
-0.9
-0.2116
-0.1789
-0.1789
-0.2116
-0.35
-0.35
1.5625
1.5625
0.1
0.1
0.1
0.1
12.5
12.5
10
1
10
1
Yes
Yes
Yes
Yes
Yes
Yes
0.85m
0.46m
Total
ROIC
25.2m
0.89m
In Table 3.13, the comparisons in power consumption (PD) are obtained by using
transient analysis, where
listed in Table 3.13,
and
and
is the input frequency and clock frequency. As
keep their value fixed while the power supply is varied
to avoid the influence for the comparison in PD. It is found that when power supply
reduces from 1.8V to 1.0V, the PD for CVC goes down from 4.31mW to 0.13mW, and
for ADC decreases from 22.1mW to 0.85mW. The power dissipation for both CVC and
ADC save up to 96%. If the power supply is reduced to 0.8V (
=0.4V,
=-0.4V),
then some transistors will begin to reach in sub-threshold region, and more energy will be
saved. As shown in Table 3.13, the power consumption for CVC is reduced one order of
magnitude (from 0.13mW by using 1.0V power supply to 0.53 μW by using 0.6V power
supply), and for ADC is reduced 50% more (from 0.85mW by using 1.0V power supply
to 0.46mW by using 0.8V power supply). If the power supply reduced to 0.6V, the AGC
56
unit is no long working normally. The total PD of ROIC is also saved up to 96% (from
25.2mW by using 1.8V power supply for both CVC and ADC to 0.89mW by using 0.8V
power supply to CVC and 1.0V power supply to ADC).
3.3.2 Evaluation for entire system
Fig. 3.24 Schematic of Read-Out Integrate Circuit (ROIC)
Fig. 3.24 is the schematic circuit of ROIC, where two power supplies (0.8V for CVC
and 1.0V for ADC) are provided,
current from sensor,
and
(ranging from 0.1nA to 24.1nA) is the input
are the analog output and digital output
respectively. The current is firstly transferred to voltage (
) and then converted to
digital signal after analog to digital converter. The simulation results can be seen in Fig.
3.25 and Fig. 3.26.
57
Fig. 3.25 Analog and weighted sum digital output (
=100 Hz)
Fig. 3.26 Comparison between analog and weighted sum digital output (
58
=100 Hz)
Note that the digital output in Fig. 3.25 and Fig. 3.26 is the weighted digital outputs
(bout7~bout0). Fig. 3.25 shows the analog output (
where
) and digital output (
),
is calculated by the Eq. 3.44. Fig. 3.26 shows the comparison between
=(
0+
6 ∗ 64 +
1∗2+
7 ∗ 128) ∗
. ∗
2∗4+
3∗8+
−
4 ∗ 16 +
5 ∗ 32 +
(3.44)
analog output and digital output. The comparison evaluated by the error percentage is
given by Eq. 3.45,
%=
× 100%
(3.45)
Table 3.14 tabulates the input current from sensor replaced by the Piece Wise Linear
(PWL) current source (
=100Hz), analog output, digital output codes, weighted sum
digital output and error percentage. It can be seen that digitized output signal matches
well with the analog output, as the maximum error percentage is less than 1% (less than
1LSB). Note that 1 LSB=0.4V/256=1.5625mV. Fig. 3.27 is the Analog Outputs with
different input frequency varying from 100 Hz to 1 kHz. It is observed that the analog
output is acceptable (comparing to PWL) and the digital output is also following the
analog output when given 400 Hz input frequency. However, the analog output can’t
reach in steady status as the rising time is almost equal the period of output signal when
given 1 kHz input frequency. Hence the maximum operating frequency for the proposed
ROIC in this thesis can be reached at 400Hz. In the future, if require higher operating
frequency, buffer tree should be added between CVC and ADC to drive large quantities
of comparators in flash ADC.
59
Fig. 3.27 Analog Outputs and weighted digital outputs with different input frequency: (a)
=100 Hz (b)
=400 Hz (c)
Table 3.14 Input current (
=700 Hz (d)
=1 kHz
=100Hz), analog output and digital output
(nA)
(mV)
(V7~V0)
(mV)
(Weighted Sum)
0.1
6.1
12.1
18.1
24.1
-161.3
-131.8
-101.9
-71.43
-40.37
00011000
00101011
00111110
01010010
01100110
-162.4
-132.5
-102.7
-71.37
-40.00
60
(
) (mV)
1.10(<1 LSB)
0.70(<1 LSB)
0.80(<1 LSB)
0.06(<1 LSB)
0.37(<1 LSB)
Error
(%)
0.681959
0.531108
0.785083
0.083998
0.916522
4
CONCLUSION AND FUTURE WORK
4.1 Conclusion
A novel read-out integrated circuit (ROIC) applying sub-threshold technology to
provide extremely low power consumption has been proposed. This ROIC includes
automatic gain control (AGC) block to widen the dynamic detecting range. It shows that
power consumption can be saved up to 96% (from 25.2mW to 0.89mW) and detecting
dynamic range can be extended up to more than two orders ranging from 100pA to 60nA.
The digital signal from ROIC has low quantization error (less than 1 LSB).
The proposed circuit is implemented under 180 nm CMOS technology process.
Simulation results show that the circuit operating normally with 0.8V power supply to
CVC and 1.0V to ADC.
4.2 Future work
Dual slope ADC, Successive approximation (SAR) ADC consume much less power
compared to flash ADC, if replaced flash ADC with dual slope ADC in the future ROIC
design, the total power consumption will be reduced further more.
Additional, if keep reducing the power supply to 0.6 volts, the total power dissipation
will be reduced even more, however, the automatic gain control (AGC) part is no longer
working normally. A new sub-threshold AGC will be needed.
61
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