Time variable transformers operating at a near-unity
transfer ratio and some possible applications
D. Shmilovitz
Abstract: Time variable transformer network elements are reviewed. Four special topologies are
presented which are of benefit, especially in the vicinity of a unity overall transfer ratio. Analytical
expressions are derived which indicate the resulting improvements in terms of energy conversion
efficiency and systems power density (as well as expected cost). It is shown, that the use of the
proposed topologies may, in some cases, improve these figures of merit by a factor of two or more.
Additionally, when the time variable transformer realisation is achieved by means of switched
mode converters, the dynamic characteristics, and consequently, the dynamic load regulation will
improve significantly. Application of the resulting topology in an active ripple cancellation stage of
a unity-power-factor rectifier clearly validates the proposed approach.
1
Introduction
Time variable transformers (TVTs) have been desirable
network elements for many years. Such elements offer
significant advantages in the controll, manipulation, and
processing of signals with significant power content. Similar
to conventional transformers, TVTs are two-port power
conservative network elements which couple two subnetworks, N1 and N2 as shown in Fig. 1. The waveforms
and component values within the subnetwork are scaled
with respect to each other by a scaling factor, defined by the
transformers transfer ratio. However, the transfer ratio, k(t),
of TVTs is time dependent:
kðtÞ 0
v1 ðtÞ
v2 ðtÞ
¼
ð1Þ
i2 ðtÞ
0
kðtÞ1 i1 ðtÞ
i1
1
1:k (t )
i2
+
N1
Fig. 1
v1
+
v2
N2
A TVT coupling two subnetworks
Magnetically coupled variable transformers in which the
effective turns ratio is tap varied are well known and widely
used. However, for our purposes a TVT is taken to refer
to a conceptual network element whose transfer ratio is
continuously (often, periodically) varied over a wide range
at a relatively high rate. This calls for an all-electronic
realisation of the TVT. In addition, TVTs have no
r IEE, 2004
IEE Proceedings online no. 20040360
doi:10.1049/ip-epa:20040360
Paper first received 4th February 2003 and in revised form 24th September 2003
The author is with the Faculty of Engineering, Tel-Aviv University, Tel-Aviv,
Israel
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
saturation, thus they may operate with DC signal
components.
Other means of TVT realisation include a saturated core
in which the magnetic operation point is controlled by an
auxiliary bias current, varying the incremental permeability
[1, 2] or a thermoelectric-thermomagnetic coupling in which
the transfer ratio is controlled via the applied magnetic field
[3]. These variable transformers have a limited variation
range of their transfer ratio and imply power investment at
the control input.
Apparently, circuits that involve the operation of
semiconductors in a linear mode are power dissipative
and are therefore unsuitable for TVT realisation. Thus, even
though the concept of TVTs was introduced for the first
time in 1965 [4], practical realisation became possible only in
the 1970s, with the development of efficient switched mode
conversion circuits. To a large extent, modern switching
DC/DC converters may be regarded as DC transformers.
This is due to their high efficiency which implies energy
conservation in addition to the fact that their output voltage
is proportional to their input voltage and vice versa, i.e.
their input current is proportional to their output current
[4–8]. Since switched mode converters contain some energy
storage components, they can be modelled as transformers
on an average basis only. The averaging time window is
commonly chosen to be equal to a converter’s switching
period, TS [5–8]. All DC/DC converters operated with a
negative feedback control loop may be viewed as being a
DC/DC transformer whose transfer ratio is being slightly
tuned in order to provide output voltage regulation against
source and load variations. However, TVTs are characterised by the wide variation range of their transfer ratio,
implying large signal models and challenging control
schemes to ensure stability, [8–9].
The TVT concept is attractive due to the fact that this
special family of transformers exhibits a highly desirable
feature: the, so-called ‘controllable transfer ratio’. This
feature provides an important means for the improvement
of the system’s performance (through the application of
various control schemes to continuously tune the converter’s transfer ratio). Among the practical circuits, that
can be modelled by the TVT (all of which are based on
switched mode circuits) are:
161
1. Maximum power point tracking networks which couple
dynamic loads (such as a DC motor during acceleration) to
a photovoltaic generator, while conditioning maximum
power to the motor [10].
2. Switched mode power amplifiers and inverters [11], in
which the duty ratio is controlled forcing the output voltage
(large signal) to follow a small reference signal.
3. Switched-mode unity-power-factor rectifiers in which the
input current is forced to follow a small reference sinusoidal
signal, via the continuous tuning of the converter’s transfer
ratio [8].
TVTs operating at a near-unity transfer ratio will now be
investigated. Topologies will be are derived using theoretical
analysis and some possible realisations indicated. Four basic
schematic topologies will be derived which can be applied in
power converters there by yielding an improved power
density and overall efficiency. The theoretical derivations
are meant to indicate the upper bounds for improvement in
the overall efficiency and power density in power electronics
circuits due to the use of the proposed topologies,
depending on voltage levels. Once these principles are set,
different realisations may be derived, depending on the
particular case requirements. A switched-mode unitypower-factor rectifier system is chosen as an experimental
test bed to validate the theoretical derivations.
2
Consider a TVT with a transfer ratio, k(t), similar to the one
shown in Fig. 1. Its transfer matrix may be written in terms
of its deviation from unity, dk(t):
v1 ðtÞ
v2 ðtÞ
¼ KðtÞ
i2 ðtÞ
i1 ðtÞ
"
#
ð2Þ
1 þ dkðtÞ
0
KðtÞ ¼
0
ð1 þ dkðtÞÞ1
The transfer matrix, K(t), may be viewed as describing the
combined operation of two transformers: the first one
having a transfer ratio of 1:1 (with a transfer matrix I) and
the second one with a transfer matrix dK(t). As indicated by
K(t), (2), these two transformers should be connected in
series at one side, and in parallel at the other, as shown in
Fig. 2.
1:1
i11
i12
+
+
+
v11
v1
i21
1:k(t)
v21
Fig. 2
+
−
+
−
i2
v12
−
−
i22
v2
Efficiency considerations
Like any power processing network, physical TVTs have a
less then unity energy conversion efficiency. Some of the
losses are dependent on the current throughput of the TVT.
Examples of this include inductor copper losses and
conduction losses of semiconductor devices in switched
mode converters. Some of the losses are governed by the
voltage (a small part in switched mode converter implemented TVTs), while others are governed by both voltage
and current eg semiconductor switching losses. In addition,
the percentage loss may depend on operation frequency and
operation point (such as duty ratio and load). Different
models and expressions can be derived for the efficiency that
account for the loss mechanism associated with the actual
TVT realisation. With out loss of generality, a simplified
model for losses will be adopted in the present analysis.
Assume that in a given operation range the overall TVT
efficiency may be approximated by a constant value, Z.
Current-dependent losses are manifested in a reduction of
the TVT’s effective voltage transfer ratio with respect to an
ideal TVT and vice versa, losses generated by the voltage
cause a current transfer ratio which is lower than the one of
an ideal TVT. Thus, a possible way of describing a TVT
with an efficiency of Z, like the one depicted in Fig. 3a is:
vin ðtÞ
vout ðtÞ
¼KðtÞg
iout ðtÞ
iin ðtÞ
ð4Þ
a
Z
0
g¼
;
0
Z
1;
0
a
1
0 Z1a
+
v22 = v
−
−
The two-transformer topology
The symbol ‘‘C’’ in this Figure indicates that these
conceptual TVTs may operate with both, AC and DC
signals. The upper 1:1 transformer operation is given by its
162
Equations (2) and (3) are correct independent of the dk
value, however, we will concentrate on the cases in which
7dk7 is significantly smaller than one. It will be shown that
identifying such cases yields special power electronics
topologies that will improve the power density of a
converter. dk may be either positive or negative, which
would result in either an increase (v2 ¼ v1+7dv7) or decrease
(v2 ¼ v17dv7) of the voltage v2 with respect to v1. Also, the
source and the load may connect to either side of the
topology. If isolation is not required, the 1:1 upper
transformer may be omitted, shorting its input and output
terminals (which, in a way, resembles an autotransformer).
The lower transformer power throughput with respect to
the upper ones power throughput is proportional to dv/v1.
Therefore, the volume, weight and cost of the whole system
will be significantly reduced. In addition, the power
conversion efficiency is expected to increase, since part of
it will be transferred directly from the source to the load.
Efficiency issues are analysed in detail in the following
section.
3
TVTs at a near-unity transfer ratio
i1
transfer matrix I, whereas the operation of the second
transformer is described by the transfer matrix dK.
dkðtÞ
0
1 0
ð3Þ
dKðtÞ ¼
I¼
0 1
0
dkðtÞ1
where the subscripts ‘in’ and ‘out’ indicate the direction of
power flow with respect to the TVT system. The value of a
depends on the loss mechanism of the actual TVT; in
magnetic-coupling-based transformers it would be around
one-half since core losses and copper losses are about equal.
In piezoelectric transformers in which most of the losses
are dielectric losses a would be close to ‘zero’ while in
switched mode converters, where most of the losses are
generated by the current, a would be between one-half and
one. Under this representation, losses may be viewed as if
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
iin
1:k(t )
iin
iout
+
vin
+
vout
−
−
+
vin
−
iout
+
vout
−
p
p
a
Fig. 3
loss
network
1:k(t)
b
.
For a negative dk, the overall efficiency, m, is higher than the
TVTs’ efficiency Z, if:
Za
ð12Þ
dkðtÞ4
1þZ
At dk ¼ Za the output power is equal to zero as is the
overall efficiency.
Plots of the overall efficiency against the transfer ratio of
the lower TVT are provided in Fig. 4, for three values of the
efficiency of the TVT.
a Lossy TVT
b Loss mechanism modelled as a cascade loss network
1
1
=0.9
0.8
In addition, the 1:1 TVT obeys:
v12 ðtÞ
v ðtÞ
¼ I 11
i12 ðtÞ
i11 ðtÞ
ð6Þ
Also, the lower TVT, incorporating the loss model obeys:
v22 ðtÞ
v ðtÞ
¼ dK ðtÞg 21
ð7Þ
i22 ðtÞ
i21 ðtÞ
0.6
0.4
pout v2 i2
¼
pin
v1 i 1
ð8Þ
Substituting (5), (6) and (7) into (8) yields:
m¼
1 þ Za dk
dk40
1 þ Za1 dk
ð9Þ
It should be noted that the overall efficiency, m, is higher
than the TVT’s efficiency g, for all positive values of the
transfer ratio, dk.
For negative values of dk, the polarity of dv inverses,
which reverses the power flow direction through the 1: dk
lower TVT (Fig. 2). In this case (7) is replaced by:
v ðtÞ
v22 ðtÞ
¼ dK ðtÞg1 21
ð10Þ
i22 ðtÞ
i21 ðtÞ
Other than that, (5) and (6) are valid. Substituting (5), (6)
and (10) into (8) yields:
m¼
1 þ Za dk
Za dk 0
1 þ Z1a dk
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
ð11Þ
0.8
=0.7
=0.7
0.2
0
−1
0
1
2
k
a
3
4
0.7
−1
5
0
1
2
k
b
3
4
5
Fig. 4
a The overall efficiency against the TVT’s transfer ratio dk
b An expande view
Case 2: TVTs connected in parallel at the load side and in
series at power input port.
In this case the source and load are interchanged with
respect to case 1, which yields:
8
vin ¼ v2
>
>
>
>
vout ¼ v1
>
>
>
>
< iin ¼ i2
ð13Þ
iout ¼ i1
>
>
> dv ¼ v21
>
>
>
>
v ¼ v21 ¼ v1
>
: 11
i12 ¼ i22 ¼ i2
The overall power flow direction is now from right to left
(Fig. 2), hence:
Where I and g are defined in (3) and (4). The overall
efficiency, m, is defined as:
m¼
=0.8
=0.9
=0.8
being generated by a loss network applied in cascade with
the ideal TVT as is shown in Fig. 3b.
This loss model is applied to the lower TVT in the
configuration of Fig. 2. Since the upper, 1:1 TVT will
eventually be omitted, and its input and output ports will
connect directly, its efficiency is assumed to be 100%.
Case 1: TVTs connected in parallel at the power input
port and in series at the load side.
In this case the power source is applied at the part of the
parallel connected TVTs and the load is fed from the series
connected side of the TVTs:
8
vin ¼ v1
>
>
>v ¼ v
>
>
out
2
>
>
>
< iin ¼ i1
ð5Þ
iout ¼ i2
>
>
dv
¼
v
>
22
>
>
>
>
> v11 ¼ v21 ¼ v1
:
i12 ¼ i22 ¼ i2
0.9
m¼
pout v1 i1
¼
pin
v2 i2
ð14Þ
For positive values of the transfer ratio dk, the polarity of
i21 inverses which reverses the direction of the power flow
through the lower TVT, which yields:
v21 ðtÞ
v ðtÞ
¼ dK 1 ðtÞg 22
ð15Þ
i21 ðtÞ
i22 ðtÞ
Substitution of (6), (13) and (15) into (14) yields:
m¼
1 þ Z1a dk
1 þ Za dk
0 dk
ð16Þ
Which is greater than Z for all positive transfer ratios. For
negative values of dk the polarity of i21 inverses which
reverses the direction of the power flow through the lower
TVT, hence:
m¼
1 þ Za1 dk
1 þ Za dk
Z1a
dko0
Zþ1
ð17Þ
Generally the behaviour of m in both cases is similar: see a
comparison in Fig. 5, for a ¼ 0.7.
163
1
0.9
0.8
1.0
0.9
=0.9
=0.8
=0.7
0.8
0.7
increasing 0.7
case 1
0.6
case 2
0.5
cf
0.6
0.4
cf2
0.3
0.2
0.2
0.1
0.1
0
1
2
3
4
5
0
−1
k
Fig. 5
4
The overall efficiency in cases 1 and 2, a ¼ 0.7
Fig. 6
Power rating reduction
As shown in the preceeding section, power conversion
efficiency improvement (in a certain range of dk) is achieved
by the application of the proposed topology. Additionally,
it will be shown that under the proposed topology the
power rating of the TVTs is significantly reduced. In
practical implementations this reduction of power rating
should translate into volume, weight, and cost reductions.
Let us define a compactness factor, cf, as the ratio of the
system rated power when the dual TVT topology is
employed to that of a conventional, single TVT system
supplying the same load power.
pdualTVT
ð18Þ
cf ¼
psingleTVT
Improved compactness factor implies cfo1. To have a
notion of the cf behaviour, a naive assumption is made; that
the power conversion system’s size is proportional to the
power dissipated in this system [6], i.e.:
lossesdualTVT
ð19Þ
cf ’
lossessingleTVT
Thus:
cf ’
ð1=m 1Þ=pload
ð1=Z 1Þ=pload
ð20Þ
Substituting (9), (11), (16) and (17), yields the compactness
factors:
8
Za dk
>
>
dk40
<
1 þ Za dk
ð21Þ
cf1 ¼
Z1a dk
>
a
>
:
Z
dk
0
1 þ Za dk
8
Z1a dk
>
>
dk40
<
1 þ Z1a dk
cf2 ¼
ð22Þ
a
1a
Z dk
Z
>
>
:
dk
0
Zþ1
1 þ Za1 dk
Compactness factors are plotted in Fig. 6 for a ¼ 0.8 and
Z ¼ 0.8, 0.7 and 0.6.
5
DC-DC converters at a near-unity transfer ratio
Many DC applications involve voltage conversion at a
near-unity transfer ratio, for instance, the converters used in
the conversion of an automotive source (at about 10 to
15 V) to a high-quality power with low ripple content
164
cf1
0.4
0.3
0
−1
0.5
0
1
2
k
3
4
5
Compactness factors for a ¼ 0.8 and Z ¼ 0.8, 0.7 and 0.6
suitable for consumer electronics such as camcorders (which
typically requires 10 V 72%) or laptop computers (16 V)
may be viewed as near-unity transfer ratio TVTs. Other
examples include voltage conversion for digital loads such
as 5 V DC to 3.3 V DC. In a conventional power converter
configuration (see Fig. 7) all the load power is processed by
the converter, which must be rated accordingly.
Pconverter Pload
_ ∆v
ð23Þ
+
1:k(t )
+
+
vg
+
_
v1
_
Fig. 7
DC/DC
converter
v2
_
+
load
vload
_
Conventional DC/DC conversion
In the case in which the output voltage is not significantly
different from the input voltage the near-unity transfer ratio
TVT model applies.
Let us denote the voltage difference between the source
and the load voltages by Dv:
Dv ¼ vload vg
ð24Þ
The proposed approach may be applied only if isolation
between source and load is not required. In this case, we
suggest the generation of a voltage difference at one of the
converter ports rather than the generation of the load
voltage. This port will be connected in series with the load
and the source. Without loss of generality, let us assume
that the source and load voltages are positive as marked in
Fig. 7. Also, it will be assumed that a practical switched
mode realisation of the TVT can handle only unipolar
voltages at its input and output ports. In the configuration
proposed herein, the converter is connected so as to draw its
input power, p1, either from the source, from the load side
or from the voltage difference Dv. For each of which, it may
inject its output power, p2, at either one of the other two
point. This approach appears to result in six possible
topologies, however, the cases in which the source is applied
to one of the converter ports and the load to the other
implies a converter power throughput equal to that of the
load (which is the conventional configuration). Thus, four
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
possible topologies are left; depending on whether Dv is
generated at the converter input or output port and on
whether the second port is connected in parallel with either
the source or the load, see Fig. 8.
− v +
ig
vg
+
+
−
i load
p2
p1
v1
−
+
−
v2
+
1:k (t )
DC/DC
converter
load
v load
−
a
6
− v +
ig
vg
+
−
i load
p1
+
v2
p2 −
+
k (t ):1
+
v1
−
DC/DC
converter
load
v load
−
b
− v +
ig
+
vg
i load
p2 +
v2
−
−
k (t ):1
DC/DC
converter
+
+
v1
−
p1
load
v load
−
c
− v +
ig
+
vg
−
i load
p1
k (t ):1 +
DC/DC
v2
p2
converter −
−
v1
+
transformer topology (Fig. 2) with dko0, while Fig. 8d
arises from the same case with dko0. Thus, similar
advantages in terms of efficiency improvement and
compactness may be expected. Practical realisations of the
converter must comply with the voltage and current
polarities as denoted in Fig. 8. When the converter’s actual
realisation is an isolated one, its application in the proposed
topologies is straightforward. Non-isolated converters are
more difficult to apply since the proposed topologies imply
a common point between the converter input and output,
which must not violate the actual converter realisation. One
such example is shown in the following Section.
+
load
Experimental results
A second stage post regulator of a unity-power-factor
rectification system was chosen as the experimental
example. The proposed scheme, depicted in Fig. 9a,
employs two blocks, connected in series at the output
rather than cascaded as in a conventional two-stage
switched mode rectifier. The main stage is responsible for
current shaping and therefore it generates a large ripple at
its output [8]. This stage is rated to the total APFC’s power
throughput. The load is fed by the main stage in series with
a second block, which is solely responsible for output
regulation. The output of this block varies over a wide
range so as to cancel the output ripple of the main stage and
is rated only to the ripple power (less than 10% of the total
APFC’s power throughput), see Fig. 9b. Thus, although the
system is composed of two blocks, the total system’s size
and cost is not significantly larger than that of a single stage
scheme. However, the second block facilitates the tight,
wideband output regulation.
In the scheme depicted in Fig. 9a the post-regulator
(second stage) may be identified as a case 1 TVT
configuration with a positive transfer ratio (Fig. 8a). The
load, fed by the main stage in series with a second block,
sees very little ripple due to the ripple cancellation action of
v load
−
_
Fig. 8 Four possible topologies for the converters connected in an
autotransformer configuration
+
+
current
shaping
Cdc
AC/DC
Similar to (9), if the converter is viewed as a TVT, the
topology of Fig. 8a arises from case 1 of the twotransformer topology (Fig. 2) with dk40, while Fig. 8b
arises from the same case with dko0. Similarly, the
topology of Fig. 8c arises from case 2 of the twoIEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
−
+
ripple
cancellation
vac
The convention in this representation is that the converter
input is represented by the subscript ‘1’ and its output by a
‘2’. The direction of power flow is also marked. In all of
these topologies, only part of the source power is processed
by the converter, while the rest is transferred directly to the
load. The closer nload is to ng the smaller is this portion.
The converter’s rated-power reduction is achieved for all
of the topologies of Fig. 8. The topology shown in Fig. 8a
where the converter draws its input power from the source
and its output voltage appears in series with the load and
source is an example. The converters’ rating is reduced in
this topology in comparison to that of the conventional
conversion of Fig. 7 by a factor of:
p2
Dv
¼
ð25Þ
pload vload
v +
P2
iac
d
vdc−link
load v
load
_
+
P1
−
−
converter
control
a
v
Vload
Vdc−link
∆V
T/ 2
t
b
Fig. 9 APFC with active ripple cancellation
a The scheme
b The schematic waveforms
165
the second stage. The output of this block varies through a
wide range so as to cancel the main stage is output ripple
and is rated only to the ripple power (less than 10% of
the total APFC’s power throughput). Figure 9b shows
(schematically only) how the second stage generates a
ripple component, Dv opposite to that of the current
shaping stage (plus a small DC component). So, the load,
which sees the sum of Vdc-link and Dv, experiences a
considerably reduced ripple component. A 200 W unitypower-factor rectifier was build incorporating the proposed
scheme. It has been designed for a telecom voltage level of
48 V DC.
The pre-regulator stage has been implemented by a single
ended primary inductance (SEPIC) topology [8]. The details
of the current shaping pre-regulator are beyond of the scope
of the current discussion, however, it may be said that the
SEPIC presents several advantages over the conventionally
employed boost topology. In particular, a high output
voltage can be avoided, making this converter very suitable
for use as a power factor pre-regulator for telecom voltage
levels (which are lower than the input), [12]. The postregulator is the focus of this experiment (see Fig. 10). It
extracts power in parallel with the DC link capacitor Cdc
and outputs power across C2. The polarities are such that v1
and v2 are positive. Thus:
vload ¼ v1 þ v2
Fig. 11 Pre-regulator input voltage (channel 1, 50 V/div) and
current (channel 2, 1 A/div)
ð26Þ
Relating the experimental circuit to the schematic topologies
(Fig. 8) it can be seen this topology is actually similar to the
one in Fig. 8a, i.e. power is absorbed in parallel and injected
in series. v1 and v2 represent the post-regulator input and
output voltages respectively, in both Fig. 8 and Fig. 10.
current shaping
pre-regulator
ripple cancellation
post-regulator
2
ac
1
C2
L1 L2
load load
Cdc
Fig. 12
Fig. 10 Experimental setup: L1 ¼ L2 ¼ 20 mH, Cdc ¼ 940 mF
(100 V), C2 ¼ 167 mF (16 V), switching frequency 160 kHz
(i) The pre-regulator output voltage (channel 1, 10 V/div)
(ii) the load voltage (channel 2, 10 V/div). Both traces have the same
reference ground and a time base of 4 ms/div
The PFC pre-regulator input current and voltage are
shown in Fig. 11. The quality of the rectification is beyond
the scope of this experiment and harmonic analysis was not
performed. Yet it can be seen that the current shape tracks
the voltage shape pretty well, yielding a unity-power-factor
rectification.
The small active ripple cancellation stage is based on a
variation of the flyback topology, as depicted in Fig. 10.
The DC-link capacitor voltage is the pre-regulators output
voltage and the second stage input voltage, v1. As it can be
seen, the ripple cancellation stage output voltage v2 connects
in series with the input voltage v1, to form the load voltage.
Exactly as in the configuration depicted in Fig. 8a. A
tapped-inductor is used in order to avoid operation at very
low duty ratios. The pre-regulator output voltage v1, and
the load voltage vload, are shown in Fig. 12. It can be seen
that the circuit operates as predicted (comparing to Fig. 9b).
The ripple cancellation stage output voltage, v2 had to vary
in the wide range of 1.2–5.7 V in order to compensate for
the intentionally exaggerated ripple across the DC-link
capacitor. Therefore, its average efficiency was quite low
(about 60% on average). However, since it processed only
about 3% of the load power, the second stage losses were
less than 2% of the total power and the overall efficiency
from AC mains to the regulated DC load reached up to
92% at nominal load. The efficiency exceeds 90% in the
range of 160–200 W load power.
The ripple decreased from 4.4 V p-p on the DC-link
capacitor to less than 30 mV p-p across the load. In fact
almost all of the low frequency ripple has been removed and
the reminding 30 mV is mainly at the switching frequency
(160 kHz). This ripple can be easily removed by a small
filter. The ripples before and after the active ripple
cancellation stage are shown in Fig. 13.
The power MOSFET in the second stage is rated at 5 A,
20 V (Rdson ¼ 33 mO), in a SOT 23 package whereas the
switching device in the pre-regulator was an IRF720 power
MOSFET (400 V, 10 A, 55 mO) in a TO-220 package, the
size difference is evident from Fig. 14. Alhough a power
MOSFET with a lower rated current could be used in the
pre-regulator, it would not have decreased the package size
since it must withstand a high drain-source breakdown
voltage.
The SEPIC pre-regulator stage consists of two inductors
La with an inductance of 600 mH at the AC side and
166
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
with a value of 20 mH, and a saturation current of 4 A. The
difference in size can be seen in Fig. 15 where L1&L2 is the
post-regulator taped inductor.
Other components show a similar size reduction, for
instance Cdc would have to be very big and bulky if it is to
accomplish the same ripple across the load without the
second post-regulator stage.
7
Fig. 13
(i) Ripple content in the post-regulator input voltage
(ii) Ripple content in the load voltage, Note the vertical gain is 1 V/
dov, the time base is 4 ms/div, both with the same reference grand
Fig. 14
The difference in size of the active switching devices
Lb with an inductance of 400 mH at the pre-regulator
output. These inductors were designed for a 1.5 A
saturation current. The taped post-regulator inductor (L1,
and L2 in Fig. 10) was designed so that L1 was equal to L2
Fig. 15
Discussion
A rather efficient configuration incorporating TVTs was
presented, analysed and experimentally implemented. Four
basic topologies were derived in which switched mode
converters (or other types of TVT) may be applied.
Expressions for the overall energy conversion efficiency
and relative power density have been derived which indicate
that a substantial improvement in these figures of merit can
be obtained, especially when a near-unity transfer ratio is
needed. One of the proposed topologies was incorporated
as a ripple cancellation stage in a unity-power-factor
switched-mode rectifier. In addition to the high efficiency
of up to 98% (a 92% overall efficiency) and reduced power
rating, this stage provides an excellent ripple cancellation of
43 dB. The effective ripple cancellation results from the
small values of the capacitance and the inductance in the
post-regulator stage, which facilitates a considerably
improved dynamic response of this stage. Although the
efficiency varies with the load, an overall efficiency above
90% is maintained in the range of 160 – 200 W load power.
Further research will be conducted in order to determine
the improvement of the dynamics quantitatively and to find
other transformed and non-transformed topologies.
Also an optimisation procedure is being developed with
regard to the optimal topologies and optimal range of
operation. For instance, in the experimental example, the
post-regulator’s efficiency would increase if it were to
generate a higher voltage at its output. However, this would
require more power. Thus there must be a point of
maximum overall power efficiency. Similar considerations
apply regarding power density. These issues should be
approached employing detailed loss models for the
converters.
The difference in size of the inductors. La and Lb belonging to the pre-regulator stage and L1&L2 belonging to the pre-regulator stage
IEE Proc.-Electr. Power Appl., Vol. 151, No. 2, March 2004
167
8
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