a
FEATURES
4-Quadrant Multiplication
Low Cost 8-Lead Package
Complete—No External Components Required
Laser-Trimmed Accuracy and Stability
Total Error within 2% of FS
Differential High Impedance X and Y Inputs
High Impedance Unity-Gain Summing Input
Laser-Trimmed 10 V Scaling Reference
APPLICATIONS
Multiplication, Division, Squaring
Modulation/Demodulation, Phase Detection
Voltage Controlled Amplifiers/Attenuators/Filters
Low Cost
Analog Multiplier
AD633
CONNECTION DIAGRAMS
8-Lead Plastic DIP (N) Package
X1
1
X2
2
Y1
3
Y2
4
1
A
1
10V
1
8
+VS
7
W
6
Z
5
–VS
AD633JN/AD633AN
8-Lead Plastic SOIC (RN-8) Package
PRODUCT DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y
inputs and a high impedance summing input (Z). The low
impedance output voltage is a nominal 10 V full scale provided
by a buried Zener. The AD633 is the first product to offer these
features in modestly priced 8-lead plastic DIP and SOIC packages.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100 µV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, 20 V/µs slew rate, and the ability to drive capacitive loads
make the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
Y1
1
Y2
2
–VS
3
Z
4
1
1
1
10V
A
8
X2
7
X1
6
+VS
5
W
AD633JR/AD633AR
W=
(X1 – X2) (Y1 – Y2)
10V
+Z
PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered in
low cost 8-lead plastic packages. The result is a product that
is cost effective and easy to apply.
The AD633’s versatility is not compromised by its simplicity.
The Z-input provides access to the output buffer amplifier,
enabling the user to sum the outputs of two or more multipliers,
increase the multiplier gain, convert the output voltage to a
current, and configure a variety of applications.
2. No external components or expensive user calibration are
required to apply the AD633.
The AD633 is available in an 8-lead plastic DIP package (N)
and 8-lead SOIC (R). It is specified to operate over the 0°C to
70°C commercial temperature range (J Grade) or the –40°C to
+85°C industrial temperature range (A Grade).
4. High (10 MΩ) input resistances make signal source loading
negligible.
3. Monolithic construction and laser calibration make the
device stable and reliable.
5. Power supply voltages can range from ± 8 V to ± 18 V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD633–SPECIFICATIONS (T = 25ⴗC, V = ⴞ15 V, R ≥ 2 k⍀)
A
S
L
Model
AD633J, AD633A
W =
TRANSFER FUNCTION
Parameter
MULTIPLIER PERFORMANCE
Total Error
TMIN to TMAX
Scale Voltage Error
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage
DYNAMICS
Small Signal BW
Slew Rate
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise
OUTPUT
Output Voltage Swing
Short Circuit Current
INPUT AMPLIFIERS
Signal Voltage Range
Offset Voltage X, Y
CMRR X, Y
Bias Current X, Y, Z
Differential Resistance
POWER SUPPLY
Supply Voltage
Rated Performance
Operating Range
Supply Current
Conditions
(X
1
Min
–10 V ≤ X, Y ≤ +10 V
SF = 10.00 V Nominal
VS = ± 14 V to ± 16 V
X = ± 10 V, Y = +10 V
Y = ± 10 V, X = +10 V
Y Nulled, X = ± 10 V
X Nulled, Y = ± 10 V
)(
− X 2 Y1 − Y2
10 V
)+Z
Typ
Max
Unit
±1
±3
± 0.25%
± 0.01
± 0.4
± 0.1
± 0.3
± 0.1
±5
ⴞ2
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
mV
ⴞ1
ⴞ0.4
ⴞ1
ⴞ0.4
ⴞ50
VO = 0.1 V rms
VO = 20 V p-p
∆ VO = 20 V
1
20
2
MHz
V/µs
µs
f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz
0.8
1
90
µV/√Hz
mV rms
µV rms
ⴞ11
RL = 0 Ω
30
Differential
Common Mode
ⴞ10
ⴞ10
VCM = ± 10 V, f = 50 Hz
60
ⴞ8
Quiescent
±5
80
0.8
10
± 15
4
40
ⴞ30
2.0
ⴞ18
6
V
mA
V
V
mV
dB
µA
MΩ
V
V
mA
Specifications shown in boldface are tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltages3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD633J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD633A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied.
2
8-Lead Plastic DIP Package: θJA = 90°C/W; 8-Lead Small Outline Package: θJA =
155°C/W.
3
For supply voltages less than ±18 V, the absolute maximum input voltage is equal to
the supply voltage.
–2–
Model
Temperature
Range
Package
Description
Package
Option
AD633AN
AD633AR
AD633AR-REEL
AD633AR-REEL7
AD633JN
AD633JR
AD633JR-REEL
AD633JR-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Plastic DIP
Plastic SOIC
13" Tape and Reel
7" Tape and Reel
Plastic DIP
Plastic SOIC
13" Tape and Reel
7" Tape and Reel
N-8
RN-8
RN-8
RN-8
N-8
RN-8
RN-8
RN-8
REV. E
Typical Performance Characteristics– AD633
100
0dB = 0.1V rms, RL = 2k⍀
90
0
80
CL = 0dB
CMRR – dB
OUTPUT RESPONSE – dB
CL = 1000pF
–10
–20
TYPICAL
FOR X,Y
INPUTS
70
60
50
40
NORMAL
CONNECTION
30
–30
10k
1M
100k
FREQUENCY – Hz
20
100
10M
NOISE SPECTRAL DENSITY – ␮V/ Hz
BIAS CURRENT – nA
1M
1.5
600
500
400
300
–40
–20
0
20
40
60
80
100
120
1
0.5
0
10
140
100
TEMPERATURE – ⴗC
1k
FREQUENCY – Hz
100k
10k
TPC 5. Noise Spectral Density vs. Frequency
TPC 2. Input Bias Current vs. Temperature (X, Y, or
Z Inputs)
14
1000
Y-FEEDTHROUGH
12
OUTPUT, RL
P-P FEEDTHROUGH – mV
PEAK POSITIVE OR NEGATIVE SIGNAL – V
100k
TPC 4. CMRR vs. Frequency
700
2k⍀
10
ALL INPUTS
8
100
X-FEEDTHROUGH
10
1
6
4
0
8
10
12
14
16
18
PEAK POSITIVE OR NEGATIVE SUPPLY – V
20
10
100
1k
10k
100k
FREQUENCY – Hz
1M
TPC 6. AC Feedthrough vs. Frequency
TPC 3. Input and Output Signal Ranges vs. Supply
Voltages
REV. E
10k
FREQUENCY – Hz
TPC 1. Frequency Response
200
–60
1k
–3–
10M
AD633
FUNCTIONAL DESCRIPTION
APPLICATIONS
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied
to the output amplifier. The amplifier summing node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog computational functions.
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-lead DIP), which differs from the AD633JR pinout
(8-lead SOIC).
X1
1
X2
2
Y1
Y2
1
A
7
W
6
1
4
+VS
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity while achieving some desired
output polarity) or both may be driven.
+15V
0.1␮F
X
INPUT
1
10V
3
8
Multiplier Connections
AD633
X1
+VS 8
2
X2
W 7
W=
–VS
3
Y1
Z 6
4
Y2
–VS 5
(X1 – X2) (Y1 – Y2)
10V
OPTIONAL SUMMING
INPUT, Z
AD633JN
Z
Y
INPUT
5
1
+Z
0.1␮F
–15V
Figure 1. Functional Block Diagram (AD633JN
Pinout Shown)
Figure 3. Basic Multiplier Connections
Squaring and Frequency Doubling
Inspection of the block diagram shows the overall transfer function to be:
W =
(X
1
)(
− X 2 Y1 − Y2
10 V
)+Z
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E2/10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may be
reversed by interchanging the X or Y inputs. The Z input may
be used to add a further signal to the output.
(1)
ERROR SOURCES
+15V
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale factor
errors (gain error) and an irreducible nonlinearity component in
the multiplying core. The X and Y nonlinearities are typically
0.4% and 0.1% of full scale, respectively. Scale factor error is
typically 0.25% of full scale. The high impedance Z input should
always be referenced to the ground point of the driven system,
particularly if this is remote. Likewise, the differential X and Y
inputs should be referenced to their respective grounds to realize
the full accuracy of the AD633.
0.1␮F
E
1
X1
+VS 8
2
X2
W 7
W=
AD633JN
3
Y1
Z 6
4
Y2
–VS 5
E2
10V
0.1␮F
–15V
Figure 4. Connections for Squaring
When the input is a sine wave E sin ωt, this squarer behaves as a
frequency doubler, since
+VS
(E sin ωt )
2
50k⍀
300k⍀
1k⍀
ⴞ50mV
TO APPROPRIATE
INPUT TERMINAL
(e.g., X2, X2, Z)
10 V
=
E2
1 − cos 2 ωt
20 V
(
)
(2)
Equation 2 shows a dc term at the output that will vary strongly
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 5, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity:
–VS
Figure 2. Optional Offset Trim Configuration
cos θ sin θ =
–4–
(
)
1
sin 2 θ
2
(3)
REV. E
AD633
R
10k⍀
+15V
0.1␮F
E
1
R
2
X2
3
Y1
W 7
AD633JN
C
4
+15V
+VS 8
X1
Z 6
R1
1k⍀
10V
R
10k⍀
AD711
0.1␮F
E
2
E
(sin ω ot + 45°)
2
W ' = −(10V )
Y1
Z 6
4
Y2
–VS 5
0.1␮F
–15V
E
EX
(6)
1
X1
+VS 8
2
X2
W 7
Y
INPUT
R1
3
Y1
Z
4
Y2
–VS 5
6
0.1␮F
7
+VS 8
2
X2
W 7
3
Y1
Z 6
4
Y2
–VS 5
R2
S
The AD633’s voltage output can be converted to a current
output by the addition of a resistor R between the AD633’s W
and Z pins as shown in Figure 9. This arrangement forms
0.1␮F
+15V
–15V
–15V
W=
1N4148
+S
Current Output
AD633JN
1N4148
R1
100k⍀
In some instances, it may be desirable to use a scaling voltage
other than 10 V. The connections shown in Figure 8 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
may be used to add an additional signal to the output or it may
be grounded.
+15V
X1
(R1 + R2)
Figure 8. Connections for Variable Scale Factor
for the condition E < 0.
1
10V
1k⍀ R1, R2
Variable Scale Factor
(5)
+15V
0.1␮F
(X1 – X2) (Y1 – Y2)
0.1␮F
–15V
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feedback loop of an op amp. Figure 6 shows how to implement a
square rooter with the transfer function
(10 E ) V
W=
AD633JN
Generating Inverse Functions
(
10E
0.1␮F
)V
X
INPUT
1
X1
+VS 8
2
X2
W 7
R
AD633JN
Figure 6. Connections for Square Rooting
Y
INPUT
3
Y1
Z 6
4
Y2
–VS 5
IO =
1
R
(X1 – X2) (Y1 – Y2)
1k⍀
10V
R
100k⍀
0.1␮F
–15V
Figure 9. Current Output Connections
REV. E
E
EX
0.1␮F
X
INPUT
The amplitude of the output is only a weak function of frequency:
the output amplitude will be 0.5% too low at ω = 0.9 ωo, and
ω o = 1.1 ω o.
4 0.1␮F
W 7
+15V
which has no dc component. Resistors R1 and R2 are included to
restore the output amplitude to 10 V for an input amplitude of 10 V.
E
X2
3
Figure 7. Connections for Division
(4)
E
=
(sin 2 ω ot )
(40V )
OP27
2
Likewise, Figure 7 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is
(sin ω ot − 45°)
2
W =
+VS 8
W' = –10V
At ωo = 1/CR, the X input leads the input signal by 45° (and is
attenuated by √2), and the Y input lags the X input by 45° (and
is also attenuated by √2). Since the X and Y inputs are 90° out of
phase, the response of the circuit will be (satisfying Equation 3):
1
X1
–15V
Figure 5. ”Bounceless” Frequency Doubler
(10V )
1
AD633JN
0.1␮F
–15V
W =
0.1␮F
EX
E
R2
3k⍀
–VS 5
Y2
W=
+15V
0.1␮F
E2
–5–
AD633
dB
the basis of voltage controlled integrators and oscillators as will
be shown later in this Applications section. The transfer function of this circuit has the form
IO =
1 (X
1
R
)(
− X 2 Y1 − Y2
f2 f1
0.1␮F
)
CONTROL
INPUT EC
(7)
10 V
SIGNAL
INPUT ES
Linear Amplitude Modulator
The AD633 can be used as a linear amplitude modulator with
no external components. Figure 10 shows the circuit. The carrier and modulation inputs to the AD633 are multiplied to
produce a double-sideband signal. The carrier signal is fed
forward to the AD633’s Z input where it is summed with the
double-sideband signal to produce a double-sideband with carrier output.
1
X1
+VS 8
2
X2
W 7
Y1
Z 6
Y2
–VS 5
C
dB
f1 f2
0.1␮F
CONTROL
INPUT EC
SIGNAL
INPUT ES
1
X1
+VS 8
2
X2
W 7
0
f
OUTPUTB
+6dB/OCTAVE
OUTPUTA
OUTPUT B
AD633JN
C
OUTPUT A
6
3
Y1
Z
4
Y2
–VS 5
R
0.1␮F
(8)
–15V
and the rolloff is 6 dB per octave. This output, which is at a
high impedance point, may need to be buffered.
Figure 12. Voltage Controlled High-Pass Filter
Voltage Controlled Quadrature Oscillator
The voltage at output B, the direct output of the AD633, has
same response up to frequency f1, the natural breakpoint of RC
filter,
Figure 13 shows two multipliers being used to form integrators
with controllable time constants in second order differential
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied to
the X inputs of the “next” AD633. The frequency control input,
EC, connected to the Y inputs, varies the integrator gains with a
calibration of 100 Hz/V. The accuracy is limited by the Y input
offsets. The practical tuning range of this circuit is 100:1. C2
(proportional to C1 and C3), R3, and R4 provide regenerative
feedback to start and maintain oscillation. The diode bridge, D1
through D4 (1N914s), and Zener diode D5 provide economical
temperature stabilization and amplitude stabilization at ± 8.5 V
by degenerative damping. The out-put from the second
integrator (10 V sin ωt) has the lowest distortion.
1
(9)
2 π RC
then levels off to a constant attenuation of f1/f2 = EC/10.
+15V
0.1␮F
CARRIER
INPUT
ECsin ␻t
10
1
=
W2 ECRC
Figure 11. Voltage Controlled Low-Pass Filter
EC
MODULATION
INPUT
ⴞEM
T2 =
–15V
Figure 11 shows a single multiplier used to build a voltage controlled low-pass filter. The voltage at output A is a result of
filtering, ES. The break frequency is modulated by EC, the control input. The break frequency, f2, equals
f1 =
T1 = 1 = RC
W1
0.1␮F
+15V
(20 V )π RC
1 + T1P
1 + T2P
1
OUTPUT A =
1 + T2P
OUTPUT B =
R
4
OUTPUTB
OUTPUTA
Voltage Controlled Low-Pass and High-Pass Filters
f2 =
–6dB/OCTAVE
AD633JN
3
f
0
+15V
1
X1
+VS 8
2
X2
W 7
W = 1+
AD633JN
3
Y1
Z 6
4
Y2
–VS 5
EM
10V
ECsin ␻t
0.1␮F
AGC AMPLIFIERS
–15V
Figure 14 shows an AGC circuit that uses an rms-to-dc converter to measure the amplitude of the output waveform. The
AD633 and A1, 1/2 of an AD712 dual op amp, form a voltage
controlled amplifier. The rms-to-dc converter, an AD736, measures the rms value of the output signal. Its output drives A2,
an integrator/comparator whose output controls the gain of the
voltage controlled amplifier. The 1N4148 diode prevents the
output of A2 from going negative. R8, a 50 kΩ variable resistor,
sets the circuit’s output level. Feedback around the loop forces
the voltages at the inverting and noninverting inputs of A2 to be
equal, thus the AGC.
Figure 10. Linear Amplitude Modulator
For example, if R = 8 kΩ and C = 0.002 µF, then output A has
a pole at frequencies from 100 Hz to 10 kHz for EC ranging
from 100 mV to 10 V. Output B has an additional zero at 10 kHz
(and can be loaded because it is the multiplier’s low impedance
output). The circuit can be changed to a high-pass filter Z interchanging the resistor and capacitor as shown in Figure 12.
–6–
REV. E
AD633
D5
1N5236
D1
1N914
D3
1N914
D2
1N914
D4
1N914
(10V) cos ␻t
+15V
+15V
0.1␮F
R1
1k⍀
1
X1
+VS 8
2
X2
W 7
3
Y1
0.1␮F
R2
16k⍀
AD633JN
EC
4
Z 6
X1
+VS 8
2
X2
W 7
3
Y1
Z 6
4
Y2
–VS 5
0.1␮F
R3
330k⍀
0.1␮F
–15V
–15V
Figure 13. Voltage Controlled Quadrature Oscillator
R2
1k⍀
R3
10k⍀
R4
10k⍀
AGC THRESHOLD
ADJUSTMENT
+15V
+15V
0.1␮F
C1
1␮F
0.1␮F
1
X1
+VS 8
2
X2
W 7
3
Y1
Z 6
4
Y2
–VS 5
1/2
AD712
1 CC COMMON 8
0.1␮F
C2
0.02␮F
R9
10k⍀
0.1␮F
AD736
0.1␮F
3 CF OUTPUT 6
4 –VS
R10
10k⍀
CAV 5
–15V
C4
33␮F
A2
1N4148
R6
1k⍀
+15V
+VS 7
2 VIN
–15V
C3
0.2␮F
EOUT
R5
10k⍀
A1
AD633JN
E
1/2
AD712
+15V
OUTPUT
R8
50k⍀ LEVEL
ADJUST
0.1␮F
–15V
Figure 14. Connections for Use in Automatic Gain Control Circuit
REV. E
–7–
R4
16k⍀
(10V) sin ␻t
R5
16k⍀
EC
f=
kHz
10V
C3
0.1␮F
AD633JN
0.1␮F
–VS 5
Y2
1
C2
0.01␮F
AD633
OUTLINE DIMENSIONS
8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
C00786–0–10/02(E)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
PRINTED IN U.S.A.
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
10/02—Data Sheet changed from REV. D to REV. E.
Edits to title of 8-Lead Plastic SOIC Package (RN-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. E
®
OPA671
OPA
671
Wide Bandwidth, Fast Settling
Difet ® OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
● HIGH GAIN-BANDWIDTH: 35MHz
The OPA671 is a FET-input monolithic operational
amplifier featuring wide bandwidth and fast settling
time. Fabricated using Burr-Brown’s Difet, complementary bipolar process, it provides an excellent combination of high speed, accuracy, and high output
current.
● LOW INPUT NOISE: 10nV/√Hz
● HIGH SLEW RATE: 100V/µs
● FAST SETTLING: 240ns to 0.01%
● FET INPUT: IB = 50pA max
● HIGH OUTPUT CURRENT: 50mA
● WIDE SUPPLY RANGE: VS = ±4.5 to ±18V
APPLICATIONS
The OPA671 is versatile, operating from ±4.5V to
±18V power supplies. It can deliver ±10V signals into
a 200Ω load at slew rates of 100V/µs. OPA671’s Difet
input provides input bias current thousands of times
lower than bipolar-input wideband op amps.
The OPA671 is internally compensated to be unity-gain
stable, allowing use in the widest range of applications.
● HIGH-SPEED DATA ACQUISITION
● OPTOELECTRONICS
● TRANSIMPEDANCE AMPLIFIER
The OPA671 is available in an 8-pin plastic DIP, rated
for the industrial temperature range.
● LINE DRIVER
● CCD BUFFER AMPLIFIER
V+
7
Trim
Trim
1
5
+In
–In
3
2
VO
6
4
V–
Difet® Burr-Brown Corporation
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1991 Burr-Brown Corporation
PDS-1120D
Printed in U.S.A. October, 1993
SPECIFICATIONS
At TA = +25°C, VS = ±15V, unless otherwise noted.
OPA671AP
PARAMETER
CONDITION
OFFSET VOLTAGE
Input Offset Voltage
Average Drift
Power Supply Rejection
INPUT BIAS CURRENT(1)
Input Bias Current
Input Offset Current
VS = ±4.5 to ±16.5V
MIN
TYP
MAX
UNITS
±5
72
±0.5
±10
94
mV
µV/°C
dB
5
2
50
pA
pA
VCM = 0V
VCM = 0V
NOISE
Input Voltage Noise
Noise Density, f = 100Hz
f = 1kHz
f = 10kHz
f = 100kHz
Voltage Noise, BW = 10Hz to 1MHz
Input Bias Current Noise
Current Noise Density, f = 10Hz to 1MHz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
±12
74
VCM = ±10V
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time
0.01%
0.1%
1%
Total Harmonic Distortion
OUTPUT
Voltage Output
Current Output
Short Circuit Current
Output Resistance, Open-Loop
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specification
Operating
Storage
Thermal Resistance, θJA
VO = ±10V, RL = 1kΩ
VO = ±10V, RL = 200Ω
74
G = –1, 10V Step
G = –1, 10V Step
G = –1, 10V Step
G = –1, 10V Step
G = 1, f = 100kHz
VO = 3V, RL = 200Ω
±10.5
RL = 200Ω
VO = ±10V
DC
±4.5
VS = ±15V
24
15
12
10
60
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
2
fA/√Hz
±13
92
V
dB
1012 || 4.5
1012 || 6
Ω || pF
Ω || pF
80
78
dB
dB
35
107
240
150
85
0.0006
MHz
V/µs
ns
ns
ns
%
±11.5
50
–90/+105
20
V
mA
mA
Ω
±15
±14.8
–25
–40
–40
Junction to Ambient
±18
±17
+85
+100
+125
100
V
V
mA
°C
°C
°C
°C/W
NOTE: (1) Tested without warm-up at TJ = TA = 25°C.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
OPA671
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
PIN CONFIGURATION
Top View
DIP
VOS Trim
1
8
NC
–In
2
7
V+
+In
3
6
VO
V–
4
5
VOS Trim
An integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published
specifications.
NC = No Internal Connection
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
Power Supply Voltage ........................................................................ ±18V
Input Voltage ............................................................. (V+) +1V to (V–) –1V
Operating Temperature ................................................... –40°C to +100°C
Storage Temperature ...................................................... –40°C to +125°C
Output Short-Circuit to Ground ............................................................ 15s
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA671AP
8-Pin Plastic DIP
006
TEMPERATURE
RANGE
–25°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
OPA671
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
90
1k
0
–45
Phase
Phase (°)
Gain (dB)
60
–90
50
40
Gain
30
–135
20
–180
10
Voltage Noise (nV/ Hz)
80
70
0
–10
10
0
1k
100k
10k
1M
10M
1
100M
10k
1k
100k
1M
Frequency (Hz)
GAIN-BANDWIDTH PRODUCT AND
SLEW RATE vs TEMPERATURE
POWER SUPPLY REJECTION AND
COMMON-MODE REJECTION vs TEMPERATURE
Slew Rate (V/µs)
110
40
SR
105
35
GBW
100
PSR
90
CMR
100
30
10M
110
PSR & CMR (dB)
115
80
25
–25
25
0
50
75
–25
100
Temperature (°C)
0
25
50
75
100
Temperature (°C)
OPEN-LOOP GAIN vs LOAD RESISTANCE
OPEN-LOOP GAIN vs TEMPERATURE
90
Open-Loop Gain (dB)
90
Open-Loop Gain (dB)
100
10
Frequency (Hz)
45
Gain-Bandwidth Product (MHz)
100
80
RL = 200Ω
70
80
70
60
50
60
–25
0
25
50
75
20
100
®
OPA671
100
200
Load Resistance (Ω)
Temperature (°C)
4
1k
2k
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
POWER SUPPLY CURRENT vs TEMPERATURE
120
Short-Circuit Current (mA)
Power Supply Current (mA)
16.0
15.5
15.0
14.5
110
ISC+
100
90
ISC –
80
70
14.0
60
–25
25
0
75
50
100
–25
75
50
Temperature (°C)
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs JUNCTION TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
1000
100
0.001
100
THD + N (%)
Input Bias And Offset Current (pA)
25
0
Temperature (°C)
IB
10
G=1
0.0004
G = 10
IOS
1
RL = 200Ω
0
–25
0.0001
0
25
75
50
100
10
125
Junction Temperature (°C)
100
1k
10k
100k
Frequency (Hz)
MAX OUTPUT VOLTAGE SWING vs FREQUENCY
Max Output Voltage Swing (Vp-p)
30
20
10
0
100k
1M
10M
100M
Frequency (Hz)
®
5
OPA671
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
G = +1 LARGE SIGNAL RESPONSE
G = +1 SMALL SIGNAL RESPONSE
G = –1 LARGE SIGNAL RESPONSE
G = –1 SMALL SIGNAL RESPONSE
®
OPA671
6
CIRCUIT LAYOUT
(a)
With any high-speed, wide-bandwidth circuitry, careful circuit
layout will ensure best performance. Make short, direct circuit
interconnections and avoid stray wiring capacitance—especially at the inverting input pin. A component-side ground plane
will help ensure low ground impedance. Do not place the
ground plane under or near the inputs and feedback network.
The power supply connections should be bypassed with good
high-frequency capacitors positioned close to the op amp pins.
In most cases, both a 1µF solid tantalum capacitor and a 0.1µF
ceramic capacitor are required on each supply. The OPA671
can deliver peak load currents up to 100mA. Even if steadystate load currents are lower, signal transients may demand
large current transients from the power supplies. It is the power
supply bypass capacitors which must supply these current
transients. Larger bypass capacitors such as 4.7µF solid tantalum capacitors may improve dynamic performance in some
applications.
47kΩ
VO
VI
G=1
(b)
1kΩ
CL
100pF
250pF
1kΩ
CC
CL
100pF
RC
10pF 20Ω
1000pF 47pF 20Ω
CC
RC
VO
VI
CL
G = –1
1kΩ
(c)
1kΩ
330Ω
RC
VO
100pF
VI
OFFSET ADJUSTMENT
CL ≤ 100pF
G = –1
See application bulletin AB-028 for
details on circuits for driving capacitive loads.
Many applications require no external offset voltage adjustment. Figure 1 shows an optional circuit for trimming the offset
voltage. Do not use this offset voltage adjustment to correct for
offsets produced in other circuitry since this can introduce large
offset voltage temperature drift.
FIGURE 2. Compensation Circuits for Capacitive Loads.
assure that the maximum junction temperature is not exceeded.
The OPA671 may be operated at reduced power supply voltage
to minimize power dissipation.
V+
10kΩ
FIGURE 1. Optional Offset Voltage Trim Circuit.
OUTPUT CURRENT LIMIT
Output current is limited by internal circuitry to approximately
90mA at 25°C. The short-circuit limit current decreases with
increasing junction temperature as shown in the typical curves.
The current limit will protect the device from inadvertent shortcircuits to ground. The internal power dissipation under this
condition, however, is quite high so short-circuits should be
avoided.
CAPACITIVE LOADS
INPUT BIAS CURRENT
The OPA671 is internally compensated to be unity-gain stable
with minimal capacitive load. The combination of low closedloop gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Load capacitance
reacts with the op amp’s open-loop output resistance to form an
additional pole in the feedback loop. With wideband op amps,
load capacitance as low as 50pF can introduce enough phase
shift to degrade dynamic performance. Figure 2 shows circuits
which preserve phase margin with capacitive load. Request
Application Bulletin AB-028 for details on various compensation circuits and analysis techniques.
The OPA671 is fabricated with Burr-Brown’s dielectrically
isolated Difet process, giving it extremely low input bias
current. As with other FET-input amplifiers, input bias current
approximately doubles with every 10°C increase in junction
temperature. Input bias current can be minimized by soldering
the device to the circuit board to provided best heat dissipation.
Reduced power supply voltage will also minimize input bias
current by reducing internal power dissipation.
5kΩ to 50kΩ
Potentiometer
(10kΩ preferred)
7
2
3
1
5
OPA671
6
4
V–
DEMONSTRATION BOARD
The OPA671 may be evaluated using a high frequency PC
board developed for the OPA65x op amp family. This board
may be ordered from your local Burr-Brown distribution as part
# DEM-OPA65xP. It comes partially assembled but does not
include the amplifier. Since this board was intended for ±5V
amplifier, verify that any electrolytic capacitors loaded on the
board can support the higher supply voltages possible with the
OPA671.
POWER DISSIPATION
High output current can cause large internal power dissipation
in the OPA671. Copper leadframe construction improves heat
dissipation compared to conventional plastic packages. To
achieve best heat dissipation, solder the device directly to the
circuit board and use wide circuit board traces close to the
device pins. Limit the ambient temperature, load and signal to
®
7
OPA671