High Speed On-Chip Interconnects: Trade offs in Passive Termination
Raj Parihar
University of Rochester, NY, USA
parihar@ece.rochester.edu
Abstract
In this paper, several passive termination schemes
for high speed on-chip serial interconnect and trade
offs associated with them are presented. Signal
declension due to reflections in high speed
transmission lines (TL) can be minimized by
introducing adequate termination circuit. Primary
trade off involved in terminated TL is with the
optimization of bandwidth – power consumption.
Secondary trades off i.e. area – bandwidth, noise
margin – power consumption are also discussed in
brief. Few guidelines are proposed which are useful in
achieving contentious objectives i.e. low latency, high
bandwidth, and low power consumption in on-chip
high speed communication. Basis of qualitative and
quantitative analysis presented here is the state-of-theart literature of recent research. In most of the cases, it
is assumed that reflections occur mainly due to
mismatching at receiver end and proper termination is
provided at transmitter end.
Keywords:
Transmission
Line,
Passive
Termination, On-Chip Interconnects, High Speed
links.
1. Introduction
Due to various advantages of serial links over
parallel buses they are preferred in high speed on-chip
communication. Few other obvious advantages are
lesser area on chip, least crosstalk noise, and reduced
design complexity [1]. However, on-chip interconnect
delay doesn’t scale down very well as compare to gate
delays with reduced feature size. This is one of the
biggest bottleneck in designing low latency on-chip
interconnects. The magnitude of problem is enormous
and often it is termed as “interconnect wall” problem
[3]. In order to overcome on the interconnect problem
designers are forced to devise high speed signaling
medium for on-chip application. Few potential
solutions of high speed link are optical link,
waveguides, fat wires etc. These solutions fall into two
categories – some are easy to implement but not fast
enough, while others are quite fast but integration is
not easy. On contrary to this, transmission lines can be
easily implemented as on-chip thick traces – similar to
fat RC wires.
One of the disadvantages of serial communication
is that serialized data increases the switching activity.
This increased switching activity on signal line results
into increased power consumption. Keeping this in
mind, the “interconnect wall” problem also forces
designer to care about power consumption in addition
to low latency and high bandwidth. Due to the fact that
RC wires are not fast enough as compare to gates for
same technology node so they are on the verge of
becoming obsolete. Transmission lines on the other
hand – inherently fast due to the fact that signal travels
as wave – are one of the most promising alternative for
fast on-chip application as long as other fast way of
communication i.e. optical waveguides are not
economical. If we reinforce the lossless condition the
transmission lines, as oppose to simple wires, can
operate at much higher speed – virtually close to speed
of light. However, transmission lines have their own
shortcomings i.e. reflections from load on mismatch,
attenuation during propagation. Focus of this survey
paper is to study the various undesired effects which
degrade the performance of transmission line.
Section 2 is an overview of on-chip interconnects
modeling. Section 3 presents a brief description of
transmission line theory and metrics of transmission
line. In section 4, various on-chip termination schemes
are discussed with their advantages and disadvantages.
These basic schemes are the core of the most of the
state-of-art work in designing high speed on-chip links
using transmission lines. Qualitative analysis and
relationships of various parameters are presented in
section 5. Section 6 concludes the study and serves as
rough high-level guideline for designing the high
speed systems. Observations and findings are based on
most recent research work.
2. On-Chip Interconnects: Modeling
Major problem with parallel bus arise due to clock
skew and crosstalk noise. This mandates designers to
look for serial interconnects for high speed
applications. This section focuses on various models of
interconnects – ranging from the simplest and least
accurate to most complex and most accurate. Most of
the models discussed here are in distributed in nature
as oppose to lumped models where the whole
interconnect is represented using one single
component.
Simplest serial on-chip interconnects can be thought
of a distributed RC network, shown in fig – 1 below.
This modeling is more accurate than lumped
component modeling where distributed capacitance
and resistances are modeled with just a single
resistance and one capacitance.
Rwire
Cwire
Fig. 1 – Distributed RC wire model
Although “Lump RC” model is easy to comprehend
but it is least accurate and far from the real behavior of
todays interconnects. This is the reason precisely that
“lumped RC” model haven’t been considered in this
study at the first place. “Distributed RC” model is most
accurate for low frequency thus low speed application.
The threshold of low and high is decided by the overall
wire impedance. It lies at the point where the overall
impedance is dominated by wire resistance instead of
wire inductance.
In RC wire, electrical signal propagation is
somewhat similar to diffusion phenomena. Time
response of RC model is similar to cascaded RC first
order system. Delay and rise time are proportional to
the square of the length of the wire. One obvious
observation is that as feature size shrinks, global wires
don’t tend to scale down, the propagation delay and
rise time both degrade rapidly. This degradation in
delay, proportional to square of length, poses serious
challenges on achieving low latency with high
bandwidth [7].
A simple solution to enhance the performance of
RC wires is to insert the repeaters. Repeaters are kind
of signal booster inserted, in pipelined manner, at
regular intervals as shown below in fig – 2.
Repeater
Rwire
Cwire
d
d
Fig. 2 – Repeated RC wire with regular repeaters
Insertion of repeaters solves problem to some
extent. It breaks down a big RC problem into n – small
RC problems. Delay now becomes proportional to
length of wire which was originally proportional to
square of length [7]. However, this performance gain
comes at the cost of increased die-area – repeaters are
some sort of logic blocks – and higher power
consumption. In some cases, the increased area and
power is beyond the acceptable limits so this
implementation may not be pragmatic in those cases.
As the frequency of operation increases RC wire
models are no more accurate. The reason is that wire
impedance is dominated by overall inductance
( ω L>>R) rather than resistance. This region of
operation is referred a “LC region”. In LC region a
wire behaves like a transmission line rather than RC
wire. As oppose to RC wires, in transmission line
propagation of signal happens very similar to
electromagnetic wave propagation. This propagation
is much faster inherently – almost close to the speed of
light – as compare to RC wire signal propagation.
Need of repeaters is also eliminated when
interconnects are modeled as transmission line.
A lossless transmission line can be modeled as
distributed LC network without any resistive
component, shown in fig 3. Inherently fast
transmission lines suffer from their own problems i.e.
reflections due to mismatching, dispersion due to line
resistance in non-ideal cases.
L
C
Fig. 3 – Lossless LC transmission line
In the following subsequent sections we would look
more closely into transmission line model and try to
understand the trade offs involved into implementation
of transmission lines.
As energy travels in a TL towards the load it is
dispersed rather than dissipated as it does in RC wire.
Per unit length delay (D) of lossless line is given by
following expression.
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D = p LC @@@ 1
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On-chip transmission lines are implemented either
using metallic micro strips or co-planer traces. These
traces have their own sheet resistance thus
transmission lines are not completely lossless. A more
accurate model as oppose to fig. 3 is shown below with
series resistance.
R
L
C
Fig. 4 – Lossy RLC transmission line
Another more accurate model – RLGC model –
includes parallel conductance path from line to ground
after every series R and L. Although RLC model is not
most accurate even then Telegraphers’ equations for
the analysis of transmission line still hold valid. This
dispersion caused by series resistance may result into
Inter Symbol Interference (ISI) for high speed
communication.
One of the solutions to alleviate the ISI and deal
with dispersion problem is optimum termination of
transmission line. In general, on-chip interconnects are
connected to receiver stage without any termination as
shown in figure below.
Passive termination matches the characteristic
impedance of transmission line to the input impedance
of receiver stage. Introduction of lossy passive
components such as resistance (R) and conductance
(G) increases the bandwidth tremendously. However,
the introduction of such components increases the
power dissipation as well. One way to counter the
effect is to operate the signal line at lowered voltage
swing thus minimize the power consumption. Also
terminated line exhibits low rise time which helps in
achieving the high bit rate [1]. Improved ISI and low
power consumption comes at the cost of sophisticated
complex receiver design – more specifically sense
amplifier at the receiver end because the output voltage
swing is now smaller compared to open-circuit
transmission line case.
A classical challenge in designing of transmission
line based on-chip interconnect is minimize the power
consumption while maintaining the low latency and
high throughput. Next several sections would discuss
the various termination schemes using passive
components and their pros and cons.
3. Metrics of Transmission Line
This section is brief overview of various matrices
and characteristics of transmission line before. Content
of this section is simple enough and detailed partial
wave equations for transmission line and their
solutions are avoided.
3.1. Characteristic Impedance
Characteristic Impedance (Zo) of transmission line
is defined as the ratio of voltage (V+) and current wave
(I+) propagating in forward direction from source to
load [6].
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Fig. 5 – On-Chip TL without termination
Optimum termination eliminates the ISI possibility
and allows source to deliver the maximum power to
the load. It also removes the reflections which are
present when characteristic impedance of transmission
line is not matched with the load impedance. Another
advantage of optimum termination is that it avoids the
source oscillation which can arise due to additive
nature of reflective wave from far end.
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Zo = + = s
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G + jωC
I
Equation (1) is valid for RLGC transmission line.
Where R, L, G, C are resistance, inductance,
conductance and capacitance per unit-length of
transmission line. This can be easily modified for RLC
model by substituting G = 0.
For lossless transmission line (R = G = 0)
expression (2) reduces to expression (3) as below [3].
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3.2. Voltage Standing Wave Ratio
The voltage component of a standing wave in a
uniform transmission line consists of the forward wave
(with amplitude V+) superimposed on the reflected
wave (with amplitude V-). Reflections occur as a result
of discontinuities, such as an imperfection due to
impedance mismatching either at the load or along the
line. VSWR is defined as following.
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Figure below depicts a propagation of EM wave in
a mismatched TL. Yellow vectors are actual signal
while EM wave propagates from source to load. Cyan
vectors are amplitude of reflected wave which is due to
mismatching at load end.
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V z =V o z e γz + V o z e γz @@@ 5
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First term in expression (5) is wave propagating in
forward direction whereas second term denotes a wave
propagating in backward direction. γ is propagation
constant which can be expressed as following.
γ = α + jβ
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α is attenuation constant which is an indication of
deterioration of voltage across the line. Attenuation
constant is a function of frequency and increases with
the frequency.
4. High Speed TL Termination Schemes
In this section, various remedies of reflection
problem are described. In general any interconnect
operates either in RC – region (low frequency mode)
or LC region (high frequency mode). Effective
impedance in either of the region is dominated either
by resistance or by inductance. Qualitative plot below
depicts the two regions.
Fig. 7 – LC and RC region: On-Chip Interconnect
Fig. 6 – VSWR and reflections in a mismatched TL
Voltage at any point in the TL is resultant of two
vectors – forward and reflected –which is depicted by
green curve.
3.3. Reflection and Attenuation
In RLGC model voltage and current at any point in
transmission line are the solution of famous
telegrapher’s partial differential equations. General
solution of telegrapher’s equation can be expressed as
below.
In RC region, the overall impedance is almost
constant because the frequency dependent component
is still small. As the frequency increases, frequency
dependent component grows in magnitude and overall
impedance is dominated by inductance. Varying nature
of impedance increases the reflection which is due to
mismatch of impedances. In open-circuit TL reflection
losses due to this mismatch are quite high and at some
point the whole signal is reflected back. This requires
some sort of termination before the receiver stage.
Once line impedance is dominated by inductance
we need to treat the ordinary wires as transmission
lines. Reflections which occur from discontinuity make
line noisy and may also lead to source oscillation. Far
end and near end voltage waveform are no more same
as input signal rather it is a superimposed waveform of
forward and backward voltage waveform.
In open circuited transmission line the near and far
end voltages at steady states are given by following
expressions. It is assumed that transmission line is
properly matched at near end.
V near =V
far
=V dd @@@ 7
Expression (7) is valid
operation. At high frequency
far end steady state voltage
this, ordinary un-terminated
high speed communication.
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for low frequency of
due to the reflections the
reaches to zero. Due to
wires can’t be used for
For optimally terminated TL the equivalent
expressions for near and far end voltages are as
following.
V near =
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far
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It is assumed that transmission line is properly
terminated at transmitter end. This is typically the case
in general because the intention is to damp the second
and subsequent reflections.
In rest of the section we present some simple
techniques to reduce the reflections.
suffers from few drawbacks. After introduction of a
shunt resistance there is a path between signal line and
ground which always dissipates the power. Another
concern is that due to voltage divider the voltage swing
at the output is smaller than what it was in open-circuit
case. This sounds like a drawback in some sense but it
is not. First, typical voltage drop – required eye
opening voltage – can be achieved with the right
choice of termination. Second, a state-of-art sense
amplifier can easily detect the low swing signal with
typical value is 200 mV peak-to-peak.
The advantage of reduced swing is that the power
consumption is also low. Trade off for low power is
reduced noise margin which would require a
sophisticated transceiver design. Another concern is
that due to process variation the value of on-chip
resistance may change and which may lead to
mismatch. The good news is that exact value of
resistance really doesn’t matter. Only constraint in
choosing the resistance value is that it should be more
than optimal value.
4.2. Distributed Shunt Resistance
This technique is proposed by a research group at
University of California, San Diego. The idea is to
introduce the additional conductance paths to
compensate for the attenuation due to series resistances
[3]. They call it “Surfliner” architecture due the reason
that it looks similar to railway track. The name of
railway track from San Diego to San Luis Obispo is
“Surfliner”.
4.1. Shunt Resistance
The simplest way to eliminate the reflections is to
match the line impedance by placing a parallel
termination at receiver side. Reflection coefficient is
zero at the far end after perfect termination. However,
it is not always expected to terminate the line with the
impedance exactly same as characteristic impedance.
Fig. 9 – Surfliner architecture for high speed TL
Leakage conductance per unit-length G is chosen in
such a way so that it satisfies the condition of
distortion less transmission. Following expression is
for distortion less transmission line.
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RC
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G= f
@@@ 9
L
Fig. 8 – Parallel termination using a resistance
This technique increases the bandwidth by reducing
the reflections and rise time. However, at same time it
According to authors, Simulation results show that
using 65nm technology, the proposed scheme can
achieve 15Gbits/s bandwidth over a 20mm on-chip
serial link without any equalization. Also they claim
that this approach offers a 6x improvement in delay
and 85% reduction in power consumption over a
conventional RC wire with repeated buffers.
conductance and put termination resistor in the
receiver end. This is proposed by same group who
proposed “Surfliner” architecture.
4.3. Series Resistance
Series termination has become very common in
today’s high-speed designs – especially in multireceiver systems. It has the two desirable attributes of
termination schemes – a single component and no DC
current draw at all. The series termination resistor is
placed at the front end as oppose to parallel
termination at the far end [5].
Fig. 12 – Distributed conductance with shunt R
According to authors, this technique has 15x
improved jitter compare to naked TL.
5. Qualitative Analysis and Plots
5.1. Analysis and Trade offs
Fig. 10 – Series termination in high speed TL
In this case the far end is left open-circuit.
Therefore, there is a 100% positive reflection from the
far end of the TL. However, the series resistance
damps the second and subsequent reflections at near
end and avoids the perturbation in signal line. This
kind of termination is especially advantages when
there are multiple receivers and single transceivers.
4.4. Shunt Resistance with Capacitor
Yet another variation of parallel termination is the
addition of a capacitor in series with the parallel
resistance. The primary advantage of this is that the
capacitor blocks DC current at low frequency, so there
is no steady-state current flowing through the
termination at the low speed. At first glance it would
appear that this strategy otherwise has all the
advantages of the parallel termination strategy.
However, the “cost” of this, of course, is the added
component.
Fig. 11 – Parallel RC termination
4.5. Distributed Conductance with Shunt R
This is essentially combination of two techniques
mentioned before. The idea is to evenly insert shunt
Work reported in this section is qualitative in nature
rather than quantitative. Results are also derived
analytically from simplification of complex
expressions. Most of the results are valid for state-ofthe-art systems. Verification of the characteristics and
results through simulation wasn’t possible due to time
constraints.
5.1.1. Eye Opening Voltage and Bit Rate
Eye opening voltage depends very much on the bit
rate. For two different transmission lines the
relationship is depicted in plot below.
Fig. 13 – Eye opening voltage for various bit rate
Eye opening voltage is inversely proportional to the
bit rate. Eye opening voltage reaches to 0 for opencircuit TL at approx 50 Gbps. This is due the fact that
at this speed the reflections are so prominent that
whole incident wave is reflected back. In contrary to
this, terminated TL although has a lower eye voltage at
low bit rate but it is pretty consistent and provides a
high bandwidth. Some study reports that about 100mV
eye-opening at 100Gbps signaling can be achieved
with passive termination. Thus resistive termination is
necessary for high-speed signaling.
5.1.2. Energy/ Bit and Termination Impedance
One serious concern in using resistive termination
is increased static power dissipation. When resistor is
connected between the signal line and the ground,
static current flows through the terminator. Figure
below shows the energy per bit of 20Gbps signaling
[2]. Interconnect under test is 5mm long and the
characteristic impedance is 100Ω.
Fig. 15 – Eye opening vs normalized termination
Three different curves are for various attenuation
constants. As attenuation increases the eye-opening
voltage degrades [2]. However, the conclusion is that
towards the right side the curves are flats after some
optimal value of terminations. This also verifies the
claim that exact value of impedance doesn’t matter as
long as it is more than optimal value.
Fig. 14 – Energy/ Bit for various impedances
The key observation from above plot is that as we
increase the termination impedance the energy
consumption decreases and eventually we reach to
open-circuit case. This means large impedance is not a
right choice because it would consume more silicon
area and still the reflections would be present. On the
other hand, if we choose the impedance a small value it
increases the power consumption. The broken vertical
line represents the optimum value of termination
impedance which is equal to TL impedance. However,
designer may choose a value grater than optimal
termination in order to minimize the energy
consumption and yet achieve the benefits of passive
termination i.e. high bandwidth etc.
5.1.3. Eye opening and Normalized Impedance
Normalized impedance is the ratio of any
impedance in the system to the characteristic
impedance of TL. Figure 15 shows the relationship
between maximum eye-opening voltages for various
attenuation parameters. The attenuation constant is the
function of normalized termination impedance. The xaxis is the normalized impedance and the input bit rate
is fixed to some specific value, 20Gbps in this case [2].
5.1.4. Step Response of Lossy Transmission Line
The plot below shows the step response of various
transmission lines. Typical lengths of these TLs are
from few mm to tens of mm.
Fig. 16 – Step response of various transmission
lines
Smaller TL has small rise time thus signal
propagation happens rapidly. However, longer TL
exhibit slow RC response thus they are not adequate
for fast switching application.
5.2. Challenges in Implementations
One of the major challenges in designing the system
with transmission lines as on-chip interconnects is
modeling of TL components using current CAD tools
[1]. Optimization of transmission lines with lots of
parameters and various trades off involved could be
daunting thus complexity and efforts is increased. To
alleviate this problem to some extent, designers may
prioritize their performance metrics and optimize for as
per the requirement rather than optimizing for absolute
performance.
Modeling of lossy transmission line involves
finding the values of inductances. “Inductance
extraction” in itself is a major challenge to current
EDA tools. It involves finding the return path for
current to estimate the loop which is basis of on-chip
inductance estimation. Current tries to find minimum
impedance path to return in order to complete the loop.
The return path is not simple to figure out because it
changes with the frequency as overall impedance
changes. In addition to this, modeling of skin effects
and other losses are not trivial by any means.
The serious challenges are to decide about the
factors such as acceptable attenuation, reflection and
dispersion. Also deciding the optimum termination
value is not trivial because lower value of termination
resistance, close to Zo, would increase the power
consumption with increased bandwidth. Increasing the
resistance, approaching towards open-circuit case,
would require larger area on chip and also result into
increased reflection. Overall, CAD modeling,
simulation and optimization of such systems is
complex and challenging.
6. Conclusion
6.1. Parallel versus Serial
Major challenge in parallel buses was to minimize
the noise induced by parallel running wires. Also a
major portion of power is consumed by repeaters in
parallel bus architecture system. Power consumed by
all on-chip interconnects could be as high as 30% of
the total chip power consumption [7]. These problems
have been solved by serial interconnects to great
extent. Serial transmission line uses significantly less
number of repeaters thus a major portion of power is
saved. Another significant fraction of power is saved
from the proper termination of transmission lines
because the optimally terminated transmission lines
operate at low voltage with high rise time.
6.2. Passive Termination and Reflections
Two major challenges in implementation of
transmission line are avoiding the reflections and
attenuations. Reflections are overcome by proper
optimal termination. However, these terminations
involve the passive components like resistances and
capacitances. Implementation of on chip capacitor with
precision is not guaranteed due to process variation.
Also as capacitor consumes lot of on chip real state it
may not be a good idea to implement some of these
termination schemes in area constrained designs. Onchip resistance also consumes significant area. In this
case, one needs to guarantee the tolerances of
resistance value and sensitivity of compensation circuit
on resistance variation [2].
6.3. Power saving using Transmission Lines
Some experimental results show that transmission
lines could easily achieve the data rate as high as 50
Gbps [6]. It may not be required to run the circuits at
this high speed all the time. In such cases, some more
power can be saved by operating at low frequency by
doing voltage-frequency scaling or constant voltage
scaling. The motivation behind the idea is to design
system for high speed and either use for high
performance (with increased power consumption) or
low power (with decreased performance) mode.
6.4. Transmission Lines and Parameters
Plots in section 5 can be used to design the systems
for various needs. This section provides design
guideline of resistive termination from the fundamental
parameters, i.e. bit rate, characteristic impedance and
attenuation. Termination strategies can be effective in
eliminating, or at least minimizing, transmission line
reflections. But no individual strategy is perfect. Each
one has a tradeoff of some type. It is designers’
responsibility to come up with optimal solution.
7. References
[1] Michael P. Flynn and Joshua J. Kang, “Global Signaling
over Lossy Transmission Lines”, IEEE – ICCAD 2005.
[2] A. Tsuchiya et al, “Design Guideline for Resistive
Termination of On-Chip High-Speed Interconnects”, in
proceeding IEEE Custom Integrated Circuit Conf.,
2005.
[3] H. Chen, R. Shi, C. Cheng, and D. Harries, “Surfliner:
A distortion less electrical signaling scheme for speed
of light on-chip communications,” in Proc. Asia South
Pacific Design Automation Conf., 2006.
[4] Chun-Chen Liu et al, “Passive Compensation for High
Performance Inter-Chip Communication” IEEE – ICCD
2007.
[5] Yulei Zhang et al, “On-Chip Bus Signaling Using
Passive Compensation”, IEEE – EPEP 2008.
[6] H. Zhu et al, “Approaching Speed-of-light Distortion
less Communication for On-chip Interconnect”, ASP –
DAC 2007.
[7] R. Ho, K. Mai and M. A. Horowitz, “The future of
wires”, Proceedings of the IEEE, April 2001.