Logic, Boolean Algebra, and Digital Circuits
Jim Emery
Edition 4/29/2012
Contents
1 Introduction
4
2 Related Documents
5
3 A Comment on Notation
5
4 A Note on Elementary Electronics
7
5 Boolean Algebra
8
6 Logic Operators and Truth Tables
8
7 A List of Logic Identities and Properties
9
7.1 DeMorgan’s Laws . . . . . . . . . . . . . . . . . . . . . . . . . 11
8 Propositional Logic
12
9 A Truth Table Applet
13
10 Digital Logic Symbols
14
11 Disjunctive Normal Form and Minimal Disjunctive Normal
Form
14
12 Prime Implicants
15
13 The Quine-McClusky Algorithm
15
1
14 A Quine-McClusky Applet
16
15 Relays and Switches as Logic Elements
16
16 Set Theory
16
17 Sequential Machines, Finite State Machines
17
18 Digital Electronics
17
19 The Half-Adder
17
20 The Full-Adder
19
21 Flip-Flops
20
22 The Difference Between A Latch and A Flip-Flop
20
23 SR NOR Latch
21
24 SR NAND Latch, ( Also written as Sn Rn NAND Latch)
22
25 The D Flip-Flop
23
26 A Verilog D Flip-Flop
23
27 The D Latch
24
28 Constructing A D Flip-Flop With a Pair of D Latches
25
29 The JK Flip-Flop
25
30 Multivibrator and Latch
26
31 The
31.1
31.2
31.3
31.4
31.5
31.6
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26
26
28
29
30
30
Wilkson Digital Logic Test Board
Power: A Nine Volt Wall Wart Power Supply . . .
Five Volt and Three Volt Regulated Power Supplies
The 555 Timer Subcircuit . . . . . . . . . . . . . .
Properties of Light Emitting Diodes . . . . . . . .
Switches and Push Buttons . . . . . . . . . . . . .
Storing A Logic State With A Switch . . . . . . . .
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31.7 Viewing A Logic Value With an LED . . . . . . . . . . . . . .
31.8 Resistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . .
31.9 The 74LS163 Synchronous 4-Bit Binary Counter . . . . . . . .
31.10 74LVC540 Buffer-Line driver . . . . . . . . . . . . . . . . .
31.11 The Subcircuit That Drives the LEDs on the Printed Circuit
Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31.12 Testing the Wilkson Board With an SN74LS74AN . . . . . .
31.13 The Solderless Breadboard . . . . . . . . . . . . . . . . . . .
31.14 The pins from the PCB to the Breadboard . . . . . . . . . .
31.15 The Xilinx CPLD . . . . . . . . . . . . . . . . . . . . . . . .
31.16 The Circuit Board Pin Assignment for the XC9536XL CPLD
31
31
31
33
33
35
36
36
37
37
32 MUX, The Multiplexer and Demultiplexer
37
33 Programmable Logic Devices
37
34 Installing and Using the Xilinx ISE Software
38
35 Class Exercise: Create a D Flip-Flop With ISE
39
36 A Data sheet for the 74LS163 4-bit Binary Counter
39
37 More Information About Chris Wilkson’s Printed Circuit
Board: Assembly Order, Images, Bill of Materials.
40
38 A Sequential Machine: A Three Bit Binary Counter
41
39 Test Instruments and Tools for Digital Electronics
41
40 Download Cable
42
41 PCB Artist
43
42 LT Spice
43
43 A List of 7400 Series Integrated Circuits
43
44 A Class Design Project: Controlling Thunderbird Tail Lights 44
3
45 Appendix A, RC Circuits, Time Constants, and the LM555
Timer
44
45.1 A Resistor Capacitor Circuit and the Time Constant . . . . . 44
46 Appendix B, A Xilinx ISE Tutorial
49
47 Appendix C, Introduction to the Verilog Hardware Design
Language
50
48 Appendix D, Running Icarus Verilog From The Command
Line in Windows
51
48.1 MUX2 Program Listing . . . . . . . . . . . . . . . . . . . . . 54
48.2 Running the Programs . . . . . . . . . . . . . . . . . . . . . . 54
49 Bibliography
55
50 Glossary
57
51 Constants
62
1
Introduction
This document is a preliminary draft version that is not yet complete. But I
hope there is some useful material here now, which I think some might find
helpful. More circuit diagrams will be added later. As it evolves, the latest
version will be found on the STEM2 website:
To Find it on STEM2 go to
www.stem2.org.
Select Documents and Downloads. Then select Electronics.
For A direct link:
http:\\www.stem2.org\je\logic.pdf
4
2
Related Documents
Basic Electricity is a brief introduction to, and an explanation of some
concepts in electricity and electronics.
http://www.stem2.org/je/basicelectricity.pdf
Electric Circuits is an introduction to some topics in electrical engineering.
http://www.stem2.org/je/ee.pdf
Electromagnetic Theory is an outline of topics in that subject, which is
a region in mathematical physics, also sometimes called, especially in older
books, Electricity and Magnetism. The document contains a treatment
of matters related to Maxwell’s Equations, which form the basis for classical
electricity, magnetism, the theory of electromagnetic waves, the concept of
the speed of light, and a foundation for optics. This is really an outline for
someone who has already studied the subject, but by skimming over it one
unfamiliar with it might get an idea of what the subject is about, as well
as what are: electric and magnetic fields, electric potential, voltage, electric
and magnetic polarization, capacitance, inductance, and even might see why
it necessarily led to relativity theory.
http://www.stem2.org/je/electromagnetictheory.pdf
3
A Comment on Notation
Logical variables take values true and false, or 0 and 1, or low and high
(voltages). If a value is 1, the complementary value is 0, and if the value
is 0, then the complementary value is 1. If X is a logical variable, then its
complement is written in several ways in this document, with a bar, as in X̄,
or with an apostrophe as in X .
The labels to the pins of chips and logic gates can appear with a bar,
as in CLR. The label CLR suggests that this pin causes something in the
chip to be cleared, that is something to be set to zero or zeroes. Normally
5
an action takes place when a value is high or equal to 1. But sometimes the
action suggested by the pin name takes place when the value is low. So the
label CLR signifies that a pin is active low, and this does the clear when
the value is low. This convention can be rather confusing, but it is common.
Other authors might write this with a slash as in /CLR or as CLRn with
a subscript n. The later signifies that the pin is active low. In verilog this
subscript version CLRn might be written as CLR n . This is recommended
because it can be used as a logical variable in the hardware language Verilog.
Putting a bar over a variable is easy to do with handwriting, but not so easy
when writing with a computer, or in a computer generated diagram.
Conventions used for specifying that a pin is active when low are numerous. We have mentioned already that this might be denoted with a slash
as in /LOAD, meaning the loading takes place when this pin is low. Also
pins with a small circle attached in a diagram denotes an active low pin.
Another convention is to use the IEEE standard, using the so called bubble
notation or a small circle at a pin, which is to mean that the pin is active
low. This is a good method, because it avoids the ambiguity of labels and
variables. However schematic drawing programs may not support this, and
it may be used by a minority of people. The IEEE standard requires bubble
to bubble labelling that may provide some light, or perhaps to some, more
dark. The book in the bibliography by Wakerly has more information about
specifying active low pins, on symbols, on standards, and on historical usage.
As an opinionated editorial comment I think that labelling a pin with a
bar when it is active low is a very confused idea. A chip essentially is a function with input pins and output pins. There is confusion between labelling
pins, which are the inputs and outputs to functions, and the labelling of logical variables. These are two different and distinct ideas and can not help but
lead to ambiguity. This confusion extends to other fields such as computer
programming and a very long time ago, to mathematics and physics. So in
the olden days in mathematics a function was a rule or computation that
from a variable value, say x, produced a new variable value say y. So it was
a sort of sausage machine. In modern times a function is considered a set,
perhaps infinite, of ordered pairs, or of ordered n-tuples for higher dimensional functions. The use of the word variable is actually frowned upon a bit
in mathematics, because what is this thing that varies and how does it vary?
However it is not clear what we should use in place of the word variable.
We do have subjects in mathematics called Complex Variables and Real
Variables. So really the proper way to deal with pin labelling in chips is
6
to imitate mathematics and depend on the pin order or number rather than
on a label symbol to give meaning. Then one can supply an explanation of
what for example, pin 5 is, with a sentence or a word. However, I think
after further education, that this problem is well recognized in the IEEE and
in the electronics community, and so my rant may be pointless, especially
coming from a mathematics and physics person, not an expert in electrical
engineering. However consider computer programming.
In computer programming, one is instructed to give variables long explanatory names, so that programs are ”easier to read.” This has the same
kind of difficulties described above, which I won’t go into, but comes from
a simplistic understanding of algorithms, variables, functions and and the
fact that algorithms are mathematical objects. This is all too common in
the computer science community, and one of the reasons I have a distaste for
conventional computer science. So in summary, a symbol should not tell you
what it is, for to do that is to restrict its use as an unknown, to restrict its
use as something that may take on arbitrary values in various places as its
use evolves. So perhaps too much said.
4
A Note on Elementary Electronics
What is meant by elementary electronics? Elementary algebra usually is the
very elements of the subject, the idea of a variable, or of an unknown, the
techniques of manipulating algebraic expressions, the commutative laws, the
associative laws, the distributive law, solving a simple equation, and so on.
But elementary electronics seems to mean something a bit different?
My anthropological observations lead me to some answers. In one sense
elementary electronics is just what beginning electronic hobbyists do. And
what they do typically, is not what one might call elementary electrical or
electronic engineering, but it is the assembling, building, and soldering of
electronic circuits, and then observing what these circuits do, and then operating them, and then exclaiming ”cool”. So it is not the building up of
understanding, by studying the elements of the subject, rather it is that
which can be done by the beginner with perhaps very little understanding.
But the things that are built are not necessarily themselves simple. So
elementary electronics could be the building a television set, or the building of a personal computer. These machines are certainly not elementary.
No, elementary refers to the skills that the beginner brings to the task. So
7
the theory of the detailed working of the electronic components is not part
of elementary electronics. Because this would require various preparatory
courses and previous knowledge and previous skill, perhaps some mathematics knowledge, and previous electrical experience.
So elementary electronics can prove to be a bit frustrating for those thinking people who do need to know, and who do need to understand, in order
to do.
In conclusion, elementary electronics is a practical somewhat mindless
activity, that does often brings pleasure, a pleasure similar to narcotics.
Warning A class advertising itself as a class in elementary electronics,
may be a thinly veiled class in elementary or basic electrical engineering.
5
Boolean Algebra
George Boole, who lived from November 2, 1815 to December 8, 1864, published a famous book on logic, The laws of thought, in 1854. This makes
him the father of modern symbolic logic. So he invented a symbolic algebra
for logic in the first half of the nineteenth century. It has much in common
with the modern algebra of sets, and has diverse application in many fields,
including that of digital electronics.
Propositional logic, set theory, and digital logic all share the same boolean
algebra.
6
Logic Operators and Truth Tables
The ”or” operator is usually written as a ∨ in symbolic logic. So the proposition ”p or q” would be written p ∨ q. A + sign is usual in electronics, so
”p or q” is written as p + q.
The truth table for ”or”:
p q p+q
0 0
0
0 1
1
1 0
1
1 1
1
8
The ”and” operator is sometimes written with a wedge as in p ∧ q. But
often in electronics the operator is omitted as we do in algebra for multiplication. So the ”and” operator is implied when two variables are adjacent.
So we write pq as we do for the multiplication of numbers.
The truth table for ”and”:
p q pq
0 0 0
0 1 0
1 0 0
1 1 1
The ”inverter” :
The inverter changes the input value to its opposite.
The ”nor” and the ”nand” :
By inverting the outputs of the ”or” and ”and” we get the ”nor” and ”nand.”
The truth tables for ”nor” and ”nand” are obtained by changing 0 to 1 and
1 to 0 in the outputs of the ”or” and ”and”.
The Exclusive ”or” :
The exclusive ”or”, written ”xor” has output 0 if both inputs are 1.
The truth table for ”xor”:
p q p⊕q
0 0
0
0 1
1
1 0
1
1 1
0
7
A List of Logic Identities and Properties
I should give here a list of seventeen logical identities that Cris Wilkerson
supplied in one of his lectures. However, I did not write them down in my
9
104
103
91
92
93
94
95
96
XOR
81
82
83
84
AND
71
72
85
74
98
99
100
87
88
89
90
79
80
INV
86
OR
73
97
NAND
75
76
NOR
77
78
PNP
61
62
IC 63
64
51
52
53
54
FET
65
66 Connect67
55
68
69
70
56
57 Label 58
59
60
IC
41
42
43
44
45
46 IC
47
48 Wire 49
50
33
34
35
36
37
38
40
OpAmp
31
32
120 V
21
22
12
23
24
NPN
25
26
27
POT 28
29
30
17
18
19
20
9
10
L1
13
14
15
16
C1
1
2
39
C2
R1
11
D1
3
4
10 Volts
5
6
7
8
101
102
Figure 1: Circuit Symbols. A display of circuit elements available in the
program cdiagram for creating a circuit diagram, including the standard
symbols for logic gates. Node numbers, which are shown here, are used to
locate the elements.
10
notes. Some of them are pretty obvious I think, but DeMorgan’s laws are
probably not.
7.1
DeMorgan’s Laws
I could write these laws in propositional logic, set theory, or in electronic
logic notation.
I will do it in set theory. The idea is that you change each variable to
its complement, the entire expression to its complement, and change the
operator to its dual operator. So for sets, change union to intersection and
so on.
So
A ∪ B = (A ∩ B )
and
A ∩ B = (A ∪ B ) ,
where apostrophe specifies the complement.
In the case of electronics and logic this can be proved with truth tables.
In set theory you prove that the left side is a subset of the right, and that
the right is a subset of the left, and therefore the sets are equal.
De Morgan’s Laws Let A and B be sets, then
A ∪ B = (A ∩ B )
and
A ∩ B = (A ∪ B ) .
Proof. Suppose x ∈ A ∪ B. Without loss of generality suppose x ∈ A.
Then x is not in A , so x is not in A ∩ B then it is in the complement,
x ∈ (A ∩ B ) . So
A ∪ B ⊂ (A ∩ B ) .
On the other hand suppose x ∈ (A ∩ B ) . Then x is not in A ∩ B without loss of generality suppose x ∈
/ B , then x ∈ B, therefore x ∈ A ∪ B.
Then
(A ∩ B ) ⊂ A ∪ B.
So
A ∪ B = (A ∩ B ) .
A similar technique shows that
A ∩ B = (A ∪ B ) .
11
8
Propositional Logic
A proposition is a logical statement that can be true or false. A combination of such statements, which involves n propositional variables can be
analyzed using a truth table with n input columns and one output column
corresponding to the combination. For example, the statement r = (if p then
q) is considered false if and only if p is true and q is false, otherwise it is true.
This has the same truth table as ”not ( p and (not q)) = (not p) or q.” We
have reached the equality by applying one of DeMorgan’s laws. Symbolically
this equality is written
p ⇒ q = ¬(p ∧ ¬q) = ¬p ∨ q,
and is read as p implies q.
¯ propositions p and q, if both
Now given two
p ⇒ q,
and
q ⇒ p,
then p and q are called logically equivalent. Logical equivalence can be
written as
p ⇔ q,
or
(¬p ∨ q) ∧ ((¬q ∨ p).
A logical proposition that is always true is called a tautology. So p and q are
logically equivalent if the proposition
p⇔q
is always true.
Now consider the problem of minimizing gates in a digital circuit. Suppose we apply the Karnough map method, the Quine-McKlusky method,
or apply various Boolean Algebra identities to reach a minimal number of
gates. We would like to know if the application of these methods has indeed
produced a logically identical circuit, that is we want to check that we have
not made a mistake. This can be done by examining the truth tables for
the two expressions. But this can be rather tedious, and error prone itself.
12
We can use use a computer program to compute the truth tables. The next
section introduces an applet to do this. However, the two truth tables may
not produce truth tables that have the same ordering of columns, or of rows,
which makes visual comparison difficult. However, suppose the original circuit has p for a boolean algebra representation, and the minimized circuit
has expression q. So if we compute the truth table for
(¬p ∨ q) ∧ (¬q ∨ p),
then the circuits are equivalent if all outputs have values ”true” or ”1”, and
this is easy to see from the resulting truth table no matter how the rows and
colums are arranged.
9
A Truth Table Applet
Here is a link to an applet that constructs a truth table from a propositional
logic expression:
http://www.aiai.ed.ac.uk/~gwickler/truth-table.html
The expression is entered in polish notation , also called prefix notation,
where the operator preceeds the operand or operands. So writing an arithmetic problem in ordinary notation, also called infix notation, we write for
example the sum of 2 and 3 as
2 + 3.
In polish or prefix notation we would write this as
(+ 2 3).
To show that
p⇒q
is logically equivalent to
¬p ∨ q,
for example, we type into the program
(<=> (or
(not p) q)
(=> p q))
Then we select compute. From the truth table we find this to be a tautology,
which means it is true for all values of the variables.
13
10
Digital Logic Symbols
The figure labelled Circuit Symbols shows some standard electrical symbols including those for logic gates.
11
Disjunctive Normal Form and Minimal Disjunctive Normal Form
The word disjunction in logic corresponds to ”or”, and in set theory to union,
whereas conjunction corresponds to ”and”, and to intersection in set theory.
So for example, in set theory, an element x is in the union of two sets A ∪ B
if x ∈ A or x ∈ B. In logic if p and q are propositions, then ” p or q”, written
p ∨ q,
is the disjunction of p and q. Each of p and q is called a disjunct. In
electronics we would write this disjunction as
p + q.
Given a truth table for a function f , a logical function can be found
that has that truth table by keeping only the rows for which f is 1. Thus
suppose we have variables p, q, r, s and a row where f is 1, and p = 0, q =
1, r = 1, s = 0. Then p qrs is called a disjunct and is 1 if and only if
p = 0, q = 1, r = 1, s = 0. Thus it implies f . So if we write a logical
expression as a sum of products, each product is called a disjunct because
the finale expression is a sum of these products. If the disjuncts for all of
the rows for which f = 1 are summed, then this sum, has the specified truth
table. The use of the terms disjunct and conjunct tends to be confusing
caused I suppose by the concepts of operator, and operand. So a disjunction
corresponds to an operation, while disjuncts are the operands, the elements
being operated upon. The sum of all the products where the value is 1 in
the truth table is called a disjunctive normal form. So a disjunctive normal
form is a sum of products. A disjunctive normal form need not be a minimal
disjunctive normal form. In electronics we want a minimal disjunctive normal
form in order to attempt to minimize the number of gates in a digital circuit.
The term ”minterm” is sometimes used for disjunct.
14
For more information, see the books on digital circuits and logic in the
bibliography, or go to Linda Hall library, which is on Cherry St on the UMKC
campus, to find a cornucopia of books on the subjects.
12
Prime Implicants
Prime implicants are products in which redundant variables have been removed. A product or disjunct P implies F if whenever P = 1 then F = 1.
The product is a prime implicant if whenever a factor is removed from P to
form Q, then Q no longer implies F . So suppose A1 , A2 , A3 are basic logical
variables and P = A1 A2 A3 Suppose P = 1, so necessarily A1 = 1, A2 =
1, A3 = 1. If F = 1 in this case then P implies F . So P is an implicant of F .
But now suppose variable A2 is removed from P to give R = A1 A3 and R still
implies F . This means that setting A1 = 1, A3 = 1 still makes F = 1. This
means that P is not a prime implicant. So if a disjunct P implies F then if
any variable in the product that is set to zero does not change F = 1, then
that variable is redundant. When all redundant factors have been removed
from P then the resulting product is a prime implicant.
13
The Quine-McClusky Algorithm
This is an algorithm to find the minimal disjunctive normal form for a boolean
function. It is essentially equivalent to the Karnaugh map method, but can
easily be computerized, so can handle larger problems than the Karnaugh
map. It works by finding the essential prime implicants. A logical expression
p implies q if whenever p is true then q is true. If p implies q, then p is said
to be an implicant of q.
However, the Quine-McClusky Algorithm is NP-complete, which means
very roughly that the size of the computation grows exponentially with the
size n of the problem. In this case n is the number of logical variables. So
the method will work only for a relatively small n. It would not be practical
for example if n = 15.
For more information, see the books on digital circuits and logic in the
bibliography, or go to Linda Hall library on the UMKC campus to find a
plethora of books on the subjects. Quine was a famous American logician
and philosopher.
15
There are several Quine-McClusky program on the internet, it might be
educational to write one myself.
14
A Quine-McClusky Applet
Here is a link to a Quine-McClusky applet that I found from bethel.edu:
http://www.mathcs.bethel.edu/~gossett/DiscreteMathWithProof/QuineMcCluskey.html
One enters an expression like the following
D2 D0 + D2 D1 D0 + D2 D1
by clicking on the minterms or implicants in a display of inputs to a truth
table.
There are many such applets available apparently. This is the first one
I tried and appears to be a nice one. So from this full disjunctive form, a
minimal disjunctive normal form is computed by the Java applet.
15
Relays and Switches as Logic Elements
See below for a simple circuit consisting of a resistor and a switch for storing
logical values. A similar representation can be automated with relays, and
with the an electronic switch, a transistor.
16
Set Theory
The theory of sets has an algebra similar to Boolean algebra and to the
theory of propositional logic. Set theory is much more than this though,
since it includes infinite sets, strange things like the Axiom of Choice,
transfinite numbers, hierarchies of infinities, cardinal numbers and ordinal
numbers. There are many books devoted to set theory. Many advanced
mathematics books start with a condensed coverage of set theory. If you
have a mathematical inclination see for example the book Topology by
Dugundji, or books on Measure Theory or on Real Analysis.
16
17
Sequential Machines, Finite State Machines
The machine may reside in a finite set of states. An output value depends
both on the state and the input. The next state function depends also on
the current state and on the input.
See Nagle et al in the bibliography.
18
Digital Electronics
Digital electronics works with discrete voltage levels, such as the TTL voltage
levels of 5 volts for the high logic value, representing a high logic state of
one, and a 0 voltage representing low logic value of zero. Digital circuits are
constructed with electronic logic gates, one or more gates being packaged in
integrated circuit chips. This contrasts with analog electronics, where voltage
levels are continuous.
19
The Half-Adder
The half-adder is a digital circuit made up of a few gates that computes the
addition of a pair of binary bits, but does not consider the input of a carry
bit. So the half adder computes from the inputs A and B, the sum bit S,
and the carry bit C. Here is a truth table for the half-adder is
The truth table for the ”half-adder”:
A B
0 0
0 1
1 0
1 1
S
0
1
1
0
C
0
0
0
1
There are several ways to implement the half adder. One way is to compute the sum as an ”exclusive or,” and the carry as an ”and”. Thus
S = A ⊕ B,
C = A + B.
See the figure labelled Adders.
17
Half-Adder
A
B
Full-Adder
S
A
S
B
C
C
C0
Figure 2: Half-Adder and Full-Adder. The half-adder gives the sum of
two bits A amd B, generates a sum bit S, and generates a carry bit C. The
full-adder adds A and B and an input carry bit C and generates a sum bit
S, and an output carry bit C0. See the text for equations.
18
20
The Full-Adder
The full-adder computes the sum of two bits A and B and a carry bit C. So
just adding A + B + C for each possibility, and writing the result in binary
we have
0 + 0 + 0 = 0 = 00
0 + 0 + 1 = 1 = 01
0 + 1 + 0 = 1 = 01
0 + 1 + 1 = 2 = 10
1 + 0 + 0 = 1 = 01
1 + 0 + 1 = 2 = 10
1 + 1 + 0 = 2 = 10
1 + 1 + 1 = 3 = 11
So we get:
The truth table for the ”full-adder”:
C
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
CO
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
where C is the input carry, CO is the output carry, and S is the sum. So
CO = C AB + CA B + CAB + CAB
= (C + C)AB + CA(B + B) + CB(A + A )
= AB + CA + CB
19
and
S = C A B + C AB + CA B + CAB
= A ⊕ (B ⊕ C).
Notice that the truth table is divided into parts where the input carry is
zero and where the input carry is 1. So the input carry bit could be used as
input to a multiplexer to use one logic circuit when the carry input is 0, and
another when the carry input is 1. A multiplexer is abbreviated as MUX.
Strings of full adders can be combined to created a circuit capable of
adding multi-bit binary numbers. Such circuits form components of computer
processors.
See the figure labelled Adders.
21
Flip-Flops
A flip-flop is a digital circuit that can be in either of two states, zero or one,
and so stores a logical value. Signals at its inputs, together with the current
state, cause a change in state of the flip-flop and a change in the output on
the next clock edge. A latch is also sometimes called a flip-flop.
Flip-flops can be divided into common types: the SR latch or flip-flop
(”set-reset”), D (”data” or ”delay”), T (”toggle”), and the JK. The behavior
is controlled by the characteristic equation, which is the next state function
and defines Qnext . The characteristic equation is a function of the current
state and the input (or inputs). The current state Q will become equal to
Qnext at the next clock edge.
22
The Difference Between A Latch and A
Flip-Flop
The distinction between a latch and a flip-flop is that a latch does not depend
on a clock pulse to switch states, a flip-flop does. A latch is level sensitive
whereas a flip-flop is transition sensitive. Usually the flip-flop changes state
on the rising edge of a clock pulse. A latch is used as a memory element to
store data, and retains a constant value until it is set or reset. A flip-flop
potentially changes state at each rising edge of the clock pulse.
20
23
SR NOR Latch
This is a simple latch, sometimes called a Set-Reset flip-flop, that can be
constructed with a pair of NOR gates. This is accomplished by using cross
over feedback connections between the two chips. There is no clock pulse.
This latch can be constructed with two NOR gates. Call them A and B. One
of the inputs to gate A is S. One of the inputs to gate B is R. The output
of gate B is called Q, the output of gate A is the complement of Q labelled
Q̄. The second input to gate A is the output of gate B. And the second
input to gate B is the output of gate A. The output of gate A is labelled Q.
So to justify our labelling we must show that the outputs of gates A and B
are complements of one another. So if S = 1, and R = 0 then the output of
NOR gate A is necessarily 0, independently of what its second input is. That
is Q̄ = 0. This is fed back to the input of gate B, and because R is the other
input to B and R = 0, then the output of gate B, which is Q, is necessarily
1. So the output of the gate B, which is Q is 1. So we have consistency with
out labelling. So if S = 1 and R = 0 then the output of the latch is 1. That
is S = 1 sets the latch to high.
The circuit is symmetrical, so in the case of R = 1 and S = 0 we find
that Q̄ = 1 and Q = 0 and the labelling is consistent. So inputs of R = 1
and S = 0 resets the output of the latch to 0. So S stands for set, and R for
reset.
Now suppose the latch has been set with S = 1, and R = 0, so that Q = 1
and Q̄ = 0. Suppose S changes to S = 0 and R remains at R = 0. We claim
that if the state of the latch remains at Q = 1 (and Q̄ = 0) then the cicuit
is stable so that Q = 1 remains the output with the new inputs. Because
Q = 1 is fed back to NOR gate A, the output of A is 1, that is Q̄ = 0. On
the other hand because Q̄ = 1 is fed back to NOR gate B, the output of B
is 0, that is Q = 0. The circuit is stable, there is no change in output.
Similarly if the latch has been reset with R = 1, and S = 0, then if R
changes to zero and S remains at zero then there is no change in output.
However, the change to inputs S = 1, and R = 1, does not give a stable
circuit, so these inputs are forbidden. (see the figure to be drawn)
The truth table for the ”SR NOR latch”:
21
S R
0 0
0 1
1 0
1 1
24
Q
Previous Output
0
1
Forbidden Inputs
SR NAND Latch, ( Also written as SnRn
NAND Latch)
An Sn Rn latch can also be built from a pair of NAND gates. In this case the
output Q is set and reset when the inputs are low rather than high as is the
case for the SR NOR latch. We signify that the action takes place when the
inputs are low by writing them as Sn and Rn . We could also write them as
/S and /R. The analysis is nearly the same as that for the SR NOR latch
given in the previous section. In this new circuit, the pair of NOR gates are
replaced by a pair of NAND gates, with the same previous feedback connections, except that the output Q is taken from NAND gate A rather than B.
That is the input to gate A is S̄, and the input to gate B is R̄. (see the figure
to be drawn)
The truth table for the Sn Rn NAND Latch:
Sn
0
0
1
1
Rn
0
1
0
1
Q
Forbidden Inputs
1
0
Previous Output
A Verilog Module for the Sn Rn NAND Latch
module rs_latch(
input r_n;
input s_n;
output q;
22
output q_n;
);
assign q=!(s_n*q_n);
assign q_n=!(r_n*q);
endmodule
25
The D Flip-Flop
The D flip-flop is a basic flip-flop that is frequently used internally to construct more complex logic chips. The D stands for delay. When the data pin
is set it does not transfer its value to the output pin Q immediately. This
occurs on the next rising clock edge sensed at the clock pin. So the output is
”delayed.” The D flip-flop may be built from SR NAND Latches. See below
for the use of the dual D type positive edge triggered flip-flop SN74LS74AN,
to produce a symmetric square wave from a nonsymmetric 555 pulse train,
and which functions as a divide by two counter.
Flip-flops are event triggered devices, so are not purely combinatorial logic
devices. Action takes place on the event of a rising edge clock signal. The
verilog HDL (Hardware Definition Language) does deal with event triggered
devices.
26
A Verilog D Flip-Flop
This program demonstrates verilog’s ability to deal with event driven devices.
This ability is demonstrated below in the ”always” statement.
Verilog D Flip-Flop
1
2
3
4
5
6
7
8
9
10
// D flip-flop Code
module d_ff ( d, clk, q, q_bar);
input d ,clk;
output q, q_bar;
wire d ,clk;
reg q, q_bar;
always @ (posedge clk)
begin
q <= d;
23
11
q_bar <=
12 end
13
14 endmodule
27
! d;
The D Latch
The D latch is not an event driven device, there is no clock signal. So it is
a purely combinatorial logic device. The D latch may be constructed from a
Sn Rn NAND latch and is nearly equivalent to what is called a Sn Rn NAND
latch with enable ( See Wakerly). The D latch has two inputs, D and G
and two outputs Q and Qn . The three wire statements below define local
variables in the following verilog program (As I write this I have not yet tried
to run the following program in ISE, so it may well contain errors. I do not
know if verilog distinguishes between upper and lower case. I assume it does,
and I assume mixing lower and upper case will cause compiler errors. It is
easy for me to do such mixing. )
Verilog D Latch
module D_latch (
input D;
input G;
output Q;
output Q_n;
);
wire S_n;
wire R_n;
wire D_n; // I assume this is necessary?
assign D_n = !D;
assign S_n =!(G*D_n);
assign R_n = !(D*G);
RS_latch(R_n,S_n,Q,Q_n);
endmodule;
24
28
Constructing A D Flip-Flop With a Pair
of D Latches
So a D Flip-Flop is an event triggered device. It is slightly amazing that
by adding a simple clock input and using two combinatorial D latches, we
can construct an event driven device that reacts to rising clock edges. Event
driven devices can not be described by simple truth tables, but we need to
display their action with timing diagrams. They are sequential machines and
have a state, and a next state function.
Verilog D Flip-Flop Using the D Latch Module
module D_Flip-Flop (
input D;
input C;
output Q;
output Q_n;
);
wire Q1;
wire Q1_n;
wire C_n;
assign C_n = !C;
D_latch(D,C_n,Q1,Q1_n);
// According to the notes, there is a subtlety here in assigning
// Q_n caused by a glitch in the timing diagram, but I
// don’t recall the details.
D_latch(Q1,G,Q,Q_n);
endmodule;
29
The JK Flip-Flop
The JK flip-flop is like a D flip-flop, but has two inputs, with labels J and K.
Let Q be the output. If J and K are different, then the output Q takes the
value of J at the next clock edge. Put another way if J and K are different
then J high sets the output to 1, and K high resets the output to 0. If J
and K are both low then no change occurs. If J and K are both high at
25
the clock edge then the output will toggle from one state to the other. The
characteristic equation is
Qnext = J Q̄ + K̄Q.
30
Multivibrator and Latch
A latch and a multivibrator are circuits related to flip-flops. A latch is not
triggered by a clock pulse, as the flip-flop is.
A multivibrator is a somewhat more general device, and can be used in
both digital and in analog circuits. It was used long before digital electronics
was invented. In an analog circuit it may be used as a square wave oscillator.
So for example, the rectangular horizontal and vertical sync pulses in analog
television signals are generated by multivibrators. It was called a multivibrator because the square pulses it generates has many harmonics (Fourier
components) and so many multivibrations.
31
The Wilkson Digital Logic Test Board
This digital test board is used to test, study, and design digital circuits. The
printed circuit board is constructed to be mounted onto a plastic breadboard.
Pins on the bottom of the PCB fit into the breadboard. External connections
are made from a series of pins mounted to the PCB.
31.1
Power: A Nine Volt Wall Wart Power Supply
There is a jack on the PCB that accepts a 1/8th inch plug from a nine volt
DC power supply. The wall wart we are using is a Jameco (see below).
31.2
Five Volt and Three Volt Regulated Power Supplies
Five volts is available for powering TTL chips. This voltage is supplied with
a 7805, a five volt voltage regulator. As an aside, although this regulator is
designed to provide a regulated five volts, it can be tricked into supplying
other regulated voltages. The LM7805 is a three pin chip with a metal plate
26
on the back that may be attached to a heat sink with a screw through the
hole in the plate. This chip can get hot. Looking at the chip from the front,
the pin on the left is the input pin. It is connected to an unregulated positive
voltage at a higher voltage than 5 volts. In our case this voltage is being
supplied by the positive nine volts from the wall wart. See the data sheet
for the allowed input voltage range. The center pin is the ground pin. The
right pin is the output pin where the regulated five volts is available.
A 3.3 voltage is on the board for supplying CMOS chips. This voltage is
supplied with a LM317 voltage regulator. The LM317 is a variable voltage
regulator. Here external components are selected to make it have an output
of 3.3 volts. This is done as follows in the following way. First note that the
pin order for the 317 differs from that for the LM7805. Looking at the front
of the chip, the left pin is called the adjustment pin, which is connected to
a resistor called R2 , and also is connected to a second resistor and then the
resistor is to ground. The center pin is the output pin where the regulated
voltage is available. The right pin is the input pin, in our case connected to
the nine volt unregulated voltage from the wall wart. This voltage can be in
a range described in the data sheet. The LM317 has the property that the
voltage at the output pin is always at 1.25 volts above that at the adjustment
pin. There is a resister R1 between the output pin and the adjustment pin.
These two resistors R1 and R2 determine the magnitude of the regulated
output voltage. So let iq be the current flowing from the adjustment pin.
Let i2 be the current flowing through resistor R2 to ground. Let i1 be the
current flowing through R1 from the output pin to the adjustment pin. Then
the current flowing through resister R2 is the sum of the current flowing from
the chip to the adjustment pin, and the current flowing through R1 . That is
i2 = iq + i1 .
But as stated above, the voltage across R1 is always maintained at 1.25
volts. Therefore
1.25
R2 .
i1 =
R1
Let the voltage v2 be the voltage across resistor R2 ,
v2 = i2 R2 = (iq + i1 )R2
= iq R2 +
27
1.25
.
R1
Let v0 be the voltage at the output pin. Then
v0 = 1.25 + v2
1.25
R2 + iq R2
R1
= 1.25(1 + R2 /R1 ) + iq R2 .
= 1.25 +
However the current out of the chip into the adjustment pin is very small, so
we can write approximately that
vO = 1.25(1 + R2 /R1 ).
In our circuit we have specified R1 = 240 and R2 = 390 Ohms. So the
regulated output voltage is
vO = 1.25(1 + 390/240) = 3.28volts.
31.3
The 555 Timer Subcircuit
A clock pulse is supplied with a 555 timer. This LM555 circuit here creates
a rectangular wave of frequency controlled by a potentiometer. It runs in
what is referred to in the National Semiconductor data sheet, as the astable
mode. A nice reference for the way the 555 works internally is the book
Make: Electronics by Charles Platt. A resistor RA is connected between
pin 8 and pin 7 of the 555. Pin 8 is connected to the 5 volt positive supply
voltage. A resistor RB connects pin 7 to pin 6. A capacitor C connects pin
6 to ground. The wave is controlled by the charging and discharging of C
through the resistors. When the output signal is low the internal flip-flop
grounds pin 7 and also grounds the output pin 3. In this part of the cycle the
capacitor is discharging from a voltage equal to 2/3 of the supply voltage to
a voltage equal to 1/3 of the supply voltage. This voltage on the capacitor
is fed back to the pin 2 input of the 555. When the voltage at pin 2 reaches
1/3 of the supply voltage, a comparator connected to pin 2 flips the flip-flop
to disconnect pin 7 from ground and also connects the output pin, pin 3 to
the 5 volt supply voltage. This does two things, starts a positive pulse in
the output signal, and also causes the capacitor to be charged through the
resistors RA and RB . When the capacitor reaches 2/3 of the supply voltage,
a comparator connected internally between pins 6 and 5 turns on and flips
the flip-flop back to restart the cycle.
28
See ee.pdf (source ee.tex) for an analysis of the charging and discharging
on STEM2 for the latest version. See also a current version in the Appendix.
It is shown there, in the section on the RC circuit, that the frequency of the
wave is given by
f=
1/ ln(2)
1.4427
=
,
C(RA + 2RB )
C(RA + 2RB )
which is a formula that also occurs in the National Semiconductor data sheet
(pp6-7) for the LM555. In the version of the astable circuit that we are using
here, pin 6 and pin 7 are joined, so that the effective value of RB is very
small. This makes the discharge very fast so that the low pulse is very short,
and the high pulse is nearly the entire period of the wave. So the frequency
then is
1.4427
.
f=
CRA
In our circuit the resistor RA is a 1k resistor in series with a 100k potentiometer. If we use C = .1µF then we may adjust the frequency between
f1 =
1.4427
= 1.44 × 104 = 14.4kHZ
(.1 × 10−6 )(1000)
and
f2 =
1.4427
= 142.8Hz.
(.1 × 10−6 )(101 × 103 )
On the other hand if C = 100µF then the frequency ranges from
f1 =
to
f2 =
31.4
1.4427
= 14.4HZ
(100 × 10−6 )(1000)
1.4427
= .142HZ
(100 × 10−6 )(101 × 103 )
Properties of Light Emitting Diodes
Light Emitting Diodes emit photons when they are forward biased. Too much
voltage will cause too much current and heat and will destroy the diode. So
a resistor of small value is placed in series to limit the current. So suppose
a LED is connected in series with a resistor R = 270Ω to a five volt voltage
29
source. In a specific circuit we measured a voltage drop across the resistor
of 3.2 volts. This means that the voltage drop across the diode was
v = 5 − 3.2 = 1.8.
So an LED usually drops on the order of 2 volts. This voltage drop does
depend on the current. In this case the current was
i=
3.2
= 11.9mA.
270
So the diode was dissipating
(1.8)(11.9) = 21.42mW.
This energy loss is in the form of both light and heat.
The long lead of a LED is usually positive, the short end negative. Most
multimeters have a socket for testing diodes. They can also be tested and
the polarity checked by checking their resistance with a multimeter.
31.5
Switches and Push Buttons
The board contains two sets of toggle switches, (the white switch blocks)
and two black push button switches. The toggles may be placed into three
states. These switches may be used to set certain binary constants and for
controlling data and setting values on chips. I believe that pushing a black
button connects one of the external pins to ground.
31.6
Storing A Logic State With A Switch
Suppose the logic high voltage is v = 5 volts. Consider such a voltage
connected to a resistor R = 10k, in series with a switch and the switch
connected to ground. The value stored is the voltage at the junction of the
resistor and the switch. If the switch is open the current flowing through the
resistor is near zero, so the voltage is high at 5 volts. If the switch is closed,
the resistor junction is connected to ground, so the output is 0 volts. So an
open switch stores a logic value 1, and a closed switch stores a logic value
zero. With the switch closed the current is
i=
5
= .5 × 10−3 A = .5mA.
10000
30
31.7
Viewing A Logic Value With an LED
Suppose an LED has its positive terminal connected to a positive source
voltage, and its negative terminal to a node whose voltage level is to be
measured. If the level is high, then no current flows and the LED is not on.
If the level is low, then current flows through the diode and the LED is on.
A resistor is needed in series with the LED to limit the current. A resistor
of value about 270Ω will limit the current and prevent the destruction of the
LED. It would be better if the LED glowed with a high voltage. This can
be accomplished by confecting a logic inverter between the node being being
read, and the LED. The LED will now glow when the signal is high, and turn
off when the signal is low. A line driver inverter may be used, one such as
the 74LS74, which also contains an amplifier, with high input impedance to
limit the current draw from the circuit element whose voltage is measured.
31.8
Resistor Arrays
A resistor array is a collection of several resistors in one package. Typically
it looks like a long bug with a single row of pins. One pin labelled with a dot
is the common terminal, and usually has a square pin. The resistance from
the common pin to each of the other pins is some fixed resistance, say 270Ω.
Such an array might be used to serve as the resistors for a set of LEDs.
31.9
The 74LS163 Synchronous 4-Bit Binary Counter
An example part number for a synchronous 4-Bit Binary Counter is the
National semiconductor DM74LS161A. The Texas Instruments data sheet
for the SN74LS163A has been stored as a local file with name 74LS163ti.pdf.
The chip has 16 pins. Here is a list of them:
The Pins for the Fairchild DM74LS163A:
31
1
CLR
2
CLK
3
A
4
B
5
C
6
D
7
ENP
8
GRD
9 LOAD
10 ENT
11
OD
12
OC
13
OB
14
OA
15 RCO
16 VCC
A explanation of the pins:
CLR if this is low, zero levels are entered in the outputs OA, OB,OC,OD.
CLK The state change takes place during a rising edge of the clock pulse.
ENP The Clock is active only if this enable is high.
GRD The negative ground supply connection
LOAD when this value is low the A, B,C,D values are copied to the outputs
OA, OB,OC,OD.
ENT The clock is active only if this enable is high. The ripple carry requires
a high value here.
RCO Ripple Carry Output. This pin is set high when all four output pins
OA, OB, OC, OD are high and ENT is high.
VCC the positive supply connection
There is some good material on the 163 binary counter in the book
Digital Design by John F. Wakerly, pp 595-607.
An example use of the 163.
Here is a circuit that will turn on the
output pins in sequence, and then turn them off in sequence, and then re32
peat the cycle. Suppose ENP and ENT are permanently held high, LOAD is
permanently set low, and the following pairs are connected. OA is connected
to B, OB to C, OC to D, and an inverted OD to A. The CLR pin is connected to one of the two push buttons On the breadboard. The connecting
wire from is connected to hole j2 on the breadboard. When the button is
pressed CLR is connected to ground and thus causes zeroes to be copied
to the outputs. So suppose in the beginning all outputs OA, OB, OC, OD
are low. Because OD is complemented and copied to A, A will be high.
Now the LOAD pin is always low, so on the next clock pulse the values
at the data pins A, B, C, D are copied to the outputs OA, OB, OC, OD.
In the beginning the data pins B, C, D are low. So after the clock pulse
the outputs OA, OB, OC, OD = 1000. These are connected to LEDs so
only the first LED is lit. Now because of the feedback connections to the
data pins A, B, C, D, these pins now have the values A, B, C, D = 1100.
During the next clock pulse these values are copied to the outputs, so now
OA, OB, OC, OD = 1100, and after the next pulse OA, OB, OC, OD = 1110,
next OA, OB, OC, OD = 1111. Now we have a change, since OD = 1 causes
A = 0. So after the next clock pulse OA, OB, OC, OD = 0111. Now the
same way in which the one was propagated to the other positions, the zero
gets propagated, until eventually OA, OB, OC, OD = 0000. Now the whole
cycle starts over.
31.10
74LVC540 Buffer-Line driver
One may use the internet to find the data sheet for this chip. Such a data
sheet has been stored as a local PDF file on my computer with the name
74LVC540.pdf. This is a CMOS surface mount chip.
See all about circuits, buffers:
http://www.allaboutcircuits.com/vol_4/chpt_3/3.html
31.11
The Subcircuit That Drives the LEDs on the
Printed Circuit Board
Refer to the notes for December 31, 2011. A diagram will be drawn. From
this circuit diagram we see that the node between each LED and its current
limiting 270 Ohm resistor is not accessible. Therefore the LRDs can not be
dimmed by switching in another resistor. So the only means to dim the LEDS
33
/CLR
VCC
CLK
RCD
D0
Q0
D1
Q1
74LS163
D2
Q2
D3
Q3
ENP
ENT
GRD
/LD
Figure 3: LS163 4-bit binary counter example. Here is the sample
circuit for turning on LEDs in sequence, then turning them off as described
in the text. The enable pins ENP and ENT are permanently set high so that
the clock is always enabled, the load pin is permanently low so that load is
always active, the CLR can be set low with a push button, but appears to
be unnecessary. The output pins are connected to LEDs, so the LEDs cycle
on, then cycle off one by one.
34
is to use a high frequency pulse width modulation signal with an adjustable
duty cycle.
31.12
Testing the Wilkson Board With an SN74LS74AN
The SN74LS74AN or DM74LS74A is a dual D type positive edge triggered
flip-flop. The rising edge of the approximately 2 µ second off pulse from the
555 is used to get a symmetric square wave of 1/2 the frequency of the 555.
A rising edge from the 555 signal causes a count of 1, so turns on a
positive pulse. When the next rising edge is encountered, whatever is at
D is copied to the output Q. And the complimentary value is copied to Q̄.
This complimentary value is fed back to the D input, so that on the next
rising input the value at Q will be the compliment. Thus the output changes
from high to low, then low to high, then high to low and so on. This is the
divide-by-two counter, see Mims Engineer’s Notebook II p53.
The SN74LS74AN may also be used as a line driver and inverter.
The Pins for the Fairchild DM74LS74A:
1 CLR1
2
D1
3 CLK1
4
P R1
5
Q1
6
Q1
7 GRD
8
VCC
9 CLR2
10
D2
11 CLK2
12 P R2
13
Q2
14
Q2
Explanation of pins:
If CLR is low, Q is Cleared to 0 and Q to 1.
CLK The value at D is copied to Q during a rising edge of the clock pulse.
35
If PR is low, Q is Preset to 1 and Q to 0.
GRD The negative ground supply connection.
VCC the positive supply connection.
If CLR and PR are both high, they are disabled.
31.13
The Solderless Breadboard
The PCB fits on top of a Jameco Solderless Breadboard JE24 which has
1360 contact points, a red power strip near the center of the board with 100
contacts along the length of the board, and a similar blue power strip. The
board measures 6.5 by 3.25 (actually 6.5 by 3.125) inches and has two binding
posts, which are removed to make way for the PCB. The contact points on
the left side have coordinates (A,1) to (J,63) and the same coordinates on
the right side. Looking at the board so that the two binding posts are at
the top, there a 63 rows of contact points, each row is divided into 4 sets of
5 contacts. Each 5 contacts are connected together. In each row, the first
five contacts on the left have letter labels a,b,c,d,e. across the trough, the
next set of five have labels f,g,h,i,j. Then going across the center blue and
red vertical power strips in the center of the board, we find on the right side
of the board, two more sets of five labelled a,b,c,d,e, then across the trough
the set f,g,h,i,j.
31.14
The pins from the PCB to the Breadboard
On the right side of the breadboard, contacts j1 to j4 connect to the two black
push-buttons in ways that depends on whether they are presses or released.
Contact j6 connects to the output pin of the 555, so is the clock signal. j7
and j8 connect to the capacitor that controls the frequency of the 555 clock.
j8 is the negative connection, and j7 is the positive. j11 connects to the first
red LED (the one nearest the top of the breadboard), j12 to the second, j13
to the third, j14 to the fourth, j15 to the fifth, j16 to the sixth, j17 to the
seventh, and j18 to the eighth.
On the left hand side of the board, a1,...a8 connect to points between
the toggle switches and the resisters in a resistor array to store logic values.
a10,...a17 connect to points between the toggle switches and the resister in
a resistor array to store logic values.
36
Setting the toggle switches .... has the following effect:
31.15
The Xilinx CPLD
The Xilinx XC9536XL chip is a CPLD (Complex Programable Logic Device)
mounted into a socket on the PCB. The data sheet for the XC9536XL can
be found on the internet. I have stored a copy as file
xc9536xl.pdf
31.16
The Circuit Board Pin Assignment for the XC9536XL
CPLD
Here is a file showing the connections to the XC9536XL pins:
http://www.stem2.org/je/IO_Board_v100_CPLD_Pinout.pdf
32
MUX, The Multiplexer and Demultiplexer
MUX is Short for multiplexer. A multiplexer has n inputs, 1 output, and a
select pin or pins. From a select signal, it selects from a number of inputs
and sends the selected input to a single output.
DMUX is Short for demultiplexer. This is the inverse of a MUX. A demultiplexer has 1 input and n outputs with a select pin or pins. From a select
signal it selects one from n output ports, and sends the single input signal
to the selected port.
See the Wikipedia article on multiplexers. It gives a list of common 7400
series multiplexer and demultiplexer chips.
33
Programmable Logic Devices
CPLD is an abbreviation for ”Complex Programmable Logic Device.”
A Xilinx XC9536XL chip is part of the test circuit board.
Xilinx
XC9536XL
PCG44AWN1029
37
F4109624A
10C
Xilinx supplies free software, called ISE, for programming this chip and
other chips. A digital circuit can be constructed with the software using
either a schematic design process or a verilog text program. Then this circuit
is downloaded from the computer to the chip to create physical hardware in
the chip.
A huge number of logic devices are available in the Xilinx software. For
example, we constructed in class a 163 binary counter circuit, using a Xilinx
library module for the 163. We then downloaded it to the chip, using a
special wiring connector belonging to Chris.
Other Programmable Logic Array Acronyms: PAL ”Programmable
Array Logic”, FPGA ”Field Programmable Gate Array.”
Here is a link for downloading the programming software from Xilinx:
http://www.xilinx.com/support/download/index.htm
The download file is huge, being about 5 GBytes. Transferring the downloaded file to another computer via a flash drive can be a problem, because
flash drives tend to be formatted as FAT32. This format can only handle files
that are less than 4 GBytes. However, if the tar file is untarred, we obtain
a folder containing many smaller files, which can be handled in the FAT32
Windows format.
34
Installing and Using the Xilinx ISE Software
The software installation can be a bit complex. The software is free, but a
licence file must be obtained from the Xilinx WEB site. After registering, a
file is mailed to your email address. This file is required in order to make the
software work.
The best way to learn how to install the software, and to run the GUI
(Graphical User Interface), is to have someone familiar with the software
help you. It is a myth that GUI software is easy to use, especially if it is
rather complex software. Don’t be shy about asking for help. After all it is
38
just stupid software, running on a stupid computer. Those who think they
are geniuses because they know how to run a software program, or a candy
vending machine for that matter, should seek psychological help.
One might blunder through with madcap clicking, and yet not remember
what was clicked. It is rather difficult to record the icon clicking steps, in
the same way as it is difficult to record all of the keys presses when learning
to play Scarlatti, by watching Vladamir Horowitz. The secret to learning
this sort of thing, is to have a skilled music teacher show you how, and then
practice, practice, practice. After that, you will be able to tell people how
to get to Carnegie Hall.
There are some tutorials available for Xilinx ISE on the internet. See the
links below and a pdf copy of the html tutorial. The tutorial shows how to
build a half adder from primary logic gates.
After the program for the logic has been created with the software, it
is downloaded from the PC to the physical chip. There is a special wiring
harness for downloading this data. This harness is quite expensive, although
there appears to be a cheap Chinese knockoff available.
35
Class Exercise: Create a D Flip-Flop With
ISE
As an exercise, using the Xilinx ISE software, create two D latches and
connect them as described above to make a D flip-flop. Download it to your
board and test it.
36
A Data sheet for the 74LS163 4-bit Binary
Counter
The Fairchild version of this 4-bit Binary Counter is named the DM74LS163A.
The Texas Instruments data sheet for their version of this chip is stored on
my computer as
74LS163TI.pdf
39
37
More Information About Chris Wilkson’s
Printed Circuit Board: Assembly Order,
Images, Bill of Materials.
Here are some links to information about Chris Wilkson’s printed circuit
board from the Digital Electronics Class of 2011. First is a list of a suggested
assembly order. This is obtained from the following link to a document
called Assembly Order of Wilkson’s Circuit Board, which gives suggestions about the order of soldering on components, together with various
other notes.
http://www.stem2.org/je/assemblyorder.pdf
Next are images of a Top View and Bottom View of the completed board:
http://www.stem2.org/je/toppcb.jpg
http://www.stem2.org/je/botpcb.jpg
Here is a Bill of Materials for the board:
http://www.stem2.org/je/IO_Board_v100_BOM.pdf
These files can also be reached by going to the stem2 web site:
http://www.stem2.org
Select Downloads and Documents, and then Electronics.
40
38
A Sequential Machine: A Three Bit Binary Counter
See notes Dec 31, 2011. The three bits are stored in three D-Flip-Flops. The
single input resets the Flip-Flops to zero when it is zero. The current state
is D = 0, 1, 2, 3, 4, 5, 6, 7. The next state function is Q = D + 1. So the truth
table is
The truth table is:
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Q2
0
0
0
1
1
1
1
0
Q1
0
1
1
0
0
1
1
0
Q0
1
0
1
0
1
0
1
0
Let us find the next state bit functions for the three bits of Q = Q2 Q1 Q0
.
Q2 = D2 D1 D0 + D2 D1 D0 + D2 D1 D0 + D2 D1 D0
= D2 D1 D0 + D2 D1 D0 + D2 D0
= (D2 D1 + D2 D1 )D0 + D2 D0
= (D2 ⊕ D1 )D0 + D2 D0
The Quine-McClusky applet I mentioned above finds
Q2 = D2 D0 + D2 D1 D0 + D2 D1 .
39
Test Instruments and Tools for Digital Electronics
The following test instruments and tools are useful for digital electronics. A
soldering station with a grounded tip. A digital multimeter. Cheap multimeters are available at Harbor Freight for sometimes the unbelievable price
41
of 3.95 dollars. A nicer model at 19.95 measures capacitance and comes
with a thermocouple for measuring temperatures. A cheap solder sucker
(spring loaded) can be purchased at the MicroCenter computer store for a
few shekels, four bucks or so. A good oscilloscope is also quite useful. I also
purchased a cheap capacitance and inductance meter on the internet. Flush
cut diagonal pliers are cheap at harbor freight. Also Harbor freight carries a
set of cheap jeweller eye loupes, which prove quite handy for reading the microscopic printing on many electronic components. A logic pulser and probe
could be very useful.
40
Download Cable
From Tim Middleton:
Friday, December 2, 2011 7:00 PM
Sweeet!
It came in the mail today weeeeeeeeeeeee.........
Gonna try using it after dinner.
Sent from my iPad
On Nov 20, 2011, at 2:49 PM, tim middleton <versonova@gmail.com> wrote:
> Electronics class. . .
>
> I have located and ordered a DLC9G (DownLoadCable) for programming the
CPLD chips we have been working with in class. I feel I have learned
enough to move forward with having my own programming cable so
I ordered it this morning.
>
> It will arrive some time in 2011 from Hong Kong . . . if there are
any of you that are also interested in programming these chips at
home on your own. . . .
>
> here is the link to the company I ordered mine from here
> http://www.ebay.com/itm/200539866123
> the total was 42 plus 7 dollars shipping this includes having the
flying leads connector.
> I expect it to get here some time in the middle of December.
>
> For some reason the DownLoadCable from Xilinx are approx 225 each. from avnet . . .
>
> http://avnetexpress.avnet.com/store/em/EMController/Development-Tools/
Xilinx/HW-USB-II-G/_/R-7532182/A-7532182/An-0?action=part&catalogId
=500201&langId=-1&storeId=500201
>
> Chris has his DLC9G. We will be attempting to find a reliable
way to get one for the cave if the one I ordered works out it might
be cool to order another for the cave. When mine comes in I will
42
be happy to share it.
> If it is possible to construct a parallel cable based one for
the cave we might move in that direction.
>
> From what I spoke with Chis about yesterday the unit is older
is likely a "pirated" unit for it to be as cheap $41 as it is
compared to the unit for sale linked from Xilinx site on Avnet the model Chris has is authentic and out of production what is
offered on the Avnet site is version 2 and is newer in many ways .
http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm
>
> Thanks Tim
41
PCB Artist
This free program was used to construct Wilkson’s printed circuit board. The
board design was sent to China where one hundred boards were fabricated
for about ten dollars each.
42
LT Spice
This free electrical circuit simulator is a very good version of Spice. This
package can also generate schematic diagrams. In fact the usual way of
using it is to construct a circuit diagram graphically and then instructing
it to be run with specified conditions. This contrasts with other versions of
Spice that run from a net list, which is a text file specifying the circuit. A
net list can be output from LT Spice. Output may be viewed as graphs and
related to oscilloscopes displays of physical circuit signals.
43
A List of 7400 Series Integrated Circuits
Query Wikipedia for this list. A local version
listof7400integratedcircuits.pdf
is on my computer.
43
44
A Class Design Project: Controlling Thunderbird Tail Lights
The taillights on this car consist of three lights on the left tail light and three
lights on the right tail light. When a switch for a left turn is on, the three
lights blink so that the inside light 1 is on, then 1 and 2 on, and finally 1
2 3 are on, then this repeats, so indicating a turn to the left. Same type of
behavior for a right turn. When a hazard light switch is on, all lights blink
1 second on, then 1 second off. When parking, the parking lights are to be
at half intensity. From my notes I can’t really reconstruct all of the required
behaviors. The lights are to be controlled by the dip switches on the PCB
board, and the push buttons. I think there are brake lights involved too, but
don’t recall the details. The project is to be completed either with hardware
chips, or by using the ISE software to create a program for the Xilinx CPLD
chip.
45
Appendix A, RC Circuits, Time Constants,
and the LM555 Timer
The following section occurs in my document called Electrical Circuits,
which appears on the STEM2 website as ee.pdf. See that document for the
latest version.
45.1
A Resistor Capacitor Circuit and the Time Constant
Discharging a Capacitor. Consider a capacitor C with charge q(0) at
time t = 0 connected to resistor R. The voltage drops around the circuit are
zero. So
dq
q
R + = 0.
dt C
or
q
dq
+
= 0,
dt RC
and so
dq
dt
=−
q
RC
44
Integrating both sides we have
ln(q) = −
t
+ k,
RC
where k is a constant of integration. Taking the exponential we have
q(t) = exp(−t/RC) exp(k).
Evaluating at t = 0 we see that
exp(k) = q(0),
So
q(t) = q(0) exp(−t/RC).
and
q(t)
= exp(−t/RC).
q(0)
tc = RC
is called the time constant. So in one time constant
1
q(t)
= exp(−tc/RC) = = .3679.
q(0)
e
So the charge has decayed to about 37 per cent of its initial value. In five
time constants it will have decayed to
1
= .0067
e5
of its initial value. So the capacitor discharges about 100−37 = 63 percent of
its initial charge in one time constant. The energy of the capacitor is stored
in the electric field between the capacitor plates. The energy density of the
field can be shown to be
E·D
,
2
and so the total energy of the capacitor could be computed by integrating this
expression over the volume between the capacitor plates. For the definitions
of the electric fields E and D see the document mentioned above called
45
Electromagnetic Theory. As the capacitor discharges, this field energy is
dissipated as heat in the resistor due to the current flow through it.
The RC Circuit. Suppose a circuit consists of a voltage source of magnitude
ε in series with a capacitor C and a resistor R. The voltage drops around
the circuit give us the equation
iR +
q
= ε.
C
That is
q
ε
dq
+
= .
dt RC
R
We can convert the left side to a derivative of a function by multiplying by
the integrating factor et/(RC) , and then we are able to integrate to solve our
problem. So we have
q t/(RC)
ε
dq t/(RC)
+
= et/(RC) .
e
e
dt
RC
R
d
ε
(qet/(RC) ) = et/(RC) .
dt
R
Integrating, we have
qet/(RC) =
ε
R
e−t/(RC) dt =
ε
(RCet/(RC) + K),
R
where K is a constant. We have at time t = 0
q(0) =
so
K=
Then
ε
(RC + K),
R
ε
q(0) − RC.
R
q(t) = εC + (q(0) − εC)e−t/(RC) ,
is the general solution of the RC circuit.
The capacitor discharges when the source voltage is shorted so that
ε = 0.
Then as above we get
46
q(t) = q(0)e−t/(RC) .
Charging a Capacitor. Consider that the initial charge on the capacitor
is q(0) = 0. Then
q(t) = εC(1 − e−t/(RC) ).
The final charge reached when t = ∞ is qf = εC. In one time constant
RC, the charge on the capacitor is
q(t̄) = qf (1 − 1/e),
which is about
qf (1 − .37) = .63qf .
So the time constant is the time it takes to charge the capacitor to about 63
percent of its final value.
So in conclusion, the time constant RC is the time it takes for a charged
capacitor C to dissipate about 63 percent of its charge through a resistor R,
and on the other hand the time for an initially uncharged capacitor to reach
about 63 percent of its final charge.
Example, The frequency of a 555 timer in astable mode The 555
timer in astable mode charges from 1/3 of the supply voltage ε, to 2/3 of the
supply voltage through a resistor R1 for period t1 , then discharges through a
different resistor combination of value R2 from 2/3 of the supply voltage to
1/3 of the supply voltage for period t2 . The period of the oscillation is then
t = t1 + t2 .
Consider the time it takes to charge up from voltage v0 = ε/3 to voltage
v1 = 2ε/3. That is from charge
q(0) =
εC
,
3
q(t1 ) =
2εC
.
3
to
That is
2εC
= q(t1 ) = εC + (q(0) − εC)e−t/(RC)
3
47
= εC + (
Thus
So
εC
− εC)e−t1 /(RC) .
3
1
2
= 1 + ( − 1)e−t1 /(RC) .
3
3
2
1
− = − e−t1 /(RC) .
3
3
Then
et1 /(RC) = 2,
and
t1 = RC ln(2).
Now let us compute the time it takes discharge the capacitor from voltage
v2 to voltage v1 . The discharge equation has a zero source voltage, that is
ε = 0. Let t2 be the discharge time. We have
q(t2 ) = q(0)e−t2 /(RC) ,
where
q(t2 ) =
εC
,
3
q(0) =
2εC
.
3
and
So
1
2
= e−t2 /(RC) .
3
3
So
et2 /(RC) = 2.
So
t2 = RC ln(2).
Now suppose the capacitor charges through resistor R1 , and discharges
through resister R2 . Then the period of oscillation is
T = t1 + t2 = C(R1 + R2 ) ln(2).
48
The frequency is
ν=
1/ ln(2)
.
C(R1 + R2 )
We have
1/ ln(2) = 1.4427.
So
ν=
1.4427
.
C(R1 + R2 )
Referring to the National Semiconductor data sheet for the LM555, page
7-8, which gives a a circuit for the astable or oscillatory mode of the 555,
there is a resistor RA connecting the positive supply voltage at pin 8 to pin
7. A second resistor RB connects pin 7 to pin 6. A capacitor C is connected
between pin 6 and ground. So the capacitor charges through R1 = RA + RB
and discharges back through R2 = RB . Thus
R1 + R2 = RA + 2RB
So the astable frequency is
ν=
1.4427
,
C(RA + 2RB )
as given in the data sheet.
46
Appendix B, A Xilinx ISE Tutorial
A tutorial featuring a design of a half-adder is at the following link:
http://strumpen.net/xilinx/tut82i/ise.html
Here is a link to a pdf copy:
http://www.stem2.org/je/isetut.pdf
This tutorial is for an earlier version of the ISE software, and for a device
that is not our Xilinx XC9536XL.
Beginning Steps of the Tutorial:
49
1. Select New Project to get the new project wizard.
2. Fill in the project name box, project location box, and the Top Level Source Type
(schematic). Select next.
3. Now see the device properties window. Perhaps change device family and device.
4. Select next a couple of times, then finish.
5. A new project hierarchy is displayed in the Sources Window portion of the
project window.
6. You can browse through that directory by selecting the Open Project
item in the File menu of the Project Navigator.
7. In the ‘‘Processes’’ window of the Project Navigator, cf. Figure 3, double click
on the entry entitled Create New Source. (Alternatively, pull down the Project
menu and click on New Source.) Select source type Schematic and enter in File
name ‘‘halfadder’’, as shown in Figure 4 below.
8.
Click Next and Finish. The Project Navigator window now shows the
‘‘Design Summary’’ of the Schematic Editor, see Figure 5. To switch
to the drawing area of the Schematic Editor click on the halfadder.sch tab
at the bottom of the ‘‘Workspace’’ window.
Later in the design process,
clicking on that file name in the Project Manager will automatically
start up the Schematic Editor.
47
Appendix C, Introduction to the Verilog
Hardware Design Language
Verilog is a hardware description Language. Its syntax is like that of a
programming language. The Xilinx ISE program can use Verilog to create a
digital logic design.
Hello World Program
1
2
3
4
5
6
7
8
9
//----------------------------------------------------// This is my first Verilog Program
// Design Name : hello_world
// File Name : hello_world.v
// Function : This program will print ’hello world’
// Coder
: Deepak
//----------------------------------------------------module hello_world ;
50
10 initial begin
11
$display ("Hello World by Deepak");
12
#10 $finish;
13 end
14
15 endmodule // End of Module hello_world
48
Appendix D, Running Icarus Verilog From
The Command Line in Windows
The following file is a Verilog program by the author of Icarus Verilog,
which on windows is available as a command line program. The comments
at the beginning of the file show how to run the program in Unix or Linux.
The example is a hardware square root program. To run the windows version,
the two programs iverilog.exe and vvp.exe must be in the current path.
If not, run them from the iverilog bin directory.
For windows:
iverilog -osqrt sqrt.vl
vvp sqrt
File listing:
/*
* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
*
*
This source code is free software; you can redistribute it
*
and/or modify it in source code form under the terms of the GNU
*
General Public License as published by the Free Software
*
Foundation; either version 2 of the License, or (at your option)
*
any later version.
*
*
This program is distributed in the hope that it will be useful,
*
but WITHOUT ANY WARRANTY; without even the implied warranty of
*
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
GNU General Public License for more details.
*
*
You should have received a copy of the GNU General Public License
*
along with this program; if not, write to the Free Software
*
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
51
*
*/
$Id: sqrt.vl,v 1.4 2004/10/04 01:10:56 steve Exp $"
/*
* This example shows that Icarus Verilog can run non-trivial
* programs, too. This uses a variety of Verilog language features
* to implement the module of a square-root device. The program
* uses IEEE1364-1995 language features and should work correctly
* on any Verilog compiler.
*
* Run the file with Icarus Verilog under UNIX using the command:
*
*
% iverilog -osqrt sqrt.v
*
% ./sqrt
*/
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* to big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
*
x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt32(clk, rdy, reset, x, .y(acc));
input clk;
output rdy;
input reset;
input [31:0] x;
output [15:0] acc;
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
reg [15:0] acc;
reg [31:0] acc2;
// Keep track of which bit I’m working on.
reg [4:0] bitl;
wire [15:0] bit = 1 << bitl;
wire [31:0] bit2 = 1 << (bitl << 1);
52
// The output is ready when the bitl counter underflows.
wire rdy = bitl[4];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
//
guess2 = (acc + bit) * (acc + bit)
//
= (acc * acc) + 2*acc*bit + bit*bit
//
= acc2 + 2*acc*bit + bit2
//
= acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [15:0] guess = acc | bit;
wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
task clear;
begin
acc = 0;
acc2 = 0;
bitl = 15;
end
endtask
initial clear;
always @(reset or posedge clk)
if (reset)
clear;
else begin
if (guess2 <= x) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 1;
end
endmodule
module main;
reg clk, reset;
reg [31:0] value;
wire [15:0] result;
wire rdy;
sqrt32 root(.clk(clk), .rdy(rdy), .reset(reset), .x(value), .y(result));
always #5 clk = ~clk;
always @(posedge rdy) begin
$display("sqrt(%d) --> %d", value, result);
$finish;
end
53
initial begin
clk = 0;
reset = 1;
$monitor($time,,"%m.acc = %b", root.acc);
#100 value = 63;
reset = 0;
end
endmodule /* main */
48.1
MUX2 Program Listing
This is a verilog program for a two-input Multiplexor. When select is 0 it
outputs in0, and when select is 1 it outputs in1.
module testmux;
reg a, b, s;
wire f;
reg expected;
mux2 myMux (.select(s), .in0(a), .in1(b), .out(f));
initial
begin
#0 s=0; a=0; b=1; expected=0;
#10 a=1; b=0; expected=1;
#10 s=1; a=0; b=1; expected=1;
#10 $stop;
end
initial
$monitor(
"select=%b in0=%b in1=%b out=%b, expected out=%b time=%d",
s, a, b, f, expected, $time);
endmodule // testmux
//
module mux2 (in0, in1, select, out);
input in0,in1,select;
output out;
wire s0,w0,w1;
not
(s0, select);
and
(w0, s0, in0),
(w1, select, in1);
or
(out, w0, w1);
endmodule // mux2
48.2
Running the Programs
Run the programs iverilog.exe and vvp.exe on the input file testmux2.v:
iverilog -otestmux2 testmux2.v
54
vvp testmux2
Prints the output:
select=0 in0=0 in1=1 out=0, expected out=0 time=
select=0 in0=1 in1=0 out=1, expected out=1 time=
select=1 in0=0 in1=1 out=1, expected out=1 time=
** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 30 ticks.
> finish
49
0
10
20
Bibliography
[1] Boole George The Laws of Thought, 1854.
[2] Mendelson Elliot Boolean Algebra and Switching Circuits, Schaum’s
Outline Series, McGraw-Hill, 1970.
[3] Nagle H. Troy, Carroll B. D., Irwin J. David An Introduction to Computer Logic, Prentice-Hall 1975. (Presents a computer algorithm for computing the minimal sequential machine. I worked on a program implementing
this algorithm, based on someone’s PhD theses, in the 70’s.)
[4] Mano M. Morris, Digital Logic and Computer Design Prentice-Hall
1979.
[5]Flores Ivan, Computer Logic, 1979, Prentice-Hall.
[6]McWhorter Gene, Understanding Digital Electronics, 1978, Texas Instruments learning Center, Radio Shack.
[7] Roth Charles H. Jr. Fundamentals of Logic Design, 4th Edition,
1992, West Publishing, (Karnaugh Maps, Quine-McClusky Method, Sequential Networks, Reduction of State Tables and State Assignment, Design of
Binary Adders, Hazards.)
55
[8] Texas Instruments. The TTL Data Book for Design Engineers,
Second Edition, 1982, Texas Instruments Corporation.
[9] Wakerly John F, Digital Design: Principles and Practices, Second
Edition, 1994, Prentice-Hall.
[10] Platt Charles, Make: Electronics, O’Reilly, 2009.
[11] Mims Forrest, Engineer’s Notebook II: Integrated Circuit Applications, Radio Shack, 1982, (a collection of circuit examples for 7400 series
integrated circuits, see for example the circuit for the 74LS74 Dual D FlipFlop on page 53, the divide-by-two counter).
[12] Cavanagh Joseph, Computer Arithmetic and Verilog HDL Fundamentals, CRC Press, 2010. Copy at Linda Hall Library TK7868.D5 C38.
Chapter 1, Number Systems and Number Representations. Chapter 2, Logic
Design Fundamentals. Chapter 3, Introduction to Verilog HDL.
[13] Lala Parag K Principles of Modern Digital Design, Wiley-Interscience,
2007. Contains material about the Hardware Description Language called
VHDL. There is a copy of this book at Linda Hall Library TK7868.L6L36.
[14] Dailey Denton J, Programming Logic Fundamentals Using Xilinx
ISE and CPLDs, Pretince Hall, 2004, 203 pages. Introduction to PLDs
using Xilinx ISE.
[15] Pedroni Volnei A. Circuit Design with VHDL, 2004, MIT Press. Appendix B is instruction on the use of VHDL in Xilinx ISE.
[16] Chu Pong P. , FPGA Prototyping by Verilog Examples: Xilinx
Spartan-3 Version, Wiley-Interscience, 2008. Instruction on FPGA design
using a Xilinx ISE and Spartan-3 chip.
[17] Wikipedia , Flip-Flops, The article on Flip-Flops is quite good as of
November 2011. Take note of the fact that Wikipedia articles constantly
change. For this reason, when I find a good article I like to print a PDF copy
of it and store it.
56
[18] J. Wawrzynek, CS61c: Verilog Tutorial October 17, 2007, verilogberkeley.pdf, http://inst.eecs.berkeley.edu/ cs61c/resources/verilog.pdf
[19] Stephen Williams, Icarus Verilog A free verilog program available for
several systems including Linux, and a version for Windows (command line
only). GNU General Public License version 2.0
[20] Deepak Kumer Tala, Verilog Tutorial verilog tutorial.pdf.
http://www.ece.umd.edu/courses/
enee359a/verilog\_tutorial.pdf
[21] Palnitkar, Samir, Verilog HDL : a guide to digital design and
synthesis SunSoft Press, 1996. Linda Hall TK7885.7 .P34 1996, SILOS III
simulation environment for windows CDROM 234.
[22] Sternheim Eliezer, Singh Rajvir, Ttivedi Yatin Digital Design with
Verilog HDL Automata Publishing Company, Cupertino CA, 1990. Linda
Hall Library TK7885.7 S73.
[23] Thomas Donald E., Moorby Philip R., The Verilog Hardware Description Language, 2nd Edition, Kluwer Academic Publishers, 1995. Linda
Hall Library TK7885.7 .T48, Disk 331.
[24] C.-L. Chang and C.-T. Lee. Symbolic Logic and Mechanical Theorem Proving, chapter 2. Academic Press, 1973.
50
Glossary
ASIC Application-Specific Integrated Circuit.
SSI Small Scale Integration
MSI Medium Scale Integration
LSI Large Scale Integration
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IC Integrated Circuit
Preset, Set, Reset the placing of a logic chip in a certain state.
FF Flip-Flop, an integrated circuit that may be in two different logic states
controlled by inputs and by a next state function.
S-R Flip-Flop and Latch A Set Reset Flip-Flop
D Flip-Flop Delay Flip-Flop.
T Flip-Flop Toggle Flip-Flop.
JK Flip-Flop Controlled by two input values.
PB Push Button
PCB Printed Circuit Board
TTL Transistor Transistor Logic
CMOS Complementary Metal Oxide Semiconductor
ENP Enables the clock on a clocked chip when high.
ENT Enables the clock on a clocked chip when high, and allows ripple carry.
HDL Hardware Description Language.
Verilog is a Hardware Description Language used to model digital systems.
VHDL another Hardware Description Language. The syntax is similar to
the ADA programming language.
FPGA Field Programmable Gate Array
CPLD Complex Programmable Logic Device
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MUX Short for multiplexer. From a select signal, selects from a number of
inputs and sends the selected input to a single output.
DMUX Short for demultiplexer. The inverse of a MUX. From a select signal, it selects one from n output ports, and sends the single input signal to
the selected port.
RDL Register Transfer Level, the transfer of logical values to registers in a
hardware description language
Fan Out
Tautology
Logical Equivalence
The Axiom of Choice
Zorn’s Lemma
The Chain Condition
Zermelo-Frankel Axioms of set theory
Logical Implication
First Order Logic
Existential Quantifier
Syllogism
Aristotle
ROM Read Only Memory
RAM Random Access Memory
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DRAM Dynamic Random Access Memory
EPROM
UVL Ultraviolet Light
Cardinal Numbers
Ordinal Numbers
Operators
Operands
Postfix
Prefix
Transfinite Numbers
NPN
PNP
FET
Smitt-Trigger Shows hysteresis.
Electrolytic Capacitor
Tantalum Capacitor
Ceramic Capacitor
Registers
Hysteresis
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Boltzman’s Constant
The Electronic Charge of the electron
Coulomb
Ampere
Volt Unit of electrical potential
Coulomb’s Law
Maxwell’s Equations
Faraday’s Law of Induction
Magnetic Poles
Permeability
Permittivity
Henry Unit of inductance
Joule
kilo
mega
milli
micro
nano
pico
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diode
diode equation
Is Saturation Current
Zener Diode
51
Constants
Charge of the Electron
62