Jitter Transfer Functions For
The Reference Clock Jitter In
A Serial Link: Theory And
Applications
Mike Li, Wavecrest
Andy Martwick, Intel
Gerry Talbot, AMD
Jan Wilstrup, Teradyne
Li et al, ITC, 2004
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Purposes
• Understand various jitter types (phase,
period, and cycle-to-cycle) and their
relationships
• Determine the appropriate jitter type for
digital and PLL based communication links
(i.e., PCIe)
• Figure out the jitter transfer functions of
reference clock and transmitter
• Suggest an appropriate and accurate jitter
test methodology for reference clock and
transmitter for PCIe and similar architectures
Li et al, ITC, 2004
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Outline
I. Review of serial data communication architecture
II. Jitter definitions
III. Jitter transfer functions
IV. System models
V. Application of the system models
VI. Summary and conclusions
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I: Overview of Data
Communication
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Conventional Serial Data
Communication Architecture
Tx
Rx
Medium
Data
Data
Clk
D
CR/
PLL
Q
C
• Bit clock is embedded in the transmitting data bits
• Bit clock is recovered via PLL at its Rx
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Jitter Transfer Function In Conventional
Data Communication
Rx: H rx (s)
Jitter in
Jitter+out
H cr(s)
CR/
PLL
-
• “Difference function” at the sample flop
• Jitter transfer function is a high-pass
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II: Definitions
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Units Of Jitter
• Time and Phase are
used interchangeably
to quantify jitter
Time:
Tideal
• Difference in time is:
∆T = Tideal − Tmeasured
• Difference in phase is:
∆ Phase = 2π − 2π
Tmeasured
Tideal
Tmeasured
Phase:
2*pi
• The conversion is
simply:
∆Phase =
∆T
Tideal
* 2π
Li et al, ITC, 2004
2*pi *
Tmeasured
Tideal
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Phase Jitter (Φ)
• Also known
accumulated
jitter
n
200 ps
Phase Jitter, s, (radians)
Φn = t n − nT, n =1, 2,. , ∞
Φ
400 ps
(2 π)
(π)
0 ps
(0 π)
-200 ps
(− π)
-400 ps
(−2 π)
0ns
1.6ns
3.2ns
4.8ns
6.4ns
9.6ns
8.0ns
nT
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Period Jitter

The period Jitter (Φ’)
is the difference
between the
measured period
and the ideal
period
Φ'n = (tn −tn−1) −T, n =1, 2,. , N
•
Also is:
Φ
n
400 ps
(2 π)
Phase and Period Jitter, s, (radians)
•
Period Jitter (Φ’)
200 ps
(π)
0 ps
(0 π)
Φ'n
-200 ps
(− π)
-400 ps
(−2 π)
1.6ns
Φ 'n = Φ n − Φ n −1
Li et al, ITC, 2004
3.2ns
4.8ns
nT
6.4ns
9.6ns
8.0ns
10
Cycle-to-Cycle Jitter (Φ’)
• Cycle to cycle
The difference
between
consecutive bit
periods
Φ
n
400 ps
(2 π)
Φ'n' = (tn − tn−1) − (tn−1 − tn−2 ), n =1, 2,. , N
• Also is:
Φ 'n' = Φ 'n − Φ 'n −1 , n = 1, 2, . , N
Phase, Period and Cycle to Cycle Jitter, s, (radians)

200 ps
(π)
Φ''
n
0 ps
(0 π)
Φ'n
-200 ps
(− π)
-400 ps
(−2 π)
Li et al, ITC, 2004
1.6ns
3.2ns
4.8ns
nT
6.4ns
9.6ns
8.0ns
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Interrelationship in Time-Domain
• Phase Jitter → Period Jitter → Cycle-to-cycle
Φ
''
n
= (Φ
' '
)
n
= (Φ n )
''
• Cycle-to-cycle → Period Jitter → Phase Jitter
Φn = ∫ Φ
'
n
= ∫∫ Φ
''
n
• Different representations of a same physical
phenomena
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Interrelationship in Frequency-Domain
20
Various Jitter Measurement Spectrum
0
If (Φ phase ( f ) = c)
Then
Φ period ( f ) ∝ f • c
Magnitude in dB
-20
Zeroth-Order Jitter
-40
-60
Period Jitter
-80
-100
2
Φ cycle−cycle ( f ) ∝ f • c
Cycle-to-Cycle Jitter
-120
-140
-160
-180
-5
10
Li et al, ITC, 2004
-4
10
-3
-2
-1
10
10
Frequency
10
13
Phase Jitter Measurement and
Reference Clock Used
• The amount of
warping depends on
the recovered clock’s
transfer function of the
receiver
Data phase
Ref clock phase
Phase
• Calculating phase
jitter against a warped
clock (or recovered
clock ) reduces the
amount of phase jitter
calculated
Diff
0
Time
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Eye Closure/Total Jitter Modeling
• Given a clock and data signal
VClk (t ) = V0Clk [ω Clk t + PClk (t )]
VData (t ) = V0 Data [ω Data t + PData (t )]
• Eye closure ∆ P (t ) is the difference in the phase
between the clock and the data given by
∆P (t ) =| Pclk (t ) − P data (t ) |
• Eye closure direct depends on the jitter
transfer function of the receiver
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III. Jitter Transfer Functions
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LTI System in Time-Domain
• An output signal y(t) equals to the input signal
convolves with the impulse response h(t)
∞
y (t ) =
∫ x (τ ) h ( t − τ ) d τ
−∞
∑
=
• Phase jitter is modeled as continuous signal
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LTI System in S-Domain
• S-domain functions is obtained via Laplace
transformation
Y(s) = X(s)H(s)
y(t) = Laplace-1 (Y(s))
• Complex frequency s can be related to the real
frequency ω through s = jω, as done in the
models
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LTI System Summary
x (t)
X (s)
L T I S y s te m
T im e -d o m a in : h (t)
S -d o m a in : H (s )
y (t) = h (t) * x (t) =
y (t)
Y (s)
∞
∫ x (τ ) h ( t − τ )d τ
− ∞
Y ( s ) =
H (s) =
H ( s ) X ( s )
∫
∞
−∞
h (t ) e
Li et al, ITC, 2004
− st
dt
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IV. System Models
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Data Recovery Circuits (DRC)
• Receiver Data Recovery is the essence of the
system
• Traditional Serial Communication uses a PLL
based Data Recovery
• PCI Express allows a less expensive digital based
Data Recovery Circuit
 Using phase interpolator (PI), oversampled
design or digital controlled delay line
 Majority implemented DRCs are PIs
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PLL Based DRC
• The system reference clock is not used when
recovering the data
• The Rx PLL needs to track the transmitter’s jitter
output
Eye-closure/total jitter system model
Transmitte r
Chip #1
Reference
Clock #1
X
f (x 1...xn)
x1
u1
Receiver in
Chip #2
-
W1
D
f (x 1 ...xn )
PLL
x25
x1
SET
CL R
Y
Q
|Eye Closure |
Data
Q
u1
D R C PLL
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Digital PI Based DRC
• Both Tx and Rx use the reference clock
• Phase relationship between ref clock and data
path matters
Eye-closure/total jitter system model
|Eye Closure|
-
Y
Transmitter
Chip #1
Reference Clock
X
f(x1...xn)
x1
u1
W_1
D
PLL
x25
f(x1...xn
)
x1
u1
PLL
x25
Li et al, ITC, 2004
W_2
f(x
x1 1...xn)
u1
x2
Phase Alignment
SET
CLR
Q
Q
W_3
Receiver in
Chip #2
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Phase/Jitter Transfer Function For
A PLL
• The input signal to a PLL is
Vin (t ) = Ain sin (ω in t + Pin (t ) )
where Pin(t) is the input phase signal and is the state
variable of the PLL
• The output from a PLL is
Vout (t ) = Aout sin (ω out t + Pout (t ) )
where Pout(t) is the output phase.
• The PLL has a phase transfer response h(t)/H(s), they
satisfy
Pout (t ) = h(t ) * Pin (t ) Pout (s) = H (s)Pin (s)
Li et al, ITC, 2004
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Approximate Digital PI DRC
Transfer Function
Magnitude of H3(s) Transfer Function
10
5
0
-5
-10
Mag (dB)
• The DRC Response is
modeled by a first order
F_3dB high pass = 1.5
MHz
 This tracks the
spread spectrum
clock
-15
-20
-25
-30
s
H 3 (s) =
s + ω3
-35
-40
4
10
Li et al, ITC, 2004
5
10
6
10
Frequency (Hz)
7
10
25
Model For A PLL Transfer Function
• Can be approximated by
a 2nd order transfer
functions for Rx and Tx
• Some PLLs are 3rd order
or higher, additional
poles at higher frequency
do not contribute
significantly to the eye
closure
H 1( s ) =
2 sζω n + ω n2
s 2 + 2 sζω n + ω n2
ω 3dB = ω n 1 + 2ζ 2 + (1 + 2ζ 2 ) 2 + 1
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System Transfer Function Models
PLL Based DRC Model
H_1(s)
f(x1...xn)
x1
X(s)
u1
Clock Reference
f(x1...xn)
x1
W_1(s)
u1
f(x1...xn
)
x1
u1
H t ( s ) = H 1 ( s )(1 − H 2 ( s ) )
Y(s)
-
H_2(s)
TX PLL
W_2(s)
Rx PLL
Digital PI DRC Model
H_1(s)
f(x1...xn)
x1
f(x1...xn)
x1
u1
X(s)
u1
W_1(s)
-
TX PLL
f(x1...xn
)
x1
u1
f(x1...xn)
x1 u1
Phase Alignment
H_2(s)
Clock Reference
W_3(s)
W_2(s)
Y(s)
Ht (s) = ( H1 (s) − H 2 (s))H 3 (s)
H_3(S)
Rx PLL
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Delay Model
• Delay transfer function models into the system
 The phase delay is given by (L1 + L2) – L3
 This is modeled by exp(-s * t_delay)
Transmitter
Chip #1
L.1
Reference
Clock
f(x1...xn)
x1
u1
PLL
x25
L.2
L.3
y_1
D
f(x1...xn
)
x1
u1
PLL
x25
w_4
f(x
x1 1...xn)
u1
SET
CLR
Q
Q
y_2
x2
Phase Alignment
Receiver in
Chip #2
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Delay Transfer Function
• Example with 100 ns
Delay
• The transfer function has
nulls at the delay period
• It has 6dB of gain at ½
intervals of the delay
period
 Doubles the effective
jitter
20
0
-20
-40
-60
-80
-100
-120
0
10
2
10
4
10
6
10
8
10
10
10
xy
x1
u1
Delay
X
-
Y
Y = X [1 − exp( s * t _ delay )]
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PLL Based Transfer Function
• PLL Based DRC
does not have delay
dependencies
• PLL locks to the data
rate and wants a high
Rx PLL response for
best performance
H_1(s)
f(x1...xn)
x1
u1
Clock Reference
X(s)
f(x1...xn)
x1
u1
TX PLL
W_1(s)
-
H_2(s)
f(x1...xn
)
x1
u1
W_2(s)
Y(s)
H t ( s ) = H 1 ( s )(1 − H 2 ( s ) )
Rx PLL
Li et al, ITC, 2004
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Digital PI Based Transfer Function
• The difference
function includes
an arbitrary phase
delay not to
exceed 30 ns
 The delay “uncorrelates” the
clock/data and
closes the eye
Transfer Functions Mag
10
5
0
-5
F1: 7.0e+006 F2: 2.2e+007
-10
)
B
d(
g
a
M
-15
-20
-25
-30
H1
H2
H1(delayed 30ns) - H2
2* (H1-H2)
H3
-35
• This can be
estimated with 2X
multiplier of H1(s)H2(s)
-40
4
10
5
10
6
10
Frequency (Hz)
7
10
H t ( s ) = 2 [ H1 ( s ) − H 2 ( s )] H 3 ( s )
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V. Applications of System Models
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Reference Clock Jitter Induced EyeClosure Estimation
• Quantify system-level interdependencies
 Reference Clocks
PLL parameters
• Calculate eye closure from the reference
clock (most complex transfer function)
 Using previously defined models
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PLL and Digital PI Parameter Ranges
1. The BW of the Tx and RX PLLs is 1.5 MHz
to 22 MHz, 3dB peaking maximum
2. The BW of the DRC (PI) should be at least
1.5 MHz
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Models Applied to Measured Data:
One Method
• X(s)
 The input spectrum can be
measured by measuring a
clock and applying the
jitter definitions to get the
phase jitter
 The phase jitter signal is
then transformed into the
phase jitter spectrum, X(s)
• H(s)
 The models presented
here give Ht(s), the
bounding function,
including the delay
• Y(s)
Y(s) =X(s)H(s)
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Eye-Closure at The RX Sample Flop-One
Method
• The inverse Laplace transform of Y(s) gives the eye closure
in the time domain, y(t)
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Jitter “Peaking” and Broadening
•
•
•
Difference function dominated by Tx, Rx and Phase Interpolator
 PLL bandwidth difference
 PLL peaking
Reference clock noise spectrum as seen at Tx and Rx
Any noise under the difference function can cause phase jitter
• 3 Danger Areas (7-22 MHz shown)



Between “A” and “B” ref clock jitter
gets multiplied
Left of “A” rolls off
Right of “B” rolls off
• Changing Tx, Rx below 7 MHz
increases width of danger areas


A
B
Width and Amplitude
Impact varies with clock spectrum
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VI. Summary and Conclusion
• A quantitative mathematical relationship between
phase, period, and cycle-to-cycle jitter is developed
• A generic S-domain jitter transfer functions for
PCIe were established
• The jitter state variable is Phase Jitter, and cycleto-cycle is not the right merit for PCIe clock jitter
• Reference clock jitter transfer function is a ~(3th
high-2th order low) band-pass
• Tx jitter transfer function is a 1st order high-pass
with a 3dB frequency of 1.5 MHz
• The method developed here can also be applied
to new and relevant communication architectures
(i.e., FB DIMM, SATAII etc. )
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