Pravara Research Journal Vol,1,2016
Design and Implementation of Carry Look Ahead and Ripple
Carry Adder at 32 Nanometer
R. S. Mahajan1, B. G.Gawalwad2
1, 2
Department of Electronics & Telecommunication
Sir Visvesvaraya Institute of Technoilogy
Chincholi, Nashik, India-422 102
rana.entc@gmail.com
Abstract –Addition is one of the basic functions in
binary arithmetic. An adder should be designed to
achieve the requirements of many modern devices viz
small chip area and high circuit speed.Adders are
digital components which are widely used in the digital
integrated circuit design and are the important part of
all digital applications like Digital Signal Processing
(DSP), microprocessor applications. This paper
describes the implementation of Carry Look Ahead
Adder and Ripple Carry Adder. On the basis of their
performance parameters such as area, delay and
power distribution at 32nm technology node has been
compared. The proposed work of CLA and RCA has
been carried out in Hspice software.
2.
RIPPLE CARRY ADDER AND CARRY LOOK
AHEAD
Addition is the very important and frequently used
arithmetic function. It is always the speed-limiting element
of Arithmetic Logic Unit in modern Central Processing
Units. Addition develops the basis for many processing
functions, including counting, multiplication and digital
signal filtering. As a result, adder is the device that add two
binary numbers are of great interest in the field of digital
Integrated Circuits and are often used as a test bench to
compare different logic style[5-6].
Table. 1. Full Adder Truth Table
Keywords: Ripple Carry Adder(RCA); Power Delay
Product(PDP) ; Carry Look Ahead Adder (CLA);
Enerrgy Delay Product(EDP).
1.
INTRODUCTION
A major attribute of arithmetic units for most of
the applications is to maximize the speed or throughput of
the circuit. For number of applications, reducing the
power consumption is of greater importance. The most
easy way to reduce the power is to use CMOS circuits,
which generally dissipate less power than their bipolar
counterparts [1-2]. Addition is the most frequently used
function among a set of real-time digital signal processing
benchmarks. It is not surprising, that adders have received
a lot of attention from researchers and consequently
computer architects find a myriad of adder designs at their
disposal. They would, of course, like to use the best
adder; but what identifies the "best" adder? Is it the fastest
or the smallest or the least power or the one that is easiest
to integrate into the system or the one that is most faulttolerant? It has not yet been possible to integrate the
various performance criteria into a single cost function as
is evident [3-4].
In this paper, the performance parameters of
delay, average power, PDP and EDP are compared at
32nm technology node.
A
B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
CarryIn
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
CarryOut
0
0
0
1
0
1
1
1
Table 1 shows the truth table of a 1 bit full adder.
A and B are the input lines, Carry-In is the carry input line,
Sum is the sum output line , and Carry-Out is the carry
output line. Based on this truth table to construct a 8-bit
adder, 8 Full Adder units can be cascaded in series,
connecting Carry-Out of a FA unit to the next stage FA Cin
input. This architecture is called as Ripple Carry Adder
(RCA), here the carry bit get “ripples" from one stage to the
other [7-9].
A architecture of a 4-bit Ripple Carry Adder
(RCA) is shown in Figure 1. The schematic of ripple carry
adder is very simpler, which allows for fast design; however,
the ripple carry adder is relatively very slow, since each full
adder unit must wait for the carry bit to be calculated from
the previous full adder unit. The gate delay can easily be
calculated by inspection of each full adder circuit.
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Pravara Research Journal Vol,1,2016
Fig.1 4-bit Ripple Carry Adder (RCA)
Each full adder requires three levels of logic. In a
8-bit ripple carry adder, there are 8 full adders, so the
critical path or worst case delay is 7 * 2(for carry
propagation) + 3(for sum) = 17 gate delays [10-12].
A fast method as compared to ripple carry adder
is called Carry-Look Ahead. This method does not require
the carry signal to propagate from one stage to next stage,
causing a bottleneck. Instead of that it uses additional
logic to expedite the propagation and generation of carry
information, which allows fast addition at the expense of
more hardware requirements. Figure 2 shows architecture
of 4-bit Carry Look Ahead Adder [13-14].
Fig.3. Comparison of Delay as function of supply voltage
Figure 4 shows comparison of Average Power as
function of supply voltage. It is observed that the Carry
Look Ahead Adder at 32 nm has less Average Power as
compared to Ripple Carry Adder with 32nm technology.
Fig.2. 4-bit Carry Look Ahead Adder (CLA)
3. SIMULATION RESULTS
Conventional CMOS at 32nm technology model
has been used to compare performance of CLA and RCA
adder. A transistor is having gate length 32nm, threshold
voltage 0.5088 for NMOS and gate length 32nm, and
threshold voltage -0.450 for PMOS. All these parameter
has been taken from predictive technology model.
Different comparison of Average power, Peak Power,
delay, power, PDP, EDP has been done in this paper.
Figure 3 shows comparison of Delay as function
of supply voltage. It is observed that the Carry Look
Ahead Adder at 32 nm has less Delay as compared to
Ripple Carry Adder at 32nm technology.
Fig.4 . comparison of Average power as function of supply
voltage
Figure 5 shows comparion of Power Delay Product
(PDP) as function of supply voltage. It is observed that the
32 nm Carry Look Ahead Adder has less Power Delay
product as compared to 32nm Ripple Carry Adder.
Figure 6 shows comparism of Energy Delay
Product versus chnge in supply voltage. It is observed that
the 32 nm Ripple Carry Adder has less Energy Delay
Product as compared to 32nm Carry Look Ahead Adder.
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Pravara Research Journal Vol,1,2016
delay product are compared. It is observed that CLA at
32nm technology node in all the parameters like peak power
delay, power delay product, average power and energy
delay product gives better results than Ripple Carry Adder.
Fig. 5.Comparison of PDP as function of supply voltage
Fig. 7. Comparison of Peak power as function of supply
voltage
Also it is observed that Ripple carry adder gives
good power in subthreshod region at the cost of speed. All
the simulation work has been carried out in Hspice software.
REFERENCES
Fig. 6. comparison of EDP as function of supply voltage
Figure 7 shows comparison of peak power as
function of Supply voltage. It is observed that 32nm Carry
Look Ahead Adder has low peak power as compared to
32nm Ripple Carry Adder.
From figure 2,3,4,5 it is seen that the sub
threshold working of the circuits show very low power.
Power reduces 97% than the super threshold region of
working.
4. CONCLUSION
In this paper, we have implemented Carry Look
Ahead Adder and Ripple carry adder at 32nm technology
node. Different performance parameters peak power,
delay, power delay product, average power and energy
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