CS 350 – COMPUTER ORGANIZATION AND ASSEMBLY
LANGUAGE PROGRAMMING
Week 12
Reading:
Adder design and ALU design for one bit and 8 bit.
Objectives:
•
•
Understanding the concept of one bit and 8 bit ripple carry adder design.
Knowing the one bit and 8 bit ALU design.
Concepts:
1.
2.
3.
4.
5.
one bit adder.
8 bit ripple carry adder.
4 bit look ahead carry adder.
1 bit ALU design.
8 bit ALU design.
•
•
•
Overview of one bit adder.
Information about 8 bit ripple carry adder.
Briefly describing the ripple carry adder.
Circuit description of a ripple carry adder.
Carry look ahead adder.
• 1 Carry look ahead method
• 2 Demonstration of method
• 3 Implementation details
• 4 Manchester carry chain
Discussing about the ALU design
Outline:
•
•
References:
1. http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/20arithmetic/10-adders/ripple.html
2. http://en.wikipedia.org/wiki/Carry_lookahead_adder#Manchester_carry_chain
3. http://library.thinkquest.org/25111/alu.shtml
CS 350-Week 12-Page 1
Cs 350 - week 12 - Lecture notes
One bit adder:A one-bit full adder circuit produces sum and carry output signals in response to
two operand input signals and their complements, and a carry input signal and its
complement.
Table 1, shown below, is a truth table for a typical one-bit full adder. In table 1 the
operand input signals are designated X and Y, and the complements of the operand input
signals are designated X and Y, respectively. The carry input signal is designated
Z.sub.in, and the complement of the carry input signal is designated Z.sub.in. Similarly,
the sum output signal is designated S and its complement is designated S, and the carry
output signal is designated Z.sub.out and its complement is designated Z.sub.out.
TABLE 1
______________________________________
Inputs
Outputs
X Y
--X --Y Z.sub.in
--Z.sub.in
S --S Z.sub.out
--Z.sub.out
______________________________________
0 0
1 1 0 1
0 1 0 1
0 1
1 0 0 1
1 0 0 1
1 0
0 1 0 1
1 0 0 1
1 1
0 0 0 1
0 1 1 0
0 0
1 1 1 0
1 0 0 1
0 1
1 0 1 0
0 1 1 0
1 0
0 1 1 0
0 1 1 0
1 1
0 0 1 0
1 0 1 0
______________________________________
When arithmetic operations on multidigit numbers are to be performed substantially
simultaneously for all orders, a number of one-bit full adder circuits, equal to the number
of digits, are connected in parallel. In this case, the carry output signal and/or its
complement depending on the particular circuit arrangement, from a one-bit full adder
circuit operable connected to add two same order digits becomes the carry input signal to
the adjacent one-bit full adder circuit which is operable connected to add the two next
higher order digits. (See H. Taub et al, "Digital Integrated Electrons", McGraw-Hill, Inc.,
1977, pp. 362-363.) Consequently, the carry output signal at the most significant bit is
delayed by the propagation delay time of the carry signal through each one-bit full adder
multiplied by the number of one-bit full adders. As a result of this, the time required for
arithmetic
operations
is
prolonged.
The propagation delay time of the carry signal is the time interval between the entry of a
valid carry input signal into the one-bit full adder and the emergence of a valid carry
CS 350 Week 3 Page 2
output signal from the one-bit full adder. This time is dependent upon the number of
transistor gates in the carry path between the carry input and the carry output.
Accordingly, efforts have been directed to the development of one-bit full adder circuits
comprising a minimum number of transistor gates and especially a minimum number of
transistor gates in the carry path to reduce the carry delay.
8 bit ripple carry adder:
A standard 8-bit ripple-carry adder built as a cascade from eight 1-bit full-adders.
Click the input switches or use the following bindkeys: ('c') for carry-in, ('a','s', ..., 'k') for
A0..A7 and ('1','2', ..., '8') for B0..B7.
To demonstrate the typical behavior of the ripple-carry adder, very large gate-delays are
used for the gates inside the 1-bit adders - resulting in an addition time of about 0.6
seconds per adder.
Note that each stage of the adder has to wait until the previous stage has calculated and
propagates its carry output signal. Obviously, the longest delay results for operands like
A = 0b0000000, B=0b11111111 or A=0b01010101 and B=0b10101010 (select these, and
then switch carry-in to both 0 and 1, and watch the circuit to settle). Therefore, the total
delay of a ripple-carry adder is proportional to the number of bits. Faster adders are often
required for bit widths of 16 or greater.
Carry look ahead adder:
A carry look-ahead adder is one type of adder used in digital logic. It can be
contrasted with the simpler, but usually slower, ripple carry adder. Whereas in a ripple
carry adder, each bit of the adder must wait for the carry output from less significant bits.
However, in a carry lookahead adder, all the carry outputs are calculated at once by
specialized lookahead logic. The result is that instead of having to wait for the output to
"ripple" up to the most significant bit, the entire result can be computed with significantly
less delay.
Carry lookahead method:Carry lookahead logic uses the concepts of generating and propagating
carries. Although in the context of a carry lookahead adder, it is most natural to think of
generating and propagating in the context of binary addition, the concepts can be used
more generally than this. In the descriptions below, the word digit can be replaced by bit
when referring to binary addition.
The addition of two 1-digit inputs A and B is said to generate if the addition will always
carry, regardless of whether there is an input carry (equivalently, regardless of whether
any less significant digits in the sum carry). For example, in the decimal addition 52 + 67,
the addition of the tens digits 5 and 6 generates because the result carries to the hundreds
digit regardless of whether the ones digit carries (in the example, the ones digit clearly
does not carry).
In the case of binary addition, A + B generates if and only if both A and B are 1. If we
write G(A,B) to represent the binary predicate that is true if and only if A + B generates,
we have:
CS 350 Week 3 Page 3
The addition of two 1-digit inputs A and B is said to propagate if the addition will carry
whenever there is an input carry. For example, in the decimal addition 37 + 62, the
addition of the tens digits 3 and 6 propagate because the result would carry to the
hundreds digit if the ones were to carry.
In the case of binary addition, A + B propagates if and only if at least one of A or B is 1. If
we write P(A,B) to represent the binary predicate that is true if and only if A + B
propagates, we have:
P(A,B) = A + B
Demonstration of method
Let's try a little experiment. Here is a series of numbers. See how long it takes you to find
the most significant digit (the number to the far left).
3456789876543
+ 6543210123456
The most significant digit is 9. How can we tell? We can look at the far left digits being
added. 3 + 6 = 9. If we were to add 1 to this value, the most significant digit would be 1
(9 + 1 = 10). So, we have to look at the digit to the right of this one, to see if there is a
carry. Do the same for the following problem:
3456789876543
+ 6544210123456
You will notice there is 6 + 4, which will generate a carry. Since we know all the sums to
the left of this value are 9, we know immediately that the most significant digit will be 1.
Try this again for this last example:
9999919999999
+ 0000090000000
As you can see, we can quickly determine the most significant digit by looking whether
the two values sum to 9 (will propagate a carry), or sum greater than 9 (will generate a
carry). This is the basic principle behind the Carry Look Ahead adder.
Implementation details
For each bit in a binary sequence to be added, the Carry Look Ahead Logic will
determine whether that bit pair will generate a carry or propagate a carry. This allows the
circuit to "pre-process" the two numbers being added to determine the carry ahead of
time. Then, when the actual addition is performed, there is no delay from waiting for the
ripple carry effect (or time it takes for the carry from the first Full Adder to be passed
down to the last Full Adder). Below is a simple 4-bit generalized Carry Look Ahead
circuit that combines with the 4-bit Ripple Carry Adder we used above with some slight
adjustments:
CS 350 Week 3 Page 4
4-bit Carry Lookahead Adder
For any circuit larger than 4 bits, the Carry Look Ahead circuitry becomes very
complicated. For the example provided, the logic for the generate (g) and propagate (p)
values are given below. Note that the numeric value determines the signal from the
circuit above, starting from 0 on the far left to 3 on the far right:
Substituting C1 into C2, then C2 into C3, then C3 into C4 yields the expanded equations:
Manchester carry chain
The Manchester carry chain is a variation of the carry look-ahead adder that uses shared
logic to lower the transistor count. As can be seen above in the implementation section,
the logic for generating each carry contains all of the logic used to generate the previous
carries. A Manchester carry chain generates the intermediate carries by tapping off nodes
in the gate that calculates the most significant carry value. Not all logic families have
these internal nodes, however, CMOS being a major example. Dynamic logic can support
shared logic, as can transmission gate logic. One of the major downsides of the
Manchester carry chain is that the capacitive load of all of these outputs, together with the
resistance of the transistors causes the propagation delay to increase much quicker than a
regular carry look-ahead. A Manchester carry chain section generally won't exceed 4 bits.
Discussing about ALU design;
The ALU is the part of the microprocessor that handles all Boolean and
mathematical operations. However, exploring an actual ALU from one of the current
CS 350 Week 3 Page 5
microprocessors is too complex for our purposes. Thus, we have taken a more simplified
design that, although limited in functionality, will show you the general picture.
CS 350 Week 3 Page 6
The F inputs control the enable lines. As you can see, no matter which of the four
possible combinations of F inputs is put in, only one (and each time different) enable line
will be "turned on." Thus, the function of the decoder subpart is to figure out which of the
4 operations will be done. The A and B are used as the regular inputs for all operations.
The full adder is nearly the same circuit as the one shown on the Mathematical
Operations page. However, all output is ANDed with the corresponding enable line. The
logical unit is simply a collection of three boolean operations, AB, A+B, NOT B. As with
the full adder, each of their outputs is ANDed with the corresponding enable line. On the
very right, all of the outputs are ORed together. However, only one of the four inputs
could potentially be a 1 because of the enable lines.
The diagram, however only represents a 1-bit ALU. Most likely, an 8-bit ALU is more
convenient for useful operations. To create an 8-bit ALU, this diagram needs to be
repeated 8 times, linking the Carry-Out to the Carry-In of the next one each time. This
concept has already been introduced with the full adder.
Lab:
You will implement a 16-bit carry-lookahead adder. You will do this by
creating a Partial Full Adder (PFA) macro and a Carry-lookahead Logic macro
Open a new project in your folder (c:\users\your_name\) and call it MY16CLA.
Open the schematic editor.
Create a macro of the PFA using VHDL. Call the macro MYPFA. When the PFA has
been synthesized, do a functional simulation to verify that the circuit works.
NOTE: You can do a functional simulation without having to connect input and output
terminals to the macro input. Do the following:
Go to the simulator by clicking on the SIM icon on the top toolbar.
In the Waveform viewer, click on the Add Signals icon (or go to SIGNALS -> ADD
SIGNALS). In the middle panel of the Component Selection window, called Chip
Selection, you will see the name of the macro, MYPFA. Double click on it. In the right
panel, Scan Hierarchy, all the input and output pins will be displayed. Select these pins
by double clicking. When done, click the Close button.
Open the stimulator window and define the A and B bits using the Binary counter.
Do a functional simulation and verify the operation.
Create a macro for the Carry- Look-Ahead Logic block. Call this MYCLALOG. Use
VHDL to create this macro. You should also generate the Groups Generate and Propagate
signals, PG and GG, respectively. You do not need to create the carry C4. Do a simulation,
as explained above.
Now you can create a 4-bit CLA adder macro. In the schematic editor go to the TOOLS > SYMBOL WIZARD menu and create the symbol for a Schematic macro, called
MY4CLA. Once the symbol has been created, draw the schematic for the 4-bit adder
using the above defined modules of PFA and MYCLALOG. The adder should have as
input A[3:0], B[3:0], and CIN. The outputs are S[3:0], PG, and GG. Be careful when
connecting the carry signals. Since this schematic will be used as a macro, you do not
need to add input/output buffers and pads. For single signals use a terminal; and for the
CS 350 Week 3 Page 7
buses (ex. A, B and S), define the bus as "input" or "output" bus (or select End Bus if the
terminals have been defined already).
When finished, synthesize the macro and simulate the 4-bit adder. Verify its operation
and make a screen caption of the functional simulation waveforms (only one page).
You are now ready to create the top level schematic of the 16-bit carry-lookahead adder.
Use the block diagram of Figure 6.
The schematic of the 16-bit adder is the top level schematic. All the input pins (A[15:0],
B[15:0], CIN, SOUT[15:0], and COUT) need to be connected to pads and buffers. Cout
is the last carry of the adder, corresponding to C16 and can be generated from the groups
Propagate and Generate signals.
In order to keep the schematic and its interconnections manageable, use buses as much as
possible. It may be helpful to use a 16-bit wide bus for input signals A and B. This bus
can be split up into segments of 4 bits that each feeds into the 4-bit inputs of each of the
4-bit CLA macros. This can be done by first drawing a 16-bit wide bus (e.g. AIN[15:0]).
Then connect the 4-bit wide input bus (e.g. A[3:0]) of the first 4-bit CLA to the 16-bit
wide A bus; next connect the input of the 2nd 4-bit CLA to the same A bus, etc. until all
16 inputs have been connected. Now you need to specify how the bus signals are
connected. This can be done by giving the bus segment the proper name by clicking on
the bus. This will open the Edit Bus window. Keep the name but change the bus width.
For instance, to specify a 4-bit wide bus segment that connects to the input of the first 4bit adder, give it the name AIN and as width [3:0]. It is important that the name of the bus
segment is the same as the name of the 16-bit bus. Do the same for the other bus
segments (e.g. AIN[7:4], etc.). For more information about buses in the Schematic Entry
window, select HELP -> SCHEMATIC EDITOR HELP CONTENTS. In the help
window select INDEX and type "buses" or "bus connections".
When done, do a functional simulation and verify that the circuit works properly. Instead
of defining each input signal A0, A1 ... A15, B0, B1, ... B15 separately, it is more
convenient to use the Formulas to define the input signals of the input buses. See section
on Formulas in the Logic Simulator Tutorial. When the simulation give the right
result, take a screen capture of the waveforms (again only one page).
When the circuit works properly, you need to implement it so that you can do a timing
simulation later on.
Make sure you added pads and buffers for each input and output. If you don't add pads,
the mapping software will remove all the logic between input and output "connectors"
and your circuit will have no logic or little logic left!
Before implementing the design, go to the Program Manager and select the
IMPLEMENTATION -> IMPLEMENT DESIGN menu (or ->OPTIONS menu). In the
Implement Design window click on the Option button. When the Options window opens,
click on the Edit Options button for the Simulations (Foundation EDIF). In the
Simulation Options window, click on the General Tab and De-select the option:
Correlate Simulation Data to Input Design. This will prevent that the timing
CS 350 Week 3 Page 8
simulation will give undefined signals (see also undefined signals in the timing
simulation tutorial).
For the implementation, see previous lab or check the tutorial on Design Implementation.
Use a device speed of 4.
Check the reports and write the results in your lab notebook:
Check the Map Report for the device utilization and the equivalent gate count. Check if
logic has been removed during the mapping step.
Check the Post Layout Timing Report. Find the maximum combinational path delay and
net delay. Between which input pin and output pin does the maximum delay occur? What
is the maximum frequency at which the input signals can applied without causing
erroneous operation of the 16 bit adder?
Timing simulation (Verification): In the Project Manager click on the Verification
(Timing Simulation) icon. This will open the timing simulator. Do a worst-case
simulation of the CLA and determine the delay of the Sum bits and the Carry out bit
COUT. In case you have problems with the timing simulation and some of the signals
are undefined (gray waveform), see the notes below. You do not need to go through all
the possible input combinations because you have verified that the circuit works properly
by doing a functional simulation above.
Apply input signals A[15:0] and B[15:0] which give a worst case scenario for the delays
of the sum and carry-out signals? Measure the delays between the time the input signal is
applied and the sum and carry-out signal changes (use the measurement option in the
simulator). Write these numbers down in your lab notebook. Do they correspond to the
ones reported in the Post Layout Timing report?
When doing the timing simulation, be careful that the period of the stimuli (i.e. the
signals applied to the input) is larger than the longest delay of the circuit. If your input
signal is changing before the output signals appear (due to the delay), you will get useless
and unpredictable results. You can change the period of the binary counter output (Bc:)
by going to the OPTIONS -> PREFERENCES -> SIMULATIONS; adjust the Clock
Period of B0 to a value larger than the maximum delay (e.g. 50 ns). The input signal
should not change until all the output signals have settled to the proper value.
Besides the delays of the Sum and Carry signal determine also the delay of the input and
output buffers.
Take a screen capture of the simulation data, including the measurement data for the
delays of the Sum, Carry-out and buffer delays (max 2 screens).
CS 350 Week 3 Page 9