5.1 Representations for unsigned numbers
Conversion from binary to decimal → evaluate polynomial with powers of 2
Conversion from decimal to binary → Repeated division by 2
Read Section 5.1
Review Section 1.6 and Lab week 1
New: Conversion among binary, octal, hex → use groups of 3 or 4 bits
5.2 Addition of unsigned numbers
x
+y
0
+0
0
+1
1
+0
1
+1
c s
0 0
0 1
0 1
1 0
Carry
Sum
(a) The f our possible cases
x
y
Carry
c
Sum
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
s
(b) Truth table
x
sHalf
y
adder (HA)
x
y
s
HA
sum
c
(c) Circuit
carry
(d) Graphical
symbol
c
Full adder (FA)
2-level implementation
Multi-level implementation (decomposed)
In class: Evaluate and compare the costs of the two-level and multi-level
implementations of the 1-bit adder.
Ripple-carry adder
In class: Evaluate the cost of the ripple-carry adderas a function of n.
Design example: Circuit that multiplies by 3
Assumption: The number to multiply, A, has 8 bits
Simple idea: 3A = A + A + A
Cost?
Better idea: 3A = 2A + A
Cost?
SKIP Section 5.3 Representing negative numbers
5.4 Fast Adders
Ripple-carry adder:
Idea: functional decomposition! Split boolean function for Carry Out into:
propagate
generate
ci+1 = xiyi + (xi +yi)∙ci
ci+1 = gi + pici
Now let’s take it one step further: substitute ci
ci+1 = gi + pici = gi + pi (gi-1 +pi-1∙ci-1) = gi + pi∙gi-1 +pi∙pi-1∙ci-1
Now substitute ci-1 …
Write down the general expression, expanded all the way to c0 … [Eqn. 5-4/274]
“Carry – lookahead”
The first two stages of a carry-lookahead adder:
The modular view:
What is gained? Let’s examine the longest path through this circuit …
74x283 = 4-bit adder w/carry lookahead (handout)
Propagate and generate signals → one level of gates
Carry-lookahead logic
→ two levels
XOR gates for sum bits
→ one level
Conclusion: “constant time” = 4 gate delays!
In notebook for next time:
Copy fig. 5.16 and draw the logic for the 3rd bit (bit 2) in!
Solve end-of-chapter 1, 6
------------------------------------------------------------------------------------------------
Review of adders:
1-bit Full Adder
n-bit Ripple-Carry Adder
ci+1 = xiyi + (xi +yi)∙ci
n-bit Carry-Lookahead Adder
ci+1 = gi + pici
Quiz: Write the carry-lookahead functions for
i = 0 (bit 0)
s0 =
c0 =
i = 1 (bit 1)
s1=
c 1=
i = 2 (bit 2)
s2 =
c2 =
Use the functions to confirm the circuit for bits 0 and 1, then design the circuit for bit 2:
What do you notice about the fan-in of the gates?
What size gates would we need to implement a 32-bit carrylookahead adder?
We combine the two ideas:
ripple and lookahead
In order to scale efficiently, we adopt a hybrid, hierarchical approach:
We use multiple layers
of circuitry
Example:
One level → Ripple-carry between carry-lookahead blocks:
Example:
Two-level structure: propagate and generate signals for an entire block!
The blocks can have any
implementation (pure ripple, pure
lookahead or hybrid) – the only
requirement is to have “P” and
“G” outputs from the MSB.
(not in text)
(in text)
5.5 Designing Adders with CAD tools (e.g. Quartus )
A. Schematic capture
Libraries of predefined (macro)functions:
Technology-dependent
Technology-independent
Example: Library of Parametrized Modules (LPM)
Includes an n-bit adder/subtractor module
B. VHDL code
Hierarchical approach: Design a FA first, then use it as a block in a
ripple-carry adder:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
ENTITY adder4 IS
PORT ( Cin : IN STD LOGIC ;
x3, x2, x1, x0
: IN STD_LOGIC ;
y3, y2, y1, y0
: IN STD_LOGIC ;
s3, s2, s1, s0
: OUT STD_OGIC ;
Cout
: OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c1, c2, c3 : STD_LOGIC ;
COMPONENT fulladd
PORT (
Cin, x, y
: IN STD_LOGIC ;
s, Cout
: OUT STD_LOGIC ) ;
END COMPONENT ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
For modularity, we can place the FA code in a separate package
(which can be stored in a separate file)
The remainder of Section 5.5 will be covered in the lab
Skip Section 5.6 (Multiplication)
Skip Section 5.7 (Other number representations)
5.8 ASCII
7-bit ASCII
Homework for Ch.5:
17
Hint: The answer at the back of the text tells you that it’s a multiplier. Prove this,
by converting the binary numbers to decimal and checking that all the multiplications
are correct!
21
Hint: The answer at the back of the text tells you that you can use a 1-bit adder.
Prove this, by considering all 8 possible combinations of inputs.
27
Hint: Checking whether two bits are equal can be achieved with only one gate.
Which one?
Problem not from text: Redraw the gate diagram of 74x283 (4-bit adder) for the case
where the input c0 is zero. Hints:
Some gates will disappear, others will have fewer inputs.
A datasheet for 74HC283 is available on Fermat, or you can find your own on
the web.