Spring 2015
Week 9 Module 50
Digital Circuits and
Systems
Ripple Carry Adder
Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Adders and Subtracters


The most basic arithmetic operation in a digital computer is
addition.
Half Adder is a combination circuit that performs addition of 2
bits.
Inputs
Outputs
a
b
Carry
Sum
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
Sum  a b  a b  a  b
Carry  a b
Ripple Carry Adder
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Half Adder
Sum  a b  a b  a  b
Carry  a b

Half adders cannot accept a carry input and hence it is not possible
to cascade them to construct an n-bit binary adder.
Ripple Carry Adder
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Full Adder

Full Adder is a combinational circuit that forms the arithmetic sum of
three input bits. It is described by the following truth table:
Inputs
Outputs
c
b
a
Cout
Sum
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 
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Full Adder Implementation - 1
Sum  a b c  a b c  a b c  a b c  a  b  c
C out  a b  a c  b c  a b  c a  b 
ai
bi
si
ci+1
ci+1
bi
ai
Full
Adder
(FA)
ci
ci
Full Adder at bit i
Ripple Carry Adder
si
5
Full Adder Implementation - 2

A full adder can be implemented using 2 half adders and an OR gate
si
ai
bi
ci+1
ci
ai bi
ci+1
Full
Adder
(FA)
ci
si
Ripple Carry Adder
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Performance of a Full Adder

Use a 2-input NAND gate implementation of a 1-bit full adder.
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Ripple Carry Adder

4-bit Binary Adder: ( Sum = A + B )
A 4-bit binary adder can be implemented by cascading four 1-bit full
adders as follows:

Inputs:

A = (a3a2a1a0)
B = (b3b2b1b0)
Cin = cin = c0
Outputs:
Ripple Carry Adder
Sum = (s3s2s1s0)
Cout = c4
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Performance of an n-bit Ripple Carry
Adder


Carry ripples from input co to output cn
Worst case propagation delay for sum in terms of 2-input NAND gate
delay (1 gd) is given by,
n 2
t sum  5  i 1 2  3  5  2n  2  3  2n  4

Worst case propagation delay for carry output is given by,
t carry  delay for cn 1  2  5  ni12 2  2  2n  3

Therefore, propagation delay for an n-bit Ripple Carry Adder is O(n).
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Exercises

Design a signed comparator for comparing two 4-bit 1’s
complement numbers A and B


Design a signed comparator for comparing two 4-bit 2’s
complement numbers A and B


If A > B, the circuit should produce 1 as output, otherwise 0
If A > B, the circuit should produce 1 as output, otherwise 0
Design an n-bit absolute (ABS) value generator for 2’s
complement represented numbers, i.e., for an n-bit input,
X, the output is |X|
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End of Week 9: Module 50
Thank You
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