6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBV0641
DATASHEET
Description
Features/Benefits
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
• Direct connection to 100ohm transmission lines; saves 24
Recommended Application
•
•
•
•
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
•
•
Output Features
• 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
•
Key Specifications
•
•
•
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF additive phase jitter <300fs rms for SGMII
•
•
•
resistors compared to standard PCIe devices
55mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Block Diagram
vOE(5:0)#
6
DIF5
CLK_IN
CLK_IN#
SSCompatible
PLL
vSADR
9DBV0641 REVISION D 04/28/16
DIF3
DIF2
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF4
DIF1
CONTROL
LOGIC
DIF0
1
©2016 Integrated Device Technology, Inc.
9DBV0641 DATASHEET
VDD1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
9DBV0641
Paddle is GND
NC
vOE3#
DIF3#
DIF3
VDDIO
VDDA1.8
vOE2#
DIF2#
DIF2
vOE1#
NC
DIF1#
DIF1
VDDIO
DIF0#
VDD1.8
DIF0
vOE0#
VDDIO
VDDDIG1.8
11 12 13 14 15 16 17 18 19 20
40-pin VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
DIFx
SMBus
OEx# Pin
OEx bit
True O/P Comp. O/P
0
X
X
X
Low
Low
1
Running
0
X
Low
Low
1
Running
1
0
Running
Running
1
Running
1
1
Low
Low
1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.
CKPWRGD_PD#
CLK_IN
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
2
PLL
Off
On1
On1
On1
REVISION D 04/28/16
9DBV0641 DATASHEET
Power Connections
Pin Number
VDD
VDDIO
5
41
11
16, 31
GND
8
12,17,26,32,
39
25
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
Frequency Select Table
FSEL
Byte3 [1:0]
00
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
REVISION D 04/28/16
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
3
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1
vSADR_tri
2
^vHIBW_BYPM_LOBW#
3
FB_DNC
4
FB_DNC#
5
VDDR1.8
6
7
8
9
10
11
12
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
13
vOE0#
14
15
16
17
18
19
20
DIF0
DIF0#
VDD1.8
VDDIO
DIF1
DIF1#
NC
21
vOE1#
22
23
DIF2
DIF2#
24
vOE2#
25
26
27
28
VDDA1.8
VDDIO
DIF3
DIF3#
29
vOE3#
30
31
32
33
34
NC
VDD1.8
VDDIO
DIF4
DIF4#
35
vOE4#
36
37
DIF5
DIF5#
38
vOE5#
39
VDDIO
40
^CKPWRGD_PD#
41
ePAD
PIN TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are connected
DNC
internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input are
DNC
connected internally on this pin. Do not connect anything to this pin.
1.8V power for differential input clock (receiver). This VDD should be treated as an Analog
PWR
power rail and filtered appropriately.
IN
True Input for differential reference clock.
IN
Complementary Input for differential reference clock.
GND
Ground pin for digital circuitry
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
PWR
1.8V digital power (dirty power)
PWR
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
PWR
Power supply, nominal 1.8V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
N/A
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
1.8V power for the PLL core.
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
N/A
No Connection.
PWR
Power supply, nominal 1.8V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND
Connect paddle to ground.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
4
REVISION D 04/28/16
9DBV0641 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100W
2pF
Rs
2pF
Device
Driving LVDS
3.3V
Driving LVDS
Cc
R7a
R7b
R8a
R8b
Rs
Zo
Cc
Rs
LVDS Clock
input
Device
Driving LVDS inputs
Component
R7a, R7b
R8a, R8b
Cc
Vcm
REVISION D 04/28/16
Value
Receiver has Receiver does not
termination
have termination Note
10K ohm
140 ohm
5.6K ohm
75 ohm
0.1 uF
0.1 uF
1.2 volts
1.2 volts
5
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0641. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
VDDx
VIN
VIHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
-0.5
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
MAX
2.5
VDD+0.5
3.6
150
125
2000
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Input High Voltage - DIF_IN
VIHDIF
Input Low Voltage - DIF_IN
VILDIF
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
300
750
1150
mV
1
VSS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
200
725
mV
1
VSWING
dv/dt
IIN
dtin
J DIFIn
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
VIN = VDD , VIN = GND
Measurement from differential wavefrom
Differential Measurement
300
0.35
-5
45
0
1450
8
5
55
150
mV
V/ns
uA
%
ps
1
1,2
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
6
REVISION D 04/28/16
9DBV0641 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Supply Voltage
Output Supply Voltage
VDDx
VDDIO
Supply voltage for core and analog
Supply voltage for Low Power HCSL Outputs
1.7
0.95
1.8
1.05-1.8
1.9
1.9
V
V
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
TAMB
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
50MHz PLL mode
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
25
25
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
°C
°C
V
V
V
uA
200
uA
1.5
1.5
MHz
MHz
MHz
MHz
nH
pF
pF
pF
1
1
1,6
1
1
ms
1,2
30
33
kHz
0
66
kHz
1
3
clocks
1,3
300
us
1,3
VILSMB
VIHSMB
VOLSMB
I PULLUP
VDDSMB
tRSMB
t FSMB
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
200
140
175
65
7
5
2.7
6
5
5
0.8
3.6
0.4
2
2
4
5
3.6
1000
300
ns
ns
V
V
V
mA
V
ns
ns
1
1
fMAXSMB
Maximum SMBus operating frequency
400
kHz
7
Input Current
Input Frequency
Pin Inductance
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll
Fipll
Fipll
Lpin
CIN
Capacitance
CINDIF_IN
COUT
Clk Stabilization
TSTAB
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
f MODINPCIe
f MODIN
OE# Latency
tLATOE#
Tdrive_PD#
tDRVPD
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
-200
1
50
62.5
25
2.1
4
1.7
100.00
125.00
50.00
UNITS NOTES
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5
For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
6
DIF_IN input
2
7
The differential input clock must be running for the SMBus to be active
REVISION D 04/28/16
7
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Electrical Characteristics–Low Power HCSL Outputs
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
1.7
1.1
Slew rate matching
dV/dt
dV/dt
dV/dt
2.9
2.1
7
4
3.4
20
Voltage High
VHIGH
660
791
850
Slew rate
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns
V/ns
%
1,2,3
1,2,3
1,2,4
7
mV
-150
16
150
800
-3
1548
414
13
1150
-300
300
250
550
140
7
mV
mV
mV
mV
7
7
1,2
1,5
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
Powerdown Current
1
2
SYMBOL
CONDITIONS
IDDA
VDDA+VDDR, PLL Mode, @100MHz
11
15
mA
1
IDD
VDD, All outputs active @100MHz
6
10
mA
1
IDDO
VDDIO, All outputs active @100MHz
VDDA+VDDR, CKPWRGD_PD#=0
24
0.4
0.5
0.0003
30
0.6
0.8
0.1
mA
1
mA
mA
mA
1, 2
1, 2
1, 2
IDDAPD
IDDPD
IDDOPD
VDD, CKPWRGD_PD#=0
VDDIO, CKPWRGD_PD#=0
MIN
TYP
MAX
UNITS
NOTES
Guaranteed by design and characterization, not 100% tested in production.
Input clock stopped.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
8
REVISION D 04/28/16
9DBV0641 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
1.8
0.8
2.7
1.4
1.3
3.8
2
2
45
50.1
55
MHz
MHz
dB
%
1,5
1,5
1
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode @100MHz
-1
0
1
%
1,3
Jitter, Cycle to cycle
tjcyc-cyc
Bypass Mode, VT = 50%
PLL Mode VT = 50%
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
3000
0
Skew, Output to Output
tpdBYP
tpdPLL
tsk3
3600
-4
39
14
0.1
4500
200
50
50
5
ps
ps
ps
ps
ps
1
1,4
1,4
1,2
1,2
Skew, Input to Output
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
3
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4
All outputs at default slew rate
5
The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
2
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
tjphPCIeG1
tjphPCIeG2
Phase Jitter, PLL Mode
tjphPCIeG3
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
INDUSTRY
LIMIT
UNITS
86
ps (p-p)
ps
3
(rms)
ps
3.1
(rms)
ps
1
(rms)
TYP
31
MAX
52
0.8
1.4
2.3
2.5
0.5
0.6
0.5
0.6
0.7
ps
(rms)
1,2,3,5
ps
(rms)
1,2,3,5
tjphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
1.9
2
N/A
tjphPCIeG1
PCIe Gen 1
0.1
5
N/A
ps
(p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3,5
1,2,3,5
1,2,3,5
1,2,3,5
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.4
N/A
0.01
0.4
N/A
0.00
0.1
N/A
tjphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
165
200
N/A
fs
(rms)
1,6
tjphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251
300
N/A
fs
(rms)
1,6
tjphPCIeG2
Additive Phase Jitter
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
MIN
tjphPCIeG3
1,2,5
1,2,5
1,2,4,5
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGV0831 or equivalent
6
Rohde&Schartz SMA100
2
REVISION D 04/28/16
9
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Additive Phase Jitter: 125M (12kHz to 20MHz)
RMS additive jitter: 251fs
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
10
REVISION D 04/28/16
9DBV0641 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
•
•
•
Index Block Write Operation
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
IDT
Controller (Host)
starT bit
T
Slave Address
WR
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
starT bit
Slave Address
WRite
WR
ACK
WRite
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
X Byte
Beginning Byte N
Repeat starT
Slave Address
RD
ACK
ReaD
ACK
O
O
O
O
O
O
Data Byte Count=X
ACK
Beginning Byte N
Byte N + X - 1
ACK
ACK
P
stoP bit
O
O
Note: Read/Write address is latched on SADR pin.
REVISION D 04/28/16
X Byte
O
11
N
Not acknowledge
P
stoP bit
O
O
O
Byte N + X - 1
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE5
Output Enable
RW
Low/Low
Bit 7
DIF OE4
Output Enable
RW
Low/Low
Bit 6
Reserved
Bit 5
DIF OE3
Output Enable
RW
Low/Low
Bit 4
DIF OE2
Output Enable
RW
Low/Low
Bit 3
DIF OE1
Output Enable
RW
Low/Low
Bit 2
Reserved
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
0
1
PLLMODERB1
PLL Mode Readback Bit 1
Bit 7
R
See PLL Operating Mode Table
PLLMODERB0
PLL Mode Readback Bit 0
Bit 6
R
Values in B1[7:6]
Values in B1[4:3]
Enable SW control of PLL
PLLMODE_SWCNTRL
RW
Bit 5
set PLL Mode
set PLL Mode
Mode:
1
PLLMODE1
PLL Mode Control Bit 1
Bit 4
RW
See PLL Operating Mode Table
PLLMODE0
PLL Mode Control Bit 0
Bit 3
RW 1
Reserved
Bit 2
AMPLITUDE 1
RW
00 = 0.6V
01 = 0.7V
Bit 1
Controls Output Amplitude
AMPLITUDE 0
RW
10= 0.8V
11 = 0.9V
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 7
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 6
Reserved
Bit 5
SLEWRATESEL
DIF3
Adjust
Slew
Rate
of DIF3
Bit 4
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 3
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 2
Reserved
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Enable SW selection of
FREQ_SEL_EN
Bit 5
frequency
FSEL1
Freq. Select Bit 1
Bit 4
FSEL0
Freq. Select Bit 0
Bit 3
Reserved
Bit 2
Reserved
Bit 1
SLEWRATESEL FB
Adjust Slew Rate of FB
Bit 0
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Type
RW
RW
0
Slow setting
Slow setting
1
Fast setting
Fast setting
RW
RW
RW
Slow setting
Slow setting
Slow setting
Fast setting
Fast setting
Fast setting
RW
Slow setting
Fast setting
Type
0
1
RW
SW frequency
change disabled
SW frequency
change enabled
RW 1
RW 1
RW
Default
Latch
Latch
0
0
0
1
1
0
Default
1
1
1
1
1
1
1
1
Default
1
1
0
0
See Frequency Select Table
Slow setting
Default
1
1
1
1
1
1
1
1
Fast setting
0
1
1
1
Byte 4 is Reserved and reads back 'hFF
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
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REVISION D 04/28/16
9DBV0641 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
REVISION D 04/28/16
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
13
Type
RW
RW
RW
RW
RW
1
A rev = 0000
0001 = IDT
1
00 = FG, 01 = DB
10 = DM, 11= DB fanout only
000110 binary or 06 hex
0
Default
0
0
0
0
0
0
0
1
Default
0
1
0
0
0
1
1
0
1
Default
0
0
0
0
Writing to this register will configure how
1
many bytes will be read back, default is
0
= 8 bytes.
0
0
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Marking Diagrams
ICS
BV0641AL
YYWW
COO
LOT
ICS
V0641AIL
YYWW
COO
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
PARAMETER
SYMBOL
Thermal Resistance
θJC
θJb
θJA0
θJA1
θJA3
θJA5
TYP
VALUE
Junction to Case
42
Junction to Base
2.4
Junction to Air, still air
39
NDG40
Junction to Air, 1 m/s air flow
33
Junction to Air, 3 m/s air flow
28
Junction to Air, 5 m/s air flow
27
CONDITIONS
PKG
UNITS NOTES
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
ePad soldered to board
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
14
REVISION D 04/28/16
9DBV0641 DATASHEET
Package Outline and Package Dimensions (NDG40)
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
1
(Typ)
If ND & NE
2
are Even
2
Sawn
Singulation
E
E2
E2
Top View
(NE-1)x e
(Ref)
2
b
A
D
(Ref)
ND & NE
Odd
C
0.08 C
Symbol
Millimeters
Min
Max
A
A1
A3
b
e
N
ND
NE
D x E BASIC
D2
E2
L
0.80
1.00
0
0.05
0.20 Reference
0.18
0.30
0.40 BASIC
40
10
10
5.00 x 5.00
3.55
3.80
3.55
3.80
0.30
0.50
e
Thermal Base
D2
2
D2
EP – exposed thermal
pad should be
externally connected
Ordering Information
Part / Order Number Shipping Packaging
9DBV0641AKLF
Trays
9DBV0641AKLFT
Tape and Reel
9DBV0641AKILF
Trays
9DBV0641AKILFT
Tape and Reel
Package
40-pin VFQFPN
40-pin VFQFPN
40-pin VFQFPN
40-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
REVISION D 04/28/16
15
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Revision History
Rev.
A
Intiator
RDW
B
RDW
C
RDW
Issue Date Description
9/8/2014 Move from Advance to Preliminary
1. Updated front page text for consistency.
2. Updated block diagram for consistency.
9/10/2014 3. Updated electrical tables with characterization data.
4. Updated SMBus nomenclature - bits did NOT change.
5. Changed IDD spec from 8mA to 10mA MAX.
11/7/2014 1. Widened input frequency ranges for PLL modes.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
16
Page #
Various
7
REVISION D 04/28/16
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.idt.com/go/sales
www.idt.com/go/support
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