PIERS Proceedings, Beijing, China, March 23–27, 2009
546
A 2.4 GHz Low Phase Noise Voltage Controlled Oscillator
R. M. Weng and J. Y. Lin
Department of Electrical Engineering, National Dong Hwa University, Taiwan, R.O.C.
Abstract— A fully integrated voltage-controlled oscillator (VCO) fabricated with tsmc 0.18 µm
1P6M CMOS technology for Bluetooth specifications is presented. With the memory reduction
tail current source and coupling capacitors, the proposed VCO achieves phase noise as low as
−126.1 dBc/Hz at 1 MHz offset from 2.4 GHz carrier frequency. Figure-of-Merit (FOM) value at
2.4 GHz is around −188.8 dBc/Hz at 1 MHz offset. The power consumption is only 3.1 mW.
1. INTRODUCTION
Voltage-controlled oscillator (VCO) is an important part of wireless communication systems, especially in frequency synthesizer and Phase-Locked Loop (PLL). VCO is widely used to generate the
local oscillation (LO) carrier frequency for up-conversion and down-conversion mixing of the input
baseband and RF signal in a superheterodyne transceiver, respectively.
As a local oscillator in the transceiver, phase noise of VCO is one of the most important parameters for the quality and reliability. Phase noise in the oscillator can be determined by the
VCO gain (Kvco ) [1]. A large VCO gain will amplify the noise coupling to the control node and
hence degrade the phase noise performance. It also makes VCO very susceptible to noise, because
of AM to FM conversion. A VCO with a small Kvco is desirable because of its less susceptibility to
noise. But when suffer from process and temperature variations, small Kvco may cause the central
frequency of VCO drift away from the desired frequency. Tuning range and phase noise are the
trade-off in optimization of VCO performance.
2. PHASE NOISE ANALYSES OF THE VCO
To minimize the flicker noise generated after up-conversion, all even harmonics must be suppressed,
meaning the circuit must be symmetric [2]. The complementary differential structure can enhance
the symmetry of the circuit and further minimize the flicker noise. By proper sizing of the transistors, the circuit can be optimized to have more symmetry in the output waveform, thus it can
get lower 1/f 3 noise corner frequency. To achieve low phase noise and low power consumption,
complementary cross-coupled structure would be chosen in this design. Phase noise can be modeled
by the modified Lesson’s formula [3]:
("
)
µ
¶2 # µ
¶
2
f0
fc F kT
2kT RKvco
L(fm ) = 10 log
1+
1+
+
,
(1)
2
2fm Q
fm 2Pav
fm
where
L(fm ) phase noise in dBc/Hz;
fm frequency offset from the carrier in Hz;
f0 central frequency in Hz;
fc flicker noise corner frequency in Hz;
Q the loaded quality factor (Q) of the tuned circuit;
F noise factor;
k Boltzmann’s constant in J/K;
T temperature in K;
Pav average power at oscillator output;
R the equivalent noise resistance of the varactor;
Progress In Electromagnetics Research Symposium, Beijing, China, March 23–27, 2009
547
Kvco oscillator voltage gain in Hz/V.
From (1), Kvco dominates the phase noise performance in the modified Lesson’s formula, thus phase
noise performance can be improved by reduction Kvco . Kvco can be written as:
Kvco =
df
df dC
−1
dC
dC
=
·
=
· L−1/2 · C −3/2 ·
= −2π 2 Lf 3
,
dV
dC dV
4π
dV
dV
(2)
Thus for a given inductance L, Kvco is proportional to dC/dV of varactor within a small range of
frequency.
3. PROPOSED LOW PHASE NOISE VCO
Figure 1 shows the proposed low phase noise VCO. The complementary structure has high transconductance compared to that of NMOS-only or PMOS-only architecture. Current reusing in double
cross-coupled pairs (PMOS and NMOS) can be used to decrease the supply current so as to achieve
low power design.
Vdd
C1
M2
M1
C2
C3
C v2
C v1
V out-
V tune
L
M3
M4
M5
M6
Figure 1: Proposed low phase noise VCO.
The cross-coupled pairs (M 1 ∼ M 4) provide the negative resistances to compensate the parasitic
resistance of an LC-resonator to have better quality factor. The negative resistance can be expressed
as:
−2
,
(3)
Rnegnative =
GM n + GM p
where GM n and GM p are the transconductances of NMOS and PMOS pair.
Table 1: Definition of four types of VCOs.
Type
Definition
VCO1
Traditional LC-tank VCO (Figure 1 without C1 ∼ C3 and M 5, M 6)
VCO2
Proposed VCO with C1 = C2 = 0.5 pF without memory reduction tail current source (M 5 and M 6)
VCO3
Proposed VCO with C1 = C2 = 1 pF without memory reduction tail current source (M 5 and M 6)
VCO4
Proposed VCO with C1 = C2 = 1 pF and memory reduction tail current source (M 5 and M 6)
The oscillator frequency can be expressed as
fosc =
1
√
,
2π LC
(4)
PIERS Proceedings, Beijing, China, March 23–27, 2009
548
where L is the inductance of LC-tank, C is mainly the capacity of Cv1 and Cv2 in parallel. The
effect of C3 and coupling capacitors C1 and C2 are included in the total capacitance C.
In the previous section, Kvco is proportional to dC/dV . Coupling capacitors C1, C2, and
fixed capacitor C3 are added to decrease dC/dV . The slope of CV curve is smoother than the
traditional LC-tank VCO. When coupling capacitors become larger, the tuning range of VCO would
be narrower. Thus a VCO with low phase noise can be achieved.
A small tuning range will result in central frequency drifting due to the process and temperature
variations. In order to reduce phase noise while maintaining tuning range large enough to cover
the process and temperature variation, C1 and C2 are designed with 1 pF.
Tail current source is usually added for two reasons. One is for the limiting of the VCO output
amplitude, hence preventing devices from going into deep triode region which degrades phase noise
performance [4]. The other is to provide large common-mode impedance to reject the noise coupling
from ground. Unfortunately, the tail current source is one of the major contributor to the phase
noise of VCO. Besides, traditional biasing circuit needs an extra biasing voltage, which increase
the power consumption and also introduces noise to the VCO.
Hence, a memory reduction tail current source is formed with M 5 and M 6. M 5 and M 6 were
used to force a trap and release its capture electron, rendering the transistors to be memory-less [5].
Since all the transistors in Figure 1 are switched biasing, it is expected to have lower flicker noise.
4. SIMULATION RESULTS
The VCOs are simulated with tsmc 0.18 µm CMOS process. Four types of VCOs are defined in
Table 1 to demonstrate the performance of the proposed VCO.
When coupling capacitors C1 and C2 becomes larger, the tuning range of VCO would be narrow
as shown in Figure 2. Thus low phase noise can be achieved by decreasing Kvco . Figure 3 shows
a phase noise comparison with four types of VCOs. By adding the memory reduction tail current
source (M 5 and M 6) with the same power consumption, phase noise of VCO4 at 1 MHz offset is
about 1.5 dB lower than VCO3.
3.0
40
VCO1
VCO2
VCO3
VCO4
20
VCO1
VCO2
VCO3
VCO4
0
Phase Noise (dBc/Hz)
Output Frequency (GHz)
2.8
2.6
2.4
2.2
-20
-40
-60
-80
-100
-120
2.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Vtune (V)
Figure 2: Tuning range performance.
1.6
-140
10
100
1k
10k
100k
1M
Frequency Offset (Hz)
Figure 3: Phase noise performance.
Simulation results show that VCO4 has the lowest phase noise. The simulated phase noise of the
proposed VCO4 is −126.1 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz.
Figure 4 shows the output power 5 dBm at 2.4 GHz. The figure of merit (FOM) which used to
depict the performance of VCO is defined as [6]:
µ
¶
µ
¶
f0
PDC
F OM = L{∆f } − 20 log
+ 10 log
,
(5)
∆f
1 mW
where L{∆f } is the phase noise at the offset frequency ∆f from the carrier frequency of f0 and
PDC is the power consumption in mW. The layout of the fabricated chip is shown in Figure 5. The
whole chip area is 0.816 × 0.976 mm2 .
Progress In Electromagnetics Research Symposium, Beijing, China, March 23–27, 2009
549
5 dBm@2.4 GHz
Figure 4: Output spectrum of the proposed VCO.
Figure 5: Layout of the proposed low phase noise
VCO.
Table 2: Performance comparison of VCOs in 0.18 µm CMOS.
Ref
PDC (mW)
Freq (GHz)
Tuning Range (MHz)
Phase Noise (dBc/Hz) FOM (dBc/Hz)
Figure 1
3.1
2.4
330
−126.1@1 M
−188.8
[7]
2.77
1.95
341
−112.75@0.6 M
−178.6
[8]
1.5
2.55
131
−119.2@1 M
−185.6
[9]
2.7
2.6
560
−122.3@1 M
−186.3
[10]
3.06
1.57
240
−120@1 M
−179.1
5. CONCLUSIONS
Low phase noise and low power VCO in 0.18 µm CMOS technology is presented. With the memory
reduction tail current source and coupling capacitors, the proposed VCO achieves phase noise as
low as −126.1 dBc/Hz at 1 MHz offset from 2.4 GHz carrier frequency. The output oscillation
frequency can be tuned from 2.25 GHz to 2.58 GHz with 14% tuning range. The performance
comparison with the proposed VCO and some prior works are summarized in Table 2, a superior
FOM of −188.8 dBc/Hz compared with other VCOs is proved. The proposed low phase noise VCO
is suitable for 2.4 ∼ 2.4835 GHz ISM band of the Bluetooth standard.
ACKNOWLEDGMENT
The authors wish to thank the Chip Implementation Center (CIC) of the National Applied Research
Laboratories, Taiwan, R.O.C., for supporting the tsmc CMOS process and further fabrication.
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