ECEN: 607
Advanced Analog Circuit Design Techniques
Homework – 1
Spring 2008
By
Shweta Anugu
UIN: 917000951
Date: January 25th, 2008
Problem1:
Plot of f T , Power Consumption (W/L) vs inversion level if(id)
Equations connecting the inversion level (id) and the required parameters to be plotted in
the ACM model are given below:
1 + 1 + id
2
W
gm
1
=
(
)
L μ .Cox.φt 1 + id − 1
μ .φt
fT =
2( 1 + id − 1)
2πL2
Id = gm.n.φt
The above plot was generated using MATLAB. Please see the appendix for the code.
Plot of fmax ( f T ) versus id (if) for (W/L) = (100µ/0.6µ, 100µ/3µ):
Using f T =
μ .φt
2( 1 + id − 1) and MATLAB (please refer to the appendix for the code)
2πL2
the below plot is generated.
Comments:
Î fT decreases with increase in length
Problem2:
Extraction of parameters for the NMOS transistor for the ACM Model:
For the extraction by simulation, a MOS transistor with W = 22µm and L = 3µm and
BSIM were used.
Extraction of IS:
For the circuit in Fig.1, when operated in strong inversion (if>100), the current IS can be
determined from
Cadence Schematic:
Using VDD=1.5V and VSS=-1.5V, I=40µA, ΔI = 4µA, we obtain IS = 341.27nA
Extraction of VT0:
A general expression for VGS, if the MOSFET is saturated and VSB = 0, can be written as
VGS = VT + nφt [ 1 + id − 2 + ln( 1 + id − 1)
Hence, with an id of 3 and VS = VB = 0, we get VG = VT from the above equation.
Circuit for extracting VT is given below in Fig. 2
Cadence Schematic with the DC Voltages annotated:
VT0 is thus found out to be 0.7129V.
Extraction of VP and n:
Expression for VP in terms of the inversion level id is given by the following equation:
VP − VS ( D ) = φt [ 1 + id − 2 + ln( 1 + id − 1)
For id =3, VP = VS. Therefore the setup in Fig. 3 is used to extract VP.
From the VG Vs VP curve, and for VG=0V, VP = VS = 0.6V
Circuit in Fig. 3 is used for extraction of n. Plot of n versus VP is given in the below
figure
Cadence Schematic:
Plot of n Vs VP:
Thus from the graph we find n = 1.266 for VP = 0.6V.
Extraction of γ:
GAMMA is the body effect coefficient, whose value can be obtained from the expression
below
γ = (n − 1).2. 2φ F + VP .
With the extracted n and VP values and 2ΦF = 0.7V, γ = 0.592V1/2
Extraction of µ0 and θ (THETA):
µ0 is the carrier mobility for low values of the electric field and Ө is the ACM fitting
parameter which accounts for the mobility variation with the transverse field.
The following setup (Fig. 6) is used to extract these parameters. Transistor is
biased in the linear region (VDS=100mV) and in strong inversion. VGS is varied from
2VT0 to VDD.
Cadence Schematic:
Using the equation
1
Versus VGS curve is obtained by means of DC simulation as shown in Fig 7.
μC ox (W / L)
Using Equation
And from the coefficients A(Slope=175.676) and B(Intercept=1102.973) of the straight
line in the above figure, µ0 and θ are extracted from the following equations
Ö µ0 = 602.14cm2/Vs
Ö θ = 0.378V-1
Extraction of SIGMA
DIBL (Drain-Induced Barrier Lowering) effect is modeled by SIGMA, defined as
Where σ represents the variation of the threshold voltage with both VD and VS:
The circuit in Fig 8 is used for the extraction of Sigma. Since DIBL is more important for
short-channel transistors, the channel length was set to minimum for this technology
(0.6µm). IB = 0.1IS is used and VD is varied from 200mV to 500mV and using
SIGMA Versus VD (Figure 10) is obtained.
Fig 9: Cadence Schematic
Fig 10: SIGMA versus VD
SIGMA was measured at VD=350mV resulting in SIGMA = 6.62622*10-15 m2
Extraction of PCLM:
PCLM represents the reduction of the effective length of the inversion channel due to an
increase in the drain voltage VD.
The PCLM parameter can be obtained by plotting the Early Voltage (VA) as function of
VDS-VDSAT obtained using the circuit of Fig 11. VA is defined as
The plot of VA vs VDS is shown in Fig 12. The value of IB is such that the inversion level
if=200. In this case W=220.5µm and L=30µm. Slope(192.73) of the straight line
approximation of the plot would give the PCLM value from the following equations.
PCLM thus extracted is 0.6172
Fig 12: Plot of VA vs VDS
Extraction of parameters for the PMOS transistor for the ACM Model:
For the extraction by simulation, a PMOS transistor with W = 54.75µm and L = 3µm and
BSIM were used.
Extraction of IS:
For the circuit in Fig.1, when operated in strong inversion (if>100), the current IS can be
determined from
Cadence Schematic:
Using VDD=5V and VSS=0V, I=40µA, ΔI = 4µA, we obtain IS = 232.114nA
Extraction of VT0:
A general expression for VGS, if the MOSFET is saturated and VSB = 0, can be written as
VGS = VT + nφt [ 1 + id − 2 + ln( 1 + id − 1)
Hence, with an id of 3 and VS = VB = 0, we get VG = VT from the above equation.
Circuit for extracting VT is given below in Fig. 2
Fig 2: Cadence Schematic with the DC Voltages annotated
VT0 is thus VGS = 4.084-5 = -0.916V.
Extraction of VP and n:
Expression for VP in terms of the inversion level id is given by the following equation:
VP − VS ( D ) = φt [ 1 + id − 2 + ln( 1 + id − 1)
For id =3, VP = VS. Therefore the setup in Fig. 3 is used to extract VP.
Fig 3: Cadence Schematic for the extraction of VP and n
From the VG Vs VP curve, and for VG=2.5V, VP = VS = 3.73V
Fig 4: Plot of VG Vs VP
Circuit in Fig. 3 is used for extraction of n. Plot of n versus VP is given in the below
figure.
Fig 5: Plot of n Vs VP
Thus from the graph we find n = 1.2 for VP = 3.78.
Extraction of γ:
GAMMA is the body effect coefficient, whose value can be obtained from the expression
below
γ = (n − 1).2. 2φ F + VP .
With the extracted n and VP values and 2ΦF = 0.7V, γ = 0.84V1/2
Extraction of µ0 and θ (THETA):
µ0 is the carrier mobility for low values of the electric field and Ө is the ACM fitting
parameter which accounts for the mobility variation with the transverse field.
The following setup (Fig. 6) is used to extract these parameters. Transistor is
biased in the linear region (VDS=100mV) and in strong inversion. VGS is varied from
2VT0 to VDD.
Fig 6: Cadence Schematic for the extraction of µo and θ
Using the equation
1
Versus VGS curve is obtained by means of DC simulation as shown in Fig 7.
μC ox (W / L)
Using Equation
And from the coefficients A(Slope=258.06) and B(Intercept=1214.774) of the straight
line in the above figure, µ0 and θ are extracted from the following equations
Ö µ0 = 205.56cm2/Vs
Ö θ = 0.474V-1
Extraction of SIGMA
DIBL (Drain-Induced Barrier Lowering) effect is modeled by SIGMA, defined as
Where σ represents the variation of the threshold voltage with both VD and VS:
The circuit in Fig 8 is used for the extraction of Sigma. Since DIBL is more important for
short-channel transistors, the channel length was set to minimum for this technology
(0.6µm). IB = 0.1IS is used and VD is varied from 200mV to 500mV and using
SIGMA Versus VD (Figure 9) is obtained.
Fig 9: Cadence Schematic for the extraction of SIGMA
Fig 9: SIGMA versus VD
SIGMA was measured at VD=350mV resulting in SIGMA = 16.47*10-15 m2
Extraction of PCLM:
The PCLM parameter can be obtained by plotting the Early Voltage (VA) as function of
VDS-VDSAT obtained using the circuit of Fig 10. VA is defined as
Fig10: Cadence Schematic for extraction of PCLM
The plot of VA vs VDS is shown in Fig 11. The value of IB is such that the inversion level
if=200. In this case W=547.5µm and L=30µm. Slope (0.95) of the straight line
approximation of the plot would give the PCLM value from the following equations.
PCLM thus extracted is 391.34
Fig 11: Plot of VA vs VDS
3.
Buffer1: Design of a low impedance buffer with if=8 and VDD=-VSS=1.65
Designing for Rout = 1KΩ.
1
. Equating both gives gm1 = 0.91mA/V.
g m1 + g mb1
Designing for gm1=1.1mA/V. As we know gm1 and if, we can calculate ID, W/L from the
ACM model equations.
Rout of the above circuit is
1 + 1 + id
2
W
gm
1
(
=
)
L μ .Cox.φt 1 + id − 1
Id = gm.n.φt
Thus we get Id = 72.24µA and (W/L)1=162.47. For L1=0.6µm, W1=97.485µm
As M2 transistor also carries same Id current and has same if (=8), it is also designed for
(W/L)2=162.47.
VG2 voltage is generated using a current mirror of same W/L and current as M2.
M1 transistor is biased at a voltage which would give equal output voltage swing in both
the directions.
From the DC transfer curve (as shown in Fig 3.1), we see that Vin of 0.3621V would give
a swing of 1.1735V in both the directions i.e., from -1.58V to 0.767V.
Fig 3.1 DC Transfer Curve
Thus we see the Max vout is 1.1735V.
Max Iout :
Following setup is used to measure Max Iout
Max Iout thus measured = 589.7uA
Voltage Gain and 3dB frequency:
As seen from the plot (Fig3.2) below for the gain of the buffer (obtained from the ac
simulations), the voltage gain is -0.97dB.
And f3dB =174.162MHz
Fig 3.2 Plot of the gain of the buffer
Output Impedance:
Following setup is used to measure the output impedance.
Fig 3.3 Cadence schematic showing the setup for measuring output impedance
From the below plot, we get output impedance = 0.6824KΩ
PSRR+:
PSRR+ = 34.81dB
Fig 3.4 PSRR+ plot
PSRRPSRR- = 19.99dB
Fig 3.5 PSRR- plot
Settling Time 0.1%
Settling Time(0.1%) = 103.254ns
Fig 3.6 Plot showing the settling time (0.1%)
DC Operating point of the M1 transistor is given in the following figure:
Power Consumption
Power Consumption = (VDD-VSS)*I = 3.3*86.03u = 0.2834mW (excluding the bias
current source)
Cin
Input Capacitance Cin = Cgg=128.4fF
Input referred noise
Integrated noise summary report for the 3 transistors:
CMR
CMR = -1.02V to 1.65V (Obtained from the DC transfer curve in Fig 3.1)
Buffer2: Design of a low impedance buffer with if=8 and VDD=-VSS=1.65
Designing for Rout = 1KΩ.
1
. Equating both gives gm1 = 0.91mA/V.
g m1 + g mb1
Designing for gm1=1.1mA/V. As we know gm1 and if, we can calculate ID, W/L from the
ACM model equations.
Rout of the above circuit is
1 + 1 + id
2
W
gm
1
(
=
)
L μ .Cox.φt 1 + id − 1
Id = gm.n.φt
Thus we get Id = 72.24µA and (W/L)1=162.47. For L1=0.6µm, W1=97.485µm
M2 transistor is also designed for (W/L)2=(W/L)1 =162.47.
VG2 voltage is generated using a current mirror of same W/L and current as M2.
M1 transistor is biased at a voltage which would give equal output voltage swing in both
the directions.
M3 and M4 transistors are carrying the same current and inversion level as M1.
Therefore (W/L)3 = (W/L)4 = 2.5(162.47) = 406.175.
From the DC transfer curve (as shown in Fig 3.9), we see that Vin of 0.3168V would give
a swing of 1.0995V in both the directions i.e., from -1.59V to 0.609V.
Fig 3.9 DC Transfer Curve
Thus we see the Max vout is.0.6V
Max Iout :
Max Iout = 568.8uA
Voltage Gain and 3dB frequency:
As seen from the plot (Fig3.10) below for the gain of the buffer (obtained from the ac
simulations), the voltage gain is- 0.94dB.
And f3dB =275.025MHz
Fig 3.10 Plot of the gain of the buffer
Output Impedance:
Following setup is used to measure the output impedance.
Fig 3.11 Cadence schematic showing the setup for measuring output impedance
Thus Output impedance calculated is 45.17Ohms
PSRR+
PSRR+ = 32.34dB
Fig 3.12 PSRR+ plot
PSRRPSRR- = 20.89dB
Fig 3.13 PSRR- plot
Settling Time 0.1%
Settling time = 14.18ns
Fig 3.14 Plot showing the settling time (0.1%)
DC Operating point of the input transistor M1
Power Consumption
Power Consumption = (VDD-VSS)*I = 3.3*144.4u = 0.47652mW
Cin
Input Capacitance Cin = 127.1fF
Input referred noise
CMR
CMR is -1.01126V to 1.48067V(As obtained from the DC transfer curve)
Table comparing the various specifications of a low impedance buffer for buffer1
and 2
Max vout
Max Iout
Gain
F3dB
Output Impedance
PSRR+
PSRRSettling Time (0.1%)
Power Consumption
Input Capacitance Cin
Input Referred Noise
CMR
Buffer1
1.1735V
589.7uA
-0.97dB
174.162MHz
0.6824KΩ
34.81dB
19.99dB
103.24ns
0.2834mW
128.4fF
5.87nV2/Hz
-1.02V to 1.65V
Buffer2
1.0995V
568.8uA
-0.94dB
275.025MHz
0.04517KΩ
32.34dB
20.89dB
14.18ns
0.47652mW
127.1fF
11.457nV2/Hz
-1.01126V to 1.48067V
Comments:
1. Buffer 2 has lower impedance than Buffer1 as the gm of the input transistor is
boosted with the amplifier in the feedback.
2. Settling time is less in case of buffer 2 but ringing is seen.
APPENDIX:
1. MATLAB code to generate the plot of various parameters ( fT, power consumption,
silicon area vs inversion level(id) ):
id = logspace(-2,3);
loglog(id,1./((sqrt(1+id))-1),'-<',id,((sqrt(1+id))+1)./2,'-*',id,((sqrt(1+id))-1)*2,'-.+');
legend('Normalized Silicon Area','Normalized Power
Consumption','Normalized fT');
xlabel('Inversion Level(id)');
ylabel('Normalized Power Consumption,fT and Silicon Area');
title('Normalized parameters vs Inversion Level(id)');
2. MATLAB code to generate the plot of fT Vs if for different Ls:
id = logspace(-2,3);
loglog(id,((sqrt(1+id))-1)*2*1222.8264,'--*',id,((sqrt(1+id))1)*2*48.9131,'-.+');
legend('fT for L=0.6um','fT for L=3um');
xlabel('Inversion Level(id)');
ylabel('fT in MHz');
title('fT vs Inversion Level(id)');
References:
1. S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design
Techniques: A Tutorial, IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp 179196, February 2000
2. Rafael M. Coitinho, Luis H. Spiller, Marcio C. Schneider, Carlos Galup-Montoro,
"A Simplified Methodology for the Extraction of the ACM MOST Model
Parameters," sbcci, p. 0136, 14th Symposium on Integrated Circuits and Systems
Design, 2001