ESE 570 Chip Input and Output (I/O)
Circuits
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
1
OVERVIEW
1. INPUT PADS – ESD PROTECTION
2. TTL-TO-CMOS LOGIC LEVEL SHIFTING
3. DIFFERENTIAL SIGNALING
4. OUTPUT PADS – L di/dt NOISE
5. BIDIRECTIONAL I/O PADS
6. ON-CHIP CLOCK GENERATION AND DISTRIBUTION
7. LATCH-UP PROTECTION IN OUTPUT PADS
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
2
ESD PROTECTION
Machine Model (MM)
Human Body Model (HBM)
Charged-Device Model (CDM)
Electrostatic charge
builds up on a chip
due to improper
grounding and then
discharges
when a lowresistance path
becomes available.
1 MΩ
Vesd
B
Bulk or
Ground
Pin
DUT
low
resistance,
low
inductance
probe
Simulates ESD phenomena of packaged ICs
during manufacturing and assembly.
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
3
ATE HBM ESD and MM ESD TEST
SETUP
1.4
current I (A)
SPICE-generated shortcircuit HBM output
current waveform
specified by MIL-STD
883.C/3015.7 for Cc
charged to 2kV
0
0
100
time (ns)
After exposure to the ESD waveform, a
failed IC exhibits latch-up or fails one or
more data sheet specifications.
200
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
4
TYPICAL ESD PROTECTED INPUT PAD
VDD
I
or 8A ≥ I ≥ 2.6 A.
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
5
INPUT PAD WITH SERIES
TRANSMISSION GATE
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
6
INVERTING INPUT PAD WITH TTL-TO-CMOS
LEVEL SHIFT
VDD = 5 V
CMOS
TTL
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
7
VARIATIONS IN LEVEL-SHIFT VTC DUE
TO PROCESS VARIATIONS
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
8x
8
WORST CASE SIMULATION METHOD
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
9
Differential Signaling System
Transmitter
Two-wire pair
Receiver
I = +i
I = -i
Terminator
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
10
DIFFERENTIAL SIGNALING (LOGIC
LEVELS) FOR GBPS SYSTEMS
1.400 V
VOL
1.000 V
0.400 V
1.220 V
1.100 V
1
2
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
11
OUTPUT PADS
CK or
CK
ST
1
1
00
D
1
0
xx
P
0
1
11
N Z
0
1=D
1
0=D
HIGH
0 0 High
Z Z
MP1
MP2
MN2
CK = 0 => MN2 & MP2 OFF => Z = HIGH Z
CK = 1 => MN2 & MP2 ON => Z = D
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
MN1
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OUTPUT PADS – L di/dt NOISE
Cload
I max
ts/2
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
assume
Cload
charged
to VDD
13
OUTPUT PADS – L di/dt NOISE
REDUCE NOISE => lower VDD or increase ts -> limits speed
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
14
OUTPUT PADS – REDUCE L di/dt NOISE
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
15
DIFFERENTIAL DRIVER OUTPUT PAD
VDD/2
tD Delay Element
tD
“1”
“1”
“0”
A = IN (t - tD)
“1”
“0”
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
“1”
Much
reduced
[di/dt]max
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BIDIRECTIONAL I/O PAD WITH TTL
INPUT CAPABILITY
E=1
E=0
D
1
X
D
0
E = 1 => Z = D
E = 0 => X = high Z
E = 0 => DI = Z
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
17
ON-CHIP CLOCK GENERATION AND
DISTRIBUTION
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
18
TWO-PHASE CLOCK GENERATION
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
19
H-TREE CLOCK DISTRIBUTION NET
FOR UNIFORM CLOCK DISTRIBUTION
CAD
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
20
LATCH-UP IN CMOS CIRCUITS
2
A
q
D
n
BJT saturation
E
n i
I
=
S
current
N AW
2
1
1
x

NSUB nMOS − pMOS spacing
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
21
LATCH-UP – POSITIVE FEEDBACK
Bipolar Current Gains
IC
IC
= 1 0= 1
IB
IE

=
1−
IB1 = IC2
IB1
IC2 = β2β1IB1
Rwell = Rsub.=∞
Latch-up
Analysis with
Rwell = Rsub.=∞
Prevent latch-up by reducing
positive feedback
β1β2 ≤ 1
1
2
1  1 =
≤ 1⇒ 1 2 ≤ 1
1−1 1− 2
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
IB2
IC1 = β1IB1
IB2 = IC1
time = t1 > 0:
IB1 = x => IC1 = β1 x
time = t2 > t1
IB2 = IC1 = β1 x => IC2 = β2β1 x
positive feedback! if β2β1 22
≥1
LATCH-UP PREVENTION
Latch-up prevention with
parasitic resistances Rwell
and Rsub
RT
RT
1 
2
R well
R sub
1  2 ≥≤ 1
V DD
−2
make small
V
V BE BE
Reduce α1, α2
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
Latch-up occurs
if NOT satisfied
; Decrease VDD
23
OUTPUT BUFFER CELL LAYOUT WITH
LATCH-UP PREVENTION
Kenneth R. Laker, University of Pennsylvania, updated 25Mar13
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