Freescale Semiconductor
Application Note
Document Number: AN5181
Rev. 0, September 2015
Introduction to the MPC5746R
Trace Adapter
Including an overview of the Emulation Device
by:
Randy Dees
Contents
1 Introduction
The MPC5746R is a dual-core Power Architecture® based
microcontroller (MCU) that includes an enhanced Timing
Processor Unit 2. It is typically used in automotive powertrain
or transmission applications. The MCU is available in three
different production packages to handle a range of application
requirements. A fourth package is available that is primarily
used for development. This development package includes
additional features that are not available in the production
packages. The development device is called the Emulation
Device or ED. The following table shows the different
package options.
Table 1. MPC5746R Package options
Device
Package
MPC5646R Production
Device
144 LQFP
MPC5646R Production
Device
176 LQFP
MPC5646R Production
Device
252 MAPBGA
MPC5646R Emulation Device 292 MAPBGA
© 2015 Freescale Semiconductor, Inc.
1
Introduction............................... ............................... 1
2
Trace Adapter overview............................................2
3
Emulation Device overview............ ......................... 8
4
BD Nexus Read/Write Access client...................... 14
5
Attaching the MPC5746R Trace Adapter
to an EVB.................................................. ............. 15
6
Using the MPC5746R Trace Adapter with
a customer target system............................. ............16
7
MPC5746R Trace Adapter orderable
parts ...................................................... ................. 17
A
MPC5746R Trace Adapter schematics
and drawings........................................... ................17
B
Debugging Emulation Devices with
Lauterbach TRACE32............................ ................ 35
C
Debugging the MPC5746R Emulation
Device with the PLS UDE...................................... 38
D
MPC56xx and MPC57xx available
Trace Adapters........................................................ 41
E
References...............................................................44
Trace Adapter overview
To support development of new systems, the development or emulation device is available on a small board that can be used
to adapt the Emulation Device into the footprint of the production packages. This is the Trace Adapter (TA).
This application note provides an overview of the MPC5746R TA boards, an overview of the features of the Emulation
Device, and an introduction to use of the Emulation Device with the Lauterbach TRACE32® debugger and the PLS
Universal Debug Engine debugger. While this application note is written about the MPC5746R TA, many of the concepts
apply directly to the MPC5777M TA and may also apply to other development solutions available from Freescale for other
MPC56xx and MPC57xx Microcontrollers (MCUs).
2 Trace Adapter overview
Freescale has created "Trace Adapters" (TA) to provide a full development environment that does not require that the
customer include a full trace connector in their production module. The TA provides access to the full trace capabilities that
are included in the emulation version of the device.
• 12 V power supply input
• Power supply for portions of the emulation device
• Full Nexus high-speed (Aurora) trace connector (17 position [34 pin] Samtec ASP–137973–01)
• Standard 14-pin Freescale Automotive Power Architecture JTAG connector
• User configurable options for some connections to the customer module
In cases where the emulation device has a different package than the production packages, TAs are available for the different
production device footprints.
2.1 Trace Adapter hardware requirements
Use of the Trace Adapter (TA) allows access to all of the development features of the device without requiring a trace
connector in the end-user's module. Modules should include a 14-pin JTAG connection, but a trace connector is not required.
The TA has options that allow the JTAG pins of the Emulation Device to be disconnected from the JTAG connector in the
production module. This eliminates signal integrity issues with the multiple JTAG connectors and allows higher speed access
of the JTAG port of the MCU. By default the TA JTAG signals are isolated from the production module signal traces, but can
be connected if required.
The TA includes power regulators to power extra circuitry available in the Emulation Device. This allows the Buddy Die
(BD) of the Emulation Device to be powered independently of the standard Production Die (PD), also located in the
Emulation Device (see Emulation Device overview. These additional power supplies can be used to preload the calibration
memory (overlay SRAM) prior to powering up the PD. This does require minimal power sequencing.
NOTE
The power supplies of the BD must be powered either prior to the power supplies of the
PD or at the same time. The PD power supplies should never be powered prior to the BD.
The different power supplies of the MPC5746R are shown in the following table.
Table 2. MPC574xR power supplies
Supply name
Nominal Voltage
Description
Circuitry powered
Production die power supplies
VDD_LV
1.25 V
Core Logic Low Voltage Supply
Most internal circuitry
VDD_HV_IO_MAIN
5.0 V
Main I/O Voltage Supply
Most device Input and output circuits
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Trace Adapter overview
Table 2. MPC574xR power supplies (continued)
Supply name
Nominal Voltage
Description
Circuitry powered
VDD_HV_ADV_SA
R
5.0 V
SAR ADC Voltage Supply
SAR ADC converter
VDD_HV_ADR_SA
R
5.0 V
SAR ADC Voltage Reference
Reference for SAR_ADC
VDD_HV_ADV_SD
5.0 V
Sigma-Delta (SD) ADC Voltage Supply
SD ADC Converter
VDD_HV_ADR_SD
5.0 V
Sigma-Delta ADC Voltage Reference
Reference for SD ADC
VDD_HV_IO_JTAG
3.3 V or 5.0 V
Production Device JTAG I/O and
External Oscillator Voltage Supply
JTAG pins1 on production device and
the crystal oscillator circuits
VDD_HV_IO_FEC
3.3 V or 5.0 V
Ethernet I/O Supply
Ethernet controller pins
VDD_HV_IO_MSC
3.3 V or 5.0 V
Microsecond Channel (MSC) I/O Supply MSC pins
VDD_HV_PMC
5.0 V
Power Management Controller Supply
VDD_HV_FLA2
3.3 V
PMC Flash Regulator Bypass Capacitor Flash circuitry
VDDSTBY
1.3 V to 5.9 V
Internal regulators
Standby RAM Supply Input
Standby SRAM
1.25 V
Buddy Device Core Logic Low Voltage
Supply
Internal BD circuitry
3.3 or 5.0 V
Buddy Device Main I/O Voltage Supply
JTAG3 and Nexus pins on the BD
Buddy die power supplies
VDD_LV_BD
VDD_HV_IO_BD
1. In the emulation device, the JTAG pins of the production die are not connected in the package.
2. No connection to external supply required, but requires a bypass capacitor.
3. The JTAG pins of the Emulation device must be powered in the emulation device.
2.2 Trace Adapter connector locations
The Trace Adapter (TA) allows the use of either the Nexus Aurora connector or a JTAG only connection. The Nexus Aurora
connector permits the full debugging capabilities to be accessible to the tool The JTAG only connector can be used for cases
where features of the Emulation Device are needed, but Nexus trace is not required.
The TA requires a 12 V power supply for operation of the Emulation Device. A 2-pin connector is provided for this supply.
The TA is shipped with a connector/wire assembly for power. The ends of the wires can be stripped and connected to the 2terminal screw-connector on the Freescale MPC57xxMBB (Evaluation board[EVB]) motherboard to supply this power.
NOTE
The screw terminals are powered even when the ON/OFF switch on the motherboard is
off.
The figure below shows the placement of components on the MPC5746R 252 BGA TA. It shows the external power
connector and both the Nexus Aurora trace connector and the JTAG debug connector. The board dimensions are shown in the
appendix MPC5746R Trace Adapter schematics and drawings.
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Trace Adapter overview
Nexus Aurora connector
Power Connector
GND
12 V
MCU
JTAG connector
Figure 1. MPC5746R 252 BGA Trace Adapter parts placement
NOTE
The power connector on the first revision of the MPC5746R TA (REV 0) reversed the
ground and 12V power connections.
2.3 MPC57xx standardized/legacy JTAG connector
The following table shows the pin out of the recommended JTAG connector to support the MPC57xxX devices.
This connector for the target system is the Tyco part number 2514-6002UB.
NOTE
This pin out is similar to the previous Freescale MPC5500/MPC5600 family of devices.
The differences are shown below.
Table 3. JTAG only connector pin-out
Description
Pin
Pin
Description
TDI
1
2
GND
TDO
3
4
GND
TCK
5
6
GND
EVTI/EVTO1
7
8
PORST2, 3
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Trace Adapter overview
Table 3. JTAG only connector pin-out (continued)
Description
Pin
Pin
Description
RESET/ESR0
9
10
TMS
VREF
11
12
GND
RDY4
13
14
JCOMP
1. One set of EVTI and EVTO pins may be multiplexed together in the MCU package. (This pin was EVTI-only on the
MPC5500/MPC5600 devices).
2. This pin was a no-connect on the MPC55xx and MPC56xx devices.
3. On some devices, this pin is named ext_POR.
4. The RDY signal is not available on the MPC57xxM devices. EVTO0 can be placed on this pin instead.
2.4 MPC57xx high-speed serial trace connector
For high speed Nexus Aurora trace applications, the Samtec ERF8 Series connector is recommended in the IEEE-ISTO
5001-2011 standard. For the MPC57xx family, the 17 position (34 pins) connector is recommended. The part numbers of the
Samtec connectors are shown in the following table.
Table 4. Recommended high-speed serial trace connector part numbers
Connector
Part number
(Samtec)
Style
Description
HS34
ASP-137973-01
Samtec ERF8 Series, 17 position by 2
row
Vertical mount for MCU module
HS34
ASP-177706-02
Samtec ERF8 Series, 17 position by 2
row
Right Angle mount for MCU module
The Samtec ERF8 series of connectors is intended for high speed applications requiring a minimum footprint size with a
reliable, latching connection. The recommended connector has two rows of seventeen contacts each with a spacing of
0.8 mm. The connector provides isolation between the high-speed trace signals and the low-speed JTAG and control signals.
It also provides ample ground connections to ensure signal integrity.
If at all possible, the connector should be placed onto the target system with the even numbered pins nearest the edge of the
printed circuit board.
In addition, care should be taken in the layout of the high speed Aurora signals (TXn+, TXn-, CLK+, and CLK-) with a good
return path (usually ground).
The following picture is courtesy of Samtec U.S.A (http://www.samtec.com/search/NEXUS.aspx ).
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Trace Adapter overview
Figure 2. HS34 (ASP-137973-01) connector
The following table shows the recommended pin out for the Samtec connector.
Table 5. Generic MPC57xx high-speed serial trace connector
Position
MPC57xx
Signal
Direction
Pin
number
Pin
number
Direction1
MPC57xx
Signal
IEEE-5001-2012
GEN_IO signal
name
GND2
GND
1
TX0+
Out
1
2
Out3
VREF
2
TX0-
Out
3
4
In
TCK/TCKC
3
GND
5
6
In/Out
TMS/TMSC4
4
TX1+
Out
7
8
In
TDI
5
TX1-
Out
9
10
Out
TDO
6
GND
11
12
In
JCOMP
TRST
GEN_IO0
TX2+
Out
13
14
Out
EVTI15
8
TX2-
Out
15
16
In
EVTI(0)
9
GND
17
18
Out
EVTO(0)
10
TX3+
19
20
In/Out
RSTOUT6
GEN_IO3
In/Out
RESET7
RESET
7
11
TX3-
12
GND
13
TX4+
Out
Out
Out
Out
21
22
23
24
25
26
In
CLK+
27
28
In8
CLK-
29
30
GND
14
TX4-
15
GND
16
TX5+
Out
31
32
Out
RDY9
17
TX5-
Out
33
34
In/Out
WDT10
GND
GEN_IO5
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Trace Adapter overview
Table 5. Generic MPC57xx high-speed serial trace connector (continued)
Position
MPC57xx
Signal
Direction
Pin
number
Pin
number
Direction1
GND2
MPC57xx
Signal
IEEE-5001-2012
GEN_IO signal
name
GND2
1.
2.
3.
4.
5.
6.
7.
8.
Viewed from the MCU.
The connector locking mechanism provides additional ground connections on each end of the connector.
This is an output from the connector standpoint. It may or may not be from the MCU.
TCKC and TMSC are the IEEE 1149.7 signals on devices that support that interface.
Not available on all devices. No connect if the device does not support the signal.
PORST on the MPC57xxM and ext_POR on the MPC5744P.
ESR0 on the some devices
Per the IEEE-ISTO 5001-2012, CLK+ and CLK- can either be outputs from the MCU or inputs to the MCU. For this family
of devices, Freescale has defined this to be an input to the MCU. The tool must provide a LVDS clock at the desired
Aurora transmission frequency from the MCU.
9. This pin can be used for EVTO1 if RDY is not available.
10. WDT is an optional Watchdog Disable signal. It has no defined connection to the MCU. For systems that implement an
external hardware watchdog circuit, this signal allows an external tool to disable that watchdog for debug purposes.
2.5 Nexus Auxiliary port and Aurora trace signals
The following table lists all of the Nexus serial trace signals.
NOTE
The Aurora signals require a 100 Ω termination resistor in the tool. The termination
resistor should be located inside the tool near the receiver. In many cases, it may be
located internal to the tool receiver.
NOTE
The MPC57xx devices incorporate an internal termination resistor in the Nexus Aurora
Physical (NAP) block of the MCU for the LVDS clock (CLKP/CLKN).
Table 6. Nexus Auxiliary port and Aurora connector signals
Signal name
Full signal name
TXnP (+)
Positive polarity transmit signal
TXnN (–)
Negative polarity transmit signal
CLKP (+)
Positive polarity clock signal
CLKN (–)
Negative polarity clock signal
EVTI (EVTI0)
Nexus Event Input
Description
The Nexus Aurora port uses one or
more lanes of low voltage differential
signals to transmit Nexus trace
information. When multiple lanes are
used, the data is striped between the
different lanes. Zero to four lanes are
currently projected on future devices.
The connector supports up to six lanes.
The Nexus Aurora physical interface on
the MCU requires a differential clock
from the tool for formatting the Nexus
trace information. The clock frequency
should be the same as the transmit data
speed.
After reset, the EVTI2 pin is used to
initiate program and data trace
synchronization messages or generate a
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Emulation Device overview
Table 6. Nexus Auxiliary port and Aurora connector signals (continued)
Signal name
Full signal name
Description
breakpoint. If asserted during reset,
upon negation of RESET, the device will
enter debug mode and not begin code
execution.
EVTI11,
Nexus Event Input
Additional EVTI1 pin for additional
synchronization or break functionality.
EVTO (EVTO0)1
Nexus Event Output
EVTO is an output that provides timing
to a development tool for a single
watchpoint or breakpoint occurrence.
EVTI has multiple Nexus functions. In
addition, the Development Semaphore
Trigger module can also use the EVTO
output pin.
EVTO11,3
Nexus Event Output
EVTO1 is an additional event output
signal.
1. Most of the pins on the device that support the Event signals can be defined to be either inputs (EVTIn) or outputs
(EVTOn).
2. If no number is included, then 0 is assumed for both EVTI and EVTO.
3. Not all devices will support multiple EVTI and EVTO signals.
3 Emulation Device overview
The Emulation Device (ED) is a multi-chip device that includes additional features that are not available on the production
die. These extra features are implemented on a second die ("buddy" die). The features that are available with the buddy die
include the following:
•
•
•
•
•
•
•
Separate power system
1 MB of overlay/trace SRAM
Nexus high-speed (Aurora) Auxiliary trace port
Separate System Integration Unit Lite (SIUL)
Nexus Read/Write access client (NRWA)
Independent Internal Resistor/Capacitor Oscillator (IRC)
Control of JTAG pins of the device
The figure below shows the overall architecture of the PD and BD development resources.
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Emulation Device overview
Production Die (PD)
Debug Block Diagram
DMA Ch MUX
Zipwire
Ethernet
eTPU
Concentrator
Concentrator
Nexus XBAR Client 1
(NXMC)
Nexus XBAR Client 0
(NXMC)
In-Circuit Trace
(NICT)
Counter
Values
Trigger Sources
NC Ports
& Control
JTAG
Nexus
Client
CPU0
Nexus Client
(NZxC3)
Nexus Client
(NZxC3)
IRQ
Controller
JTAG
64 ch. eDMA
w/ E2E Ecc
JTAG
Trigger Actions
Nexus Aurora
Router
(NAR)
Sequence Processing
Unit
(SPU)
AHB Master
Nexus Parallel
IPS
AHB Slave
IPS
DTS
DTS Trigger
System Reset Status/Control
JTAG
IPS
Debug Reset & Control
JTAGM
Flash Array
DCI
Overlay RAM
Overlay RAM
JTAGC
JTAG to
PD Clients
AHB Master
Intra-Die Pads
1149.7
Flash BIU
w/Overlay
Function
SEL_1
M.JTAG
P.JTAG
Device
Pads
(LVDS or
CMOS)
I.JTAG
SEL_0
Intra-Die Pads
Intra-Die Pads
Copper Pillars or Solder Ball Interconnect
Intra-Die Pads
Intra-Die Pads
Intra-Die Pads
Nexus
Parallel
PD SYSTEM CLK
DCI
SEL_0 = 0 (fixed)
JTAG
SEL_1
IRC
Nexus RWA
Client
(NRW)
Nexus Aurora
Router
(NAR)
Nexus Parallel
JTAG
P.JTAG
JTAG to
BD Clients
Master
CLK
Device
Pads
(CMOS)
JTAGC
1149.7
NC Ports
& Control
JTAG
NC
System Reset Status/Control
Debug Reset & Control
AHB Master
JTAGtoIPS
BD_XBS_RAM
Nexus Aurora
Link
(NAL)
AIPS
Overlay or
Trace RAM
Overlay or
Trace RAM
Overlay or
Trace RAM
Overlay or
Trace RAM
BD_SIU
IPS
IPS
IPS
IPS
IPS
Nexus Aurora
Phy
(NAP)
IPS
IPS = Internal peripheral slave bus, connected to the PBridge.
Nexus Aurora Port
Output lanes plus LVDS clock in
Buddy Die (BD)
Block Diagram
Figure 3. MPC5746R Emulation and Production Device debug architecture
3.1 Emulation Device internal physical construction
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Emulation Device overview
Internally, the Emulation Device consists of two die that are packaged in a single package. The first die in the package is the
production die. This is the standard (same) die that is included in the production packaged device. The second die is a
"buddy" die that includes additional functionality. This ensures that the functionality is the same during development as it is
during production for the production features. The Emulation Device (for the MPC5746R) is packaged in a 292 Plastic overmolded Ball Grid Array (PBGA) package.
The figure below shows a cross-section of the construction of the emulation device. All balls are connected (through wire
bonds) to bonding pads on the production die. The second die is mounted "flip-chip" on top of the production die.
underfill
molding compound
die 2
Copper pillars
wire
die 1
die
attach
substrate
Figure 4. Emulation device physical construction cross-section
The two die are connected through copper pillars and the die are held in place with an under-fill. The figure below shows a
magnified view of the die with the copper pillar construction.
die 2 (buddy die)
die 1 (production die)
Figure 5. Die cross section
The following figure shows a larger view of the actual connections between the two die; a copper pillar on each die with
solder making the connection between the pillars.
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Emulation Device overview
copper
pillar 1
solder
copper
pillar2
Figure 6. Copper pillar cross-section
3.2 MPC5746R Buddy Die architecture
The Buddy Die (BD) for the MPC5746R includes additional resources that can be used to supplement the development
features that are available on the MPC5746R Production Device (PD). Functional block and descriptions of these blocks are:
• Debug and Calibration Interface (DCI) - The DCI includes the JTAG (IEEE 1149.1) controller and the IEEE 1149.7
interfaces and replaces the DCI/JTAG interface of the PD, but allows access to the PD JTAG interface by passing
control from the BD JTAG interface to the PD JTAG interface. This requires the BD to be powered in the Emulation
Device (ED) for debug operations of the Production Die (PD).
• Overlay/Trace SRAM - 11 MB of SRAM that can be split into four partitions allowing access by different masters and
can be split between use as calibration overlay SRAM (for mapping over the internal PD FLASH) or as trace memory
(holding trace information of the PD.
• Nexus Aurora Router (NAR) - The NAR receives trace information from the PD and allows it to either be sent to the
Nexus Aurora Link (and ultimately out of the Nexus physical trace interface) or to the trace memory contained on the
BD.
• Nexus Aurora Link (NAL) - The NAL takes the 30 Nexus Message Data Out parallel signals (MDO) and 2 Message
Start/End Outputs (MSEO) and splits the data into lanes and encodes it with an 8b10b format for transport over a multilane Aurora interface.
• Nexus Aurora Physical interface (NAP) - The NAP takes the parallel 8b10b data and serializes it for transmission out
of the MCU.
• Nexus Read/Write Access client (NRWA) - The NRWA client provides an interface between the JTAG port of the BD
to the BD resources (NAR and SRAM) to allow access from the JTAG port independent of the of PD.
• Crossbar (XBAR) slave interface - The XBAR allows parallel access between PD bus masters or access by the BD
resources.
• Internal Resistor/Capacitor Oscillator (IRC) - The IRC provides a non-precise clock reference to the BD modules when
the PD is not powered. It has a nominal frequency of 64 MHz, however, there is no trim capability and therefore, the
accuracy of the frequency is ±30%.
The figure below shows the block diagram of the BD. This is a subset of the complete Emulation Device development
resources (shown in Emulation Device overview).
1.
The BD used on the MPC5777M includes 2 MB of SRAM.
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Emulation Device overview
Intra-Die Pads
Intra-Die Pads
Nexus
Parallel
JTAG
NC Ports
& Control
IRC
DCI
SEL_0 = 0 (fixed)
SEL_1
NC
P.JTAG
Nexus
Client
(Nexus RWA)
Nexus Aurora
Router
(NAR)
Master
CLK
JTAG to
BD Clients
JTAGC
Device
Pads
(CMOS)
1149.7
JTAG
Intra-Die Pads
PD
SYSTEM
CLK
Nexus Parallel
System Reset Status/Control
Debug Reset & Control
AHB Master
JTAG
BD_XBS_RAM
Nexus Aurora
Link
(NAL)
AIPS
Overlay or
Trace RAM
Overlay or
Trace RAM
IPS
IPS
Overlay or
Trace RAM
Overlay or
Trace RAM
BD_SIU
Nexus Aurora
Phy
IPS
IPS
IPS
IPS
Buddy Die (BD)
Block Diagram
Nexus Aurora Port
Output lanes plus LVDS clock in
Figure 7. MPC5746R Buddy Die block diagram
There are two other important views of the overall emulation device debug architecture, The JTAG view of the system and
the Nexus trace view of the system.
The MPC57xx family of devices implement a JTAG "TAP sharing" scheme to allow access to multiple JTAG clients inside
of the microcontroller (MCU). The JTAG view of the debug architecture is shown in the following figure. It shows the
hierarchy and access commands of the JTAG clients available in the ED and the split between the PD and the BD. The JTAG
Auxiliary Access Command (AUX_ACCESS_PD) is 0x3E. For tool compatibility, the command to switch from the BD to
the Production Device die is ignored by the JTAG Controller (JTAGC) in the Production Device die. This allows the tool to
implement all commands that access features of the Production Device die in the same manner, regardless of whether the BD
is present or not.
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Emulation Device overview
Tool
Buddy Die
DCI
JTAGC
0x23
0x22
0x20
NRWA
NAR
NAL
0x3E
Production Die
DCI
JTAGC
NXMC_0
64-ch
DMA
IPC
Ethernet
NXMC_1
0x29 0x28 0x3C
0x34
0x35
ICT
0x21
0x30
eTPU
NZ4C3
NAR
0x3A
SPU
0x26
JDC
JTAG ACCESS command shown for each client.
Figure 8. JTAG client hierarchy
The flow of Nexus trace data from the Nexus clients on the PD is shown in the following figure. Trace data is accumulated in
the PD NAR before being sent to either the PD on-chip Trace Memory or to the BD NAR. The BD NAR can then filter trace
data to be transmitted either to the internal BD trace memory or to the physical Nexus Aurora interface (NAL to NAP).
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BD Nexus Read/Write Access client
NXMC_1
64-ch
DMA
IPC
Ethernet
Production Die
SPU
NXMC_0
ICT
NZ4C3
Core 0
NZ4C3
Core 1
eTPU
PD_NAR
Overlay/Trace SRAM
(16K)
BD_NAR
NAL
Overlay/Trace SRAM
(1M)
NAP
Buddy Die
Tool
Figure 9. Nexus trace data flow
Both the PD on-chip trace memory and the BD memory can also be used for calibration (overlay SRAM over portions of the
internal flash). However, the overlay/trace memory on the BD can be spilt to allocate part of the BD SRAM for the overlay
function and part for the trace function. There are four (4) partitions in the BD SRAM. One (1), two (2), three (3), or four (4)
partitions can be allocated to either use. The trace memory does need to be continuous since the trace function uses a base
address and size to implement the trace memory. Trace can be configured to use the SARM either as a one-shot use (once the
trace memory is full, trace stops) or as a circular buffer that continues until stopped.
4 BD Nexus Read/Write Access client
The Emulation Device includes a Nexus Read/Write Access (RWA) client for accessing the memory systems in the buddy
die (BD). This Nexus client cannot access the memory space of the production device. The buddy die memory can also be
accessed either via the production device die though the Nexus RWA client of one of the two cores or via the cores
themselves.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
14
Freescale Semiconductor, Inc.
Attaching the MPC5746R Trace Adapter to an EVB
Table 7. Nexus memory access methods
Memory region
Starting address
Access via core 0 or core 11
Accessible through the BD
NRWA client
Extended Overlay SRAM
0x0C00_0000
Yes
Yes
Buddy Device registers
(BD_SIUL2)
0x0C80_0000
Yes
Yes
Internal (PD) Overlay SRAM
0x0D00_0000
No
Yes
1. Reads of the BD memory space must be enabled by setting the Buddy Device Read Mode (BDRM) bit in the Platform
Flash Configuration Register 3 (PFLASH_PCFR3) - 0xFC03_008 = 0x0010_0000.
5 Attaching the MPC5746R Trace Adapter to an EVB
The MPC5746R Trace Adapter (TA) is designed to be used primarily with either a Freescale MPC5746R Evaluation board or
to a customer target system. The MPC5746R 252 BGA daughter card is recommended (which attaches to a MPC57xxEVB
motherboard). The TA provides:
• A 14-pin Automotive Power Architecture JTAG connector
• A 34-pin Nexus Trace/debug connector
• A 3.3 V power supply for the JTAG and Nexus pins on the Buddy Die (BD) in the Emulation Device (ED)
• A 1.25 V power supply for the internal logic on the BD in the ED
• A 2-pin connector to provide power to the BD regulators.
NOTE
To use a 144 or 176 QFP daughter card, the socket or microcontroller (MCU)2 would
have to be unsoldered from the board and replaced with the appropriate BGA to QFP
adapter.
As shipped from Freescale, the 252 PBGA daughter card ships with a 252 PBGA socket mounted on the board. This socket
must be removed to allow connection to the TA. To install the TA, perform the following steps.
1. On the bottom of the daughter card, there are four (4) screws that must be removed.
2. Once the screws are removed, the socket can be removed.
3. The TA can then be inserted into the receiver that is soldered to the daughter card. The receiver includes alignment
holes to assist in aligning the TA. The TA includes alignment pins that are longer than the pins used by the device.
4. The daughter card with the TA can then be plugged into the MPC57xxEVB to provide power to the Production Die
(PD) and provide physical interfaces for some of the Input/Output systems of the MCU. Access to the MCU pins is also
available on this motherboard.
5. The TA ships with a short power cable for the nominal 12 V input to the TA. The connector plugs into J4 of the TA.
For the EVB, the other ends of the wires can be stripped and connected to the screw terminals on the MPC57xxEVB
(B33) or connected to an appropriate supply in the customer target system.
NOTE
The screw terminals (B33) are always powered when the power is connected to the
EVB supply (P26).
This allows the On/Off switch (SW5) to control power supplied to the PD, allowing the BD to be powered separately.
The figure below shows a photograph of a MPC5746R TA connected to the MPC5746R daughter card (MPC5746R-252DC)
and the MPC57xx motherboard.
2.
This depends on whether the board uses a socket to hold the MCU or if the MCU is
directly soldered to the daughter card.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
15
Using the MPC5746R Trace Adapter with a customer target system
Figure 10. MPC5746R TA mounted on EVB
NOTE
By default, when the TA is connected to the daughter card, the JTAG connector on the
daughter card is not connected to the MCU. Only the JTAG connector or the Nexus
connector on the TA can be used for debugging the system. The TA does includes an
option to connect these signals to the target system, but by default, they are left open.
6 Using the MPC5746R Trace Adapter with a customer target
system
The MPC5746R Trace Adapters (TA) are designed to be used in a customer target system for development purposes. This
allows the use of trace and the use of the overlay/trace memory in the target system. There are some precautions and actions
that must be taken into account when using the TA.
1. Since the TA is mounted via pins, a receiver must be soldered into the target system. For the MPC5746R in the 252
PBGA package, this consists of a simple receiver. The receiver is basically a socket with alignment pins that is soldered
to the target board. The TA then plugs into the socket. For the 144 or 174 LQFP devices, an adapter is required to
convert the pin-grid TA to the surface mount footprint of the target system. For the MPC5746R, a single TA is used for
both the 144 and the 176 LQFP devices. The target adapter for the LQFP packages uses a 208 pin-grid TA that plugs in
to either a 208 to 176 target adapter or into a 208 to 144 target adapter. Part numbers for all of the TAs, receivers, and
target adapters are shown in MPC5746R Trace Adapter orderable parts .
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
16
Freescale Semiconductor, Inc.
MPC5746R Trace Adapter orderable parts
2. A keep-out area is required for the TA board to insure that components on the TA do not interfere with components in
the target system.
3. Power (nominal 12 V) must be supplied to the TA through the supplied power connector. The system power supply
must be capable of handing the additional current requirements of the TA and the Emulation Device. See the
MPC574xR (device) Data Sheet for the maximum current required for these supplies.
4. Depending on the target system a connection mechanism may be required to allow the debug connectors to be
accessible. In other words, if the target system is in a sealed box, a hole may be required to access the JTAG or Nexus
connectors on the TA.
7 MPC5746R Trace Adapter orderable parts
The following table shows the orderable components for the MPC5746R Trace Adapters (TA), including the TAs and the
receivers or TAs required.
Table 8. Orderable parts
Package footprint
252PBGA
176LQFP2
144LQFP3
Part Number
Description
LFDBGK46RT4S2A
292 PIN 0.8MM BGA to 252 0.8MM PGA Adapter with Aurora interface for
MPC574xR
LFBGARBS2AO
SURFACE MOUNT PGA SOCKET FOR 252 Pin 0.8MM VertiCal and
Microcontrollers with pins1
LFDBGK46RT4QA
292 PIN 0.8MM BGA to 208 1.0MM PGA Adapter with Aurora interface for
MPC574xR.
LFTAK46MQM2A
208 pin 1.0mm PGA to 176 pin 0.5mm QFP target Adapter board for
MPC574xR
LFDBGK46RT4QA
292 PIN 0.8MM BGA to 208 1.0MM PGA Adapter with Aurora interface for
MPC574xR.
LFTAK46RQLA
208 pin 1.0mm PGA to 144 pin 0.5mm QFP target Adapter board for
MPC574xR
1. Also known as a receiver for mounting into a target system
2. For the 176QFP, the TA converts the 292 MAPBGA to a 208 BGA footprint. A separate adapter is required to convert the
208 footprint to the 176 PQFP footprint.
3. For the 144 QFP, the TA converts the 292 MAPBGA to a 208 BGA footprint. A separate adapter is required to convert the
208 footprint to the 144 PQFP footprint.
Appendix A MPC5746R Trace Adapter schematics and drawings
This appendix contains the schematics, bill of materials, and drawings for the 252-pin MPC5746R Trace Adapter (TA). The
208-pin TAs are similar, but are not included. However, since the 208-pin TA has a different outline and component
placement, a drawing of the 208-pin TA is also included. In addition, a drawing of the 208 BGA to LQFP footprint adapter
and a drawing of the 208-pin TA mounted on the 208 BGA to 176 LQFP adapter to show the stacked dimensions.
The latest version of the schematics and dimension drawings can be downloaded from freescale.com.
A complete list of the schematics and dimension drawings that are included in this application note and which are not
included is shown in the following table.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
17
252 PBGA Trace Adapter
Table A-1. MPC5746R TA schematics and other drawings
Type
Drawing number
Revision
Description
Included in
Application Note
Package adapter
LFTAK46RQLA
—
208 PGA to 144 QFP target adapter
dimension drawings
Yes
Package adapter
LFTAK46MQM2A
—
208 PGA to 176 QFP target adapter
dimension drawings
Yes
Receiver
LFBGARBS2AO
0
252 BGA receiver
Yes
Schematics
LFDBGK46RT4QA
A
MPC5746RR 208 BGA Trace Adapter No
schematics
Schematics
LFDBGK46RT4S2A
A
MPC5746RR 252 BGA Trace Adapter Yes
schematics
Schematics
LFTAK46MQM2A
O
MPC5746R 208 to 176 Trace Adapter Yes
schematic
Schematics
LFTAK46RQLA
—
MPC5746R 208 to 144 adapter
schematic
No
Stack dimensions
DBGK46RT4S2A_BRBS2AO
—
MPC5746R 252 BGA with 252
receiver stack dimension drawing
Yes
Stack dimensions
DBGK46RTQA RevA- —
TAK46RQLA
MPC5746R 208 PGA with 144
adapter stack dimension drawing
Yes
Stack dimensions
DBGK46RTQA RevA- —
TAK46MQM2A
MPC5746R 208 PGA with 176
adapter stack dimension drawing
Yes
TA Board Dimensions LFDBGK46RT4S2ALAYOUT
B
MPC5746R 252 BGA Trace Adapter
dimension drawing
Yes
TA Board Dimensions LFDBGK46RT4QA
A
MPC5746R 208 BGA Trace Adapter
dimension drawing
Yes
A.1 252 PBGA Trace Adapter
This section contains the schematics, Bill of Materials, 252 PBGA layout drawing, and the stacked side drawing of the 252
PBGA Trace Adapter (TA) with the receivers mounted.
A.1.1 Schematics 252 BGA
The figures below show the schematics of the MPC5746R 252 BGA Trace Adapter (TA).
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
18
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
A
B
C
D
1
2
3
4
4
5
4
NOTES:
1. Unless Otherwise Specified:
All resistors are in ohms, most are 1%, 1/10 Watt.
Otherwise are 5%, 1/8 Watt.
All capacitors are in uF, some are 10% or 20%
All voltages are DC
All polarized capacitors are tantalum
2. Interrupted lines coded with the same letter or letter
combinations are electrically connected.
3. Device type number is for reference only. The number
varies with the manufacturer.
4. Special signal usage:
_B Denotes - Active-Low Signal
<> or [] Denotes - Vectored Signals
5. Interpret diagram in accordance with American National
Standards Institute specifications, current revision, with
the exception of logic block symbology.
TI TLE & REVI SI ON STATUS
292, JTAG and AURORA CONN
252 CONNECTI VI TY
POWER SUPPLY
5
Tabl e of Cont ent s
3
Drawn by:
CDC Technologies, Inc.
Designer:
CDC Technologies, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
3
xxxxx
A
Rel eas e
Or i gi nal
O
Revi si ons
Des c r i p t i on
Rev
1
xxxxx
xxxxx
Da t e
2
LFDBGK46RT4S2A
1
Date:
12-18-2014
Ref:
CDC2375-A SIZE
DWG. NO.
GEDTTL:
Date:
B
GEDABV:
LFDBGK46RT4S2A
<Date>
LAST MODIFIED=
Date:
SHEET 1 o f
Thursday, December 18, 2014
<Date>
28125 Cabot Drive, Suite 100
Novi, MI 48377
TITLE:
Detroit Automotive Technology Center
2
4
A
REV:
A
B
C
D
252 PBGA Trace Adapter
Figure A-1. 292 to 252 Trace Adapter (page 1)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
19
A
B
C
D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PB0
PB1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
VSS
TX3P
TX3N
TX2P
TX2N
TX1P
TX1N
TX0P
TX0N
292BGA_RAINIER
PZ0
PZ1
PZ2
PZ3
PZ4
PZ5
PZ6
PZ7
PZ8
PZ9
PZ10
PZ11
PZ12
PZ13
PZ14
PZ15
EXTAL
XTAL
JCOMP
PORST
RESET
TCK
TMS
TESTMODE
CLKN
CLKP
LVDS_TEST_N
LVDS_TEST_P
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
J1F
H20
H19
H17
H16
J20
J19
J17
J16
K17
K16
L17
L16
M17
M16
M20
M19
F1
G1
F2
G4
F4
E2
E1
M2
K8
K7
L8
L7
G10
H10
G12
H12
K14
K13
M13
M14
292BGA_RAINIER
J1A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
TDO
TDI
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
37
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
CLKP
J3
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
5
SH3
38
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
EVTO1
CLKIN_P
CLKIN_N
TCK
TMS
TDI
TDO
JCOMP
EVTI1
EVTI0
EVTO0
PORST
ESR0
VDD_HV_IO_BD
ASP-137973-01 VSS
VSS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
AURORA
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
PZ0 SH3
PZ1 SH3
PZ2 SH3
PZ3 SH3
PZ4 SH3
PZ5 SH3
PZ6 SH3
PZ7 SH3
PZ8 SH3
PZ9 SH3
PZ10 SH3
PZ11 SH3
PZ12 SH3
PZ13 SH3
PZ14 SH3
PZ15 SH3
EXTAL
XTAL
JCOMP
JCOMP SH3
PORST
PORST
SH3
ESR0
ESR0 SH3
TCK
TCK SH3
TMS
TMS SH3
TESTMODE
CLKN
PZ0
PZ1
PZ2
PZ3
PZ4
PZ5
PZ6
PZ7
PZ8
PZ9
PZ10
PZ11
PZ12
PZ13
PZ14
PZ15
A3
B3
A4
D5
E5
B4
B5
D6
D7
A6
A7
B7
B8
A8
D1
E4
Y9
W9
U9
T9
W10
U10
T10
Y11
U11
T11
Y12
W12
U12
T12
C32
10pF
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
A1
A2
A20
B12
B19
B2
B6
D2
D4
E16
E19
E6
F5
G2
G9
H11
H14
J10
J11
J13
J7
K10
K11
K12
K9
L10
L11
L12
L13
L14
Y3
W3
Y4
W4
U5
Y5
W5
T6
U6
Y7
W7
U7
T7
Y8
W8
U8
T8
G20
G19
G17
G16
F19
F17
E20
F16
D20
D19
E17
C20
C19
B20
10pF
C33
CLKN
CLKP
292BGA_RAINIER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J1I
292BGA_RAINIER
J1B
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
4
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
EVTO0
EVTI0
ESR0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
4.7K
R1
TDI
TDO
TCK
1
3
5
7
9
11
13
4.7K
R2
J5
HEADER 7X2
JTAG
VDD_HV_IO_BD
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
2
4
6
8
10
12
14
VSS
292BGA_RAINIER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSHV_ADR_SAR
VSSHV_ADR_SAR
VSSHV_ADR_SD
VSSHV_ADV_SAR
VSSHV_ADV_SAR
VSSHV_ADV_SD
J1J
292BGA_RAINIER
J1C
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
JCOMP
PORST
TMS
L2
L9
M10
M11
M7
N10
N11
N12
N9
P11
P13
P9
R2
T15
T5
W11
W2
W6
Y1
Y2
W18
Y19
L19
W19
Y20
K19
A18
A17
B17
D17
B16
A16
D16
E15
A15
B15
B14
A14
D15
D14
E13
A13
B13
D13
E14
A12
D12
E12
B11
E11
D11
A10
B10
E10
D10
A9
VSS
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
3
SH3
SH3
PI0
PI1
PI2
PI3
PI4
PI5
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PK0
PK1
PK2
PK4
PK5
PK7
PK8
PK9
PK10
PK11
PK12
PK13
PK14
XTAL_TGT
XTAL
EXTAL_TGT
EXTAL
292BGA_RAINIER
2
2
SH3
SH3
SH3
SH3
SH3
SH3
PJ0
EVTO1
PJ2
EVTI1
EVTI0
PJ5
PJ6
EVTO0
PJ8 SH3
PJ9 SH3
PJ10 SH3
PJ11 SH3
PJ12 SH3
PJ13 SH3
PJ14 SH3
PJ15 SH3
PK0 SH3
PK1 SH3
PK2 SH3
PK4 SH3
PK5 SH3
PK7 SH3
PK8 SH3
PK9 SH3
PK10 SH3
PK11 SH3
PK12 SH3
PK13 SH3
PK14 SH3
PI0
PI1
PI2
PI3
PI4
PI5
Y18
L20
V19
W20
K20
N1
G8
Y10
C1
A11
A19
B18
F20
K1
T1
Y6
A5
M1
1
2
VDD_HV_PMC
2
R5
1M
C48
10pF
C49
10pF
VSS
PL0
PL1
PW0
PW1
PW2
PW3
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
PX8
PX9
PX10
PX11
PX12
PX13
PX14
PX15
PY0
PY1
PY2
PY3
PY4
PY5
PY6
PY7
PY8
PY9
PY10
PY11
PY12
PY13
PY14
PY15
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV
VDD_LV_BD
VDD_LV_BD
VDDSTBY
VRC_CTRL
J1H
Drawn by:
CDC Tech, Inc.
Designer:
CDC Tech, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
VSS
R5
U4
Y13
W13
U13
T13
U19
T17
U17
Y17
W17
T16
Y16
W16
T14
Y15
W15
U15
Y14
W14
U14
U16
N20
N19
N17
N16
P20
P19
P17
P16
R20
R19
R16
T20
T19
R17
U20
V20
1
SH3
1
Date: Thursday, December 18, 2014
Sheet 2
LFDBGK46RT4S2A
of
4
Size
292, JTAG and Aurora Connectivity
LFDBGK46RT4S2A
28125 Cabot Drive, Suite 100
Novi, MI 48377
Detroit Automotive Technology Center
VDDSTBY
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
VRC_CTRL
PW0
PW1
PW2
PW3
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
PX8
PX9
PX10
PX11
PX12
PX13
PX14
PX15
PY0
PY1
PY2
PY3
PY4
PY5
PY6
PY7
PY8
PY9
PY10
PY11
PY12
PY13
PY14
PY15
Document Number:
Page Title:
Drawing Title:
VSS
VSS
CDC2375-A
Date:
<Date>
Date:
<Date>
Date:
12-18-2014
R ef:
C42
.1uF
VDD_LV_BD
PW0
PW1
PW2
PW3
PX0
PX1
PX2
PX3
PX4
PX5
PX6
PX7
PX8
PX9
PX10
PX11
PX12
PX13
PX14
PX15
P Y0
P Y1
P Y2
P Y3
P Y4
P Y5
P Y6
P Y7
P Y8
P Y9
P Y10
P Y11
P Y12
P Y13
P Y14
P Y15
C35
.1uF
VDD_LV
B1
C2
G11
H7
J14
J8
M8
N14
N7
P10
P12
P8
V2
W1
G13
H9
J1
L1
292BGA_RAINIER
J1E
292BGA_RAINIER
Y1
NX5032GA-20.000M
VDD_HV_IO_JTAG
VDD_HV_IO_FEC
VDD_HV_IO_BD
VDD_HV_FLA
VDD_HV_IO_MSC
R4
2
VDD_HV_ADV_SD
VDD_HV_IO_MAIN
J10
J9
SH3
SH3
SH3
SH3
SH3
SH3
SH3
SH3
VDD_HV_ADV_SAR
VDD_HV_ADR_SD
EVTO0
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PK0
PK1
PK2
PK4
PK5
PK7
PK8
PK9
PK10
PK11
PK12
PK13
PK14
EVTI1
EVTI0
PJ5
PI0
PI1
PI2
PI3
PI4
PI5
PJ0
EVTO1
VDD_HV_ADR_SAR
B9
D9
E9
D8
E8
E7
H1
G5
H2
H4
H5
J2
J4
J5
K2
K4
K5
L4
L5
M4
M5
N2
N4
N5
P1
P2
P4
P5
R1
R4
T2
T4
U1
U2
V1
VDD_HV_ADR_SAR
VDD_HV_ADR_SD
VDD_HV_ADV_SAR
VDD_HV_ADV_SAR
VDD_HV_ADV_SD
VDD_HV_FLA
VDD_HV_IO_BD
VDD_HV_IO_FEC
VDD_HV_IO_JTAG
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MAIN
VDD_HV_IO_MSC
VDD_HV_PMC
J1G
292BGA_RAINIER
J1D
1
4
1
3
1
3
1
2
20
2
5
C
A
R ev
A
B
C
D
252 PBGA Trace Adapter
Figure A-2. 292 to 252 Trace Adapter (page 2)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
A
B
C
D
PK14
VDD_LV
VSS
PD4
PD7
PD8
PD11
PD15
PC2
PC5
PC8
PC12
PW2
PX14
PX11
PX15
PX5
PX2
VDD_HV_ADV_SAR
PY15
J2J
252BGA_Rainier
VDDSTBY
PJ5
PJ6
PJ7
VDD_LV
VDD_LV
VDD_LV
VDD_LV
PZ7
PZ6
PZ5
PZ4
VDD_HV_IO_MAIN
PJ8
PJ9
PJ10
VSS
VSS
VSS
VSS
PZ9
PZ8
VSS_HV_ADV_SD
VDD_HV_ADV_SD
J2F
252BGA_Rainier
VSS
VSS
PA0
PA2
VDD_HV_IO_MSC
PA9
PA10
PA13
PH15
PH11
VDD_HV_IO_MAIN
PH5
PH1
PG13
PG10
PG6
PG2
PG1
VDD_HV_IO_MAIN
VSS
J2A
252BGA_Rainier
5
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
PZ13
PZ12
PZ15
PZ14
SH2
SH2
SH2
SH2
TESTMODE
PJ13 SH2
PJ14 SH2
PZ11
PZ10
PJ11
PJ12
VRC_CTRL
VDD_HV_ADR_SD
VDD_HV_PMC
VDD_LV
PF13
PH2 SH2
PG12 SH2
PG11 SH2
PG5 SH2
PG3 SH2
VSS
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
PK14
PD4
PD7
PD8
PD11
PD15
PC2
PC5
PC8
PC12
PW2
PX14
PX11
PX15
PX5
PX2
PY15
4
VDD_LV
VSS
PD1
PD3
PD6
VSS
PD10
PD14
PC1
PC4
VSS
PC11
PW1
PX13
PX10
PX7
PX4
VSS_HV_ADR_SAR
VSS_HV_ADV_SAR
VDD_HV_ADV_SAR
VSS
SH2
SH2
SH2
PC11
PW1
PX13
PX10
PX7
PX4
SH2
SH2
SH2
SH2
SH2
SH2
PD10 SH2
PD14 SH2
PC1 SH2
PC4 SH2
PD1
PD3
PD6
VDD_LV
VDD_HV_ADV_SAR
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
L1
L2
L3
L4
L9
L10
L11
L12
L17
L18
L19
L20
M1
M2
M3
M4
M9
M10
M11
M12
M17
M18
M19
M20
VSS
SH2
SH2
SH2
PA11 SH2
PA12 SH2
PI0 SH2
PH12 SH2
PH8 SH2
PA1
PA3
PA6
VDD_LV
VDD_HV_ADV_SAR
J2K
252BGA_Rainier
VRC_CTRL
VSS
PJ11
PJ12
VSS
VSS
VSS
VSS
PZ11
PZ10
VSS_HV_ADR_SD
VDD_HV_ADR_SD
VDD_HV_PMC
TESTMODE
PJ13
PJ14
VDD_LV
VDD_LV
VDD_LV
VDD_LV
PZ13
PZ12
PZ15
PZ14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
VDD_LV
VDD_HV_IO_MAIN
VSS
SH2
SH2
SH2
J2G
252BGA_Rainier
VDD_LV
VSS
PA1
PA3
PA6
VSS
PA11
PA12
PI0
PH12
PH8
VSS
PH2
PG12
PG11
PG5
PG3
VDD_HV_IO_MAIN
VSS
PF13
J2B
252BGA_Rainier
4
VSS
PZ9
PZ8
PJ8 SH2
PJ9 SH2
PJ10 SH2
PZ7
PZ6
PZ5
PZ4
VDDSTBY
PJ5 SH2
PJ6 SH2
VDD_HV_ADV_SD
VDD_LV
VDD_HV_IO_MAIN
PH5
PH1
PG13
PG10
PG6
PG2
PG1
PA9 SH2
PA10 SH2
PA13 SH2
PH15 SH2
PH11 SH2
PA0
PA2
VDD_HV_IO_MSC
VDD_HV_IO_MAIN
VSS
J1
J2
J3
J4
J9
J10
J11
J12
J17
J18
J19
J20
K1
K2
K3
K4
K9
K10
K11
K12
K17
K18
K19
K20
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
5
SH2
SH2
N1
N2
N3
N4
N17
N18
N19
N20
P1
P2
P3
P4
P17
P18
P19
P20
R1
R2
R3
R18
R19
R20
3
1
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
VDD_HV_IO_MAIN
PK10
PK11
PY13
PY12
PY11
PK12
PK13
VDD_LV
PD12
PE0
PC3
PC6
PC9
PC13
PW3
PX8
PX1
PX0
PY14
J2I
252BGA_Rainier
VSS
SH2
SH2
SH2
PC7
PC10
PW0
PX12
PX9
PX6
PX3
SH2
SH2
SH2
SH2
SH2
SH2
SH2
PD9 SH2
PD13 SH2
PC0 SH2
PD0
PD2
PD5
PF6
SH2
PI5 SH2
PI4 SH2
PI2 SH2
PH14 SH2
PH10 SH2
PH7 SH2
PH4 SH2
PH0 SH2
PF10 SH2
PF9 SH2
PF8 SH2
TMS_TGT
TCK_TGT
TDI_TGT
PF7 SH2
TDO_TGT
VDD_LV
VSS
2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
SH2
PD12
PE0
PC3
PC6
PC9
PC13
PW3
PX8
PX1
PX0
PY14
2
ESR0
Drawing Title:
SH2
SH2
SH2
1
1
1
1
1
1
1
JMP7
JMP6
JMP5
JMP4
JMP3
JMP2
JMP1
2
2
2
2
2
2
2
F1
F2
F3
F18
F19
F20
G1
G2
G3
G4
G17
G18
G19
G20
H1
H2
H3
H4
H17
H18
H19
H20
VSS
SH2
SH2
SH2
SH2
PZ3
PZ2
PZ1
PZ0
TMS_TGT
TDO_TGT
TDI_TGT
TCK_TGT
PORST_TGT
JCOMP_TGT
ESR0_TGT
SH2
SH2
SH2
SH2
SH2
SH2
PF3
PF2
PF1
PF0
PJ0
PJ2
PORST_TGT
XTAL_TGT
SH2
LFDBGK46RT4S2A
28125 Cabot Drive, Suite 100
Novi, MI 48377
1
of
4
Size
B
A
Rev
EXTAL_TGT SH2
JCOMP_TGT
ESR0_TGT
PF5 SH2
PF4 SH2
VDD_HV_IO_MAIN
Detroit Automotive Technology Center
TMS
TDO
TDI
TCK
PORST
JCOMP
SH2
SH2
SH2
SH2
EXTAL
JCOMP
RESET
PF5
PF4
VDD_HV_IO_MAIN
XTAL
VSS
PORST
PJ1
PF3
PF2
PF1
PF0
PJ0
PJ2
PJ3
PJ4
PZ3
PZ2
PZ1
PZ0
J2E
252BGA_Rainier
1
Page Title:
CDC2375-A
252 Connectivity
Date:
Document Number:
<Date>
LFDBGK46RT4S2A
Date:
<Date>
Date: Thursday, December 18, 2014
Sheet 3
Date:
12-18-2014
Re f:
SH2
SH2
SH2
SH2
SH2
SH2
SH2
PK10
PK11
PY13
PY12
PY11
PK12
PK13
Drawn by:
CDC Tech, Inc.
Designer:
CDC Tech, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
T1
T2
T3
T18
T19
T20
U1
U2
U3
U7
U8
U9
U10
U11
U12
U13
U14
U18
U19
U20
VDD_HV_IO_MAIN
VDD_LV
J2D
252BGA_Rainier
PB0 D1
VSS D2
VDD_LV D3
PI5 D7
PI4 D8
PI2 D9
PH14 D10
PH10 D11
PH7 D12
PH4 D13
PH0 D14
PF10 D18
PF9 D19
PF8 D20
TMS E1
TCK E2
PB1 E3
PF7 E18
VSS E19
PF6 E20
VDD_HV_IO_MAIN
VDD_HV_IO_FEC
VDD_HV_ADR_SAR
PK9 SH2
PY10 SH2
PY9 SH2
PY8 SH2
PJ15
PK0
PK1
PY3
PY2
PY1
PY0
PK2
PK4
PK5
PK7
PY7
PY6
PY5
PY4
PK8
2
VDD_HV_FLA
JMP9
VSS
PA4 SH2
PA5 SH2
PA7 SH2
PA8 SH2
PI3 SH2
PI1 SH2
PH13 SH2
PH9 SH2
PH6 SH2
PH3 SH2
PG15 SH2
PG14 SH2
PG9 SH2
PG7 SH2
PG4 SH2
PF12 SH2
PF11 SH2
VDD_HV_IO_JTAG
VDD_LV
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
VSS
VSS
VSS
PD0
PD2
PD5
VDD_HV_IO_MAIN
PD9
PD13
PC0
VDD_HV_IO_FEC
PC7
PC10
PW0
PX12
PX9
PX6
PX3
VDD_HV_ADR_SAR
VSS_HV_ADR_SAR
VSS_HV_ADV_SAR
J2L
252BGA_Rainier
VDD_HV_FLA
PJ15
PK0
PK1
PY3
PY2
PY1
PY0
PK2
PK4
PK5
PK7
PY7
PY6
PY5
PY4
PK8
VSS
PK9
PY10
PY9
PY8
J2H
252BGA_Rainier
VDD_HV_IO_JTAG
VDD_LV
VSS
PA4
PA5
PA7
PA8
PI3
PI1
PH13
PH9
PH6
PH3
PG15
PG14
PG9
PG7
PG4
PF12
PF11
J2C
252BGA_Rainier
3
A
B
C
D
252 PBGA Trace Adapter
Figure A-3. 292 to 252 Trace Adapter (page 3)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
21
A
B
C
S2B-PH-SM4-TB
1
2
5
VSS
A
K
0.68uH
L1
C39
.1uF
D1
MBRS140TRPBF
40V
VSS
C18
.1uF
VDD_HV_FLA
C40
.1uF
C38
47uF
35V
Vin
VSS
C17
.1uF
VDD_HV_IO_FEC
VSS
C11
.1uF
VDD_HV_ADR_SAR
+
7
VSS
4
VSS
C16
.1uF
VDD_HV_IO_JTAG
VSS
C12
.1uF
VDD_HV_ADR_SD
3
2
1
8
VSS
C45
.1uF
VDD_HV_IO_MSC
VSS
C14
.1uF
1A
C41
100uF
10V
L2
220uH
+
VSS
C46
.1uF
VDD_HV_PMC
VSS
C13
.1uF
3
3
D3
GRN
VDD_HV_IO_BD
VDD_HV_ADV_SD
D2
10BQ060PBF
60V
NC3
NC2
NC1
OUTPUT
VDD_HV_ADV_SAR
GND
6
J4
U2
LM2594M-3.3/NOPB
ON/OFF
5
D
P
N
4
FEEDBACK
4
K
A
P
N
1
2
A
K
R3
470
1%
C37
.1uF
VSS
C26
1.5uF
3
1
EN
IN
VSS
C1
.1uF
VSS
C2
.1uF
C24
.1uF
VSS
5
C3
.1uF
.1uF
.1uF
.1uF
C22
C4
.1uF
2
.1uF
C44
C5
.1uF
Date:
12-18-2014
Re f:
CDC2375-A
Date:
<Date>
Date:
<Date>
C15
.1uF
VSS
Drawn by:
CDC Tech, Inc.
Designer:
CDC Tech, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
C20
C19
VSS
VSS
C36
.1uF
VDD_LV_BD
VDD_HV_IO_BD
OUT
VDD_HV_IO_MAIN
C25
4.7uF
SMT_0805
VDD_HV_IO_BD
VDD_LV
VSS
C34
.1uF
2
U1
LD39015M125R
GND
22
2
5
C8
.1uF
VSS
C28
4.7uF
SMT_0805
C9
.1uF
C27
.1uF
VDD_LV_BD
C30
.1uF
C10
.1uF
Date: Thursday, December 18, 2014
1
Sheet 4
LFDBGK46RT4S2A
Power Supply
LFDBGK46RT4S2A
28125 Cabot Drive, Suite 100
Novi, MI 48377
of
4
Size
Detroit Automotive Technology Center
.1uF
C23
C7
.1uF
Document Number:
Page Title:
Drawing Title:
.1uF
C21
C6
.1uF
C29
1.5uF
VSS
C43
.1uF
VDD_LV_BD
1
B
A
Rev
A
B
C
D
252 PBGA Trace Adapter
Figure A-4. 292 to 252 Trace Adapter (page 4)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
252 PBGA Trace Adapter
A.1.2 Trace Adapter bill of materials 252 BGA
Below is information about the components used on the MPC5746R 252 BGA Trace Adapter (TA).
Ref Number
Part Type
Value
Vendor/Source
Part Number
C32,C33,C48,C49
Capacitor, Ceramic 10pF 16V 10%
X5R
Package Type
TDK Corporation
C1005C0G1H100D 0402 (1005 Metric)
050BA
C1-C24,C27,C30, Capacitor, Ceramic 0.10uF 16V 10%
C34X5R
C37,C39,C40,C42C46
Taiyo Yuden
EMK105B7104KV- 0402 (1005 metric)
F
C26,C29
Capacitor, Ceramic 1.5uF 10V 10%
X5R
TDK Corporation
C1005X5R1A155K 0402 (1005 metric)
050BC
C25,C28
Capacitor, Ceramic 4.7uF 16V 10%
X5R
Samsung ElectroMechanics
America, Inc
CL21A475KAQNN
NE
0805 (2012 Metric)
C38
Capacitor,
Tantalum
47 uF, 35 V, 10%
AVX
TAJE476K035R
2917 (7343 Metric)
C41
Capacitor,
Tantalum
100uF 10V 10%
Vishay Sprague
293D107X9010C2
TE3
2312 (6032 Metric)
R1,R2
Resistor
4.7k-Ohm 1/16W
5%
Stackpole
Electronics Inc
RMCF0402JT4K70 0402 (1005 metric)
R3
Resistor
470 ohm 1/10W 1% Rohm
Semiconductor
MCR03ERTF4700
0603 (1608 metric)
R5
Resistor, Chip
1M-Ohm
Panasonic - ECG
ERJ-2GEJ105X
0402 (1005 Metric)
D1
Diode,Schottky
40V 1A
Vishay/
Semiconductors
VSMBRS140TRPBF
DO-214AA, SMB
D2
Diode,Schottky
60V 1A
Vishay/
Semiconductors
VS-10BQ060TRPB DO-214AA, SMB
F
D3
LED
523nM Green clear Avago
Technologies
HSMM-A100S00J1
PLCC-2
L1
Inductor
0.68 uH 614mA
Shielded
API Delevan
S1210R-681K
1210 (3225 Metric)
L2
Inductor
220 uH 320mA
Shielded
API Delevan
SPD62R-224M
SPD-62
J2
Header, Pin Array
252 Pin 1.0mM
Pitch
Advanced
Interconnections
10484PT
BGA-252
J3
Connector, Aurora
2x17 Pin 0.8mM
Pitch
Samtec
ASP-137973-01
SMT - Special
J4
Connector
2 pos 2mm
JST
S2B-PH-SM4TB(LF)(SN)
SMT - Special
J5
Header, JTAG
2x7 Pin 2.54mM
Pitch
FCI
67996-114HLF
Through - Hole
J1
Socket, Receiver
292 Pin 0.8mM
Pitch
Advanced
Interconnections
10278PT
BGA-292
U1
IC
REG LDO 1.25V
0.15A
STMicroelectronics LD39015M125R
SOT-23-5
Table continues on the next page...
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
23
252 PBGA Trace Adapter
U2
Voltage Regulator
4.5-40V DC/DC
Conv. 0.5A
National
Semiconductor
LM2594M-3.3/
NOPB
SOIC-8
Y1
Crystal
20MHZ 8PF
NDK
NX5032GA 20MHZ 2-SMD
AT-W
A.1.3 Trace Adapter drawing
Dimensions of the MPC5746R Trace Adapter (TA) are shown in the following figures.
Figure A-5. MPC5746R 252 BGA Trace Adapter dimensions (top)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
24
Freescale Semiconductor, Inc.
252 PBGA Trace Adapter
Figure A-6. MPC5746R 252 BGA Trace Adapter dimensions (side)
Figure A-7. MPC5746R 252 BGA Trace Adapter dimensions (bottom)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
25
252 PBGA Trace Adapter
A.1.4 Receiver drawing - 252 BGA
The MPC5746R Trace Adapter (TA) requires that a 252-pin BGA receiver be mounted in the target system. The receivers
purchased from Freescale include three (3) alignment holes to assist in plugging the TA into the target board receiver. The
receiver is shown in the following figure, including the holes for the guide (alignment) pins (marked "G" in the drawing). The
guide pins prevent the TA from being inserted into the receiver rotated. The receiver is soldered into the target system similar
to the standard BGA device.
Figure A-8. 252-pin BGA receiver
A.1.5 292 BGA to 252 BGA stack drawing
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
26
Freescale Semiconductor, Inc.
208 BGA Trace Adapter (for 144 and 176 LQFP)
The figure below shows the dimensions of the MPC5746R 252 BGA Trace Adapter (TA) mounted on the 252 BGA receiver.
Figure A-9. 292 BGA to 252 receiver stacked drawing
A.2 208 BGA Trace Adapter (for 144 and 176 LQFP)
This section includes the component layout file for the 208 BGA Trace Adapter (TA) and the side view of the TA stacked
with the 208 to 176 that is used to match the TA to either the 144 LQFP or 176 LQFP package footprints.
A.2.1 208 PGA Trace Adapter drawing
Dimensions of the MPC5746R 208 pin-grid array (PGA) Trace Adapter (TA) are shown in the following figures.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
27
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-10. MPC5746R 208 BGA Trace Adapter dimensions (top)
Figure A-11. MPC5746R 208 BGA Trace Adapter dimensions (side)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
28
Freescale Semiconductor, Inc.
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-12. MPC5746R 208 BGA Trace Adapter dimensions (bottom)
A.2.2 Adapter 208 BGA to 176 or 144 LQFP
The 208-pin Trace Adapter (TA) inserts into a second adapter to match either the 176-pin or 144-pin LQFP packages. An
example schematic of the 208 to 176 adapter is shown in section Schematic 208 to 176 adapter. The bottom side of this 208
to 176/144 adapter has solder balls that match the footprint of either the 176-pin or the 144-pin LQFP package. The 208-pin
to 176-pin adapter dimension drawing is shown in the following figure.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
29
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-13. 208 BGA to 176 LQFP adapter
The 208-pin to 144-pin adapter dimension drawing is shown in the following figure.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
30
Freescale Semiconductor, Inc.
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-14. 208 BGA to 144 LQFP adapter
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
31
208 BGA Trace Adapter (for 144 and 176 LQFP)
A.2.3 208 PGA to 176/144 stacked drawings
The figure below shows the stacked view of the 208 PGA Trace Adapter (TA) with the 176 target adapter.
Figure A-15. 208 PGA stacked with the 176 target adapter dimensions
The 208 PGA TA with the 144 LQFP target adapter is shown in the following figure.
Figure A-16. 208 PGA stacked with the 144 target adapter dimensions
A.2.4 Schematic 208 to 176 adapter
A single adapter is used to convert the 292-pin MPC5746R Emulation Device (ED) to the QFP footprint for both the 176
LQFP and the 144 LQFP packages. The figures below show the schematic (mapping of the 208-pin BGA footprint to the 176
LQFP. The 208 BGA to 144 LQFP is similar and not shown.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
32
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
A
B
C
D
1
2
3
4
5
4
5. Interpret diagram in accordance with American National
Standards Institute specifications, current revision, with
the exception of logic block symbology.
4. Special signal usage:
_ B De not es - Ac t ive- Low Si gnal
< > or [] De not es - Ve ct or ed Si gnal s
3. Device type number is for reference only. The number
varies with the manufacturer.
2. Interrupted lines coded with the same letter or letter
combinations are electrically connected.
1. Unless Otherwise Specified:
A l l resi st or s ar e in ohms , m
o st ar e 1%, 1/ 10 W
a t t.
Otherwise are 5%, 1/8 Watt.
A l l capaci tor s ar e in uF, some ar e 10% or 20%
A l l vol tages ar e DC
A l l pol ar i zed capaci tor s ar e tant al um
NOTES:
TI TLE & REVI SI ON STATUS
CONNECTI VI TY
CONNECTI VI TY
5
Tabl e of Cont ent s
3
Drawn by:
CDC Technologies, Inc.
Designer:
CDC Technologies, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
3
Date:
3/21/2012
Ref:
CDC2264
Date:
xx/xx/xxxx
Date:
xx/xx/xxxx
Rel eas e
Or i gi nal
O
Revi si ons
Des c r i p t i on
Rev
1
xxxxx
Da t e
2
1
SHEET 1
LFTAK46MQM3A
DWG. NO.
Wednesday, March 21, 2012
LAST MODIFIED=
SIZE GEDTTL:
B
GEDABV:
LFTAK46MQM3A
28125 Cabot Drive, Suite 100
Novi, MI 48377
TITLE:
of
Detroit Automotive Technology Center
2
3
O
REV:
A
B
C
D
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-17. 208 to 176 adapter (page 1)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
33
34
A
B
C
D
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
5
208BGA_FREESCALE
J1A
5
175
173
170
167
164
161
158
156
152
149
146
143
140
137
135
131
3
2
171
168
165
162
159
155
153
150
147
144
141
138
124
129
J2A
J1D
H1
H2
H3
H4
H7
H8
H9
H10
H13
H14
H15
H16
J1
J2
J3
J4
J7
J8
J9
J10
J13
J14
J15
J16
K1
K2
K3
K4
K7
K8
K9
K10
K13
K14
K15
K16
4
208BGA_FREESCALE
176QFP_FREESCALE
175
173
170
167
164
161
158
156
152
149
146
143
140
137
135
131
3
2
171
168
165
162
159
155
153
150
147
144
141
138
134
129
4
H1
H2
H3
H4
H7
H8
H9
H10
H13
H14
H15
H16
J1
J2
J3
J4
J7
J8
J9
J10
J13
J14
J15
J16
K1
K2
K3
K4
K7
K8
K9
K10
K13
K14
K15
K16
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
107
104
106
105
110
109
108
26
27
28
31
113
111
112
24
23
25
20
21
22
J2D
176QFP_FREESCALE
107
104
106
105
110
109
108
26
27
28
31
113
111
112
24
23
25
20
21
22
208BGA_FREESCALE
J1B
142
136
130
124
123
151
163
5
6
176
174
169
166
160
157
154
148
145
139
133
132
127
126
8
9
1
4
172
J2B
3
176QFP_FREESCALE
142
136
130
124
123
151
163
5
6
176
174
169
166
160
157
154
148
145
139
133
132
127
126
8
9
1
4
172
3
E1
E2
E3
E4
E13
E14
E15
E16
F1
F2
F3
F4
F13
F14
F15
F16
G1
G2
G3
G4
G7
G8
G9
G10
G13
G14
G15
G16
E1
E2
E3
E4
E13
E14
E15
E16
F1
F2
F3
F4
F13
F14
F15
F16
G1
G2
G3
G4
G7
G8
G9
G10
G13
G14
G15
G16
Drawn by:
CDC Tech, Inc.
Designer:
CDC Tech, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
2
208BGA_FREESCALE
J1C
2
Date:
3/21/2012
Re f:
CDC2264
Date:
<Date>
Date:
<Date>
119
116
115
114
122
118
117
17
18
16
19
11
12
7
10
128
125
121
120
14
15
13
J2C
Date: Wednesday, March 21, 2012
1
Sheet 2
LFTAK46MQM3A
Connectivity
LFTAK46MQM3A
Document Number:
Page Title:
Drawing Title:
28125 Cabot Drive, Suite 100
Novi, MI 48377
of
3
Size
Detroit Automotive Technology Center
176QFP_FREESCALE
119
116
115
114
122
118
117
17
18
16
19
11
12
7
10
128
125
121
120
14
15
13
1
B
O
Rev
A
B
C
D
208 BGA Trace Adapter (for 144 and 176 LQFP)
Figure A-18. 208 to 176 adapter (page 2)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
Figure A-19. 208 to 176 adapter (page 3)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
35
A
B
C
D
L1
L2
L3
L4
L13
L14
L15
L16
M1
M2
M3
M4
M13
M14
M15
M16
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
5
J2H
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
176QFP_FREESCALE
L1
L2
L3
L4
L13
L14
L15
L16
M1
M2
M3
M4
M13
M14
M15
M16
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
208BGA_FREESCALE
J1E
5
84
92
89
97
96
75
63
101
103
102
32
33
37
40
98
95
100
99
35
36
42
48
54
29
30
34
J2E
176QFP_FREESCALE
84
92
89
97
96
75
63
101
103
102
32
33
37
40
98
95
100
99
35
36
42
48
54
29
30
34
4
4
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
176QFP_FREESCALE
J2I
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
208BGA_FREESCALE
J1F
38
39
44
45
51
57
60
66
69
72
78
81
86
88
94
93
41
46
50
53
56
59
62
65
67
71
74
77
80
83
90
91
J2F
3
176QFP_FREESCALE
38
39
44
45
51
57
60
66
69
72
78
81
86
88
94
93
41
46
50
53
56
59
62
65
67
71
74
77
80
83
90
91
3
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
Drawn by:
CDC Tech, Inc.
Designer:
CDC Tech, Inc.
Approved:
Daniel Beeker
Quality:
Daniel Beeker
2
208BGA_FREESCALE
J1G
2
Date:
3/21/2012
Re f:
CDC2264
Date:
<Date>
Date:
<Date>
43
47
49
52
55
58
61
64
68
70
73
76
79
82
85
87
J2G
Date: Wednesday, March 21, 2012
1
Sheet 3
LFTAK46MQM3A
Connectivity
LFTAK46MQM3A
Document Number:
Page Title:
Drawing Title:
28125 Cabot Drive, Suite 100
Novi, MI 48377
of
3
Size
Detroit Automotive Technology Center
176QFP_FREESCALE
43
47
49
52
55
58
61
64
68
70
73
76
79
82
85
87
1
B
O
Rev
A
B
C
D
Appendix B Debugging Emulation Devices with Lauterbach TRACE32
The emulation devices allow debuggers to connect to the Buddy Die (BD) separately in the case that the Production Die (PD)
inside the ED is not yet powered. The script below shows a connection to the BD with the PD disabled.
Here is an example sequence for the MPC5746R. This script defines the device type and assigns both cores to a single
instance of the Lauterbach TRACE32 software. Optionally, this sequence can be modified to use the START32 environment
for independent instances of the TRACE32 software for each core. The CORE.ASSIGN command would be commented out
and the SYStem.CONFIG command would need to be uncommented.
;-------------------------------; Initialize the MPC5746R Emulation Device
; rd 24 October 2013/August 2015
; Assumes that power to the PD is off.
; Initializes 1M of overlay/trace memory
; Opens memory windows on the SRAM and on the SIUL MIDR register area.
;-------------------------------; make sure system is not connected.
SYStem.Down
; select the correct MCU type
SYStem.CPU MPC5746R
; SYStem.CPU MPC5777M
; Control all cores in a single window
CORE.ASSIGN 1 2 ; MPC5746R
; CORE.ASSIGN 1 2 3 ; MPC5777M
;SYStem.CONFIG.CORE 2. 1. ; MPC5746R - multiple window use with START32
;SYStem.CONFIG.CORE 3. 1. ; MPC5777M - multiple window use with START32
;Make sure the PD is not powered
; Power the MPC5746R Trace Adapter from a separate supply (or prior to switch
; and leave power switch off)
; on the MPC5777M EVB, remove LV_CORE jumper from board
;
SYStem.Mode.Prepare
This will then allow the SRAM on the BD to be accessed through the BD Nexus Read/Write Access client (NRWA). The
TRACE32 memory class EEEC uses the NRWA client on the BD to access memory located on the BD. There is also a
reduced size System Integration Unit Lite instantiated on the BD that contains registers for identifying the BD and for
determining the status of the PD. The SIUL Device Identification registers (1 and 2) show the BD part number, mask revision
information, SRAM size, and which BD device is assembled into the Emulation Device.
;now you can access BD memory and BD DCI registers
; the debugger reacts similar to when the core is running,
;i.e. you need /DualPort option
;or an extra "E" for the access classes
NEXUS.Register , /DualPort; read the BD SIUL DIDR registers
Data.dump EEEC:0xc800000
; Initialize the ECC in the BD SRAM
Data.Set EEEC:0x0C000000--0x0C0FFFFF %Long 0x11223344
;read the BD SRAM space
Data.dump EEEC:0x0C000000
ENDDO
The figure below shows a memory dump of the DIDR registers of a MPC5746R Emulation Device.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
36
Freescale Semiconductor, Inc.
Figure B-1. Trace32 window showing DIDR1 and DIDR2 of the BD
Table B-1. Decoded DIDR1 and DIDR2
Address
0x0C80_0000
0x0C80_0004
Field
Bits
Value
Description
PARTNUM
0:15
57BD
The MPC57BD family of Buddy die
MASK_MAJOR
24:27
0x0
The initial major revision.
MASK_MINOR
28:31
0x0
The initial minor revision.
RAM_SIZE
12:15
0x3
1M byte
PARTNUM
16:23
0x01
Buddy Device 1
At this point the PD can be powered, however, it may be desirable to power up the device with RESET asserted to allow
debugger access to the device prior to executing code on the device. This is shown in the following example.
; Command file to run after configuring the BD in an emulation device
; rd 24 October 2013/August 2015
LOCAL &PON
;to make the transition from Prepare to up, assert reset
JTAG.PIN NRESET Low
;now power up the PD
; MPC5746R Switch on the EVB power, Trace Adapter powered by 12V supply
;(MPC5777M EVB - connect LV_CORE on board)
; Prompt to turn power on
REPEAT
(
DIALOG.YESNO "Turn on power to the PD in the Emulation Device"
ENTRY &PON
)
WHILE !&PON
IF &PON
(
;attach debugger to core -> status shows running (inactive)
SYStem.Mode.Attach
;issue debug request
Break
;release reset
JTAG.PIN NRESET High
CORE 1
; -> core halted at reset vector, show program code:
Data.List
; Enable read access to the BD memory space
Data.Set EA:0xfc030008 %long 0x100000
; view the MIDR register of the PD
Data.dump EA:0xFFFC0000
)
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
37
ENDDO
Figure B-2. TRACE32 window showing MIDR1 and MIDR2 of the PD
Table B-2. Decoded MIDR1 and MIDR2
Address
0xFFFC_0004
0xFFFC_0008
Field
Bits
Value
Description
PARTNUM
0:15
5746
MPC5746 part of MPC5746R
ED
16
0b1
Emulation Device
PKG
17:21
0b0_1000
292 MAPBGA package
MASK_MAJOR
24:27
0x1
The initial major revision.
MASK_MINOR
28:31
0x1
The initial minor revision.
Manufacturer
0
0b0
Freescale Semiconductor
FLASH SIZE_1
1:4
0b1000
4 MBYTE of Flash
FLASH_SIZE_2
5:7
0b0000
Needs to be combined with
FLASH_SIZE_1 to calculate the size of
the Flash = 0 x (Flash_SIZE_1 / 8)
PARTNUM
16:23
0x52
ASCII "R" character of MCU Part
Number MPC5646R
This section was written with assistance from Reinhard Weiß, Lauterbach GmbH.
Appendix C Debugging the MPC5746R Emulation Device with the PLS UDE
The PLS Universal Debug Engine (UDE) debugger can make a connection to the Buddy Die in the MPC5746R Emulation
device, even with the Production Die un-powered. This is primarily used for Automotive calibration, but can be very helpful
during normal debug as well.
To connect the debugger to the BD with the PD un-powered (called ‘Cold Start’), start with default UDE configuration and
modify it via Menu Config->Target Interface following the steps below.
1. Select the ‘KeepRunning’ option in the connect pull down menu to allow a "hot attach" to the target device in the
PowerPC JTAG Target Interface Setup window.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
38
Freescale Semiconductor, Inc.
Figure C-1. Target Interface Setup
2. Disable the check for the device JTAG ID, since the JTAG ID of the PD can not be read when the PD in the Emulation
Device is not powered:
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
39
Figure C-2. Disable JTAG ID check
With these settings, a connection to the powered BD can be made. The UDE detects the "Cold Start" condition and
both cores of the production device are shown as "inactive".
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
40
Freescale Semiconductor, Inc.
Figure C-3. Cold Start
In this state, the UDE is using the BD Nexus Read/Write Access (NRWA) client to read and write memory of the BD.
Finally when applying power to the rest of the Emulation Device (power up the PD), the UDE recognizes the state
change and shows the updated status.
Figure C-4. Ready for debug
This section was written with assistance from Mathias Noack, PLS Programmierbare Logik & Systeme GmbH.
Appendix D MPC56xx and MPC57xx available Trace Adapters
Trace Adapters (TA) are available for a number of devices in the MPC56xx and MPC57xx families of devices. The following
table shows TAs that are available. Drawings of these adapters, receivers, and TAs are available by searching the Freescale
web site for the part numbers shown.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
41
NOTE
The MPC55xx family of devices implement VertiCal, which can also be used as a TAs
for those devices. However, the Nexus/debug connector is on a separate board that plugs
into the VertiCal stack. A VertiCal stack can consist of the MCU VertiCal, a trace
connector board, and an SRAM board.
Table D-1. Supported Trace Adapters
Device
MPC560xB
MPC560xE
MPC560xP
MPC5643L
MPC5646C
Trace Adapter part
number
LFMAJO4QJM1
LFMAJO7QJM, 2
Production Package
footprint
Adapter
Receiver
64 LQFP
LFTAJ56E2T
LFTQSE2T
100 LQFP
LFTAJ56HT
LFTQSHT
144 LQFP
LFTAJ56LT
LFTQSLT
176 LQFP
LFTAJ56M2T
LFTQSM2T
LFMAJ04EE2M
64 LQFP
LFTAJ56EE2T
LFTQSE2T
LFMAJ04EHM
100 LQFP
LFTAJ56EHT
LFTQSHT
LFMAJ04PLHT
100 LQFP
Not required
LFTQSHT
LFMAJ04PLT
144 LQFP
Not required
LFTQSLT
LFMAJ43LT3LT
144 LQFP
Not required
LFTQSLT
LFMAJ43LT3A
257 PBGA
Not required
LFBGARBT3AO
LFMAJ46CS1A
256 PBGA
Not required
LFBGARBS1AO
LFMAJ46CS1NT
208 LQFP
Not required
LFTQSNT
208 PBGA
LFTAJ46CNQA
LFBGARBQAO
176 LQFP
LFTAJ46CNM2T
LFTQSM2T
144 LQFP
LFTAJ46CNLT
LFTQSLT
MPC5676R
LFJ76DBGWSA
416 PBGA
Not required
LFBGARBWAO
MPC574xG
LFMAK48GU3M
100 PBGA
LFTAK48GH1A
LFBGARBH1AO
176 TQFP
LFTAK48GM2T
LFTQSM2T
256 PBGA
LFTAK48GS1A
LFBGARBS1AO
LFMAK48GU3U3A
324 PBGA3
Not required
LFBGARBU3AO
LFDBGK46RT4QA
144 LQFP
LFTAK46RQLA
Not required
176 LQFP
LFTAK46MQM2A
Not required
LFDBGK46RT4S2A
252 MAPBGA
Not required
LFBGARBS2AO
MPC5775K
LFDBGK75KV1A
356 PBGA
Not required
LFBGARBV1AO
MPC5777C
LFDBGK77CWSA
416 PBGA
Not required
LFGARBWAO
LFK77CIDBZ2W1A
422 PBGA
Not required
LFBGARBW1AO
LFDBGK77MWA
416 PBGA
Not required
LFBGARBWAO
LFDBGK77MZ3A
512 PBGA
Not required
LFBGARBZ3AO
MPC574xR
MPC5777M
1. Uses the MPC5604B die.
2. Uses the MPC5607B die.
3. This is a special (full array, 18x18) 324 PBGA pin out. Other tools/devices use a different 324 PBGA package in a 23x23
1.0 pitch array.
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
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Freescale Semiconductor, Inc.
Table D-2. Trace Adapter complete part descriptions
Trace Adapter part
number
Description
LFMAJ04QJM
MPC5604B 208 Pin 1.0mm PGA Nexus debug board
LFMAJ04PLHT
MPC560xP 100 pin QFP JTAG Debug Board
LFMAJ04EE2M
MPC5604E 64 Pin 0.5mm QFP JTAG Debug Board
LFMAJ04EHM
MPC5604E 100 Pin 0.5mm QFP Nexus Debug Board
LFMAJ04PLT
MPC5604P 144 Pin 0.5mm QFP Nexus Debug Board
LFMAJ43LT3A
MPC5643L 257 Pin 0.8mm PGA Nexus Debug board
LFMAJ43LT3LT
MPC5643L 257 Pin 0.8mm PGA to 144 Pin 0.5mm QFP Nexus Debug board
LFMAJ46CS1A
MPC5646C 256 Pin 1.0MM PGA Nexus Debug Board
LFMAJ46CS1NT
MPC5646C 256 Pin 1.0MM PGA to 208 Pin 0.5mm QFP Nexus Debug Board
LFJ76DBGWSA
MPC5676 416 Pin 1.0mm Calibration Adapter. Calibrate using special Samtec connector
LFMAK48GU3M
MPC5748G Nexus Debug board
LFMAK48GU3U3A
MPC5748G Nexus Debug board
LFDBGK46RT4QA
292 PIN 0.8MM BGA to 208 1.0MM PGA ADAPTER WITH Aurora interface FOR MPC5746R
LFDBGK46RT4S2A
292 PIN 0.8MM BGA to 252 0.8MM PGA ADAPTER WITH Aurora interface FOR MPC5746R
LFDBGK75KV1A
356 PIN 0.8MM BGA TO PGA ADAPTER WITH AURORA INTERFACE MPC5775K
LFDBGK77CWSA
MPC5777C 416 Pin 1.0mm Calibration Adapter. Calibrate using special Samtec connector
LFK77CIDBZ2W1A
MPC5777C Integrated Debug Board
LFDBGK77MWA
416 PIN 1.0MM BGA TO PGA ADAPTER WITH AURORA INTERFACE MPC5777M
LFDBGK77MZ3A
512 PIN 1.0MM BGA TO PGA ADAPTER WITH AURORA INTERFACE MPC5777M
Table D-3. BGA receivers
BGA receiver part
number
Description
Pins
Pitch
LFBGARBH1AO
SURFACE MOUNT PGA SOCKET FOR 100 PIN 1.0mm VertiCal 100
and Microcontrollers with pins
1.0mm
LFBGARBQAO
BGA base w/receiver 208 pin, 1.0mm pitch (lead-free)
208
1.0mm
LFBGARBS1AO
SURFACE MOUNT PGA SOCKET FOR 256 Pin 1.0MM VertiCal
and Microcontrollers with pins
256
1.0mm
LFBGARBS2AO
SURFACE MOUNT PGA SOCKET FOR 252 Pin 0.8MM VertiCal
and Microcontrollers with pins
252
0.8mm
LFBGARBT3AO
SURFACE MOUNT PGA SOCKET FOR 257 Pin 0.8MM VertiCal
and Microcontrollers with pins
257
0.8mm
LFBGARBU3AO
SURFACE MOUNT PGA SOCKET FOR 324 Pin 1.0MM
Microcontrollers with pins (19x19 packages only)
324
1.0mm
LFBGARBV1AO
SURFACE MOUNT PGA SOCKET FOR 356 Pin 0.8MM VertiCal
and Microcontrollers with pins
356
0.8mm
LFBGARBW1AO
SURFACE MOUNT PGA SOCKET FOR 422 Pin 1.0MM VertiCal
and Microcontrollers with pins
422
1.0mm
LFBGARBWAO
BGA base w/receivers 416 position, 1.0mm pitch (lead free)
416
1.0mm
Table continues on the next page...
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
43
Table D-3. BGA receivers (continued)
BGA receiver part
number
Description
LFBGARBZ3AO
Pins
SURFACE MOUNT PGA SOCKET FOR 512 PIN 0.8MM VertiCal 512
and Microcontrollers with pins
Pitch
1.0mm
Table D-4. Target Adapter complete part descriptions
Receiver part number
Description
LFGARBWAO
MPC5777C 416 BGA Target Adapter
LFMAJ07QJM
Nexus Debug Board, MPC5607
LFTAJ46CNLT
MPC5646C 144 QFP target adapter
LFTAJ46CNM2T
MPC5646C 176 Pin 0.5mm QFP target adapter
LFTAJ46CNQA
MPC5646C 208 Pin 1.0mm PGA target adapter
LFTAJ56E2T
64 LQFP Target adapter for MPC5600 devices
LFTAJ56EE2T
64 Pin target adapter for MPC5604E
LFTAJ56EHT
100 Pin target adapter for MPC5600E
LFTAJ56HT
100 LQFP target adapter MPC5600
LFTAJ56LT
144 LQFP target adapter MPC5600
LFTAJ56M2T
MPC5600 176 LQFP adapter board
LFTAK46MQM2A
208 pin 1.0mm PGA to 176 pin 0.5mm QFP target adapter board for MPC5746
LFTAK46RQLA
208 Pin 1.0mm pitch PGA to 144 pin 0.5mm QFP target adapter board for MPC5746R
LFTAK48GH1A
MPC57xx 100 Pin 1.0MM BGA Target Adapter Board.
LFTAK48GM2T
MPC57xx 176 Pin 0.5MM LQFP Target Adapter Board.
LFTAK48GS1A
MPC57xx 256 Pin 1.0MM PGA Target Adapter Board.
LFTQSE2T
64 pin 0.5mM QFP Surface Mount Target Interface Set
LFTQSHT
QFP Surface Mount target interface set - 100 pin 0.5mm (Lead free)
LFTQSLT
QFP Surface Mount target interface set - 144 pin 0.5mm (Lead free)
LFTQSM2T
176 PIN 0.5MM QFP Surface Mount Target Interface Set
LFTQSMT
QFP Surface Mount Target Interface Set, 160 PIN
Appendix E References
For more information on the device Trace Adapters and Nexus on the MPC57xx family of devices, see the specific device
reference manual and the additional documents listed in the following table.
Table E-1. References
Document
Title
e200z4RM
e200z4 Power Architecture Core
Reference Manual
e200z759N3CRM
e200z759n3 Power Architecture Core
Reference Manual
Location/Availability
freescale.com
Table continues on the next page...
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
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Freescale Semiconductor, Inc.
Table E-1. References (continued)
Document
Title
Location/Availability
e200z760RM
e200z760 Power Architecture Core
Reference Manual
MPC5746RM
MPC5746R Reference Manual
MPC5777MRM
MPC5777M Reference Manual
AN2614
MPC553x, MPC555x, and MPC556x
Family Nexus Interface Connector
AN3968
Nexus Interface Connector for the
MPC567xF and MPC5676R Families
AN4088
Nexus Overview and Nexus Support for
the MPC5500 and MPC5600 Families
AN4224
MPC57xx Nexus Debug Connectors
IEEE-ISTO 5001-1999
The Nexus 5001 Forum™ Standard for a IEEE-ISTO Nexus web site http://
Global Embedded Processor Debug
www.nexus5001.org
Interface, Version 1
IEEE-ISTO 5001-2003
The Nexus 5001 Forum™ Standard for a
Global Embedded Processor Debug
Interface, Version 2.0
IEEE-ISTO 5001-2012
The Nexus 5001 Forum™ Standard for a Available only to IEEE-ISTO 5001
Global Embedded Processor Debug
Consortium Members
Interface, Version 3
IEEE Std 1149.1-1990
IEEE Standard Test Access Port and
Boundary-Scan Architecture
IEEE web site http://www.ieee.org
Introduction to the MPC5746R Trace Adapter, Rev. 0, September 2015
Freescale Semiconductor, Inc.
45
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Document Number AN5181
Revision 0, September 2015