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Abstract
The EC has financially supported a pan-European collaboration on the development of lead-free interconnection materials and use of these materials for electronic assembly in a wide variety of industrial applications. The project started in April
2002 and is now close to the end.
For the lead-free interconnection materials the focus was on lead-free solders, as well as on adhesives. The materials were developed by Heraeus, Germany. The developed solders and adhesives were used in following industrial sectors : displays
(Tecdis Iberica, Spain), automotive (Fiat, Italy), telecom systems (Alcatel, Belgium), smart cards / smart labels (KSW
Microtec, Germany) and portable telecom (Elcoteq, Finland). Conventional passive components, as well as more sophisticated ones like BGA’s or CSP’s were assembled. Special emphasis was on flip-chip assembly. For this purpose dedicated test chips were designed and fabricated (AMIS, Belgium). Industrial partners were assisted in their technology developments by two research institutes : TUBerlin, Germany, and IMEC, Belgium. TUBerlin also developed lead-free solder wafer bumping technologies, while IMEC performed mechanical and thermal-mechanical modelling activities. IMEC also served as the co-ordinator of the project. In this introductory talk the IMECAT project objectives and main realisations will be highlighted.
Introduction
In the frame of the project it is the objective to develop environmentally friendly materials (lead-free solders and adhesives) and to apply these materials effective no-flow underfill technologies are a target.
• Introduction of these new materials and technologies in existing products, thus creating for electrical interconnection and assembly technologies in a wide variety of applications. In environmentally compatible versions of these products (e.g. lead-free soldering instead of Pb short the technical objectives/innovations are :
• Development of a variety of lead-free solders and based soldering), or, on the other hand, introducing the new materials and technologies to adhesives (ICA : isotropically conductive and
NCA : non-conductive), responding to the specific requirements of various industrial applications.
• Development of advanced, environmentally compatible, and cost-effective interconnection and assembly technologies (e.g. new fine-pitch flip-chip technologies, assembly on low temperature substrates, interconnection technologies using solders and adhesives, which are compatible with other materials, like liquid crystal environment). As an example, for flip-chip technologies (both solder and adhesive), cost
• create more advanced products (smaller size, higher functionality), e.g. flip-chip instead of wire bonding.
Developing lead-free solder bumping technology on wafers, using screen printing, including indepth reliability study of assembly technologies using lead-free solder bumped chips. This technology, necessary for lead-free solder flipchip assembly, is not commercially available today.
• Developing thermomechnical models and performing simulations on the realized assembly configurations.

The paper/presentation will contain a summary of main results extracted from following project topics:
• Development of a Lead-free Solder Paste
(Heraeus)
• Technological Advancements in Lead-free Wafer
Bumping using Stencil Printing Technology
(TUBerlin)
• Lead-free Flip Chip: a comparison between leadfree solder and adhesives (IMEC)
• Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip
Applications (IMEC)
• Lead-free soldering development for assembly of complex telecom boards (Alcatel Bell)
• Lead-free Electronic Assembly for Automotive
Applications (CRF)
• Development of the lead free soldering process for portable applications (Elcoteq)
Development of a Lead-free Solder Paste [1]
As a result of the RoHs directive, lead free solder pastes will become a new standard in the electronic industry at least after July 2006. The development of such a lead free solder paste was done in the
IMECAT project by Heraeus. The alloy used in most cases was SnAg4Cu0.5 and the powder was type 3.
The flux was optimised in different aspects: soldering quality, printing and slump behaviour, corrosion resistance, stability and colour of flux residues.
Soldering quality was optimised by means of wetting performance and solder balling results. These tests were conducted under different conditions: two different profiles (see below) and two environments: in air and in nitrogen.
Linear profile 1:
300
250
200
150
100
50
0
0 50 100 150 200
High (soak) profile 2:
300
Tim e in Sec
250
200
150
100
50
0
0 50 100
250
150 200 250
Time in Sec
300
300
350 400
350
450
Printing behaviour was tested in most cases with an
EKRA printer type X5 and a special test layout
(Heraeus Benchmarker II). Important items were fine pitch capability, stencil life (viscosity change during continuous printing), cold and hot slump and printafter-wait performance. It is planned to make this paste a standard product. Therefore we made a benchmark of the developed product (called F640) and compared it with 2 different products, which are already available on the market.
All three pastes have strong and weak points when
compared to each other. Table 1 summarizes the
results (more details in [1]). However, the developed
F640 shows promising results as it scores in generally better than the other two pastes.
Table 1: Summary of the test results for the three pastes
Test Paste 1 Paste 2 F 640
Solder balling
Aperture test
Spread & Slump
Print after wait
Screen Life
0
+
0
0
0
+
-
+
0
0
+
0
-
0
0
Dedicated test chips for flip chip with low pitches
The flip chip test IC’s for this project were developed by AMI Semiconductor Belgium. The chips consist of one metal layer and one passivation layer. Two different test structures are available on the test IC’s: four-point contact resistance measurement structures, to measure the precise resistance of one contact, and one daisy chain to determine the overall contact yield. All chips were designed with a peripheral bond pad layout.
Four different test IC’s were used. The pitch of the chips was ranging from 200µm to 120µm and the size of the IC’s from 10mm x 10mm to 5mm x 5mm.
The most important differences in the flip chip test
IC’s are summarized in Table 1.
Table 2: IMECAT test chip dimensions
Test IC name C1 C2 D1 D2
Size (mm 2 ) 10x10 5x5 10x10 5x5
# of I/O 188 88 252 152
Padsize (µm 2 ) 80x80 80x80 50x50 50x50

Lead-free Wafer Bumping for small pitches using
Stencil Printing Technology [2]
The present study intends to reveal the key process issues involved in stencil printing technology for very- fine- pitch wafer bumping down to 120µm pitch . In parallel, it provides insight into printability issues of newly developed lead-free pastes and attempts a comparison with their eutectic Sn63Pb37 counterparts. Type 6 lead-free pastes with a powder size of 5-15µm were prepared with Sn4%Ag0.5%Cu and Sn3.5%Ag compositions. Their rheological behaviour and product stability were carefully examined using as guide well established type 6 eutectic Sn63Pb37 pastes. Printing experiments have revealed the significance of stencil design parameters, print speed, print pressure, separation speed and shear thinning behaviour of the pastes to the success of the wafer printing up to 120µm pitches. Laser-cut stencils of 75µm thickness were used for bumping of 300µm and 200µm pitch peripheral arrays. Furthermore, the study extended up to 120µm pitch peripheral and area arrays using an electroformed 30µm thick stencil.
Bumping processes have yielded bump heights of
129 ± 2.6 µm and 110 ± 4.5µm for 300µm and
200µm pitch peripheral configurations, respectively.
For very fine pitch structures, lead-free bumping has resulted in bump heights of 57.2±2.6µm and
41.6±2.8µm for 120µm pitch peripheral and area arrays, respectively.
Figure 1: Stencil printed leadfree solder dots (120
µm pitch
Figure 3: Bump height distribution at 120µm pitch peripheral arrays (Number of measured bumps: 34656, Paste:1A-419 SnAgCu)
Cleaning of flux residues, at least for the flux used in these pastes, does not seem to differ from cleaning of the corresponding eutectic pastes. Shear tests have provided strength values of 4.26 g/mil² for the
Sn4%Ag0.5%Cu bumps and 3.07 g/mil² for the
Sn3.5%Ag bumps.
45
Bump height: 130 µm
Bump diameter: 150µm
Pad area: 8.45 mil ²
She ar height: 15µm
Sn4Ag0.5Cu
40
Sn3.5Ag
35
30
25
20
1 3 5
Number of reflow s
7 10
Figure 4: Shear strength of Sn4Ag0.5Cu and
Sn3.5Ag bumps after multiple reflows
Assembly and reliability studies of bumped chips from wafer “C”(200µm pitch) and “D”(up to 120µm pitch) are planned and results will be reported in future communication.
Figure 2: Area array leadfree bumps at 120 µm pitch (after reflow)

Adhesives Flip Chip using combined ICA/NCA
technology [3]
Adhesives as leadfree alternative will use an original technology developed by IMEC to connect the chip
to the printed circuit board [4]. With this technology
isotropic conductive adhesives will make the electrical connections, while non-conductive adhesives will ensure the physical connection.
Special Imecat test boards were designed and manufactured at IMEC. The base of the boards was an epoxy FR4 with a copper layer of 12µm thickness on top. A 4µm nickel gold layer was plated to end with a solderable finish. As can be seen from the finished test board in Figure 1, one board can be assembled with one C1 and one D1 chip and four C2 and four D2 chips.
Figure 6: Stencil printed ICA on PCB (step 1)
Figure 7: Dispensed NCA on PCB (step 3)
Figure 5: IMECAT test board for flip chip assemblies
The use of Isotropic Conductive Adhesives (ICA) for flip chip is very limited in the assembly industry today. Anisotropic conductive adhesives have grown very popular because of the limited number of process steps and the ease of using in a reel-to-reel process. Flip chip with ICA on the other hand needs more processing steps and is therefore also less used in the high-volume production. But the ICA process certainly has some advantages over the ACA process: the contact resistances are lower and more reliable and the costs of the adhesive are much lower.
A new original process was developed at IMEC [4] consisting of the following steps:
1. Application of the (Heraeus) ICA by stencil printing or dispensing on the substrate
2. Pre-curing of the ICA
3. Dispensing of the (Heraeus) Non Conductive
Adhesive (NCA) on the substrate
4. Placing of the die
5. Thermocompression of the chip onto the substrate
More information about process conditions is
described in [3].
Figure 8: Final NICA assembled flip chip on PCB
Figure 9: Cross-section of an interconnection at
150µm pitch

The first experiments already result in very good yields and low contact resistances for both assemblies using lead-free solders and adhesives.
From the electrical measurements we can conclude that soldered interconnections have a lower resistance value than the adhesives interconnection, as expected. However the values of the adhesive interconnection resistance are still very low. The
100% yield of both solder and adhesive interconnections indicates that both technologies are reliable and mature. In the future these assemblies will undergo extensive reliability testing.
LF solder
200µm pitch
0.4 ± 0.1 m Ω
3.0 ± 0.5 m Ω
150µm pitch
1.7 ± 0.2 m Ω
5.8 ± 3.2 m Ω
Adhesive
Lead-free soldering development for assembly of
complex telecom boards [2]
In the framework of the IMECAT project, Alcatel
Bell developed technologies for lead-free reflow, wave and selective soldering processes applicable for soldering large and heavy telecom boards with a broad range of components.
At first a lead-free solder alloy was selected for the different processes. Based on literature and research results the SAC alloy (Sn/Ag/Cu) was chosen. Three different lead-free solder pastes were evaluated.
Important in the choice of solder pastes for telecom applications are:
• Long term reliability
• Performance of the solder paste: o
Printing perfomance
Start-up properties
Idle time o
Environmental stability tests
Tackiness
Stencil life o
Solder paste quality
Solder balling
Metal content
They have been tested to all these properties and the
best solder paste has been chosen [2].
Typical telecom boards have large differences in thermal mass across the PBA. Therefore, a maximized reflow window is necessary. In a preliminary test the process reflow window was determined. One of the more difficult processes is wave soldering since there is a very high interdependency of soldering equipment settings, flux performance and board and component properties. For the evaluation of this process a VOCfree flux is used.
Finally, an existing telecom product as an alternative lead-free version, where all developed lead-free soldering technologies are presented, was realized
(Figure 10). From assembly point of view, no big
problems were seen.
Figure 10: IMECAT demonstrator for telecom applications (ADSL board)
Lead-free Electronic Assembly for Automotive
Applications [2]
Although the automotive industry is exempted from the RoHS directive to the introduction of the lead-free soldering by the 1 st of July 2006, CRF, the research organization of FIAT, aims to develop completely lead-free assembly (WEEE and ELV compatible) even before the directive’s deadline.
Leadfree soldering in the automotive environment is more difficult to implement than any other electronic consumer product since high reliability and high safety level must be proven. The required lifetimes for electronic components in automotive applications range from typically 5,000 hours for passenger cars to 20,000 hours for commercial vehicles: specified failure probabilities for ECU typically vary between
100 and 500 out of 1 million in 10 years.
The requirements for harsh environment (e.g. onengine, on-transmission) electronic controllers units (ECU) in automotive applications have been steadily becoming more and more stringent.
Table 1 shows the temperature extremes that would be encountered by the electronic device depending on its location in the vehicle. It should be noted that internal temperatures would be higher due to the power dissipation. Typical junction temperatures for IC’s are 10-15 ºC higher than base plate temperature, and power devices can reach temperature even 25 ºC higher than that of the base plate.
Table 3: Automotive Temperature/Vibration
Extremes
On Engine
On Transmission
Under Hood
Near Engine
Passenger
Compartment
Max Temperature
140 ºC
120 ºC
80 ºC
Level
17 Grms
17 Grms
3,15 Grms

In the frame of the IMECAT project, three boards
and one final demonstrator (Figure 11) have been
designed, assembled and submitted to combined temperature / vibration tests in order to understand if the state-of-the-art of electronic assembly allow the implementation of the lead-free soldering in automotive already by the 2006. A wide variety of components have been used, commercial and dummy, from flip-chip with pitch from 200 to 500
µm provided within the consortium, to power packages (D-PAK, D2PAK, PSSO) with a particular attention to standard BGA (1mm pitch) package used in all the most recent ECU applications. New highdensity substrates together with new materials with high-T g
have been selected and used.
Results for BGA’s
A particular attention has been dedicated to the large
1 mm pitch BGA (PBGA388), which is the most critical component in every recent ECU application.
X-ray analysis at time 0 showed a really good shape
of the balls and no visible voids (Figure 12).
showed many problems, especially on the balls at the
corner, where cracks are easily visible (Figure 13).
Cross-section together with SEM-EDAX analysis gives an explanation for the failure mechanism. The first intermetallics layer (Ni,Cu)
3
Sn
4 continuous layer of (Au,Ni)Sn the famous AuSn
4
is the typical intermetallics layer formed at the SAC-Ni/Au interface. The Au dissolves in the solder during reflow and the Ni surface reacts with the Sn and Cu from the solder. The second intermetallic is an almost
4
, which is based on
causing the “Au-embrittlement”
(Figure 14) [7]. As a result it is possible to conclude
that on the topside of the solder joints the failure mode in this sample is brittle fracture caused by the formation of a 4-5 μ m thick (Au,Ni)Sn4 layer, which is well known of its brittle behaviour. This combined with the stresses due to the warpage of the package lead to the corner joint failure. The finish at the board side also contains Au, but the level is smaller, which provides a better reliability of this interface.
Figure 12: X-ray picture of a Pb-free assembled
BGA
BGAs showed no failures after the standard validation for the passenger compartment, while after the vibration test for the underhood environment they
Figure 11: IMECAT demonstrator for automotive applications (containing flip chip, BGA, …)
For all the boards, the following analysis have been performed, at time 0 and after all the temperature – vibration test performed:
• Visual inspection
• X-Ray Analysis
• SAM Analysis on flip chip
• Cross Section on BGA and flip chip
• SEM-EDAX Analysis on BGA and flip chip
• Planarity measurement on BGA
• Shear test on passives
• Functional Verification
Two kinds of different sequence of tests have been performed:
• Standard validation according to Fiat requirements o
Passenger compartment (temperature + vibrations) o
Underhood (temperature + vibrations)
• Accelerated life test o
Thermal shock => 1500 h -40÷ 150 °C o
Storage => 1000 h @ 150 °C
Results for standard components
None of the standard components (passives, TSOP,
SOIC, PSO, PQFP, DPAK) failed after both tests and good wetting was found everywhere after assembly.
Figure 13: Fracture of BGA corner solder joint after underhood environmental testing
(temperature+ vibration cycling).

(Ni, Cu)
3
Sn
4
(Au,Ni)Sn
4
Figure 16: Failed flip chip connection after
Figure 14: BGA – SEM-EDAX Analysis of the near-crack area
After 1500 hours pure temperature shocks, and after
1000 hours of storage, no evidence of failures was found, only the beginning of them are present sometimes at the edge of the ball. This concludes that the additional vibration loading cause the “so-called” brittle fatigue mechanism.
Figure 15: BGA – SEM-EDAX Analysis of the near-crack area (after thermal storage and pure temperature cycling).
Results for flip chip assemblies
Similar trends have been found as for the BGA’s: all flip-chips on the board survived to all the test for the validation in the passenger compartment, while many failures showed after the harsh vibration tests for the validation in the underhood environment. However, the failure mode seems to be different: pure solder
fatigue inside the joint (Figure 16). The SEM-EDAX
analysis shows that two different intermetallics layer
on the component side are formed (Figure 17): the
first is (Ni,Cu)3Sn4 +3 at % of P, which shows a clear diffusion of P in it. The second intermetallics layer on the component side is (Au,Ni)Sn4, which is the same “Au-embrittlement” phase, however it is not a full layer (as what we saw in the BGA’s) and therefore no full brittle intermetallic fracture was found.
(Au,Ni)Sn
4
(Ni,Cu)
3
Sn
4
+P
Ag
3
Sn
Figure 17: SEM-EDAX analysis of flip chip joint
To summarize, the results have revealed that leadfree soldering is already suitable from now for devices placed on the passenger compartment while for the underhood applications improvements are still needed in every step of the process.
Development of the lead free soldering process for
portable applications [8]
In the frame of European Union founded IMECATproject the lead free soldering process for portable electronic devices has been developed. For the evaluation a special PCB test board has been
designed (Figure 18). The lead free components
which are selected to this test board are commonly used in portable applications. The smallest components are 0201-type lead free resistors which are assembled in groups of 72 components. The effective coverage level of the PCB area was 30 %.
Also the behaviour of package types like LGA, BGA,
QFP and CSP was studied. The finish on the test board pads were Sn, organic coating (OSP) and traditional nickel/gold. All the boards were inspected with sub-micron level X-ray equipment. The soldering profile used, was linear type and was also carefully adjusted for suitable leadfree components.
The differences in the measured temperatures between components were optimised. As a result a robust process for leadfree SMT-assembly of portable electronics was achieved.

Figure 18: IMECAT test board for portable applications
The main results are summarised below:
• The geometry of electroformed nickel stencil
(openings and thickness) has been optimised in order to avoid tombstoning problems, in particular for small components (0201).
• The reflow profile is optimised with the highest temperature equal to 245°C and temperature differences between the different components of
4°C (Figure 19). In portable applications,
temperature range is not so critical since the difference in size between the components is smaller than for example in industrial or telecom applications.
• Good alignment is achieved, even with initial misalignment of 0.1 mm.
• There was no big differences between the formation of voids in ENIG ,Sn and OSP plated
boards (Figure 20). The OSP seems to give the
lowest number of voids. There is however one component TQFN16 (Thin Quad Flat No-lead), where a large contact pad of 2x2mm is located in the middle of component
Figure 19: temperature profile used for leadfree reflow process for portable application boards
Figure 20: X-ray image of BGA solder joints
Brittleness transition temperature for a range of
leadfree solder compositions [9]
The fracture toughness of bulk Sn, Sn-Cu, Sn-Ag and
Sn-Ag-Cu lead-free solders was measured as function of the temperature by means of a pendulum impact test (Charpy test). A ductile to brittle fracture transition was found for them, i.e. a sharp change in their fracture toughness, compared to no transition for the eutectic Sn-Pb. The transition temperature of high purity Sn, Sn-0.5%Cu and Sn-0.5%Cu(Ni) alloys is around -125°C. The Ag-containing solders show a transition at higher temperatures: in the range of –78° to–45°C. The highest transition temperature of –45°C was measured for Sn-5%Ag, which is ductile only above –30°C. The increase of the Ag content shifts the transformation temperature towards higher values, which can probably be related to the higher volume fraction of SnAg3 particles in the solder volume. These results are believed to be very important for the selection of the best lead-free solder composition.
70
60
50
40
Sn-5%Ag
Sn-4%Ag-0.5%Cu
Sn-3%Ag-0.5%Cu
Sn-37%Pb
Sn-0.7%Cu(Ni)
99.99%Sn
Sn-0.7%Cu
30
20
10
0
-200 -150 -100 -50
Temperature, o
C
0 50 100
Figure 21: Fracture toughness of the leadfree solders as function of the test temperature.
This will influence considerably its range of applications. It is believed also that the failure mode in real solder joints can change considerably around and below the brittle fracture temperature, i.e. the ductile “solder fatigue” failure mode to change to a catastrophic brittle fracture into the solder.

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip
Applications
A 3D Finite Element Model (FEM) was used to simulate the visco-plastic constitutive behaviour of the solder in a f lip chip package when submitted to a
thermal cycle test (Figure 22). When the solder is
subjected to cyclic stresses generated during the thermal cycling, the reliability of the solder joint depends on its resistance to fatigue. The goal of the thermo-mechanical analysis in the electronic industry is to be able to predict, before extensive testing, the reliability of the solder joints. This paper focuses on predicting the thermomechanical behavior of fine pitch flip-chip packages using SnAgCu and SnPb solder alloys. Three different sizes and 2 different pitches were analysed. The number of cycles to failure was correlated to the accumulated creep strain using an empirical relationship found in literature
[11]. Moreover, the results also indicate that this lead
free alloys may be used as alternative solder to improve the resistance to fatigue when compared
with standard lead containing solder (Table 4).
A typical problem encountered in the lead free solder alloys is the presence of voids after the reflow
(Figure 23) because the more aggressive fluxes that
must be used and the subsequent outgassing. In some cases, excessive solder voids can cause some reliability problems because they act as stress concentrators and therefore may allow the crack to initiate and propagate.
Figure 22: FEM mesh for the underfilled 10x10 mm2 flip chip assembly mounted on a 1 mm thick
FR4 board
Table 4: Reliability “estimation” of the different
IMECAT demonstrators (N50 cycles), subjected to –55°C to 125°C cycling.
2,5 x 2,5
5 x 5
10 x 10
IMECA IMECA
T B T C
SnAgCu 793 517
SnPb 622 360
SAC / SnPb 1,27 1,44
SnAgCu 736 483
SnPb 572 331
SAC / SnPb 1,29 1,46
SnAgCu 636 414
SnPb 475 275
SAC / SnPb 1,34 1,51
Figure 23. Cross section of a solder joint showing a void.
A 2D FEM has been built in order to study the presence of voids in the solder joints. Several configurations were analyzed including different size and position of the voids inside the solder joint and the existence of several voids. A solder joint without voids was also model and considered as reference.
From the FEM results, it was found that the maximum inelastic strain of solder joints with voids is not always larger than those without them. This is only true in the case of a single void located randomly in the solder as can be observed in
Figure 25. However, if several voids are located one
aside the other, the accumulated strain in the region between the two voids is much higher than the reference joint because the effective cross section is
reduced (Figure 26).
ε max
= 4.44 %
Figure 24. Equivalent creep strain in a solder joint without voids

ε max
= 4.43%
ε max
= 4.55 %
Figure 25. Equivalent creep strain in a solder joint with a void in different locations
ε max
= 11.58%
ε max
= 10.64%
Figure 26. Equivalent creep strain in a solder joint with several voids.
Thermo-mechanical testing and modelling of the
CSP16x6 area array package
Similar work has been performed for IMEC’s 16x6
memory like CSP package (Figure 23). This relative
large package (DNP of about 7 mm) has been tested using two solder joint materials (SnPb and SAC) and
for two cycling conditions (Figure 28). An FEM has
been built in order to validate the experimental results. The highest creep strains have been found in the same locations as where cracks started to grow in the solder joints.
Figure 28. Weibull plot for the 16x6 memory CSP
Kritische connectie
@–40°C
Silicon: 2.6 ppm/°C
SnAgCu
FR4: 17 ppm/°C
Silicon: 2.6 ppm/°C
FR4: 17 ppm/°C
@+125°C
Silicon: 2.6 ppm/°C
SnAgCu
FR4: 17 ppm/°C
Figure 27. IMEC’s memory like 16x6 CSP
Figure 29. Good agreement between highest creep strain deformations (FEM) and crack locations.

Conclusions
The authors would like to conclude this paper mentioning that the strong collaboration between the
10 European partners lead to huge amount of results and technology improvements. This would have never been possible without this collaboration:
• New solder pastes are developed
• Both leadfree solder and adhesive “fine pitch” flip chip has been successfully assembled, based on stencil printing
• Leadfree assembled demonstrators have been designed and manufactured for portable, telecom and automotive applications
• Characterisation lead to more insight in formed intermetallics and brittleness behaviour of solder materials
• Modelling techniques have been developed for solder joint reliability optimisation.
Acknowledgments
This work has been supported by the EC-Growth
GRD1-2001-40712 project with acronym IMECAT
( www.imec.be/IMECAT ).
References
[1] Wiese J. et al., Development of a Lead Free
Solder Paste, EMPC 2005, June 12-15, Bruges,
Belgium.
[2] Manessis et al., Technology advancements in
Lead-free Wafer bumping using stencil Printing technology, EMPC 2005, June 12-15, Bruges,
Belgium.
[3] Vandecasteele B. et al, Leadfree flip chip, a comparison between leadfree solder and adhesives, EMPC 2005, June 12-15, Bruges,
Belgium.
[4] United States Patent No. US 6.555.414 B1 (April
29, 2003): “Flip Chip assembly of semiconductor devices using adhesives”,
Vanfleteren et al.
[5] Schildermans I., Lead-Free soldering development for assembly of complex telecom boards, EMPC 2005, June 12-15, Bruges,
Belgium.
[6] Mango M., Lead-Free Electronic assembly for
Automotive Applications, EMPC 2005, June 12-
15, Bruges, Belgium.
[7] P. Ratchev, B. Vandevelde and I. De Wolf,
Reliability and Failure analysis of SnAgCu solder interconnections for PSGA packages on
Ni/Au surface finish, IEEE Transactions on
Device and Materials Reliability, Vol. 4, no.1,
March 2004.
[8] Maattanen J., Development of the lead free soldering process for portable applications,
EMPC 2005, June 12-15, Bruges, Belgium.
[9] Ratchev P. et al., A Study of Brittle to Ductile
Fracture Transition Temperatures in Bulk Pb-
Free Solders, EMPC 2005, June 12-15, Bruges,
Belgium.
[10] Gonzalez M. et al, Thermo-Mechanical FEM
Analysis of Lead Free and Lead Containing
Solder for Flip Chip Applications, EMPC 2005,
June 12-15, Bruges, Belgium.
[11] Dudek, et al., "Thermal fatigue modelling for
SnAgCu and SnPb solder joints", EuroSimE
2004, pp. 557 – 564