UNIVERSITY OF CINCINNATI
11/14/2008
Date:___________________
Sachin Gupta
I, _________________________________________________________,
hereby submit this work as part of the requirements for the degree of:
Master of Science
in:
Computer Engineering
It is entitled:
Design and Implementation of Control Logic Interface of In-situ
Environmental Monitoring System
This work and its defense approved by:
Dr. Fred R. Beyette Jr.
Chair: _______________________________
Dr. Carla Purdy
_______________________________
Dr. Ian Papautsky
_______________________________
_______________________________
_______________________________
Design and Implementation of Control
Logic Interface of In-situ Environmental
Monitoring System
A thesis submitted to the
Division of Graduate Studies and Research
University of Cincinnati
In partial fulfillment of the requirements for the degree of
Masters of Science
Department of Computer Engineering
College of Engineering
University of Cincinnati
November 2008
By
SACHIN GUPTA
Institute of Technology, Banaras Hindu University, India, 2003
Thesis Advisor and Committee Chair: Dr. Fred R. Beyette Jr.
ABSTRACT
Environmental pollution, especially water pollution, is one of the most serious problems faced by
environmental engineers and scientists. Hence it is of utmost importance to build a system which
can measure the concentration of various pollutants in water. These pollutants can be inorganic
chemicals such as nitrates, chlorides, sulphates, phosphates etc. One of the foremost requirement
of such a system is that user should be able to control it from base locations. These are called in
situ environmental monitoring systems. The system essentially has a set of sensors to detect the
concentration of pollutants in water and it should also have a signal processing interface which
can digitize the outputs of these sensors (analog output) and send it to a user through a wireless
communication link. User, at the base location, should be able to back annotate the received bits
to check the actual pollution level. The signal processing interface should be reconfigurable in
addition of other features so that user can program the interface according to their requirements.
A research group under the supervision of Dr Papautsky at University of Cincinnati has
developed microelectrode sensor array. The signal processing interface is a mixed signal
interface with analog to digital converter and a control logic block with a set of reconfigurable
registers. The control logic block is designed using standard cell based methodology. Such a
mixed signal ASIC is designed and fabricated through MOSIS using AMI 1.5µm process and
packaged in 40 pin DIP package. This mixed signal ASIC communicate with sensor chip on one
side and with wireless system on the other side.
The in situ monitoring system described finds application in various areas like soil, water,
medicines, laboratory research and monitoring of bioreactors.
This thesis work concentrate upon the control logic block interface of the mixed signal ASIC as
mentioned above.
ii
iii
Acknowledgement
My sincere thanks to my thesis advisor and committee chair Dr. Fred R. Beyette Jr. for his
invaluable technical suggestion, guidance and support throughout the thesis work.
I would like to sincerely thank, Dr. Carla Purdy and Dr. Ian Papautsky for becoming a part of the
thesis defense committee and for giving their precious time to review my thesis.
I would like to thank, University of Cincinnati for providing me the opportunity for pursuing my
Graduation in Electrical and Computer Engineering department.
A special thanks to my parents and siblings for their constant encouragement and blessings that
they have given me at every step on my life.
I would like to thank all the members of the Photonics System Development Laboratory.
Working with them as part of a single team was an enriching and memorable experience.
I would like to thank my friends at UC, Shazia and Manoj for their support. Shazia helped me
immensely with corrections in thesis writing. It will be difficult to forget the time I spent here at
UC with them which made my college life so memorable and enriched.
iv
Table of Contents
List of Figures …………………………………………………………………………………viii
List of Tables ………………………………………………………………………………….xi
1 Introduction
1
1.1 Background ………………………………………………………………………………..3
1.1.1 Microelectrode Sensor Array …………………………………………………....3
1.1.2 Sensor Chip containing Potentiometric and Amperiometric Setup ……………..4
1.2 Problem Statement ………………………………………………………………………...6
1.3 Organization of the thesis ………………………………………………………………….10
2 System Design and Implementation
11
2.1 Mixed Signal ASIC Architecture ………………………………………………………….11
2.2 Analog Multiplexer Block ………………………………………………………………...15
2.3 Control Block Interface …………………………………………………………………...16
2.3.1 Test mode of Operation …………………………………………………………18
2.3.2 Normal mode of Operation ……………………………………………………...19
2.3.3 Control Block Interface Design …………………………………………………22
2.3.3.1 SEQDET Block ………………………………………………………..22
2.3.3.2 PULSE_TO_HIGH Block …………………………………………….24
2.3.3.3 COUNT_CFGBITS Block ……………………………………………24
2.3.3.4 SYNCHRONIZER Block ……………………………………………..25
2.3.3.5 PC Block ………………………………………………………………26
2.3.3.6 CFG_PROG Block ……………………………………………………27
v
2.3.3.7 MUX block ……………………………………………………………27
2.3.3.8 MUX_CTRL Block ……………………………………………………28
2.3.3.9 HOLD_MUXCTRL Block …………………………………………….30
2.3.4 Complete Control Interface Operation …………………………………………..31
2.4 Memory Interface Block …………………………………………………………………...32
3 ASIC Design and Pre-silicon verification Results
36
3.1 Target technology process …………………………………………………………………36
3.2 ASIC DESIGN FLOW …………………………………………………………………….37
3.2.1 Engineering Specification ……………………………………………………….37
3.2.2 Design Entry …………………………………………………………………….38
3.2.3 RTL Simulation …………………………………………………………………39
3.2.4 RTL Synthesis …………………………………………………………………..40
3.2.5 Gate Level Simulation …………………………………………………………..41
3.2.6 Test Logic Insertion ……………………………………………………………..42
3.2.7 Floorplanning, Place & Route …………………………………………………..44
3.2.8 GDS-II to mag …………………………………………………………………..46
3.2.9 DRC and Extraction …………………………………………………………….47
3.2.10 SPICE/IRSIM Simulation ……………………………………………………..47
3.2.11 PADS insertion and final simulation ………………………………………….48
3.2.12 Tape Out ………………………………………………………………………48
3.3 Gate Level Simulation Results …………………………………………………………...49
3.3.1 Block level GLS ………………………………………………………………..49
3.3.1.1 Control block interface GLS …………………………………………49
vi
3.3.1.2 Memory Interface Block GLS …………………………………………..55
4 Layouts and Results
58
4.1 Analog multiplexer layout and its Spice simulation results ………………………………...59
4.2 Control Block Interface layout and IRSIM simulation results ……………………………...60
4.3 Memory Interface Block layout and IRSIM simulation results ……………………………..65
4.4 Complete layout of Digital Interface (Both Control and Memory modules together) ……...66
4.5 Pad Frame Design …………………………………………………………………………...67
4.6 Pad to Pad testing ……………………………………………………………………………69
4.7 Pin assignment and signal description ………………………………………………………69
4.8 Post Fabrication testing of in situ ASIC …………………………………………………….71
5 Conclusions and Future Work
78
5.1 Summary …………………………………………………………………………………….78
5.2 Future Work …………………………………………………………………………………79
References
80
vii
LIST OF FIGURES
Figure 1.1 Potentiometric measurement setup ……………………………………………….15
Figure 1.2 Amperiometric measurement setup ………………………………………………16
Figure 1.3 Overall System Block Diagram …………………………………………………..18
Figure 2.1 In Situ Monitor Block …………………………………………………………….22
Figure 2.2 Analog and Digital interface of the designed ASIC ……………………………...23
Figure 2.3 Analog Multiplexer design ……………………………………………………….26
Figure 2.4 Configuration register format …………………………………………………….27
Figure 2.5 Control Block Operation Flow Chart …………………………………………….29
Figure 2.6 Top level pin interface of control block ………………………………………….30
Figure 2.7 Sub Block Diagram of Control Block ……………………………………………31
Figure 2.8 Overlapping sequence detector (1011) state machine (Mealy) …………………..33
Figure 2.9 184 bit Top_Reg shift register organization in terms of eight 23 bit registers …..38
Figure 2.10 Flowchart showing operation of MUX_CTRL block ………………………….39
Figure 2.11 Black Box Diagram of Memory Interface Block ………………………………43
Figure 2.12 Sub Block diagram of Memory Interface Logic ……………………………….45
Figure 3.1 ASIC Design Flow ………………………………………………………………48
Figure 3.2 Typical simulation process ……………………………………………………...50
Figure 3.3 Logic Synthesis process …………………………………………………………51
Figure 3.4 Scan chain Insertion ……………………………………………………………..53
Figure 3.5 Cadence Encounter flow …………………………………………………………55
Figure 3.6 SEQDET block Gate Level Simulation ………………………………………….59
Figure 3.7 PULSE_TO_HIGH block Gate Level Simulation ……………………………….60
viii
Figure 3.8 COUNT_CFGBITS block Gate Level Simulation ……………………………….61
Figure 3.9 SYNCHRONIZER block Gate Level Simulation ………………………………...61
Figure 3.10 SYNCHRONIZER block schematic …………………………………………….62
Figure 3.11 PC block Gate Level Simulation ………………………………………………...62
Figure 3.12 CFG_PROG block Gate Level Simulation ………………………………………63
Figure 3.13 MUX block Gate Level Simulation ………………………………………………64
Figure 3.14 MUX_CTRL block Gate Level Simulation ………………………………………64
Figure 3.15 HOLD_MUXCTRL block Gate Level Simulation ……………………………….65
Figure 3.16 FIFORESET block Gate Level Simulation ……………………………………….65
Figure 3.17 FIFOREAD block Gate Level Simulation ………………………………………...66
Figure 3.18 FIFOWRITE block Gate Level Simulation ……………………………………….66
Figure 4.1 Analog MUX decoder (3:8) logic layout ……………………………………….…..68
Figure 4.2 Analog MUX Transmission Gate layout ……………………………………………68
Figure 4.3 Analog MUX SPICE simulation result ……………………………………………..69
Figure 4.4 Control Block layout ………………………………………………………………..70
Figure 4.5 Complete control block IRSIM simulation (Normal mode) ………………………...72
Figure 4.6 Complete control block IRSIM simulation (continued) ……………………………..73
Figure 4.7 Memory Interface module layout ……………………………………………………74
Figure 4.8 Memory Interface Block IRSIM simulation (Normal mode) ………………………..75
Figure 4.9 Complete Digital Interface layout …………………………………………………...77
Figure 4.10 Magic Layout of Custom PAD frame for mixed signal ASIC (40 Pins) …………...77
Figure 4.11 Complete ASIC with PAD frame …………………………………………………..78
Figure 4.12 Pin assignment of ASIC ……………………………………………………………79
ix
Figure 4.13 Bonding Diagram as created by MOSIS for DIP-40 Packaging ………….………81
Figure 4.14 The fabricated ASIC (40 pin DIP package) ……………………………….………82
Figure 4.15 Lab testing of ASIC ……………………………………………………………….82
Figure 4.16 Lab testing of ASIC (continued) ……………………………………….………….83
Figure 4.17 Lab testing of ASIC (continued) …………………………………………………..83
Figure 4.18 Complete System Block diagram (testing) …………………………………...……85
Figure 4.19 Base station (User end) Software Interface to capture results ……………………..87
x
LIST OF TABLES
Table 4.1 Top level pin description of the ASIC …………………………………………….80
Table 4.2 Configuration register bits decoded from the 188 bits sent for programming the ASIC
………………. ……………………………………………………………………………….86
Table 4.3 Data comparison between the expected ADC data and the actual ADC data …......86
Table 4.4 Features of in situ ASIC ……………………………………………………….…..88
xi
Chapter 1
Introduction
Because of the long term effects on many ecosystems, environmental pollution has become one
of the most frequently discussed environmental issues. In order to address the issues associated
with environmental pollution, there is a critical need for micro systems which can quantify
environmental levels of pollutants and monitor the changing status of environmental conditions
that are impacted by these pollutants.
Typically, systems that are currently used to quantify the levels of important pollutants in
aqueous solution, ground water, and soil mediums require that the sample analyzed in a
controlled laboratory setting. Unfortunately, many critical environmental monitoring situations
require in situ measurement and/or continuous monitoring that must be done at the field site of
the contaminated sample. Applications requiring accurate, in situ monitoring encompass a large
number of areas including the monitoring of water and waste water treatment reactors, water
distribution systems, stream or lake sediments and a wide variety of soil sampling applications.
The In situ monitoring applications are in medical industry, drug manufacturing, chemical
industry, bio research and the food industry, and for to monitor bioreactors. [1].
1
In situ measurements are done with the help of microelectrode sensors which can measure the
concentration of various pollutants. A microsystem can be defined as a user controlled system
which can accept input from such microelectrodes and output the measurements in readable
digital format to either a display device or a memory device (for data archival purposes). The
microsystem may also include control circuitry that enables a user to control the use of multiple
microelectrode sensors in a coordinated fashion.
In some cases (including many environmental monitoring applications) it is desirable to deploy a
monitoring device that records sensor readings at regular time intervals. In such a system, the
collected data is archived on the device for subsequent download by the user. Such systems
require a communication link to be established between the monitoring device and the “base
station” that will collect the archived data for further data analysis. Communication links
between a remote monitoring device and a base station can be implemented as either hardwired
or wireless links. While hardwired links have the benefits of reduced cost and system complexity
they impose physical access limitations that may ultimately require the removal of a monitoring
system from the field site before the data download can be performed. In contrast, a wireless
system can receive continuous data in a digital format from the monitoring device without
disrupting the deployment of the device at the field monitoring site.
Regardless of the communication link implemented in the system, application software at the
user end can be used to analyze the data that is collected by the environmental monitoring
system.
At the heart of any microsystem, is the digital control hardware that insures proper operation of
the entire system.
In an environmental monitoring system this control hardware can be
responsible for activating individual micro electrodes, enabling the data acquisition and A/D
2
circuitry that is necessary for collecting a reading from an activated electrode, controlling the
short term storage of collected data and ultimately interacting with the data link hardware (either
hardwired or wireless) to insure that sampled data values are properly transmitted to the base
station. Building the digital controller interface of such an environmental monitoring system is
the focus of this thesis work.
This chapter serves as preface to the entire thesis work which details various phases of the
complete system. It starts with brief introduction, in section 1.1, of the work done of the
complete system by previous groups and also to the microelectrode sensor measurements.
Section 1.2 describes the overall System with emphasis on this thesis work. Section 1.3 briefly
summarizes the organization of the remaining chapters in the Thesis work.
1.1 Background
Different Research teams under the supervision of Drs Beyette and Papautsky at University of
Cincinnati have worked on various parts of a complete microelectrode sensor system. The
sections 1.1.1 and 1.1.2 describe briefly the work accomplished by these previous efforts.
1.1.1 Microelectrode Sensor Array (MEA)
A Research team under the direction of Dr Papautsky at the University of Cincinnati has been
involved in the development of a MEMS based microelectrode sensor array. They have
fabricated a microelectrode sensor array with four different probes on a single wafer [2]. Each of
the probes measures the concentration of different analyte in a solution under test.
Microelectrode sensors are based on the principles of reduction oxidation reactions. The outputs
of these sensors can be either in the form of a voltage or in the form of a current. In either case,
the measured electrical signal can be related to the concentration of the different pollutant or
toxicants in the solution under test. The operating voltage range of these microelectrodes is
3
typically on the order of micro-volts while the operating current range is typically in the picoampere to nano-ampere range.
1.1.2 Sensor
Chip
containing
Amperiometric Setup
Potentiometric
and
In order to utilize the microelectrode array described, in the previous section, students under the
direction of Dr. Beyette have developed a sensor chip that interfaces the MEA to a data
acquisition/analysis device.
The purpose of the sensor chip is to amplify and process the
electronic signals received from MEA. Of particular importance is the fact, the sensor chip
significantly reduces the effects of external noise through various noise canceling schemes that
are inherent to the sensor chip circuitry.
The sensor chip contains amperiometric and potentiometric circuitry. Each of these circuits is
discussed in the following subsections.
Potentiometric Measurements
A set of two probes – Sensing probe and Reference probe, are placed in a solution under test.
Because of the activity of Hydrogen ions in the sample (pH of the solution), a voltage difference
is produced which can be measured using a voltmeter. Figure 1.1 shows the experimental setup
for a potentiometric measurement. [3]
The use of a Faraday Cage is required for blocking various noises sources that can couple
electronic noise into this relatively simple microelectrode measurement setup. Unfortunately,
the Faraday Cage severely limits the ability of using this system for in situ measurements. The
incorporation of noise cancellation features into the sensor chip circuitry allows for removal of
the Faraday Cage and enables the field deployment of potentiometric microelectrode
4
measurements. In addition, the potentiometric circuit produces an analog voltage in the range of
0-5 volts which can be transmitted to other signal processing circuitry without the need for bulky
Figure 1.1 Potentiometric measurement setup
signal shielding components like a Faraday Cage.
Amperiometric Measurements
In this mode of measurement, a control voltage is applied across the two probes i.e. reference
probe and sensing probe. With the application of control voltage, a current starts flowing through
the solution under test. The magnitude of the current is a direct reflection of the
pollutants/contaminants contained by the solution. Figure 1.2 shows the experimental setup of
Amperiometric measurement:
In this mode of measurement too, canceling the noise is utmost requirement. The sensor chip for
amperiometric circuitry also amplifies the amperiometric signal produced by the probes and
5
Figure 1.2 Amperiometric measurement setup
produces an analog output voltage in the range of 0-5 volts that is proportional to the current
sensed. [1]
Two different generations of sensor chip have been fabricated by previous groups working under
the direction of Dr. Beyette in the department of Electrical and Computer Engineering at the
University of Cincinnati. The layout of first generation chip was done using Tanner Tools L-Edit
Layout Editor for CMOS 1.5µm technology whereas the layout of second generation chip was
done using Magic Layout Editor for CMOS 0.5µm technology. Both the chips were packaged in
a standard 40 pin DIP package through the MOSIS foundry [5]. The details of the sensor chips
can be found in the research work and thesis write-up from previous students. [1, 3, 4].
1.2 Problem Statement
As discussed earlier, the sensor chip output is an amplified analog voltage signal. The main
motivation of in situ monitoring system is to convert the output of Sensor Chip into Digital
format, storing the output to short term data storage and when requested, send the data to base
6
station user through a data communication link to the base station system where it can be further
analyzed.
As discussed earlier the system should also meet the following requirements:
1. The system should be able to detect the output current from Amperiometric measurement
in the range of pico amperes (pA).
2. The system should be able to detect the output voltage from Potentiometric measurement
in the range of milivolts (mV).
3. The system should be able to select one of the output of the many sensor chips outputs as
per requested by user.
4. The time for monitoring of the different outputs of sensor chip should be user
configurable.
5. System should convert the Analog data from the requested/selected output into readable
digital format and should be able to send the corresponding digital data to user with
wireless communication protocol.
6. The system should be able to store the digital data in case of user is not available and
once the user is available, it should be able to send the stored data through a data
communication link to a base system when requested by the user.
7. The System should be user configurable i.e. the user can program the system so as to
make it work under different configurations.
8. The System should be immune to noise.
9. The System should be low power and cost effective.
A generic system diagram of such a system is as shown in figure 1.3. Note: the figure assumes a
wireless communication link as was ultimately implemented in the overall system developed for
7
Figure 1.3 Overall System Block Diagram
this project. As shown in the figure, the system is divided into three major interfaces: MEA and
Sensor Chip interface, in situ monitor interface and wireless communication interface.
Previous groups under the guidance of Prof R. Beyette Jr. have worked on MEA and Sensor
Chip interface. The in situ monitor is essentially a mixed signal ASIC with contains the Analog
Multiplexer, Sample and Hold circuit, Analog-to-Digital converter, Digital Controller , short
term data storage.
8
This thesis work focuses on the design and implementation of the Analog Multiplexer, Digital
Controller and interface to the short term data storage. All circuits are implemented along with
the Sample and Hold circuit and the Analog-to-Digital converter circuit using a single custom
designed Mixed Signal ASIC. The requirement for the control block and memory interface block
is further divided into the following:
1. The MEA requires a time (on the order of minutes) to stabilize before and accurate
reading can be taken. To accommodate this settling time, the control block should be able
to generate at least 10 minutes of wait time for each of the selected sensor outputs.
2. Once power-on reset is done, the base station user should be able to configure the system
as per the specific measurement requirements of the application. Once configuration is
done, the system should be able to start in active mode.
3. A Base station user should be able to reset the system at any point of time for the purpose
of re-configuring the system. Once a user reset of the system has been initiated, the
device should go into program mode to allow for the loading of a new set of
configuration values.
4. The control block should initiate a sample with the ADC circuitry only after the sensor
stabilization interval has passed (i.e. at the end of the time configured by the user for each
sensor connected to the system). For example, if user wishes to monitor 3rd sensor for 12
minutes then the control block should only sample ADC with 3rd sensor analog data at the
end of 12th minute.
5. To facilitate deployment in field setting that requires batter power operation, the design
should be low power and have a minimum system footprint.
9
1.3 Organization of the thesis
Following the Introduction, the remaining portions of the thesis have been organized in the
following fashion:
•
Chapter 2 presents the technical details of the mixed signal ASIC. This chapter then
continues for the detailed implementation of the Digital Control Block, Memory Interface
Block and the Analog Multiplexer Block of the ASIC.
•
Chapter 3 starts with discussion of the design methodology followed in the design of this
ASIC.
This discussion is followed with simulation results for the different blocks
implemented in this thesis at various stages in ASIC design flow.
•
Chapter 4 deals with the Physical layouts, PAD frame, and final IRSIM/HSPICE
simulation result of the complete layout. It also explains the test plan of the complete
verification of the ASIC and the results of actual testing of the fabricated ASIC in the lab.
•
Chapter 5 outlines the goals accomplished as part of this thesis work. It also briefly
describes the scope of future work.
10
Chapter 2
System Design and Implementation
The previous chapter introduces the need for an in situ monitoring system that could be used for
environmental pollution control. In addition to describing such a system in general terms, the
main requirements of such a system were detailed. As suggested by the first chapter, this thesis
work contributes to the design of an ASIC to implement that analog interfacing and control
operations for an in situ monitoring system. This chapter explains the ASIC design in more detail
and later divides the ASIC into two parts: the Analog Interface and the Digital Control/Memory
Interface. Thereon, this chapter concentrates on the latter part which is the main focus of this
thesis work.
2.1 Mixed Signal ASIC Architecture
In the last chapter, the main requirements for the in situ monitoring system were described. The
mixed signal ASIC, as part of the system should follow all of these requirements. The top level
block diagram of such an ASIC is as shown in figure 2.1.
As shown in the figure 2.1, the in situ monitor block takes input from the output produced by
sensor chip. The ASIC designed as part of this thesis supports a sensor chip with 8 such sensors
inputs. Each of these inputs provides analog voltages corresponding to concentration of
pollutant/toxicant in solution under test. In addition, the figure also shows that the ASIC accepts
user configuration data as an input. Finally, the figure shows the signals required to handle
11
Reset and Clocks
8 different sensor inputs from Sensor‐
Chip External memory interface and ADC output data signals In Situ Monitor (Mixed Signal ASIC) Configuration and Request‐
Data Interface from Wireless System Figure 2.1 In Situ Monitor Block
Power-on reset (PoR) and the various clocks are also part of the inputs to the ASIC. On the
output side, the figure indicates that the output data produced by the ASIC is comprised of
signals for interfacing with an external memory and with the digitized values of the input data
signals. As described in the previous chapter, and shown in the overall system diagram, the
output data from this ASIC is first stored in the external memory and then as per the user request
to access data, it is forwarded to the wireless system which then transmits it to the base station
for further processing. Hence this ASIC must also have memory handshake signals as part of its
inputs and outputs.
As shown in figure 2.2, the main functionality of this ASIC can be sub-divided into two different
interfaces (i.e. the Analog Block and the Digital Control/Memory Interface Block).
The Analog Multiplexer block, as the name suggests, chooses one of the sensors input, out of the
8 available sensor inputs as instructed by the control block. This selection, as mentioned
12
Analog Multiplexer Sample/Hold and Analog to Digital Converter Interface Analog Block (CLK1) Digital Control/ Control Interface
Memory Interface (CLK2 and CLK3) (CLK2) Memory Interface Block Figure 2.2 Analog and Digital interface of the designed ASIC
previously, is user configurable. User can configure the time window during which he wants to
monitor the selected sensor. At the close of the time window, the sensor output from Analog
Multiplexer Block is acquired by the Sample/Hold (S/H) circuitry. The S/H output is then
forwarded to Analog to Digital conversion (ADC) circuitry which converts the corresponding
analog data selected by analog multiplexer block into a 16 bit binary value. This 16 bit binary
value is then forwarded to the Memory Interface block for further processing. Memory Interface
block places the binary value onto the data bus for the External FIFO memory and then generates
read/write enable signals necessary to write the data value into the memory.
The dotted line in the above figure represents the analog to digital boundary. All the circuits
above this line are analog circuits. As indicated in the figure, the ASIC utilizes three different
clocks. The ADC circuitry works on CLK1. The designer of ADC circuitry has fixed this clock
to 4 MHz. CLK2 and CLK3 are 20 MHz and 1 KHz respectively and are used by the control
13
interface and memory interface. The operation of the complete ASIC is as explained sequentially
below.
1. After the power-on reset (PoR), the user sends the bit sequence “1011” to indicate the
start of valid configuration bits being transmitted from the station to the control circuitry.
The control circuitry stores the configuration bits in the control registers (maintained by
control block). Each configuration register contains two fields (a 3 bit sensor ID field and
a 20 bit counter time delay field)
2. Once all the configuration registers are programmed, the first configuration register is
selected. Based on the Sensor ID value held in the first configuration register, the control
block sends a select signal to the Analog Multiplexer indicating which of the eight
possible electrodes to choose.
3. With the microelectrode selected, the control circuitry uses counter time delay value from
the first control register to load a counter that counts down the time interval that the
selected electrode is held as active.
4. Once the time interval expires, the control block sends a “sample” signal to the Sample
and Hold block. This causes the output voltage from the selected electrode to be held in a
capacitor in preparation for conversion to a digital value.
5. The Control block also generates an ADC enable signal on the next clock cycle. This
signal causes the ADC to convert the analog sensor voltage into a 16 bit binary number
which is passed to the memory interface. The ADC also generates a data valid signal that
indicates to the control circuitry that valid data is ready for storage in the FIFO memory.
14
6. Before writing the 16 digital valued into the FIFO memory, the Memory Interface block
appends the 3 bit sensor ID to the 16 bit ADC output and stores these 19 bits into a 19 bit
parallel to serial converter logic.
7. External memory used as temporary data storage in the system is a 1 bit wide
synchronous dual port FIFO [7]. The FIFO also works on a clock signal (CLK_RXTX).
The Memory interface block generates write enable signal to store the 1 bit serial data
from parallel to serial converter into the FIFO.
8. When a base station is present (as determined by the wireless communication link control
circuitry) the Memory Interface Block generates the FIFO read signal for FIFO to
forward data to wireless transmission system.
9. Meanwhile, the next set of user configuration data is selected and step 2-8 repeat for the
next configuration register. (Note: after the last configuration register is processed, the
control circuitry starts again with the first configuration register.)
The main focus of this thesis is to design and implement Analog Multiplexer Block, Control
Interface Block and Memory Interface Block. Also, a modular approach was followed for the
design of Digital Interface (Control Interface and Memory Interface). Design of these three
interface blocks i.e. Analog Multiplexer Block, Control Interface Block and Memory Interface
Block is explained in the next sections. The chapter ends with a discussion of all the blocks
work together to form the complete control system.
2.2 Analog Multiplexer Block
The Analog Multiplexer selects one input out of the various analog inputs based on the select
inputs. The main requirement of the Analog Multiplexer is to maintain signal integrity i.e. the
selected analog output should be equal to the corresponding input. As the number of sensor
15
inputs to the ASIC is 8, and only one of them is to be selected, the requirement is to design an
8:1 MUX with 3 select lines. The basic switch used in the multiplexer design is a Transmission
Gate (TG). Transmission Gate switch has advantage of outputting complete voltage swing. The
design of Analog MUX is as follows in the figure 2.3.
The Control Block generates 3 bit sensor select signal which indicates the sensor to be activated.
These 3 bits are then converted to 8 bits with the help of a 3 to 8 decoder. The decoder output
then enables one of the Transmission Gates. The output signals from the sensor chip provides the
inputs of the TG and the corresponding voltage is thus made available on the MUX Output.
2.3. Control Block Interface
The control block logic works as master controller. It meets the following requirements:
1. User Configurability: Control block maintains 8 sets of 23-bit user configurable
Registers. User can program these registers at any time after the power-on reset. The
8 Input Sensor Channel
3 bit Sensor Select Signals 7 2
1
0
TG
TG
3 Bit to 8 Bit Decoder Logic TG
MUX Output TG
Figure 2.3 Analog Multiplexer design
16
20 bit counter (Represents the Time user want to select a sensor programmed in Sensor ID) field) Sensor ID (Represents the sensor to be selected or monitored out of 8 Sensors) Figure 2.4 Configuration register format
programming of these registers is done at the same clock frequency used by the wireless
system (20MHz). The structure of a 23-bit register is as shown in figure 2.4.
2. The various microelectrode sensors takes approximately 15 minutes to reach stabilized in
real world scenario. The, 20 bit counter in Fig. 2.4 works on a very slow clock of 1.0
KHz frequency (1.0ms time period). Hence the maximum time that a sensor can be
monitored is 220 x 1.0ms which is 17.5 minute.
3. Reset Logic: There are two different Reset implemented in the system, Power-On Reset
and User generated Reset. Power-On reset is used at the very beginning of system use
(i.e. power up). The other type of reset is generated by the user at any point of time of
system operation. Whenever user want to reset the system and program the configuration
registers with a new set of data, he sends “1011” bit sequence. Once this is detected, the
control system initiates a reset i.e. system stops what it was doing and all the memory
data are cleared. After the ‘1011’ sequence, the user programs the configuration registers
again and then normal system operation resumes.
17
4. Low Power Design: Various low power schemes have been considered while designing
the control block. Some of them are clock gating, power gating and Gray code encoding
of state machines to reduce the signal activity factor and thus reduce power consumption.
5. Testable System: The control block design has been implemented with 4 different sets of
scan chains. With the help of these scan chains, the different bit patterns can be sent over
the control block interface and various faults testing can be done. Almost all of the flipflops have been connected in the design so that 100% fault testing can be done.
The control block operation, in normal mode, is as explained with flow chart as mentioned in
Fig 2.5. The Top level diagram for control block interface is as shown in Fig 2.6
2.3.1 Test mode of Operation
In this mode of operation, different scan enables are set active high as per the testing of the
different blocks in the design. There are 4 different scan chains maintained in the system and
each of these scan chains can inject bit parents to test different segments of design for detection
of various stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) faults. The scan chain enable signals are
SCE*, scan chains inputs are SCI* and the outputs are SCO*. Scan testing is further explained in
the next chapter.
18
2.3.2 Normal Mode of Operation
In Normal mode operation, all scan enable signals (SCE*) for the different scan chains are set to
Figure 2.5 Control Block Operation Flow Chart
19
RST CLK_RXTX CLK_CTRL X reset Start_ADC CONTROL BLOCK INTERFACE (CTRL BLK) Start_SH 3
muxctrl_fifo SCE0 SCE1 ctrl_start SCE2 SCO0 SCE3 SCO1 SCI0 SCO2 SCI1 SCO3 SCI2 Figure 2.6 Top level pin interface of control block
low. As explained in the flowchart (Fig 2.5), after RST, the user needs to send a sequence of
“1011” indicating to the control block that configuration bits are being sent to program the
control circuit operation. The reception of this sequence also generates an Internal Reset to the
system. This signal reset is also sent to the output of control block connected to the Memory
Interface block. This is a necessity considering the fact that the system needs to be cleared when
the user decided to send another set of configuration data. This programming interface is a serial
bit interface with signal name X and it works with the CLK_RXTX clock which is the 20.0MHz
clock shared with the Wireless Receiver/Transmitter Interface.
Once the program sequence is detected on the interface, the configuration registers maintained in
the CTRL BLK have to be programmed with the next 184 bits. Once all the registered have been
programmed as per the user configured data, the Program Counter (PC) selects the first
configuration register (23 bit). The 3 bit sensor ID is sent to the Analog Multiplexer as shown in
Fig 2.3. The 20 bit counter value is loaded into the counter and then decremented on each
positive edge of the 1.0 KHz Control Clock (CLK_CTRL). Once the counter expires (i.e. reaches
to all zeros), the signal Start_SH is generated to enable the Sample and Hold Circuitry (S/H) in
Analog Block. The Analog Multiplexer output is connected to the input of S/H. The S/H circuit
output is almost constantly the analog sensor voltage. Start_ADC is created on a one cycle (on
20
CLK_CTRL clock) delay after the Start_SH signal. The Start_ADC signal is used to enable the
Analog to Digital Converter circuitry (ADC). The ADC then processes the analog voltage held
by S/H and produces a corresponding 16 bit digital binary value.
The interesting thing to note here is that ADC takes some processing time to convert the analog
data into a binary format.
Hence the S/H circuit holds the previous data till the counter
expiration of the next configuration register. The Program Counter (PC) is then increment by one
and points of the next configuration register. This process repeats and after serving the last
configuration register, PC points back to the first configuration register. Finally, as described
Figure 2.7 Sub Block Diagram of Control Block.
21
before, the user can interrupt/reset the system operation and reprogram the registers at any time
by sending a “1011” sequence on the signal X.
2.3.3 Control Block Interface Design
The Control Block Interface, as explained previously, as been divided into a number of subblocks. The lower level block diagram of control block is as shown in Fig 2.7.The description of
individual sub-blocks is as follows in the next section.
2.3.3.1 SEQDET Block
The SEQDET block is responsible for the initial detection of the “1011” sequence after the
power on reset, which also implies detection of the valid sequence of 184 configuration bits that
follows the “1011” flag. The SEQDET block also generates an internal reset to the system on
the reset pin. Input RST is the power on reset to the block and X is the serial input sent by
Wireless Interface at the frequency of the CLK_RXTX clock. The output Z implies the
completion of detection of overlapping sequence of “1011” on input X. Once the sequence is
detected, it is implied that user wants to write a new set of programming bits into the
configuration registers. Hence an internal reset signal called reset is asserted to the various
blocks of the design for clearing the previously collected data. The user then sends 184 bits of
configuration registers programming bits t input X on 184 clock cycles of CLK_RXTX. Also if
“1011” bit pattern is a part of the write data for configuration registers then there will not be any
reset assertion. To accomplish this requirement, the input Z_high from PULSE_TO_HIGH subblock is used. The signal Z_high is asserted high as soon as the sequence “1011” is detected first
and remains high till the end of configuration write of 184 bits data i.e. for next 184 CLK_RXTX
clock.
22
~RST ~Z_high & ~X | Z_high / reset= 1, Z = 0 S0
~Z_high & ~X | Z_high / reset= 1, Z = 0 ~Z_high & X / reset = 1, Z = 0 ~Z_high & ~X | Z_high / reset= 1, Z = 0 Z_high / reset = 1, Z = 0 S1
~Z_high & X / reset = 1, Z = 0 ~Z_high & ~X / reset = 1, Z = 0 S2
~Z_high & ~X | Z_high / reset= 1, Z = 0 ~Z_high & X/ reset= 0, Z = 1 ~Z_high & X / reset= 1, Z = 0 S3
Figure 2.8 Overlapping sequence detector (1011) state machine (Mealy)
A separate scan chain (Scan chain 0) is maintained for this block with SCE0, SCI0, SCO0 as scan
enable and scan input and scan output signals respectively. The mealy form of state machine
which detects the sequence “1011” in the block is as shown in Figure 2.8.
The “Mealy” state machine detects overlapping patterns of “1011” sequence.
Mealy state
machines have the advantage of having lesser states than the same logic implemented on Moore
state machines. Also, Mealy machines react faster to the inputs as they react in the same cycle.
In Moore machines, more logic may be necessary to decode states into outputs and hence more
logic delays. On the other side, Moore machines are safer to use [6]. But in this case any kind of
state machine can be used without much concern for the large state machines i.e. state machines
with large number of states, the gray encoding or One Hot/Cold encoding is usually preferred as
23
it reduces the output and next state decoding logic. It also reduces the switching power as the
number of transitions from one state to another state is minimal because of inherent
characteristics of the above mentioned encoding schemes.
The important thing, in terms of writing synthesizable RTL code for state machines is to specify
all the outputs for the states and all the combinations of inputs. In terms of simulation, RTL code
which does not follow this criterion may work well but Synthesis of this code may implement
unwanted implicit latches in the netlist and thus, the Gate level simulation may not simulate
correct values.
2.3.3.2 PULSE_TO_HIGH Block
This block takes inputs Z and ctrl_start from SEQDET and COUNT_CFGBITS blocks and
provides the output signal Z_high. The ctrl_start signal is an indication to the Wireless
receiver/transmitter system that the 184 bits configuration register programming data has been
received. This signal is used by the Wireless interface to switch itself from Configuration mode
to the Data Transmit mode. Signal Z_high remains high from the start of the signal Z till
ctrl_start signal. Hence the state machine shown in Fig 2.8 will make sure that pattern “1011”
can appear in configuration data without disruption to the configuration process.
The Pulse_To_High block maintains a different scan chain (Scan Chain 1) than the SEQDET
Block with SCE1and SCI1 as scan enable and scan input signals respectively while the scan out
signal of the Pulse_To_High block is connected to scan input signal of COUNT_CFGBITS
block explained in next section.
2.3.3.3 COUNT_CFGBITS Block
The COUNT_CFGBITS Block is responsible for counting the number of configuration bits (i.e.
for counting the 184 clock of CLK_RXTX pulses). Counting starts when the input signal Z_high
24
becomes high and it keeps counting untill it remains high on the positive edge of CLK_RXTX
clock. When the count reaches 183, it asserts a pulse on signal ctrl_start. This signal is used by
the PULSE_TO_HIGH block to assert the Z_high signal low on the next clock. Also it is used by
the wireless receiver/transmitter system as an indication of completion of configuration register
programming data as explained in the previous section. The output ctrl_start_high is asserted
high as soon as the count reaches 183 and is never asserted low until the user writes new
configuration programming data (sends “1011” to indicate the start of new set of programming
data and a internal reset is generated on signal reset). The reset input can only asserts this output
to active low as explained. The purpose of this output signal is explained in the next section
which explains the functioning of the block that uses this signal as input.
This block share the scan chain with the PULSE_TO_HIGH block as explained previously. The
scan input to this block is connected to the scan output of PULSE_TO_HIGH block. SCE1 and
SCO1 are the scan enable and final scan output signals respectively for this scan chain.
2.3.3.4 SYNCHRONIZER Block
The synchronizer block is used for transmitting signal from one clock domain to another clock
domain. The signal ctrl_start generated by COUNT_CFGBITS block is also used as an
indication to the other blocks of the control logic (i.e. core of the control logic) to start their
operation. The core of the control logic works 1.0 KHz clock, CLK_CTRL. As the signal
ctrl_start is generated on a sufficiently high frequency clock CLK_RXTX (20.0 MHz), it is
difficult to detect this signal on CLK_CTRL clock. The issue is that the ctrl_start signal may be
completely missed by the positive edge of clock CLK_CTRL. To overcome this problem,
ctrl_start_high signal is used which is asserted high by the COUNT_CFGBITS block as soon as
count reached 183 and never asserted low unless system resets, as explained in previous section.
25
Now the ctrl_start_high signal is now used by the synchronizer block on the very first positive
edge of CLK_CTRL clock and it generates a single pulse output ctrl_start_new on CLK_CTRL
clock which is now used by core of the control logic to start their operations. Two stage of
synchronization is used to reliably transmit the ctrl_start signal into CLK_CTRL clock domain. It
is noticeable that this signal is generated only once unless user resets the system to write new set
of configuration register programming data. The input reset is asynchronous reset to this block as
reset input is generated on the CLK_RXTX clock.
The synchronizer block uses a Scan Chain 3 with SCE2, SCI2 as scan enable and scan input
signals respectively while the scan out signal of this block is connected to scan input signal of
program counter (PC) block as explained in next section.
2.3.3.5 PC Block
The PC block i.e. Program Counter block points to the current configuration register and once
the counter value of this configuration register expires, the PC increments by 1 and points to the
next configuration register. It is noted that there are 8 sets of configuration registers are
maintained in the control logic. Once it reaches the end of the 8th configuration register, PC
jumps back to pointing at the first register for the next computation. The PC block works on
CLK_CTRL clock. The 4 bit ctrl output represents the current configuration register selected.
The default value of ctrl vector is “0000”. Value “0001” on ctrl vector represents the first
configuration register selection and so on. When the ctrl_start_new is asserted high by the
SYNCHRONIZER block, the ctrl vector increments from default value to “0001” and points to
the first configuration register. This is to be noted that ctrl_start_new signal is asserted only once
unless user resets the complete system again. The next increment on the ctrl vector happens after
the assertion of ctrl_start1 pulse signal which is asserted by the MUX_CTRL block. The output
26
ctrl_start_muxctrl signal is one clock delayed version of input ctrl_start_new or ctrl_start1 input
signal.
The PC block shares Scan Chain 3 with the SYNCHRONIZER block and MUX_CTRL block.
The scan output signal of SYNCHRONIZER block is connected to scan input of this block and
its scan output is connected to scan input of MUX_CTRL block. The scan enable signal is SCE2.
2.3.3.6 CFG_PROG Block
This block maintains the configuration register sets to be programmed by the user. There are 8
such 23 bit register maintained in the design. Hence an 8*23 i.e. 184 bits shift register called
Top_reg is maintained in this block. The serial input is signal X and the clock to the shift register
is gated clock which is the logical AND of Z_high signal and CLK_RXTX clock. Z_high signal,
as mentioned in the previous sections, remains high for 184 clock cycles of CLK_RXTX clock.
Hence the 184 bits are loaded into the shift register as the programming data and after that the
shift register clock gets disabled. It will get enabled only when the user wants to write the
configuration register again and “1011” sequence appearing on signal X is detected by the
SEQDET block again. Also, this block does not require any reset input as the shift register
overwrites the previous values written into it. The output of this block is 184 bit shift register
Top_reg as mentioned above.
It can be easily noticed that this block does not require a shift input. Input signal X works as shift
input to this block. This default scan chain of this block is enabled by scan enable input SCE3
and the scan output of this block is the final flip flop output of shift register and is named as
SCO3 and this output is available at the Chip I/O for further testing.
2.3.3.7 MUX block
27
The MUX block consists of purely combinational logic. As the configuration register is designed
in the form of a shift register, the input signal ctrl decides the 23 bits of the corresponding
register to be selected out of the 184 bit shift register Top_reg. The organization of this shift
register is as mentioned in the Fig 2.9. If the input signal ctrl has value “0001” i.e. if it points to
the first configuration register (CFG REG-1), then the 23 bits selected are bit 167 to bit 183. As
mentioned in configuration register format on Fig 2.4, the bits 167-169 (3 bits) are the outputted
to muxctrl signal which works as a sensor ID and bits 170-183 (20 bits) are outputted to
CtrlCounter signal which works as the 20 bit counter value. The other registers bits are selected
in the same manner from the Top_reg shift register.
2.3.3.8 MUX_CTRL Block
183 167 CFG REG‐1 166 138 CFG REG‐2 115 CFG REG‐3 137 92 CFG REG‐4 114 9
69 CFG REG‐5 6
46 CFG REG‐6 4
23 CFG REG‐7 2
0 CFG REG‐8 20 bit output signal CtrlCounter
3 bit output signal muxctrl Figure 2.9 184 bit Top_Reg shift register organization in terms of eight 23 bit registers
28
The MUX_CTRL block is responsible for generating the time interval as per requested by the
user in the corresponding configuration register. The operation of this block is as shown in the
flowchart in Fig 2.10. The 20 bit CtrlCounter value selected (based on the ctrl signals) in MUX
block is loaded in a 20 bit binary down counter on asserting of ctrl_start_muxctrl signal from PC
block. From this point onwards, on each positive edge of CLK_CTRL, the down counter value
decrements by 1. Once it reaches the binary value ‘1’, it asserts Start_SH signal high for one
clock. On reset, the down counter is cleared to a value of zero. On the next positive edge of
clock, the counter reaches Zero (i.e. the counter expires). When the counter expires, the output
signal ctrl_start1 is asserted high for one clock pulse. The output signal Start_ADC is the same
Load the down counter with CtrlCounter value selected in MUX block when ctrl_start_muxctrl is asserted high by the PC block. Decrement the down counter by 1 on positive edge of CLK_CTRL clock.
Is down counter value ‘1’? No
Yes
Assert Start_SH signal high for one CLK_CTRL clock. Assert Start_ADC (same as ctrl_start1) high on next positive edge of CLK_CTRL for one cycle. Figure 2.10 Flowchart showing operation of MUX_CTRL block.
29
as the output ctrl_start1. It can be easily noticed that signal Start_ADC (i.e. ctrl_start1) is one
clock delayed (on CLK_CTRL clock) version of Start_SH signal. As mentioned previously, the
requirement of the design is to generate a time interval that is on the order of 10 minutes (The
designed microelectrode sensors usually take minutes of time to reach a stabilized value). Hence
at the CLK_CTRL clock frequency of 1.0 KHz, the down counter can generate maximum time of
220 x 1.0ms which is 17.5 minute.
The MUX_CTRL block, as mentioned previously, shares the scan chain (scan chain 3) with the
SYNCHRONIZER block and PC block. The scan output of PC block is connected to scan input
of this block. SCE2 and SCO2 are the scan enable and final scan output signals respectively for
this scan chain.
2.3.3.9 HOLD_MUXCTRL Block
Start_SH and Start_ADC signals generated in the previous blocks enable the Sample & Hold
circuit (S/H) and Analog to Digital Converter (ADC) circuitry respectively. ADC takes a finite
amount of conversion time to convert the analog value latched in the last clock window
(activated by the Start_SH signal) into the corresponding 16 bit binary value. The control
interface then appends the Sensor ID (i.e. 3 bit muxctrl signal) to this 16 bit value. This is done
for easy and reliable decoding of output data at the user end. Once Start_ADC is asserted, the PC
increments and selects the next configuration register and the next sensor is selected as
programmed by the user. As ADC takes some time for its conversion process, the previous value
of Sensor ID (i.e. 3 bit muxctrl signal) is held so as to append it to the 16 bit ADC binary output.
The HOLD_MUXCTRL block serves this purpose. On Start_SH signal, this block store the
previous value of sensor ID (i.e. 3 bit muxctrl signal) to 3 bit muxctrl_fifo signal and when the
30
ADC output is ready, signal muxctrl_fifo is appended to the ADC data. On reset, the muxctrl_fifo
value is assigned zero.
2.3.4 Complete Control Interface Operation
The complete operation of Control Interface is explained in the following steps:
1. The first step is to provide the system a power-on reset (PoR) on input signal RST. Once
PoR is complete, the user sends a “1011” sequence on serial input signal ‘X’ to indicate
the start of a set of valid configuration bits. This sequence detection (done by SEQDET
block) also generates an internal reset to the system on signal reset.
2. The PULSE_TO_HIGH and COUNT_CFGBITS count the next 184 clocks (on
CLK_RXTX clock) after the “1011” sequence detection to provide the enable signal to the
gated clock of the CFG_PROG block. Hence the CFG_PROG block is enabled only for
the next 184 clocks during which the user write the 8 sets of 23 bits (184 bits in all)
configuration registers. This configuration register set is named Top_reg. These blocks
also generate a signal ctrl_start to indicate to the Wireless receiver/transmitter system
that it has accepted the configuration data. The SYNCHRONIZER block then
synchronizes this ctrl_start signal generated in CLK_RXTX clock domain to
ctrl_start_new signal in CLK_CTRL clock domain.
3. Once the configuration register writes is done, the PC block will be incremented (on
detection of ctrl_start_new signal) by 1 to point to the first configuration register and
generates a 4 bit ctrl signal as selector input to be used by MUX block. It also generates
the one clock delayed version (named as signal ctrl_start_muxctrl) of ctrl_start_new
signal or ctrl_start1 signal.
The following increments on ctrl signal are done on
detection of ctrl_start1 signal.
31
4. The multiplexer block then select the 23 bit register as pointed by the ctrl signal and
outputs the 20 bit CtrlCounter value and 3 bit muxctrl (sensor ID) value from the selected
register.
5. The 3 bit muxctrl signal (sensor ID) selects one sensor out of the 8 input sensors. This
muxctrl signal connects to the 3 bit sensor select signal in the Analog Multiplexer block
interface. The selected output is connected as input to the Sample and Hold circuitry.
6. The 20 bit CtrlCounter is loaded in a down counter value on detection of
ctrl_start_muxctrl signal. The down counter decrements by 1 on each positive edge of
CLK_CTRL block. Once the down counter reaches the values of 1 and 0, it generates
Start_SH and Start_ADC (same as ctrl_start1 signal) respectively. The steps 3 to 5 repeat
from now on with the next configuration resister selected.
7. Start_SH signal enables the S/H circuit which holds the analog data in that cycle window
to be processed by ADC circuitry.
8. ADC then gets enabled on the next cycle (on Start_ADC signal) and converts the analog
data latched by S/H into the 16 bit binary data.
9. The previous value of Sensor ID (i.e. 3 bit muxctrl signal) is stored on muxctrl_fifo signal
and is appended to 16 bit ADC output for easier and reliable processing of data at user
end software.
2.4 Memory Interface Block
The 19 bit output (16 bit ADC data appended with 3 bit sensor ID) generated in the previous
block is to be stored in an external FIFO. An external FIFO is used because the core area inside
the PAD frame of the ASIC chip was insufficient to design the memory circuits. The FIFO used
is manufactured by Texas Instruments and is 256 deep, 1 bit wide Synchronous FIFO [7]. The 1
32
bit wide FIFO is used as the 19 bit binary output data is outputted to external FIFO in a serial bit
fashion. This requirement comes out due to the constraints on the number of external I/O pins on
the PAD frames used. It was difficult to accommodate anything greater than 1 bit output on the
external I/O pin. The memory interface block generates the Read enable and Write enable signals
and also converts the parallel 19 bits data from control Interface into the serial bits necessary for
writing into the external FIFO. Also as per the requirement of the FIFO reset, the memory
interface block generates the FIFO reset to external I/O pin. The top level diagram of this
interface is as shown in figure 2.11
The Memory Interface block receives the internal reset generated by control interface on signal
reset. SCE and SCI are the scan enable and scan input signals. It also receives the 19 bit binary
data (16 bit ADC output appended with 3 bit sensor ID) as its input on bus ADC_data. ADC
also provides a signal Data_Valid when ADC generates the valid data ADC_data corresponding
to the analog value held by the S/H. This data needs to be written to the external FIFO. The reset
for FIFO is required to be at least 4 cycles of CLK_RXTX signal. Hence this block also generates
the fiforeset signal from input reset signal as per the requirement of FIFO. When Data_Valid
reset fiforeset CLK_RXTX MEMORY INTERFACE SCE BLOCK SCI WRTEN RDEN Data_Valid Send_data ADC_data fifodata_rdy fifo_serdata 19 Fig 2.11 Black Box diagram of Memory Interface block 33
signal is asserted by ADC, the 19 bit ADC_data input is loaded in a parallel to serial shift
register and from next cycle of CLK_RXTX clock, each bit of shift register is shifted out to the
single bit fifo_serdata signal in 19 cycles of CLK_RXTX clock. Signal fifo_serdata connects to
the input data signal of external FIFO. The output WRTEN (Write Enable for FIFO) is asserted
high during these 19 clock cycles of CLK_RXTX clock. The FIFO also works on CLK_RXTX
clock. Once the data is written into the external FIFO, the user may access it by reading from the
FIFO. Such request from user is received on Send_Data signal. When Send_Data signal is
detected, the memory interface block generates one pulse on fifodata_rdy signal to indicate the
wireless transmitter that it is ready to send the data from next clock onwards. On the next clock
the output signal RDEN (Read Enable for FIFO) is asserted high and remains high for the next
19 cycles of CLK_RXTX clock. Once RDEN becomes low, another pulse on fifodata_rdy signal
is asserted on next cycle of CLK_RXTX clock to indicate wireless transmitter the completion of
data sent. The complete memory interface design is divided into 3 sub blocks as mentioned in the
Figure 2.12.
As explained earlier, The FIFORESET block incorporates the logic to generate the specific reset
requirement of external FIFO used in the design. This block incorporate a scan chain with signals
SCE and SCI as scan chain enable and scan input signal as Inputs and signal fiforeset also works
as scan output for this scan chain in the scan mode.
The FIFOWRITE block implements logic for writing the ADC_Data (19 bits) to the external
FIFO with help of write enable signal WRTEN. The data is written to the FIFO on serial bit
signal fifo_serdata. The data is output on the negative edge of the CLK_RXTX clock as
fifo_serdata signal is going to the outside world hence it is logical to output the data on the
negative edge which will be detected by the FIFO on the Positive edge of CLK_RXTX clock.
34
Figure 2.12 Sub Block diagram of Memory Interface Logic
The FIFOREAD block detects the user request to read the data from FIFO on Send_Data signal
and generates read enable signal RDEN for external FIFO so that FIFO can output serial data to
the Wireless Transmitter to send the data to the base station user. It also generates the
fifodata_rdy signal to wireless transmitter logic so that it knows the start and end of data
reception from external FIFO. The read clock and the write clock of the external FIFO are same
as CLK_RXTX clock.
These two blocks are connected in another scan chain, different from FIFORESET block scan
chain, with signals SCE and SCI as scan chain enable and scan input signals. The output signal
WRTEN also works as scan output signal in the test mode.
35
Chapter 3
ASIC Design and Pre-silicon verification
Results
The ASIC was fabricated by MOSIS AMI 0.5µm technology (C5 process run) [8]. Standard
ASIC design methodology is being followed for the design. The following section describes the
various steps taken during the design phase. Section 3.1 explains the details of the manufacturing
process selected. Section 3.2 deals with the ASIC design methodology followed in the control
circuit design. Section 3.3 illustrates the results of various pre-silicon simulations at module level
and full chip level.
3.1 Target technology process
The ASIC was fabricated by MOSIS under using the AMI 0.5 µm technology process. AMI
0.5µm is a non-silicided CMOS process that supports 3 metal layers (M1, M2, M3), 2 poly
layers [1]. It also supports stacked contacts and is suitable for 5V applications. This process
supports the MOSIS scalable CMOS (SCMOS) design rules [9]. MOSIS Scalable CMOS
consists of design rules, which gives a flexibility to implement a nearly process and length
independent layout design to many CMOS fabrication processes available on MOSIS foundry.
The designer works in the abstract layers and length unit ("λ"). The designer then selects the
feature size ("λ") and process for his design to be fabricated in. MOSIS integrates the SCMOS
design rules for that process [9]. This makes the design process independent of process. We have
36
selected the submicron SCMOS design rules SCMOS_SUBM with lambda equals 0.3 µm and
feature size of 0.6 µm. The selection was based on the following reasons:
1. Standard cell library and the Pad frame for AMI 0.5µm is available from Oklahoma State
University (OSU) [10].
2. All the standard library files, VHDL/Verilog models and the layout files are available for
the synthesis and Place and route tools used in Design flow.
3. In Physical VLSI Design coursework, we fabricated the chip under the same process
successfully.
3.2 ASIC DESIGN FLOW
The ASIC Design flow used in this design is slightly modified as per the project requirements.
The industry standard ASIC Design flow consists of two phases: Logic Design phase or Frontend and Physical Design phase or Back-end. The front end design work includes design
specification using a hardware description language, behavioral simulation, synthesis, scan chain
insertion and gate level simulation etc. The back-end design converts the netlist received from
front end design to a physical layout. It comprises of Floor Planning, Place & Route, DRC
(Design Rule Check) Verification, and Dynamic Timing Analysis using IRSIM/SPICE. The
detailed flow chart of the design methodology is shown in figure 3.1. Each of these phases serves
a different purpose and requires a unique tool. Each of them is briefly described in the next
sections.
3.2.1 Engineering Specification
This step creates an architecture document of the ASIC from the user requirements. This consists
of rough analysis of the ASIC and division of the ASIC in smaller modules. The complete
system is divided into a smaller blocks using divide and conquer approach and then the rough
37
Figure 3.1 ASIC Design Flow
block connections are made. Lower level design details as bus width, number of signals etc are
also fixed here.
3.2.2 Design Entry
The purpose of this step is to convert the description of the ASIC from the engineering
specification into a format that can be understood by various tools for creating actual hardware.
This is normally done by schematic capture or by using HDLs (Hardware description languages).
38
Schematic Capture is essentially a drawing with various gates which are connected together.
HDLs are most frequently used method for design entry and it provides the flexibility to the
designer to start implementing a design at a higher abstract level, making the step independent of
the technology process used later. This method is also called RTL (Register Transfer Level)
design. Generally, Verilog HDL or VHDL is used as a preferred language for writing the RTL
code. We have used VHDL as the main HDL for writing the design. The RTL code of each of
the modules mentioned in the previous chapters has been written in VHDL. Verilog HDL was
also used for writing test bench for Gate Level Simulation.
3.2.3 RTL Simulation
The aim of RTL Simulation is to verify the functionality of each of the modules designed using
VHDL in the last phase. The requirement is to design a test bench which creates different test
vectors or stimulus to be applied to the DUT (Design under test). These test vectors, along with
the actual design are read into the simulator. The simulator then calculates the output vectors.
These results are then checked and compared with the expected results. This is done either by
manual inspection of with score-boarding. If there is a match in the output vectors and the
expected results then the simulation is assumed to be passed. If an output does not match with
the expected value then the design fails and the design changed to take care of the failed case.
The simulation at this level is usually technology independent. There are various simulators
available for this kind of simulation. We used ModelSim and Synopsys VCS for RTL simulation.
This is also called behavioral simulation. Generally, no timing is verified in this type of
simulation. The typical RTL simulation process is shown in the figure 3.2
39
Figure 3.2 Typical simulation process
3.2.4 RTL Synthesis
Once the Simulation process completes, the designer has a working HDL code that describes the
design functionally. This RTL code is then converted into the actual hardware (in terms of
Gates). This is done in the RTL synthesis step. RTL synthesis converts the HDL description of
the design into technology specific logic circuits. Usually ASIC vendors provide a technology
library (i.e. Standard Cell library) that provides the definitions of logic circuits, input-output
delays, physical layouts, Capacitances, Area related information. The synthesis tool converts the
RTL design into the gate level models and then it checks the technology library to find a match
between the required gates and the gates included in the standard library. The synthesis tool then
uses the mapped gates into the design and this process repeats for all the lines in the HDL code.
Generally designed provides constraints like power, timing and area. The gates selected by the
tool are determined by the constraints provided by the designer. The Synthesis process is as
shown in Figure 3.3. [11]
40
Figure 3.3 Logic Synthesis process
Synthesis tool takes information from Standard Cell Library, the RTL code of the design and the
design constraints and produce a technology dependent Gate level netlist. The Synopsys Design
Compiler (DC) was used for synthesis of this design. DC is widely used across all the
semiconductor industry for synthesis. A script was written and executed, which contains all the
Design compiler tool commands for synthesis. The various steps and commands were followed
from reference [12]
3.2.5 Gate Level Simulation
The new ASIC design flow usually makes this phase optional due to the inclusion of Static
timing Analysis phase in the new ASIC design flows. Still this phase provides a good idea about
the timing and the ‘feel-good’ factor about the design. Gate-level simulation provides the initial
simulation of chip and several modeling issues usually get caught here [13]. GLS is also very
helpful in simulating reset behavior of design and bring up sequences. It takes as input a gate
level netlist created by the synthesis process, a Standard cell library. All the logic circuits in the
41
netlist incorporate some timing delay as specified in the library file. The same test vectors are
used as stimulus as were used for RTL simulation. Synopsys VCS was used for GLS. For our
design a significant number of RTL coding errors were caught during the GLS phase. This is
understandable because there are constructs in HDL languages that work fine with simulation but
are not synthesizable.
3.2.6 Test Logic Insertion
Test Logic insertion is a method to make chip more testable by inserting more logic in the design
[7]. This process is also called Design for testability (DFT). DFT is very important part of the
chip design process. DFT improve the controllability and observability factors of the internal
design nodes. DFT targets a certain part of the logic in the complete design and tests its
functionality.
Internal scan is most widely used DFT technique. In this scheme, all the sequential elements (i.e.
every Flip Flop and latch in the circuit) are connected into a series of shift registers in test mode.
As a result, test data can be scanned into the registers through the scan-in port of the chip and the
test results can be scanned out through the scan-out port on the system clock. Hence the complex
nature of the circuit can be tested in terms of much smaller combinational logic between
sequential elements. To achieve this goal, all the flip flops or latches of the design have to be
converted into the scannable flip flops or latches. This is done by adding a Multiplexer at the
input of the each sequential logic. The first input of the MUX is connected to previous output
and the other input is connected to the previous sequential element output. The select pin of
MUX is the test mode pin. In this configuration, when the test mode pin is enabled, all the
sequential elements get connected to form a shift register. When test mode is not enabled, the
circuit behaves in the normal mode. An example of internal scan is shown in Figure 3.4 [14] [18]
42
Figure 3.4 Scan chain Insertion
Internal scan chains can be of two types depending on the amount of fault coverage covered by
them. Full internal scan ensures 100% fault coverage and in this type of testing all the sequential
elements is part of the scannable shift registers in test mode. In Partial internal scan, only a
selected number of sequential elements are part of the scannable shift registers. This might
provide less than 100% fault coverage but has an advantage over the former in terms of the
silicon area.
In our design, we have followed the test synthesis done by the tool. The test logic was part of the
RTL design at block level and then extended to the chip level. The design is synthesized again
and Gate level simulation is run again with the same test vectors as well as tests with test scan
mode enable. The simulation is verified again to make sure added logic doesn’t violate any
functionality and basic timing.
3.2.7 Floorplanning, Place & Route
The gate level netlist received after the test synthesis phase is in terms of virtual gates. To
receive the actual gates and the actual placement of wires to connect them together, the physical
design phase comes into the picture. Initial Floorplanning is done to decide the location of
43
various design blocks/modules in the actual pad frame core area available. This design is
restricted to a core area of 5000λ by 5000λ. The Memory block netlist is synthesized alone while
the Control block interface module is synthesized as single netlist file. The complete floorplan,
considering the analog modules and control/memory modules was first decided. The next step is
the placement and routing of physical logic blocks. We have used Cadence Encounter as the tool
for P & R.
The Gate level netlist is processed by Encounter which places the standard cells onto the region
specified by the constraints. The routing tool then routes the metal wires to connect the logic
gates. If the tool is unable to route because of the high net congestion, either a different floorplan
is needed or the initial constraints must be modified. The basic flow of the Encounter tool is as
illustrated in Figure 3.5 [15] [16]
The various steps in the Encounter flow are as described briefly.
Initial set up, Read the design
During this phase the LEF (Library Exchange Format) file from the Standard cell Library is
imported into the tool. LEF file is the master file which is used by Encounter throughout the
Place and Route process. It contains information about the DRC rules, physical area, pin
information of cells etc. Once the tool is set-up, the design netlist (verilog format) is read into the
tool.
44
Figure 3.5 Cadence Encounter flow
Floorplan
In the size of the core is selected in terms of Aspect Ratio (Height/Width) as per the constraint of
the final ASIC core area. Also cell utilization is selected as 80%-90%. This specifies the
congestion of cells placed in the core. A low value in this field is specified for low effort routing
by the tool. The distance of I/O pins from the core is also specified in this phase.
I/O Pin Placement
In this phase, the pins of the design are placed on the periphery of the chip according to the
requirement of the design. Based on the external I/O pads, the constraint on the I/O pins of the
design is set. The I/O pins can also be specifies with specific metal layer in this mode.
45
Standard Cell placement
One of the I/O placements is decided, the standard cells are placed. The filler cells are placed in
the gap between the standard cells to maintain the continuity of n-wells and power supply rails.
Power rails routing
The next step is to route the Vdd and Gnd rails in the design. Power nets are routed which
connects all the standard cells Vdd and Gnd rails.
Signal net routing
The Signal net routing is done next. We selected nanoroute out of the various options available
for routing. All of the available 3 metal levels (as supported by AMI 0.5µm process) were used
for the signal routing. Different constraints have to be selected if the tool is unable to perform
DRC free routing. The tool provides a report if it is not able to perform the routing and mentions
the number the DRC errors in routing performed. If the number of errors is few then manual
changes can be done in the layout to correct them.
Save and export to GDS-II
Once routing is done without any DRC, the tool provides options to check antenna rule
violations, connectivity checks, metal percentage check, minimum size checks etc. Once these
checks are done, the layout is then saved to GDS-II format which is a standard format for layout
information.
3.2.8 GDS-II to mag
The layout editor tool used in the thesis work was Magic. The GDS-II format layout was
converted into the compatible magic layout format using the script (osucells_enc2magic)
available as part of OSU standard cell library package. This script converts and saves the GDS-II
format to magic format and then scales the final magic file to AMI 0.5µm process.
46
3.2.9 DRC and Extraction
The magic layout file output from the previous phase is first checked for Design Rule Check
(DRC) errors for AMI 0.5µm process. Magic layout editor does the DRC check. MOSIS
submicron SCMOS Design rule check (SCN3ME_SUBM.30) with lambda as 0.30µm was used
for DRC errors.
The layout is then extracted using the commands available in magic and then converted into
SPICE and IRSIM [17] format for functional simulation of the final physical layout. The SPICE
and IRSIM netlists are transistor level netlists with MOS transistors, resistors and capacitances.
3.2.10 SPICE/IRSIM Simulation
The SPICE or IRSIM netlists available in the last step are the transistor level netlists of the actual
design. The SPICE simulation provides accurate simulation results as it uses accurate device
models and parameters though SPICE simulations take large simulation time and CPU usage.
Hence we used SPICE simulations to verify the functionality and timing of individual blocks
rather than the complete chip. The simulations were done with the worst case input patterns to
verify timing. SPICE is more frequently used for Analog modules simulations.
As most of the thesis work is digital logic design, IRSIM simulations are used more frequently
for logic circuit simulations. IRSIM is an event driven switch level simulator with less accuracy
than SPICE simulations. Although IRSIM simulations take much less time than SPICE
simulations while providing reliable analysis of logic circuit behavior. At the full chip level,
IRSIM simulations were done and the same test vectors were used as for GLS to verify
functionality. The Results of SPICE and IRSIM simulations are discussed in the next chapter.
47
3.2.11 PADS insertion and final simulation
The next step is to integrate the Control/Memory block layouts with the Sample/Hold and ADC
block layouts. This analog work is part of the thesis work carried out by Mr Ravi Alla [19] under
the guidance of Prof R. Beyette Jr. The common routing (Clocks, digital data from ADC to
memory module etc) for both the blocks were done manually. Once the complete system is
integrated, the next task is to insert the complete design into a pad frame. The standard pad frame
provided by OSU library is modified for our mixed signal ASIC requirements. The analog pads
and digital pads were different. It was decided to keep them separate from each other in the
actual frame. The top half portion of the core area is taken by Analog blocks and bottom half is
taken by control block and memory interface module. The pad frame core and number of pins
were also modified to our requirements. Earlier the decision was to separate the power supplies
for digital and analog block due to noise effects especially on analog circuits. But later we
decided to keep single power supplies for both the blocks. The final SPICE/IRSIM simulations
with pad frame were done as mentioned in an earlier step. Once this was verified, chip was ready
for tape out. To accomplish tape our, the layout was converted from magic to CIF (Caltech
Intermediate Format). The CIF file is then flattened (without any hierarchy) and simulated once
again for any process errors. The chip layout is then sent to MOSIS for fabrication. The pad
frame design, pin details and final simulations are part of discussion in next chapter.
3.2.12 Tape Out
There are a few checks that need to be performed (as specified by MOSIS) before converting the
final magic layout to the CIF layout. These checks are mainly the minimum poly density and the
minimum metal density checks. The poly density can be increased by adding a continuous ring
of poly between the core logic and the Pads. The power supply rails were run on this poly ring.
48
The layout was then converted to CIF format. The CIF file contains a CMFP abstract layer which
is to be removed by command “erase m1p” on magic prompt. The final CIF file is now ready to
be sent to MOSIS foundry for fabrication. We ordered the packaging to be 40 pin DIP package.
3.3 Gate Level Simulation Results
After Synthesis, Gate level simulations (GLS) were done as part of ASIC design flow as
mentioned in section 3.2.5 earlier. GLS was done first on block level and then later extended to
Full chip level. The sections below describe the results of block level GLS.
3.3.1 Block level GLS
The various blocks in the control block interface and memory interface are simulated with the
gate models of standard cell library for AMI 0.5 µm technology. Simulations for each block were
done with a number of test vectors. The test vector mentioned in any of the next simulation
graphs are selected at random.
3.3.1.1 Control block interface GLS
The control block interface design is previously discussed in chapter 2. Figure 2.7 describes the
block level diagram for the block. The GLS for each of the blocks below are mentioned with the
discussion on the test patterns injected. All the waveforms below are for the test patterns injected
Figure 3.6 SEQDET block Gate Level Simulation
49
Figure 3.7 PULSE_TO_HIGH block Gate Level Simulation
in normal mode of operation (SCE = ‘0’).
SEQDET block GLS
The timing diagram in Figure 3.6 shows the GLS of the SEQDET block. In normal mode (SCE0
= ‘0’), after power-on reset sequence on RST pin bits patterns on input pin X are sent. When
Z_high input signal is active low, a bit pattern ‘1011’ on signal X asserts low on output reset and
in next clock output Z is asserted high. If similar bit patters ‘1011’ is injected on input pin X
while Z_high is active high then nothing happens and bit patterns is accepted as it is.
PULSE_TO_HIGH block GLS
Figure 3.7 depicts the Gate level simulation of PULSE_TO_HIGH block. The reset signal in this
block is the one which is internally generated in the previous block. As soon as the Z signal is
asserted high for one clock then Z_high is asserted high on next clock and remain asserted until
input ctrl_start is asserted later by COUNT_CFGBITS block.
COUNT_CFGBITS block GLS
As shown in Figure 3.8, the input signal Z_high is made high and the counting of configuration
programming bits starts on each positive edge of CLK_RXTX clock. This count is shown as an
50
Figure 3.8 COUNT_CFGBITS block Gate Level Simulation
internal counter vector cnt[7:0]. As soon as cnt[7:0] reaches ‘10110101” i.e. decimal equivalent
of 183, the ctrl_start signal is asserted for one clock pulse. The output signal ctrl_start_high is
also asserted high at the same point. The cnt[7:0] stops counting until the next set of
configuration programming is done by the user.
SYNCHRONIZER block GLS
This block converts the ctrl_start signal from high frequency clock (CLK_RXTX) to low
frequency domain clock ctrl_start_new (CLK_CTRL). As soon as ctrl_start_high signal is
asserted on the CLK_RXTX clock, the first positive clock edge of CLK_CTRL after it asserts
ctrl_start_new pulse. This is shown in the figure 3.9. This is a typical clock frequency domain
Figure 3.9 SYNCHRONIZER block Gate Level Simulation
51
Figure 3.10 SYNCHRONIZER block schematic
crossing problem. The circuit which is used in this conversion is as mentioned below in Figure
3.10.
PC block GLS
The ctrl_start pulse in PC block, as shown in Figure 3.11 is logical OR of ctrl_start_new pulse
output from SYNCHRONIZER block and ctrl_start1 pulse output from MUX_CTRL block. As
soon as ctrl_start pulse is asserted high, the ctrl[3:0] increases by 1 and points to the next
configuration register. ctrl[3:0 ]= ‘0001’ represents the first configuration register and ‘1000’
represents the 8th configuration register. Once ctrl[3:0] reaches ‘1000’ i.e. the last configuration
register of value 8, it jumps back to serve first configuration register. Output signal
ctrl_start_muxctrl is one clock delay output of ctrl_start input on clock CLK_CTRL.
Figure 3.11 PC block Gate Level Simulation
52
Figure 3.12 CFG PROG block Gate Level Simulation
CFG_PROG block GLS
Z_high signal, as mentioned previously remains high for 184 clock pulses of CLK_RXTX clock
and serves as Gated clock enable signal (GATED_CLK) for the configuration programming shift
register of 184 bits, as shown in Figure 3.12. Internal signal GATED_CLOCK is enabled only till
Z_high is asserted high. The serial input X of shift register is loaded in shift register
The
Top_reg[183:0].
serial
bits
on
signal
inputted
X
are
000000000000000111110010000000001111111110001100000000110000000000000000000000
000000001100110000000000000000111110100000000000000011000011000000000000100110
0111000000000000001001100111.
Hence
the
Top_reg[183:0]
is
loaded
with
value
(in
hex
format)
0001F200FF8C030000000330000FA00030C00267000267. Once Z_high becomes low i.e.
GATED_CLK is disabled.
MUX block GLS
MUX block separates the different configuration registers from Top_reg[183:0] based on the
ctrl[3:0] input. In Figure 3.13, The Top_reg[183:0] is asserted with value as mentioned in the
53
Figure 3.13 MUX block Gate Level Simulation
previous block and ctrl[3:0] input is asserted from “0000” to “1000”. The corresponding values
of the CtrlCounter[19:0] and muxctrl[2:0] outputs were checked manually.
MUX_CTRL block GLS
In Figure 3.14, the ctrl_start signal is same as the signal ctrl_start_muxctrl output signal from
PC block. The CtrlCounter[19:0] value input is loaded into tempcounter (internal counter) on
assertion on input ctrl_start and is decremented on every positive edge of CLK_CTRL clock. As
soon as the counter reaches zero, start_SH signal (same as signal ctrl_start1) is asserted. In the
next clock start_ADC signal is asserted.
Figure 3.14 MUX CTRL block Gate Level Simulation
54
Figure 3.15 HOLD_MUXCTRL block Gate Level Simulation
HOLD_MUXCTRL block GLS
Input muxctrl[2:0] is loaded into muxctrl_fifo[2:0] output on every positive edge of start_SH
signal as shown in Figure 3.15.
3.3.1.2 Memory Interface Block GLS
The following sections describe circuit simulation results for the blocks that comprise the
memory interface block.
FIFORESET block GLS
The reset input is extended to 4 pulses of CLK_RXTX clock on output fiforeset output as shown
in waveform on Figure 3.16.
Figure 3.16 FIFORESET block Gate Level Simulation
55
Figure 3.17 FIFOREAD block Gate Level Simulation
FIFOREAD block GLS
As soon as the user wants to read the data (assertion of input rxtx_send_data for one clock
CLK_RXTX), fifodata_rdy signal is asserted on the next clock. Also, the RDEN signal is asserted
active high and remains high for next 19 cycles of the CLK_RXTX clock. Another pulse on
fifodata_rdy signal is asserted after this. Figure 3.17 depicts the waveform of FIFOREAD block.
FIFOWRITE block GLS
As shown in Figure 3.18, on reception of ADC_Data and Data_Valid signals from ADC analog
Figure 3.18 FIFOWRITE block Gate Level Simulation
56
block in the design, the WRTEN signal is asserted high and remains high for next 19 clocks of
CLK_RXTX clock. During these 19 clock pulses, on every negative edge of CLK_RXTX, serial
data is outputted from ADC_Data on fifo_serdata output signal. ADC_Data input of 55555 is
represented by 1010101010101010101 on fifo_serdata output.
57
Chapter 4
Layouts and Results
The previous chapter explained the ASIC Design flow and the Gate level Simulation results
which were part of Logic Design phase in ASIC Design methodology. This chapter covers to
Physical Design phase and discusses the actual layout as created by Place and Route phase. The
tool used was Cadence Encounter. This chapter also discusses the circuit simulation results
(IRSIM results) of the complete Control circuit and memory interface block. Also Analog
Figure 4.1 Analog MUX decoder (3:8) logic layout
Figure 4.2 Analog MUX Transmission Gate layout
58
multiplexer SPICE simulation results are discussed. It also discusses the pad frame design and
the final ASIC layout after pad frame insertion. In last section, lab results of actual fabricated
chip are discussed as part of the design evaluation.
4.1 Analog Multiplexer layout and its Spice simulation results
The analog multiplexer is discussed in Section 2.2. Figure 4.1 shows the layout of 3:8 decoder
of Analog Multiplexer and figure 4.2 shows the Transmission gate logic of the Analog
Multiplexer. In figure 4.1, The 3 bit muxctrl input is injected from the bottom and 8 enables
output signals of each Transmission Gate are collected from the top.
In figure 4.2, the 8 Transmission gates are shown, each enable signals of there transmission gates
are connected to one of the 8 outputs of decoder logic. As shown in figure 4.2, the layout of the
Figure 4.3 Analog MUX SPICE simulation result
* The Red, Yellow and Purple digital signal in the range of 0-5V represents the 3 bits Sensor ID and the other
continuously changing signals represent the 8 different Analog inputs. The Dark Black line represents the final
analog MUX output based on the sensor ID.
59
Transmission Gate transistors is done using a multi fingered layout technique. The size of
NMOS and PMOS transistors is chosen to be L= 120λ and W= 2 λ.
Figure 4.3 shows the simulation waveform of the Analog Multiplexer. Inputs a, b and c are the 3
bit input connected to 3 bit muxctrl signal. The signal in1 to in8 are the 8 analog inputs coming
from external sensor chip which signifies the analog voltage corresponding to the concentration
of the pollutants in consideration. Each of these 8 inputs was varied randomly in 0V to 5V range.
Inputs ‘c’, ‘b’ and ‘a’ are changed in binary fashion from 000 to 111 in every 1ms time window
(Input a being LSB). The output is as shown by the dark black line which follows the
corresponding input in the window decided by the value of a, b and c. (cba=000 implies in1,
cba=001 implies in2 and so on). The error due to the transmission gate drop is in terms of 10-4
volts and can be corrected at the software at the user end (assuming uniform error).
4.2 Control Block Interface layout and IRSIM simulation results
The Figure 4.4 represents the complete layout of the Control Block Interface as done by the
Cadence Encounter Place and Route tool. The gate level netlists of each of the blocks as
Figure 4.4 Control Block layout
60
mentioned in figure 2.7 were integrated into a single netlist. This final netlist is then imported
into Cadence Encounter which takes care of the layout with in the given area constraints.
The size of the Control Block layout is 1400λ x 3700λ. The pins were routed such that the
minimum manual routing needs to be done while connecting the analog circuitry with this block
at the time of mixed signal integration. This block is then extracted into IRSIM netlist and
simulated. Figure 4.5 and 4.6 shows the complete system level waveform of the Control Block
Interface. In figure 4.5, after power-on reset assertion on RST signal, the sequence “1011” is
detected on serial bit input signal X and internal reset is generated which is used as the main reset
for the other blocks in the design. The GATED_CLK for the 184 bit shift register, used for
storing configuration programming data, becomes active for next 184 clocks of CLK_RXTX
clock and the 184 bits input on signal X during this time is then stored in the shift register. Once
the programming completes, the ctrl_start signal is asserted high for one CLK_RXTX clock to
indicate the receiver-transmitter circuitry for reception of 184 valid configuration bit data.
On the very next CLK_CTRL clock from the ctrl_start signal assertion, T_CTRL (same as
ctrl[3:0] in previous chapters) increments to 0001 and points to the first 23 bit configuration
register. T_CTRL signal then selects the corresponding bits from the shift register and stores the
20 bit counter value programmed into T_CTLCOUNT (same as CtrlCounter[19:0] in previous
chapters) and 3 bits sensor ID into T_MUXCTRL (same as muxctrl[2:0] in previous chapters)
vector. T_MUXCTRL signal drives the Analog Multiplexer decoder inputs and hence enables the
path between ADC and the selected Sensor. T_CTRLCOUNT value decrement on every positive
edge of CLK_CTRL clock and when it becomes zero, start_SH is asserted high which enables the
sample and hold circuit. On the next clock, start_ADC is asserted, which enables the Analog to
Digital multiplexer circuitry.
61
Figure 4.5 Complete control block IRSIM simulation (Normal mode)
62
Figure 4.6 Complete control block IRSIM simulation (continued)
63
The negative edge of start_SH signal holds the value sampled by analog multiplexer for the
computation for ADC. ADC then gets enabled in start_ADC signal and converts this hold analog
voltage into 16 bits binary digital format and sends back to memory block interface with a
Data_Valid signal. T_MUXCTRL_FIFO holds the previous value of T_MUXCTRL on every
positive edge of start_SH signal as T_MUXCTRL changes after this and we need to store the
previous value. The previous value i.e. T_MUXCTRL_FIFO is appended to the 16 bit digital data
sent by the ADC to memory interface. This is done so as to easier data processing by software at
the user end. Signal fiforeset is asserted for 4 CLK_RXTX clocks as soon as 1011 is detected on
signal X except the time when configuration programming data is being written. This signal
resets the external FIFO. start_ADC also triggers the T_CTRL to increment and the cycle repeats
for the next configuration register. Once all the 8 configuration registers are served i.e. T_CTRL
is reached “1000” (8th configuration register), it points back to “0001” (1st configuration register)
The figure 4.6 shows the situation when the user wants to reload another set of configuration
programming data which system is in operation with previous configuration. The detection of
“1011” on signal X triggers this to happen and as soon as this sequence is detected, all the blocks
in the system gets reset and next set of configuration data is loaded in shift register on next 184
CLK_RXTX clocks. The fiforeset signal is also asserted low and external FIFO is also reset.
Figure 4.7 Memory Interface module layout
64
Hence the system does not hold the previous data once the new set of configuration is written
into the shift register.
4.3 Memory Interface Block layout and IRSIM simulation results
Figure 4.7 shows the layout of the Memory Interface logic explained previously in figure 2.12. It
also integrates Analog multiplexer decoder layout as shown in upper left hand corner block in
Figure 4.8 Memory Interface Block IRSIM simulation (Normal mode)
65
the figure. The Layout size is 3900λ x 500λ. The IRSIM simulation of memory interface block is
as shown in figure 4.8 with the waveforms of FIFOREAD and FIFOWRITE blocks. The timing
waveform of FIFORESET block is already covered in figure 4.3 and 4.5.
The FIFO chosen in the design is 20MHz 1-bit synchronous FIFO from Texas Instruments. ADC
sends the 16 bit ADC_Data output with Data_Valid signal. At the next clock of Data_Valid
signal, WRTEN is asserted for next 19 clocks of CLK_RXTX signal during which the 19 bit data
(16 bit ADC_Data appended with 3 bits of T_MUXCTRL_FIFO) is outputted 1-bit serially on
negative edge of CLK_RXTX signal. This data is written to the external FIFO. WRTEN is the
control signal for the FIFO.
When user wants to read the data, rxtx_send_data is asserted by user for one clock and in the
next clock the fifodata_rdy signal is asserted for one clock pulse to indicate the receivertransmitter interface the transmission of digital data from FIFO. RDEN signal is also asserted at
the same time and is kept asserted for next 19 clock cycles. During this time, on each negative
edge of CLK_RXTX signal, the 19 bit data from FIFO is outputted serially to receiver-transmitter
block which will send the data through the wireless interface to the user end where software will
decode the data and back process it to convert it into the approximate analog value. The
fifodata_rdy signal is asserted once the 19 bit data transmission from FIFO is finished.
4.4 Complete layout of Digital Interface (Both Control and Memory
modules together)
Figure 4.9 represents the complete layout of the design without the pad frame. The Control and
Memory Interfaces were integrated manually and clocks were also routed manually with
sufficient Clock buffers. The thick black line in between the layout shows the boundary between
the Control block interface and the Memory interface.
66
Figure 4.9 Complete Digital Interface layout
Figure 4.10 Magic Layout of Custom PAD frame for mixed signal ASIC (40 Pins)
4.5 Pad Frame Design
The mixed signal ASIC was fabricated with AMI 0.5µm technology and packaged in a 40 pin
DIP packaging. There is a standard pad frame available from OSU standard cell library but the
67
Figure 4.11 Complete ASIC with PAD frame
core area in it was limited to 3000λ x 3000 λ. As our ASIC requires more area than this, we
decided to modify the PAD Frame for achieving core area of 5000 λ x 5000 λ. For this we kept
pad space between the two pads. For Analog signals we chose PadAref pads and for digital pins
we utilized PadBiDir pads. PadAref are the bidirectional pads specifically good for using analog
signals. Though we used pin # 23 i.e. start signal (mentioned in table 4.1), as PadAref pad so that
we can use it as bidirectional signal.
There are 17 PadAref and 21 PadBiDir PADS. 2 pads for power supply were used. We tried to
make the pad frame as symmetric as possible for ease of bonding diagram. The upper half of
core area was used by Analog circuitry and lower half of core area was used by Digital circuitry.
Figure 4.10 shows the custom Pad frame created for our chip.
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4.6 Pad to Pad testing
After the custom pad frame design, the next task is to integrate the analog and digital circuitry in
the pad. First the complete digital circuit was placed inside the pad frame and then in the rest of
the core area, analog circuits were placed. Analog circuitry includes the Analog multiplexer, the
Sample and Hold, the ADC and the Capacitor for the Sample and Hold. The connections were
made from the ports of the core logic to external pads. The manual routing was completed to
connect the analog and digital blocks as well to route the global signals. Extra care was taken
while routing analog signals so that high frequency clocks signal routing does not induce any
noise problems in sensitive analog signals. The entire chip is then flattened, verified for DRC
and then extracted. IRSIM and SPICE simulations were done for functional verification of the
entire logic with pads. Figure 4.11 shows the complete layout of the chip with pad frame. The
yellow area in the centre of core area is the capacitance for sample and hold circuit. Simulation
results were same as earlier mentioned in figure 4.5, 4.6 and 4.7.
4.7 Pin assignment and signal description
Figure 4.12 shows the pin assignment of the ASIC and table 4.1 shows the I/O Pins name and
their functions of in situ monitoring ASIC.
Figure 4.12 Pin assignment of ASIC
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Pin #
Signal Name
I/O
1
CLK_RXTX
I
2
3
4
5
6
7
8
9
10
11
12-19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Functionality
20 MHz clock for configuration data write and
memory interface (FIFO) block
Counter_clk
I
4MHz clock for ADC circuitry
Data_Valid
O
Data Valid signal output when ADC circuitry
outputs 16 bit valid ADC_Data
step
O
Analog control signal for Current Mirror circuit
amuxout
O
Test signal for Analog MUX output
Comp_buffout
O
Test signal for comparator output
Nbias
I
Bias voltage for comparator circuit (1.9V)
INP
I
Input for bypassing the MUX, Test signal
Control_inp
I
Bias voltage for current mirror (1.2V)
Capout
O
External Capacitor Output (1µF)
Reset
I
Analog control signal for current mirror
Input8-Input1
I
Sensor input signals
GND
I
Ground
SCE
I
Scan chain Enable signal (SCE = 1, Normal mode,
SCE = 0 test mode)
SCI
I
Scan chain input signal
start
O
Same as start_ADC signal
RST
I
External Power On Reset
Fiforeset
O
Reset to External FIFO
ctrl_start
O
Signal to indicate receiver transmitter system that
184 bit configuration register data is accepted by
control block.
CLK_CTRL
I
1KHz clock used for down counter in Control
block.
SCO0
O
Scan chain 0 Output
SCO1
O
Scan chain 1 Output
SCO3
O
Scan chain 3 Output
VDD
I
Power Supply
X
I
Serial Input received from receiver transmitter
system
WRTEN
O
Write Enable signal to external FIFO
fifo_serdata
O
Serial bit write data to FIFO
rxtx_send_data
I
Data send request signal from user to memory
interface receiver transmitter system that data is
ready to be sent.
Fifodata_rdy
O
Data ready signal to indicate
RDEN
O
Read Enable signal to external FIFO
dataout[15]
O
MSB of ADC data
scanout_control
O
Scan chain output of ADC digital circuitry
scanout_counter
O
Scan chain output of ADC digital circuitry
Table 4.1 Top level pin description of the ASIC
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4.8 Post Fabrication testing of in situ ASIC
The bonding diagram was generated by MOSIS by default and is mentioned in figure 4.13. The
fabricated ASIC is as shown in figure 4.14. The in situ ASIC was tested in VLSI Lab, University
of Cincinnati using HP Logic Analyzer and other functions generators. The chip was mounted on
the bread board and test patterns were generated using pattern generator of logic analyzer and
outputs were verified using timing analyzer. IRSIM input vectors used for testing the final layout
was used again in the suitable format to generate test patterns for the ASIC.
The testing was done as a stone alone designs first. The Digital control interface and the analog
circuitry were tested separately. The First testing was done with test mode and injecting
alternating bit patterns in Scan chains and checked the same patterns reception at scan chains
outputs. After this the chip was operated in Normal mode to check the functionality. Various test
patterns were injected to check the control logic and memory interface logic functionality. All
the tests were run successfully and ASIC is found to be working in excellent condition.
Figure 4.13 Bonding Diagram as created by MOSIS for DIP-40 Packaging
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Figure 4.14 The fabricated ASIC (40 pin DIP package)
Maximum frequency of 100MHz was achieved for control logic block. The lab testing results of
the Digital control logic interface are shown in Figures 4.15, 4.16 and 4.17. The figure 4.15
represents the detection of initial sequence of 1011 as soon as the signal RST is disserted. This is
seen on FIFRST signal (same as fiforeset signal) which is inverted version of Z_high signal.
Figure 4.15 Lab testing of ASIC
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Figure 4.16 Lab testing of ASIC (continued)
Figure 4.16 show the completion of the configuration registers programming. This is indicated
by the output CTLSTR (same as ctrl_start signal) asserted high for one clock cycle.
Figure 4.17 Lab testing of ASIC (continued)
73
Figure 4.17 represents the START (same as start_SH signal) signal generation as soon as the
counter expires for the currently executed configuration register. This signal enables the sample
and hold circuitry of the analog interface and on the next clock the Analog to digital converter
starts its operation. The analog circuitry was tested as stand alone. Later, both the tests were
combined at the full chip level and the complete ASIC was tested. The testing was done under
the constraints of Lab equipments and Lab conditions. The Chip was found to be working with
expected result.
The ASIC was then integrated with Wireless interface design on bread board and was tested with
the complete system as a whole. Various input patterns were injected to program the ASIC from
Wireless interface and the converted digital values were collected considering system as whole.
The System testing block diagram is as shown in figure 4.18.
For the testing of the ASIC, first the configuration registers has programmed. In this test
configuration, user sends 188 bits data (“1011” followed by 184 bits of programming data) as
mentioned below.
101100011110000111100001000001111000011110000100010101101001011010010101000111
100001111000010011100101101001011010001001010010110100101100110110110100101101
00101011011100001111000011101111
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Figure 4.18 Complete System Block diagram (testing)
Table 4.2 shows the various configuration registers bits format as understand by the logic from
the above mentioned 188 bits. The analog sensors input were set as 1.2V, 2.4V, 3.2V, 2.8V,
1.5V, 3.9V, 4.3V, 1.8V.
75
Configuration
Register #
1
Counter bits (20)
Sensor ID (3)
00011110000111100001 000
Evaluation time
(Minutes)
2
2
00111100001111000010 001
4
3
01011010010110100101 010
6
4
00111100001111000010 011
8
5
10010110100101101000 100
10
6
10100101101001011001 101
11
7
10110100101101001010 110
12
8
11100001111000011101 111
15
Table 4.2 Configuration register bits decoded from the 188 bits sent for programming
the ASIC.
Sensor Voltage
#
(V)
Expected ADC
data
1
1.2
0100010001000101
ADC Data
received by
Control Logic
0100010001001010
Actual ADC Data
Received at the
ASIC pin output
0100010001001010
2
2.4
1000100010001010
1000100010001111
1000100010001111
3
3.2
1011011000001110
1011011000010100
1011011000010100
4
2.8
1001111101001100
1001111101010010
1001111101010010
5
1.5
0101010101010110
0101010101011101
0101010101011101
6
3.9
1101110111100001
1101110111100111
1101110111100111
7
4.3
1111010010100011
1111010010011010
1111010010011010
8
1.8
0110011001101000
0110011001101111
0110011001101111
Table 4.3 Data comparison between the expected ADC data and the actual ADC data.
Table 4.3 shows the comparison of the expected ADC data and actual ADC data received by the
control logic when the data conversion is done by the ADC and Data_Valid signal is asserted.
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This data is found to be the same as the data received at the Chip output. As Control logic
receives the ADC data in a parallel to serial converter circuitry and shift out this data to the
FIFO, no data is found to be corrupted in control logic circuitry. Also this is tested with the help
of scan chains. The Parallel to serial converter circuitry is also checked with scan chain patterns
for any stuck-at-faults.
Hence, the Control Logic Interface and the Memory Interface was found to be working perfectly
as per the design requirements of the system.
The summary of main features of the in situ ASIC is mentioned in Table 4.4.
Parameter
Value
Gate count
Technology
Chip size
Package
Power Supply
Maximum Operating Frequency
4K
AMI 0.5µm SCMOS
6080λ x 6080λ (2.040mm x 2.040mm)
40 Pin DIP
5V VDD and 0V GND
100MHz
Table 4.4 Features of in situ ASIC
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Chapter 5
Conclusions and Future Work
This chapter provides the summary of work done in this thesis work and discusses the important
results achieved. These are mentioned in section 5.1. Section 5.2 deals with the future work.
5.1 Summary
This thesis work carried forward the work done by previous students working under the guidance
of Prof Fred R. Beyette Jr. The previous students were responsible for the design of the Sensor
Chip. This work takes inputs from the Sensor chip and converts it to a digital binary value. The
binary value is then sent to base station user through a wireless communication link. This design
is well suited for in situ monitoring system. There project as a whole was implemented by three
people working in concert. The work presented in this thesis is solely responsible for the control
path design and memory interface design. The other interfaces were Analog Blocks Design and
Wireless Receiver Transmitter Interface design. Control Interface and Memory interface were
designed carefully following the needs of the user.
A mixed signal ASIC was implemented for this system. The chip was fabricated on die area of
2.040mm x 2.040 mm and packaged in 40 Pin DIP. The technology used for fabrication is AMI
0.5 µm (C5 Process). After fabrication, all of the digital control and memory blocks designed as
part of this thesis work were tested successfully as stand alone blocks and found to be working
78
perfectly. The Scan testing was also done as part of the lab testing of final chip and found to be
working good. The complete chip has been tested successfully after fabrication on bread board
with the Wireless receiver/transmitter interface added to it. The maximum frequency for which
the chip was found to be working is 100MHz.
5.2 Future Work
Following are a few suggestions to carry forward this thesis work.
1. The Configuration Programmable registers can be implemented as SRAM cells inside the
ASIC. It might be an interesting idea to keep much smaller SRAM cells than D flip flop
as memory elements.
2. The External FIFO used in the system can be implemented inside the ASIC. The
advantage is lesser off chip communication and less data corruption.
3. The system as a whole should be tested. The Sensor Chip needed to be redesigned from
previous students. Design of a board which contains Actual sensors, sensor chip with in
situ ASIC and wireless system might make it a good exercise.
4. The need of wireless receiver transmitter is optional. Any other transmission protocol
could be tested while keeping the interface signals same.
5. The wireless receiver transmitter and the sensor chip could be integrated in a single die
making it a low noise single chip solution.
79
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