MOSFET Optimization in Deep Submicron Technology for Charge Amplifiers Gianluigi De Geronimo and Paul O’Connor Abstract--The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the minimum channel length and the maximum available power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the Equivalent Noise Charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25µm CMOS technology are reported. 1 I. INTRODUCTION Integrated Circuits (ASICs) can Abe a valuableSpecific solution in front-end electronics for II. THE ENC EQUATION The resolution of a front-end can be measured in terms of Equivalent Noise Charge (ENC) [4-7]. The ENC corresponds to the charge that must be delivered to the front-end in order to achieve a signal to noise ratio equal to the unity. In the following we will assume that the resolution of the front-end is dominated by the noise from the input MOSFET, characterized by a gate length L, a gate width W and a drain current density Jd=Id/W. We will also assume that the front-end implements a time invariant filter with overall pulse response to a charge Q equal to Q·h(t), and characterized by a maximum Q·h(t)|max. PPLICATION radiation sensors. Detection systems with high sensor pixellation can benefit from low power, low parasitics, high front-end channel density, and low cost per channel. In addition the ASICs are characterized by good radiation tolerance [1-3] and can integrate large amount of additional signal processing and functions in analog, mixed-signal and digital domains, offering further advantage in terms of power and real estate. In a properly designed front-end the resolution is limited by the noise from the input transistor. Consequently a relevant phase of the design consists of optimizing the input MOSFET with respect to sensor, interconnects and the specific application. The choice of the polarity (n- or pchannel), size (length L and width W) and operating point (drain current density Jd and drain-to-source voltage Vds) are determinant in achieving the best performance. The optimization process relies on equations, models and parameters that can be strongly dependent on the technology. As deep submicron CMOS technologies are developed and characterized for digital design, the process of optimizing the input MOSFET can become very challenging. This contribution would like to provide the low-noise front-end designers with techniques to keep pace with the rapid evolution of CMOS technology. After a review of the traditional optimization process, the impact of properly modeling the series noise and gate capacitance of the MOSFET is discussed. As an example, the commercial TSMC 0.25µm CMOS technology is characterized and investigated for the best achievable resolution. Input MOSFET v n2 Q Q·h(t) in2 Cin Filter Fig. 1. Schematic of the front-end. The components relevant to the evaluation of the ENC are shown. In Fig. 1 a schematic of the front-end for the evaluation of the ENC is shown. The parallel noise contribution i 2n , characterized by a unilateral power spectral density Sin, is typically related to the sensor leakage current, to its bias circuitry and to the charge amplifier feedback circuitry. In the following we will initially assume a white density Sin=Sp. Then, since this contribution is not related to the input MOSFET, this term will be neglected. The series noise contribution v 2n , characterized by a unilateral power spectral density Svn, is dominated by noise processes in the input MOSFET. In the following we will initially assume a density Svn=Aƒ/ƒ+Sw. The low frequency term, known as 1/ƒ noise, is strongly technology related. The white term is strongly related to the transconductance gm of the MOSFET. The input capacitance Cin includes the sensor capacitance, the feedback capacitance and any parasitic connected to the input node and not dependent on the size (W,L) of the input MOSFET. The gate capacitance Cg includes any term dependent on the size (W and/or L) of the input MOSFET. The ENC can be expressed as follows: 2 This work was supported by the US Department of Energy, Contract No. DE-AC0298CH10886. G. De Geronimo and P. O’Connor are with the Instrumentation Division, Brookhaven National Laboratory, Upton, NY 11973, USA (telephone: 631-344-5336, e-mail: degeronimo@bnl.gov). Cg ENC = 1 2π ∫ [S ∞ in 2 ( ) H ( jω) + C in + C g 2 ω2Svn H ( jω) 0 2 2 ] dω (1) h ( t ) max where τ is the time constant of the filter and H(s) is the U.S. Government work not protected by U.S. copyright Laplace transform of the pulse response h(t). Introducing the typical spectral densities previously discussed it follows: (Cin + Cg ) 2 ENC 2 = ∞ ∞ 2 2 S w τ H( jωτ) ω2 dω + A ƒ 2π τ H( jωτ) ωdω 0 0 2 2π ⋅ h ( t / τ) max ∫ ∞ Sp + ∫ τ H( jωτ) 2 ∫ + (2) dω 0 2 2π ⋅ h ( t / τ) max where the time is normalized to an arbitrary time constant τ, and τ•H(sτ) is the Laplace transform of h(t/τ). Assuming as time constant the pulse peaking time τp, calculated from 1% to the peak, and transforming the integrals variable, the (2) becomes: S ENC 2 = Cin + Cg 2 w a w + A ƒ 2π a ƒ + Sp τ p a p τ p ( ) (3) where the three ENC coefficients: ∞ aw = ∫ H( jx) 2 ∞ x 2 dx 0 2π ⋅ h ( t / τ p ) , aƒ = 2 max ∫ H( jx ) 2 ∞ ∫ H( jx) xdx 0 2π⋅ h ( t / τ p ) 2 max , ap = 2 dx 2 ( ) CU-2 CU-3 CU-4 CU-5 CU-6 CU-7 RB-2 RB-3 RB-4 RB-5 RB-6 RB-7 CB-2 CB-3 CB-4 CB-5 CB-6 CB-7 P 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10 6 8 10 12 14 16 18 20 aw 1 0.92 0.82 0.85 0.89 0.92 0.94 0.93 0.85 0.91 0.96 1.01 1.04 1.03 1.11 1.30 1.47 1.61 1.74 8 10 12 14 16 18 20 1.08 1.27 1.58 1.86 2.11 2.31 Shape 1 2 nd th 7 0 0 1 2 3 1 2 7 0 0 nd th 1 2 1 2 nd 0 7 th -1 0 2 4 1 nd 2 0 th 7 -1 0 2 4 6 aƒ 0.44 0.59 0.54 0.53 0.52 0.52 0.51 0.59 0.54 0.53 0.52 0.52 0.51 0.75 0.77 0.81 0.84 0.87 0.89 ap 0.33 0.92 0.66 0.57 0.52 0.48 0.46 0.88 0.61 0.51 0.46 0.42 0.40 1.01 0.76 0.66 0.62 0.59 0.57 τw /τp 0.79 0.86 0.93 0.98 1.02 1.06 1.02 0.76 0.67 0.63 0.59 0.58 12.9 7.29 5.60 4.81 4.37 4.11 2 7.66 5.04 4.17 3.73 3.46 3.27 6.31 3.92 3.16 2.84 2.66 2.55 16.6 9.87 7.68 6.60 5.94 5.53 III. CONSTRAINTS, VARIABLES AND MODELS max depend only on the type of filter, and H(jx) is obtained replacing ω with x/τp in H(jω). In Table 1 the coefficients for some commonly adopted time invariant filters are reported, along with the ratio between the pulse width τw, calculated from 1% to 1% of the curve, and the peaking time τp, calculated from 1% to the peak. The R-type filters have real poles only while the C-type filters, commonly adopted in commercial discrete shapers, have complex conjugate poles nd th [8]. The order of the filters in Table 1 ranges from 2 to 7 . It can be observed that, as the order increases, the ratio τw/τp decreases making the high order filters more suitable for high rate applications. Also, at equal order, the C-type filters offer a better τw/τp ratio than the R-type filters. Finally, the advantage of zero area for bipolar filters, which in absence of effective baseline stabilization at high rate can be relevant, is compensated by worse values in the series coefficients aw and aƒ, especially for high orders. Without loss of generality we will simplify our analysis by assuming aw=1, aƒ=0.5, and ap=0.5, which are close to the typical values for a good time invariant unipolar shaper. In the rest of the analysis the parallel noise contribution Sp will be neglected, and the general expression for the ENC in (3) will be simplified as follows: S ENC 2 = C in + C g 2 w + πA ƒ . τ p W Filter Triang. RU-2 RU-3 RU-4 RU-5 RU-6 RU-7 (4) 0 2π ⋅ h ( t / τ p ) TABLE I COMMONLY ADOPTED TIME INVARIANT FILTERS AND CORRESPONDING ENC COEFFICIENTS. THE RATIO τ /τ IS ALSO REPORTED. (5) The input MOSFET must be optimized for the minimum ENC. The ENC depends on some parameters not related to the input MOSFET, specifically the input capacitance Cin, the peaking time τp, and the maximum power Pd_max available to the input MOSFET. Typically the input capacitance Cin is set by the sensor and interconnects, the maximum power Pd_max depends on system level constraints, and the peaking time τp is set by the rate or ballistic deficit. In presence of non-negligible parallel noise contribution a further constraint on the peaking time may occur. The typical optimization process consequently assumes Cin, τp, and Pd_max as constraints. One further constraint derives from the use of a single supply Vdd: Id = Pd Vdd ⇒ Jd = Id W (6) where Jd is the MOSFET drain current density. The (6) establishes a constraint on the Jd×W product. It follows that, once Cin, τp, and Pd are defined, the ENC depends only on two variables: W (or Jd) and L. The optimization process will consequently return the two optimum values Wopt (or Jd_opt) and L_opt that give the minimum ENC (ENCopt). In order to proceed with the optimization of the input MOSFET, the parameters Cg, Sw and Aƒ must be expressed as functions of W (or Jd) and L. In the following sections the modeling of these parameters will be discussed, starting from the solution that the CMOS designers frequently adopted in the past, before the advent of the deep submi- U.S. Government work not protected by U.S. copyright 120 G W 100 ƒ In the past the front-end designers frequently adopted the following models [9-13]: C g = C ox WL, S w = Kƒ 2 4kT , Aƒ = 3 g m (J d , L) C ox WL (7) where Cox is the oxide capacitance, k is the Boltzmann constant, T is the absolute temperature, gm is the MOSFET transconductance dependent on Jd and L, and Kƒ is the 1/ƒ noise coefficient. We will refer to this model as C-model. Introducing (7) in (5) it follows: Kƒ 4 kT 2 1 2 +π ENC 2 = (C in + C ox WL ) ( ) τ 3 g J , L ⋅ W C mw d ox WL p (8) Tranconductance density gmw [mS/mm] where gmw(Jd,L) is the transconductance per unit of W. The function gmw(Jd,L) can be easily extracted for specific values of L from a Spice simulation using the model and parameters available for the technology. The coefficient Kƒ can be extracted from a measurement of the input noise spectral density, it is assumed to be independent of L and it may differ for n-channels (Kƒn) and p-channels (Kƒp). 2 For the TSMC 0.25µm technology Cox≈6.1fF/µm , gmw(Jd,L) can be obtained from BSIM3v3.1 simulations (see Fig. 2) and, from measurements on samples with minimum -24 -24 L at 1kHz, it follows Kƒn≈6×10 J and Kƒp≈0.3×10 J. In Fig. 3 the optimum ENC for Cin=1pF and τp=1µs, calculated for n- and p-channels with different L as function of Pd is shown. For minimum L the white and 1/ƒ components and the optimum W are also reported. It can be observed that in this case the p-channel offers a better resolution than the n-channel (lower Kƒ) and this is generally true. It also indicates that the choice Lopt=Lmin and Pd_opt=Pd_max offers better results in an amount that depends on the relative ratio between the white and 1/ƒ contributions. 10 3 10 2 10 1 10 0 10 -1 10 -2 Nch Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm ** * ** Pch -4 10 -3 10 -2 10 -1 10 0 10 1 white 1/ƒ white 1/ƒ 1.0 0.8 Nch 60 0.6 40 0.4 Pch 20 0 -5 10 0.2 TSMC 0.25µm - Cin=1pF, τp=1µs 10 -4 10 0.0 -3 10 -2 Power Pd [W] Fig. 3. Simulated ENCopt vs Pd for n- and p-channels with different channel lengths in TSMC 0.25µm adopting the C-model (7). V. ENHANCED (E) MODEL FOR S W The model for Sw in (7) provides a crude white noise estimation valid for long channel MOSFETs operating in strong inversion. In most cases the input MOSFET of a front-end operates in moderate to weak inversion, and a better estimate is needed. In addition, in deep submicron MOSFETs an excess noise factor above unity has been frequently reported. An equation that better estimates the white noise in all regions of operation can be found in the literature [14-16]: S 2vw = α w 4kT µ eff Q I 1 L2 (9) g 2m where µeff is the mobility, QI is the total inversion charge, and αw is the excess noise factor. This equation can be approximated with [16]: S2vw = α w nγ(J d , L) 2kT g mw (J d , L)W (10) where n≈(gmb+gm)/gm is the subthreshold slope coefficient ranging around 1.2-1.3 and γ(Jd,L) is a coefficient ranging between 1/2 and 2/3. The same authors of [16] proposed the following interpolation function: Jd L 1 1 2 + u (J d , L ), u (J d , L) = 1 + u (J d , L ) 2 3 µ eff C ox 2nVt2 (11) where u(Jd,L) is known as inversion coefficient and Vt=kT/q. From the same authors is a simpler approximation for γ(Jd,L) [12]: * moderate inversion (Vgs~VT) γ ( J d , L) = -3 10 80 γ ( J d , L) = TSMC 0.25µm - BSIM3v3.1 10 ENCopt [r.m.s. electrons] IV. CLASSICAL (C) MODEL FOR C , S AND A 1.2 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm Wopt [mm] cron CMOS technologies. 10 2 Drain current density Jd [mA/mm] Fig. 2. Simulated gmw vs Jd of n- and p-channels with different L in TSMC 0.25µm. Center of moderate inversion (*) is also indicated. 2 g mw (J d , L ) 3 + nVT Jd . (12) A slower interpolation function is reported in [15], along with the companion model for the gate capacitance. A comparison to Cg simulations and to noise measurements [2] suggests that (11), here adopted, might be more accurate. In U.S. Government work not protected by U.S. copyright Fig. 4 the gamma coefficient γ(Jd,L) versus the inversion coefficient u(Jd,L) is shown. The regions of operation for the MOSFET are also indicated. In most cases the optimum input MOSFET operates in moderate inversion. 0.65 Gamma coefficient γ strong (VGS-VT > ~10Vt) 0.60 moderate VI. ENHANCED (E) MODEL FOR CG The gate capacitance Cg in (5) includes any term dependent on the size (W,L) of the input MOSFET. A better estimate of Cg should consider the gate-to-source and gate-todrain overlap components [15]. These extrinsic terms are proportional to the width W of the MOSFET and, in deep submicron technologies, are typically not negligible. In addition, the intrinsic component of Cg in saturation is a fraction ≈2/3 of CoxWL [15]. An equation that improves the estimate of Cg, here referred as Ci-model, is: 0.55 C g = 2C ov W + weak 0.50 -3 10 10 -2 10 -1 10 0 10 1 10 2 10 2 2 ENC 2 = C in + 2C ov W + C ox WL × 3 Fig. 4. Gamma coefficient γ vs inversion coefficient u. The regions of operation of the MOSFET are also indicated. 1 α w nγ (J d , L ) 4kT Kƒ ENC 2 = (C in + C ox WL )2 +π C ox WL τ p g mw (J d , L ) ⋅ W (13) For the TSMC 0.25µm technology nnch≈1.2, npch≈1.3 and, from measurements, αw≈1 whenever u<10 (weak and moderate inversion) and Vds-Vds_sat is small (Vds_sat is the drainsource saturation voltage). Good agreement with these results can be found in the literature [2,18-20]. Nch - L=0.24µm Pch - L=0.24µm 1.0 C 0.8 60 0.6 u~1 40 0.4 20 Wopt [mm] ENCopt [r.m.s. electrons] 120 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm E(Sw),Ci(Cg) 100 1.2 80 0.2 u~1 0 -5 10 For the TSMC 0.25µm technology typical values for Cov are in the range 300-600 fF/mm, where the lower values are reported by TSMC and the higher values are reported by the MOSIS Service [21]. TSMC 0.25µm - Cin=1pF, τp=1µs -4 -3 10 10 0.0 -2 10 Power Pd [W] Fig. 5. Simulated ENCopt vs Pd for n- and p-channels with different channel lengths in TSMC 0.25µm adopting the E-model for Sw. The center of moderate inversion (u=1) is also indicated. In Fig. 5 the optimum ENC from (13) for Cin=1pF and τp=1µs, calculated for n- and p-channels with minimum L as function of Pd, is shown, compared to C-model results. The optimum W is also reported. It can be observed that the new model provides a better estimate especially at low power, where the white noise component dominates. A relatively small difference in terms of optimization (Wopt) can also be observed. The Lopt=Lmin and Pd_opt=Pd_max still appears the best choice. ENCopt [r.m.s. electrons] 120 (15) 1 α w nγ (J d , L )4 kT Kƒ × +π C ox WL τ p g mw (J d , L ) ⋅ W Introducing the new model (10)-(11) in (5) it follows: E(Sw) (14) where Cov is the overlap capacitance density, equal for drain and source. Introducing (14) in (13) it follows: 3 Inversion coefficient u 100 2 C ox WL 3 Nch 80 60 Pch 40 20 TSMC 0.25µm - Cin=1pF, τp=1µs 0 -5 10 10 -4 10 -3 10 -2 Power Pd [W] Fig. 6. Simulated ENCopt vs Pd for n- and p-channels with different channel lengths in TSMC 0.25µm adopting the E-model for Sw and the Cimodel for Cg. In Fig. 6 the optimum ENC from (15) for Cin=1pF and τp=1µs, calculated for n- and p-channels with minimum L as function of Pd, is shown. When compared to Figs. 3 and 5 it can be observed that the choice Lopt=Lmin does not apply anymore. Both n-channel and p-channel can offer better resolution for L higher than Lmin. This conclusion is valid whenever 1/ƒ noise dominates, and can be understood by rewriting (15) for this case: 2 Kƒ 2 ENC 2 ≈ C in + 2C ov W + C ox WL π 3 C ox WL (16) By calculating the differential of (15) with respect to W, U.S. Government work not protected by U.S. copyright Wopt = 2C ov C in 2 + C ox L 3 . Total Gate Capacitance Density Cgw [pF/mm] the optimum width for the minimum ENC can be calculated for each L: (17) Capacitive matching applies (Cg=Cin) and, by superposition, the ENCopt can be written: 2 ENC opt ≈ 3C ov . 8 C in πK ƒ 1 + 3 C ox L (18) The plot in Fig. 7, derived from (18) for n-channel MOSFETs, illustrates the impact of L on the optimum ENC for the case of dominant 1/ƒ noise. Intuitively, as L increases the 1/ƒ noise contribution decreases more rapidly than the increase in gate capacitance. 3.6 TSMC 0.25µm - BSIM3v3.1 - MOSIS Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm 3.2 2.8 Nch Pch 2.4 Ci 2.0 Nch - L=0.24µm E 1.6 1.2 -4 10 10 -3 10 -2 10 -1 10 C 0 10 1 10 2 Drain Current Density Jd [mA/mm] Fig. 8. Simulated (BSIM3v3.1) Cgw vs Jd of n- and p-channels with different L in TSMC 0.25µm. The C- and Ci-models for the minimum L nchannel are also reported. 70 Introducing the (19) in (13) it follows: 1 α w nγ (J d , L )4kT Kƒ ENC 2 = [C in + C ow (J d , L ) ⋅ W ]2 +π ( ) τ g J , L ⋅ W C ox WL p mw d 50 assumung 1/ƒ dominant 40 1 10 Channel length L [µm] Fig. 7. Simulated ENCopt vs L for n-channel MOSFET and Cin=1pF assuming 1/ƒ dominant. The Ci-model (14) for Cg doesn’t take into account the dependence of the intrinsic gate capacitance on the drain current density Jd. This dependence in deep submicron technologies can be not negligible, especially in the transition from weak, thorough moderate, to strong inversion. An enhanced (E) model for Cg can be written as: C g = C gw (J d , L ) ⋅ W (19) where Cgw(Jd,L) is the gate capacitance density and includes the bias dependence, intrinsic and extrinsic components. As for gmw(Jd,L) the function Cgw(Jd,L) can be extracted for specific values of L from a Spice simulation using the model and parameters available for the technology. For the TSMC 0.25µm Cgw(Jd,L) can be obtained from BSIM3v3.1 simulations as shown in Fig. 8. The results for C- and Cimodels for the n-channel at minimum L are reported for comparison. It is worth noting that the cutoff frequency of the MOSFET, given by gm/(2πCg), remains an increasing function of Jd and, in the regions of interest, typically exceeds the tens of MHz. (20) In Fig. 9 the optimum ENC from (20) for Cin=1pF and τp=1µs, calculated for n- and p-channels with different L as function of Pd, is shown. For two cases the 1/ƒ component and the optimum W are also reported. It can be observed again that the choice Lopt=Lmin does not apply. In addition, for n-channel MOSFETs, the choice Pd_opt=Pd_max does not apply, since they can offer better resolution at Pd lower than the maximum available. 120 1.2 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm E(Sw,Cg) 100 80 60 1.0 1/ƒ 1/ƒ 0.8 Pch 0.6 Nch - L=0.48µm 40 0.4 20 0 -5 10 Wopt [mm] 60 ENCopt [r.m.s. electrons] ENCopt [r.m.s. electrons] TSMC 0.25µm - Nch - Cin=1pF 0.2 TSMC 0.25µm - Cin=1pF, τp=1µs 10 -4 0.0 -3 10 10 -2 Power Pd [W] Fig. 9. Simulated ENCopt vs Pd for n- and p-channels with different L in TSMC 0.25µm adopting the E-model for Sw and Cg. This conclusion is valid whenever 1/ƒ noise dominates, and can be understood by rewriting (20) for this case: [ ENC 2 ≈ C in + C gw (J d , L )W ƒ . ] 2 π C KWL (21) ox By taking into account (6) and calculating the differential of (21) with respect to W, the optimum width for the minimum ENC can be calculated for each L: U.S. Government work not protected by U.S. copyright . (22) 10 Capacitive matching does not apply except for the regions where ∂Cgw/∂Jd=0 and, by superposition, the ENCopt turns out to be: η(J d , L )C gw (J d , L ) 1 2 C in πK ƒ ENC opt ≈ 1 + C ox L η(J d , L ) . ( ) ∂ C J , L J gw d η(J , L ) = 1 − 2 d d ∂J d C gw (J d , L ) (23) The plot in Fig. 10, derived from (23) for n-channel with minimum L and Cin=1pF, illustrates the impact of Pd on the optimum ENC for cases of dominant 1/ƒ noise. The ratio Cg_opt/Cin is also reported. Intuitively, as Pd increases the gate capacitance increases while the 1/ƒ noise contribution does not change. 80 1.6 1.4 Cg_opt / Cin ENCopt [r.m.s. electrons] Nch - L=0.24µm, Cin=1pF assumung 1/ƒ dominant 60 est for our applications. Some authors have reported an increase moving towards very strong inversion [28-30]. 1.2 Noise spectral density Svn [V/√Hz] C in ∂C gw (J d , L ) Jd C gw (J d , L )1 − 2 ( ) C J , L ∂J d gw d -6 10 -7 10 -8 10 -9 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm ratio ≈2.4 slope 1/ƒ TSMC 0.25µm W=7.2mm, Jd=140µA/mm, Vds=400mV 10 -10 10 1 10 2 10 3 10 4 5 10 10 6 10 7 Frequency ƒ [Hz] Fig. 11. Measured equivalent input noise spectra for n- and p-channels with different L in TSMC 0.25µm. 10 -6 W=7.2mm, Jd=20µA/mm to 1mA/mm, Vds=200mV to 400mV Noise spectral density Svn [V/√Hz] Wopt = 10 -7 10 -8 10 -9 Nch - L=0.24µm Pch - L=0.24µm TSMC 0.25µm -10 40 -5 10 10 -4 10 -3 1.0 10 -2 10 10 2 3 10 10 VII. ENHANCED (E) MODEL FOR LOW-FREQUENCY NOISE In Fig. 11 the typical equivalent input noise spectral densities measured on n- and p-channels in TSMC 0.25µm with different L are shown, and are compared to the 1/ƒ slope. Two relevant details should be observed. The first concerns the slope, which differs from 1/ƒ, being in this case higher for p-channels and lower for n-channels. The second concerns the ratio between spectra, which is higher (≈2.4 for L=0.24µm vs L=0.48µm) compared to the square root of the ratio between L (≈1.4 for L=0.24µm vs L=0.48µm). A similar trend for short channels in deep submicron technologies was reported by other authors [2,22-25]. In Fig. 12 the typical spectra for n- and p-channels with L=0.24µm at different drain current densities Jd are shown. The dependence of the low-frequency component on the bias point appears negligible. This result seems in agreement with others in the literature for MOSFETs operating from weak inversion up to the border between moderate and strong inversion [3,26-29], which is the region of inter- 5 10 10 6 10 7 Frequency ƒ [Hz] Power Pd [W] Fig. 10. Simulated ENCopt vs Pd for minimum L n-channel and Cin=1pF assuming 1/ƒ dominant. 4 Fig. 12. Measured equivalent input noise spectra for n- and p-channels with minimum L and different Jd in TSMC 0.25µm. The results reported in Figs. 11 and 12 indicate that the low-frequency component of the noise power spectral density could be better approximated by using the following Enhanced (E) equation: Sƒ = Aƒ ƒ αƒ = K ƒ (L) C ox WLƒ (24) αƒ where Kƒ(L) now depends on L, and the slope depends on the coefficient αƒ. The non-1/ƒ slope requires a review of the low-frequency component ENCLF of the ENC. The second term of (2) now becomes: ∞ (Cin + Cg )2 A ƒ (2π)α ∫ τ H( jωτ) 2 ω2−α dω ƒ ƒ ENC 2LF = 0 2 , (25) 2π ⋅ h (t / τ) max and (3) can be rewritten: S (2π)α ƒ ENC 2 = Cin + C g 2 w a w + A ƒ 1−α a ƒ α ƒ + S p τ p a p ƒ τp τp ( ) U.S. Government work not protected by U.S. copyright ( ) (26) Fig. 13 for the case Cin=1pF, Pd=200µW, τp_opt =1µs. where the ENC coefficient aƒ(αƒ) is given by: ( ) a ƒ αƒ = ∫ H( jx ) 2 x 2−α ƒ 120 dx 0 2 2π⋅ h ( t / τ p ) E . TSMC 0.25µm - Pd=200µW, Cin=1pF, τp, opt=1µs 100 (27) ENC [r.m.s. electrons] ∞ max Concerning the two other coefficients in (4) it is worth noting that aw=aƒ(0) and ap=aƒ(2). In Table 2 the ratio ρƒ=aƒ(αƒ)/ aƒ(1) is calculated for the filters of Table 1. TABLE II Nch - L=0.48µm Pch - L=0.24µm white white 1/ƒ 1/ƒ 80 60 40 20 RATIO ρ =aƒ(αƒ)/aƒ(1) VS αƒ FOR THE FILTERS REPORTED IN TABLE 1. ƒ Relative coeff. ρƒ Filter 0 -7 10 1.1 10 7 0.8 α 0.9 1.0 1.1 -5 10 Fig. 13. Simulated ENC vs τp for a design optimized for Cin=1pF, Pd=200µW, and τp_opt.=1µs. th 0.9 -6 Peaking time τp [s] nd 2 1.0 1.2 VIII. ACHIEVABLE RESOLUTION IN TSMC0.25µM 1.1 nd 2 1.0 7 0.9 By applying (28) to the TSMC 0.25µm CMOS it is possible to estimate the ENC achievable with this technology. The results below will give a general idea of what to expect. An exhaustive analysis is beyond the scope of this work. th α 0.8 0.9 1.0 1.1 1.2 1.1 2 1.0 nd 160 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm th 7 0.9 140 α 0.8 0.9 1.0 1.1 1.2 1.1 nd 2 1.0 7 0.9 th α 0.8 0.9 1.0 1.1 1.2 The final expression for the ENC related to series noise, adopting the E-model for Sw, Cg and Sƒ, becomes: ENCopt [r.m.s. electrons] RU-2 RU-3 RU-4 RU-5 RU-6 RU-7 CU-2 CU-3 CU-4 CU-5 CU-6 CU-7 RB-2 RB-3 RB-4 RB-5 RB-6 RB-7 CB-2 CB-3 CB-4 CB-5 CB-6 CB-7 E 120 C 100 Nch 80 60 40 Pch 20 TSMC 0.25µm - Cin=1pF, τp=1µs ENC 2 = [C in + C ow (J d , L ) ⋅ W ]2 × ( ) (28) For the TSMC 0.25µm technology typical values for Kƒ and αƒ are reported in Table 3. As in previous cases we will simplify our analysis by assuming ρƒ=1.05 for n-channels and ρƒ=0.95 for p-channels, values close to the typical for a good time invariant unipolar shaper. TABLE III TYPICAL VALUES OF K AND αƒ FOR THE TSMC 0.25µM TEHCNOLOGY. ƒ Nch-0.24µm Nch-0.36µm Nch-0.48µm Pch-0.24µm Pch-0.36µm Kƒ 2.71×10-24 1.40×10-24 0.97×10-24 0.60×10-24 0.50×10-24 αƒ 0.85 0.85 0.85 1.08 1.08 As consequence of the non-1/ƒ slope, a front-end optimized for a peaking time τp_opt will show in the ENC a lowfrequency noise component dependent on τp, as shown in -4 -3 10 10 -2 10 Power Pd [W] (a) 1.2 1.0 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm E 0.8 Wopt [mm] 1 α nγ (J , L )4kT K ƒ (2π )α ƒ w d aƒ αƒ × + 1 − α ƒ C ox WL τ p τ p g mw (J d , L ) ⋅ W 0 -5 10 C 0.6 0.4 Nch 0.2 Pch 0.0 -5 10 10 TSMC 0.25µm - Cin=1pF, τp=1µs -4 10 Power Pd [W] -3 10 -2 (b) Fig. 14. Simulated (a) ENCopt vs Pd and (b) corresponding Wopt vs Pd for n- and p-channels with different L in TSMC 0.25µm adopting the E-model. Results from the C-model at minimum L are also shown. U.S. Government work not protected by U.S. copyright In Figs. 14(a) and 14(b) the ENCopt and Wopt for Cin=1pF and τp=1µs, calculated using the E-model for n- and pchannels with different L as functions of Pd are shown. For comparison the two minimum L cases with the C-model are reported. The difference between E- and C-model in the estimate of the ENCopt for the n-channels is relevant, while for the p-channel may appear small. On the other hand the difference in terms of optimization (Wopt) is in both cases relevant. 1000 E TSMC 0.25µm - Pd_max=1mW, Cin=1pF inputs, 16 with L=0.24µm and 16 with L=0.36µm. The gate capacitance was, in both cases, on the order of 1.4pF. We observed a ≈40% difference in ENC slope, a result that appears in line with the discussion here presented. In Fig. 16(b) the ENC vs τp from a prototype for a Coplanar Grid Sensor [32] is shown. The ASIC implements an n-MOS input with L=0.36µm. The gate and input capacitances were on the order of 12pF and 60pF respectively. A low-0.15 frequency noise component proportional to ≈τp , in agreement with αƒ≈0.85, can be observed. 600 -3 Nch -4 10 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm 10 -8 10 Measured ENC [r.m.s. electrons] 100 Pd_opt [W] ENCopt [r.m.s. electrons] 10 Pch -7 10 10 -6 10 -5 Peaking time τp [s] 300 - 26e /pF 200 100 TPC Front-End - TSMC 0.25µm Cg~1.4pF, Pd~230µW, τp~900ns 0 2 4 1000 -3 8 10 12 Nch 10 -4 Nch 10 Pch 10 E -5 TSMC 0.25µm - Pd_max=1mW, τp=1µs -13 10 10 -12 (a) 10k -11 10 Input capacitance Cin [F] (b) Fig. 15. Simulated ENCopt and Pd_opt vs (a) τp and (b) Cin for n- and pchannels with different L in TSMC 0.24µm adopting the E-model. In Figs. 15(a) and 15(b) the ENCopt and Pd_opt for Cin=1pF vs τp and for τp=1µs vs Cin, calculated using the E-model for n- and p-channels with different L, are shown, assuming a power budget limit of Pd_max=1mW. In the case of Fig. 15(a) the reduction in Pd_opt can be observed for higher values of τp. In the case of Fig. 15(b) the reduction in Pd_opt can be observed for smaller values of Cin. In both cases this is consequence of the dependence of the gate capacitance on the drain current density, which pushes the input MOSFET towards the weak inversion. In Figs. 16(a) and 16(b) we report some experimental results from two front-end ASICs recently developed in TSMC 0.25µm CMOS. In Fig. 16(a) The ENC vs Cin from a prototype for a Time Projection Chamber [31] is shown. The ASIC implements 32 front-end channels with n-MOS Measured ENC [r.m.s. electrons] 100 10 Nch - L=0.24µm Nch - L=0.36µm Nch - L=0.48µm Pch - L=0.24µm Pch - L=0.36µm Pd_opt [W] ENCopt [r.m.s. electrons] 6 Input capacitance Cin [pF] Pch 1 -14 10 - 37e /pF 400 0 (a) Nch. - L=0.24µm Nch. - L=0.36µm 500 CPG Front-End - TSMC 0.25µm L=0.36µm, Cg~12pF, Cin~60pF, Pd~3mW Measurement Theoretical fitting 1k white series low-frequency series τp -0.15 parallel 100 0.1 1 10 100 Peaking time τp [µs] (b) Fig. 16. ENC measurements on front-end ASICs for (a) a Time Projection Chamber and (b) a Co-Planar Grid Sensor. IX. CONCLUSIONS The optimization of the input MOSFET for charge amplifiers in deep submicron technology requires a proper modeling of the series noise and gate capacitance, and a review of the ENC equation. The enhanced modeling and associated ENC equation presented here allow a better ENC estimate and a more accurate optimization. The analysis shows that the traditional choice of selecting the minimum channel length and the maximum of the available power do not always offer the best resolution. Also, for a defined front-end, the low-frequency noise contribution to the ENC may de- U.S. Government work not protected by U.S. copyright pend on the time constant of the filter. The results here reported are based on the commercial TSMC 0.25µm CMOS, but can be easily extended to other deep submicron technologies. X. ACKNOWLEDGMENT The authors are grateful to Giovanni Anelli (CERN), Veljko Radeka (BNL), and Angelo Dragone (Bari Polytechnic) for helpful discussions. XI. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] M. Campbell, G. Anelli, E. Cantatore, F. Faccio, E. H. M. Heijne, P. Jarron, J. C. Santiard, W. Snoeys, and K. Wyllie, “An introduction to deep submicron CMOS for vertex applications”, Nucl. Instrum. Methods, A473, pp. 140-145, 2001. G. Anelli, F. Faccio, S. Florian, and P. Jarron, “Noise characterization of a 0.25µm CMOS technology for LHC experiments”, Nucl. Instrum. Methods, A457, pp. 361-368, 2001. M. Manghisoni, L. Ratti, V. Re, and V. Speziali, “Submicron CMOS technologies for low-noise analog front-end circuits”, IEEE Trans. Nucl. Sci., vol. 49, pp. 1783-1790, 2002. V. Radeka, “Semiconductor position-sensitive detectors”, Nucl. Instrum. Methods, A226, pp. 209-218, 1984. E. Gatti and P. F. Manfredi, “Processing the signals from solid-state detectors in elementary particle physics” La Rivista del Nuovo Cimento, vol. 9, pp. 1-147, 1986. V. Radeka, “Low noise techniques in detectors” Ann. Rev. Nucl. Part. Sci., vol. 38, pp. 217-277, 1988. E. Gatti, M. Sampietro, and P. F. Manfredi, “Optimum filters for detector charge measurements in presence of 1/ƒ noise” Nucl. Instrum. Methods, A287, pp. 513-520, 1990. S. Okhawa, M. Yoshizawa, and K. Husimi, “Direct synthesis of the Gaussian filter for nuclear pulse amplifiers”, Nucl. Instrum. Methods, 138, pp. 85-92, 1976. W. M. C. Sansen andZ. Y. Chang, “Limits of low noise performance of detector readout front ends in CMOS technology”, IEEE Trans. Circ. Sys., vol. 37, pp. 1375-1382, 1990. Y. Hu, J. D. Berst, and W. Dulinski, “Semiconductor positionsensitive detectors”, Nucl. Instrum. Methods, A378, pp. 589-593, 1996. C. G. Jakobson and Y. Nemirovsky, “CMOS low-noise switched charge sensitive preamplifier for CdTe and CdZnTe X-ray detectors”, IEEE Trans. Nucl. Sci., vol. 44, pp. 20-25, 1997. G. de Geronimo and P. O’Connor, “A CMOS detector leakage current self-adaptable continuous reset system: Theoretical analysis”, Nucl. Instrum. Methods, A421, pp. 322-333, 1999. T. H. Lee, G. Cho, H. J. Kim, S. W. Lee, W. Lee, and H. Han, “Analysis of 1/ƒ noise in CMOS preamplifier with CDS circuit”, IEEE Trans. Nucl. Sci., vol. 49, pp. 1819-1823, 2002. B. Wang, J. R. Hellums, and C. G. Sodini, “MOSFET thermal noise modeling for analog integrated circuits”, IEEE J. Solid-State Circuits, vol. 29, pp. 833-835, 1994. Y. Tsividis, “Operation and modeling of the MOS transistor”, 2nd ed., McGraw-Hill, 1999, pp. 414-427. [16] C. C. Enz and E. A. Vittoz, “MOS transistor modeling for lowvoltage and low-power analog IC design”, Microelectronics Engineering, 39, pp. 59-76, 1997. [17] D. Flandre, D. Levacq, and L. Vancaillie, “EKV formulation of major analog MOS parameters in bulk Si and SOI technologies”, http://www.elec.ucl.ac.be/enseignement/ELEC2650/chapter3.pdf, pp. 71-72, 2002. [18] G. Knoblinger, P. Klein, and U. Baumann, “thermal channel noise of quarter and sub-quarter micron NMOS FET’s”, Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 95-98, 2000. [19] V. Re, I. Bietti, R. Castello, M. Manghisoni, V. Speziali, and F. Svelto, “Experimental study and modeling of the white noise sources in submicron p- and n-MOSFETs”, IEEE Trans. Nucl. Sci., vol. 48, pp. 1577-1586, 2001. [20] K. Han, H. Shin, and K. Lee, “Analytical drain thermal noise current model valid for deep submicron MOSFETs”, IEEE Trans. Electron Devices, vol. 51, pp. 261-269, 2004. [21] The MOSIS Service, http://www.mosis.org/. [22] G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys “Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments”, IEEE Trans. Nucl. Sci., vol. 46, pp. 1690-1696, 1999. [23] P. F. Manfredi and V. Re, “Trends in the design of spectroscopy amplifiers for room temperature solid state detectors”, IEEE Trans. Nucl. Sci., vol. 51, pp. 1182-1190, 2004. [24] P. F. Manfredi, M. Manghisoni, L. Ratti, V. Re, and V. Speziali, “Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors”, Nucl. Instrum. Methods, A512, pp. 167-178, 2003. [25] J. F. Pratte, G. De Geronimo, S. Junnarkar, P. O’Connor, B. Yu, S. Robert, V. Radeka, C. Woody, S. Stoll, P. Vaska, A. Kandasamy, R. Lecomte, and R. Fontaine, “Front-end electronics for the RatCAP mobile animal PET scanner”, IEEE Trans. Nucl. Sci., vol. 51, pp. 1318-1323, 2004. [26] Z. Y. Chang and W. Sansen, “Effect of 1/ƒ noise on the resolution of CMOS analog readout systems for microstrip and pixel detectors”, Nucl. Instrum. Methods, A305, pp. 553-560, 1991. [27] J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures”, IEEE Trans. Electron Devices, vol. 41, pp. 19651971, 1994. [28] T. Boutchacha, G. Ghibaudo, and B. Belmekki, “Study of low frequency noise in the 0.18µm silicon CMOS transistors”, Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 84-88, 1999. [29] Y. Nemirovsky, I. Brouk, and C. G. Jacobson, “1/ƒ noise in CMOS transistors for analog applications”, IEEE Trans. Electron Devices, vol. 48, pp. 921-927, 2001. [30] H. V. Deshpande, B. Cheng, and J. C. S. Woo, “Analog deive design for low power mixed mode applications in deep submicron CMOS technology”, IEEE Electron Dev. Lett., vol. 22, pp. 588-590, 2001. [31] G. De Geronimo, J. Fried, P. O’Connor, V. Radeka, G. C. Smith, C. Thorn, and B. Yu, “Front-end ASIC for a GEM base time projection chamber”, IEEE Trans. Nucl. Sci., vol. 51, pp. 1312-1317, 2004.] [32] G. De Geronimo, G. Carini, W.S. Murray, and P. O’Connor, “Frontend ASIC for Coplanar Grid Sensor”, Proc. IEEE 2004 RTSD. U.S. Government work not protected by U.S. copyright