l
SPECIAL FEATURE
New
Chip Carrier Package
Concepts
John W. Balde Daniel I. Amey
Western Electric Sperry Univac
Introduction
The chip carrier concept was originally conceived as a
square ceramic semiconductor package that could be
surface reflow soldered to a ceramic substrate. Its advantages of reduced package size, higher board packing
density, lower lead inductance and internal propagation
delay, and easy assembly and disassembly were, unfortunately, limited to largely military applications.
The idea seemed to have larger utility than that. If
sockets were available, such a ceramic package could be
installed on epoxy-glass printed circuit boards; if the
chip carrier concept were implanted in plastic or with
compliant leads, there could be direct attachment to such
boards. In early 1976 the Computer Packaging Technical
Committee began to see a number of such efforts to adapt
the chip carrier concept to wider applications.
Clearly, if the many efforts remained independent, the
possibility of wide industry acceptance of a new package
style to replace the dual in-line package could be very
low; non-interchangeable and non-compatible package
types present problems both to the semiconductor manufacturers and to users in the computer industry. Incompatible product offerings even present problems for a
vendor, because he finds that it is difficult to sell a
package for which he is the single source. Convinced
that the advantages of this general package type could
be much more widely realized if the many individual
package types were interchangeable and compatible, the
Computer Packaging Technical Committee has therefore
served as an active coordinator and participant in a crossstandardization effort involving system users, package
and socket manufacturers, and semiconductor companies.
58
Ceramic chip carriers
First
a
look at the basic concept. The original
chip
carriers, as developed by 3M's Electronic Products
Division, are square multilayer ceramic packages with a
pattern of gold metallization pads on the bottom and
an internal cavity into which the semiconductor can be
bonded.' There is a metal sealing surface on the top edge
of the cavity and a conventional Kovar seal lid is bonded
to the top. A number of these chip carriers are illustrated
in Figure 1.
The packages are fabricated in sheet form with the
connections from the internal metallization planes to the
bottom pad connection points being made by means of
metallized via holes formed into the ceramic in the
green state. These prepunched holes not only provide a
means for getting the connection from the internal layers
to the base layers, but also provide the rows of perforations which determine the snap lines when the sheet of
ceramic is broken into pieces. Although 3M, Kyocera
and Metceram presently make carriers by cofiring metallized ceramic multilayers, this same package style may be
fabricated by dry press operations.
It is assumed that the method of attaching such chip
carriers to some larger interconnection circuit would
be by reflow soldering to a set of pre-solder coated
lands on a ceramic mother board or hybrid multi-layer
substrate (Figure 2). The packages can be assembled to
such a ceramic circuit board by the use of hot air guns,
a hot air tunnel oven, or by heating the base ceramic
with a simple hot plate. The placement and positioning
of the chip carrier to the base ceramic substrate need
not be particularly accurate since errors of both transla-
COMPUTER
Figure 1. 3M ceramic chip carriers of various types.
tion and rotation will be corrected by the surface tension
forces of the molten solder during the reflow process.
These carriers will translate and rotate in the same way
that separate chip bonded LSI semiconductor chips will
Figure 2. Chip carrier mounted on multilayer ceramic substrate.
December 1977
equalize the surface tension forces and "seek" the position
of best match between the lands of the chip and the lands
of the substrate.
These packages are not only easy to assembly to the
underlying substrate, but are particularly easy to disassemble for repair and replacement. The same hot plate
or the same hot air gun can melt the solder for a given
package which can then be lifted off with a pair of
tweezers. Many circuits use thick film metallization of
the underlying ceramic to minimize the likelihood of
solder removing gold from the substrate land pad area,
but it is possible to achieve satisfactory bonding results
with multiple reflow carrier replacement even with thin
film metallization. The metallization system must be
chosen with some care, however, to make sure that it is
not all dissolved in the molten solder.
Most such chip carrier implementations were in square
packages having pads on 40-mil centers, although some
30- and 50-mil center packages were made. Most of the
applications were military with fairly large multi-layer
or double-sided ceramic circuit boards. There was a
gradual buildup in usage because of increasing realization of the three strengths of this package format:
(]) In the larger chip carriers with leads from 24 on up
to 64 there was a considerable space advantage over the
59
equivalent DIP package format. Area reductions of at
least 3 to 1 are easily achievable.
(2) The chip carrier format gives a considerably reduced
path length, less than that of the equivalent DIP, and
therefore cuts the lead inductance appreciably. As reported
by Bauer of RCA, the upper frequency operating limit
of the typical circuit can be increased by a factor of 2 or
more by changing from a DIP design to a chip carrier
design.
(3) The ability to remove and replace chip carriers with
ease and with minimal tooling began to be recognized
as a significant improvement over the DIP package,
which has difficulties in yield and reliability associated
with the DIP removal and replacement.
Figure 3 shows one of the circuits in manufacture by
RCA; and Table 1 shows the improvement in system
performance and packing density that can be achieved
when a chip carrier based design is substituted for a
design implementation in conventional DIP-board
technology.2
Figure 3. Chip carrier hybrid assembly.
The Mini-Pak chip carrier
The advantages of this technology were also recognized
by General Instruments in early 1976 as they faced the
problem of reducing size and cost for the microprocessor
and clock modules and similar LSI circuits. Their MiniPak package (Figure 4) is a cost-effective translation of
the basic square chip carrier concept to the needs of
commercial equipment designers who normally work
with printed circuit boards.3
Figure 4. GI Mini-Pak.
As implemented by GI, a small square of glass epoxy
laminate is metallized top and bottom with the necessary
50-mil center connection pads and with a central metallization area to which an LSI chip can be bonded with
conductive epoxy. Once again there are the plated-through
holes which provide the connections from the top to the
bottom surface of the epoxy at the land area and give
the characteristic notch edge configuration to the MiniPak carrier after it is punched out of its larger manufacturing sheet.
The LSI chip is connected to edge metallization stripes
by wire bond just as it is 'in ceramic chip carriers, but
the necessary surface protection of the chip is provided
by a conformal coating or potting of epoxy (Figure 5).
There is one interesting difference between the shipped
state of the GI Mini-Pak and the ceramic chip carriers:
the ceramic packages are shipped with bare gold metallization, with the resultant assumption that the necessary
solder for the reflow solder bond must be provided by
thick solder plating of the substrate. The converse is true
of the GI Mini-Pak, since it is shipped with a reservoir
of solder on the Mini-Pak carrier that is adequate to wet
the lands and fill the curved shapes of the edge notches.
It is this quantity of solder in the notches that gives the
necessary reservoir to be sure that all the edge pads do
reflow solder properly to the underlying printed circuit
board substrate. This ability to inspect the solder fillets
for both the ceramic and plastic chip carriers is an
important feature of this technology (Figure 6).
WIRE BOND
Table 1. Comparative performance characteristics.
PAD-TO-PIN DISTANCE
(INCHES)
LEADINDUCTANCE
CLOCKED LOGIC LIMIT
(MHz)
CONNECTIONS/11N2
60
CHIP CARRIERS
DIP
FLATPACK
16 TO 64 LEAD 16 TO 64 LEAD 16 TO 64 LEAD
ID 1.5
D.1
ID 1.5
.TO15
O15
5
20 TO 75
20 TO 75
1000
80
SD
500
40
40
500
40
40
CONFORMAL COATING
LSI CHIP
CONDUCTIVE EPOXY '
GLASS EPOXY LAMINATE
SOLDER BUMP
.'
METALLIZATION
Figure 5. Mini-Pak Assembly cross-section.
COMPUTER
Broader industry interest
By the spring of 1976 it became increasingly apparent
to others in the industry that a square format like the
chip carrier will be the package of the future as one goes
to the LSI devices that require pinouts of greater than
24 pins. If one is to assume such a square package in
ceramic, however, the concurrent requirement for a
ceramic substrate was considered disadvantageous. The
only solution for those who wished ceramic packages on
PC boards seemed to be a socket or connector for ceramic
chip carriers that could provide the interface to a printed
circuit board and offer the advantages of field replacement and also resilient members that could take care of
the difference in temperature coefficient of thermal
expansion. This differential between the PC board TC,
which initially can be as high as 50 to 75 PPM/°C, and
the 5 PPM/°C of ceramic can produce dimensional differences of 10 mils to the inch in the temperature swing from
the temperature of solidifying molten solder to room
temperature, and perhaps half that in the subsequent
temperature excursions that an equipment might see in
its operating life and on/off cycles. A socket for a halfinch-square device would only have to cope with the operating temperature swings and the difference in dimension
of the end leads to the center so that a lead compliance
that could cope with 2-mil changes in position would be
quite adequate.
The concept of a 50-mil-edge spaced ceramic substrate
in a socket had particularly been recognized by Sperry
Univac and had led to their decision to use that package
style for their future systems hardware with LSI circuitry.
While it was apparent from investigations by Dan Amey
of Sperry Univac) that both package manufacturers and
semiconductor manufacturers would make almost anything if specifically asked, it was also very apparent that
there was already a lack of mechanical standardization
of the ceramic chip carriers. Any LSI packaging technology would benefit from a broader industry acceptance
and the resultant standardization activities.
64 leads. They suggested that there was a common need
among users and manufacturers because of the limitations
of the existing packages, and they felt that the Computer
Packaging Committee with its mix of major computer
manufacturers, military equipment suppliers, telecommunications companies, and component suppliers would
therefore be the best forum to provide the critical review
and comment on the Sperry Univac design approach
and the feasibility of a standardization effort. The combination of ceramic chip carriers in sockets can offer the
following new advantages:
(1) Double-sided or multilayer PC boards can be used,
and the board area using a chip carrier and socket might
be one-half or one-third of the board area that otherwise
would have been dedicated to DIP's.
(2) If the chip carrier socket is just surface reflowed
to the PC board surface, plated-through holes need no
longer be of a size to take DIP leads. Instead of being
able to get only one or two surface paths between two
DIP holes with their associated pads in a PC board, as
is the case with 45-mil holes in 60-mil pads which give
only a 40-mil-wide "street," one can assume 20-mil holes
in 30-mil lands giving a 70-mil "street" which can accommodate three paths with 10-mil line and space, or two
lower-cost 15-mil paths. That can represent tripling of
the path routing density. At the price of a socket, one
gets easy field and repair changeability.
Although this solution seemed to possess many advantages, it did introduce the need for a socket with its
resultant cost and reliability problems. Since the chip
carrier in ceramic did not use a socket when the connection was being made to a ceramic substrate, and the
GI Mini-Pak did not use a socket when it was being connected to a simple double-sided printed circuit board, it
seemed pertinent to also consider alternative designs
capable of providing compliant leads that could cope with
the dimensional changes one would see in multilayered
printed circuit boards.
Standardization activities begun
Need for compliant lead designs
Accordingly, at the March 16, 1976, meeting of the
Computer Packaging Committee, Sperry Univac presented
a proposal for standardizing LSI packages with 48 through
The use of compliant leads as a means of coping with
temperature coefficient mismatch has been an industry
tactic for many years, as exemplified not only by IBM in
their SLT technology, but of course by the leads of
ceramic DIP's. Matching the temperature coefficient of
thermal expansion of a package with that of the underlying PC board substrate can help a great deal. Unfortunately, the lateral XY change of direction is not the
only change that takes place when one uses double-sided
or multilayer PC board. The copper signal planes on a
PC board rarely have the same copper on both sides in
the same configurations. Even if there is approximately
the same density of copper stripes, one normally sees
principally vertical stripes on one side and horizontal
stripes on the other. The resultant sandwich is therefore nonsymmetrical, and this nonsymmetry causes bending stresses, as the PC board is heated and cooled, that
are not very different from the bending stresses that
one normally sees in a bi-metallic strip. PC boards
therefore flex and can flex enough so that a 10-inch-wide
PC board might see a convexity or concavity of as much
as 50 mils in the center of the board. If one assumes
a flexing of 5 mils to the inch, it is apparent that a 1-inch
chip carrier in plastic will see stresses on the solder joints
as they try to restrain the board and chip from motions
that would otherwise cause separations of as much as
Figure 6. Typical solder filleting of a mounted chip carrier.
December 1977
61
2 mils. Since solder is not elastic, these stresses will
result in cracking or fracturing of the solder bead that
is bound to increase the failure rate of the chip when
mounted to multilayer PC boards.
This increased failure rate may be almost negligible
for a double-sided PC board and may be unimportant
for a system or a circuit board that uses only a few semiconductor chips. For computer mainframe applications,
however, which use many many chips, compliant leads
can offer that slight margin of increased reliability that
may be necessary.
The compliant lead plastic premolded package
In response to suggestions to this effect, Dimitry
Grabbe of AMP began work to create a package design
by AMP that could be bonded to PC boards.4 A lead frame
design very much like that used for plastic encapsulated
DIP's has its, leads formed out, down, tucked in underneath, and the edges turned up, so that one gets leads
in soft copper to connect from the reflow solder pads
on the printed circuit board to the internal portion of
the plastic cavity. This package is shown in Figure 7 for
a 400-mil-square 24-lead device package.
This, then, is another solution to the problem of a
replacement package for the DIP. The package itself
possesses the following advantages:
(1) It is attached to a substrate by reflow soldering
either of an existing solder coated pad surface or a solder
paste coated pad surface. It can also be installed in a
socket.
(2) It can be removed and resoldered many times
without high risk of more damage.
(3) The plastic proposed, polyphenylene sulfide (R4)
with a glass fiber fill, has a TC of 22 PPM/!C, very close
to the 15-17 PPM/°C temperature coefficient of fully
cured epoxy board. Since the leads are compliant, this
new package can be connected to either ceramic or multilayer board substrate.
(4) Like leadframe DIP's, the packages can be handled
in a continuous reel fashion. This means that the chips
can be bonded by tape bonding or by automated wire
bonding without Syntron feed and individual package
handling.
Figure 7. Premolded, compliant lead package, with socket.
62
(5) Lead spacing can be identical to that of a ceramic
chip carrier so that it is possible to have sockets that
can take either. This is not only useful for possible
product use, but is important for burn-in and test sockets
and prototype development.
(6) It is possible to form the leads of such device but
still retain attachment of the package to the carrying
web, which makes possible for the first time reel transferred chip and package testing.
(7) If desired, automated bonding equipment can be
built in order to make low cost package placement on
the PC boards.
Many of these steps can be seen in the sequence of
process actions shown in Figure 8.
"Open" packages
AMP has gone on ahead and combined the idea of the
resilient leaded chip carrier format with the premolded
or open package that has been explored recently in connection with DIPs. It is increasingly apparent that the
reliability data coming in from users that have explored
the open package filled with silicon gel encapsulant is
indicating quite favorable reliability results, very comparable to that achieved by hermetic packages. If such a
premolded package is assumed with a silicon gel encapsulant, a process sequence as shown in Figure 9 is possible.
Ceramic packages with compliant leads
It is not necessary to go to a plastic premolded
package, however, to get compliant leads. The Berg
Corporation has made edge clip lead designs available
in their "Solok" termination line for converting a ceramic
circuit board into DIP configuration. The same sort of
thing can be done with an edge clip to attach to a ceramic
carrier board and provide both compliant leads and the
same pad resoldering format as could be achieved by
the plastic compliant lead design and the ceramic chip
carrier. This concept is shown in Figure 10.
The coordination activity
With the interest and willingness to participate that
was shown in the spring meetings of the Computer
Packaging Committee, an informal standardization committee began to meet in July and August of 1976. Out
of this came plans to organize a task force to seek JEDEC
standardization of the chip carrier format in a variety
of sizes to meet the expected needs for future LSI
packages. Table 2 lists the proposed package sizes to
cover a range of LSI chips from 28 leads to 156 leads.
More than 20 companies took part in this standardization task force activity, coordinated and led by Dan Amey
of Sperry Univac. A partial list is shown in Table 3.
We should not leave you with the impression that the
end result sprang full blown in the first few minutes of the
first meeting of this group. There was indeed a large
variety of possible formats for the pad configurations,
for the number of pads per side, for the package sizes,
for their thicknesses and other vital dimensions, and for
the mating printed circuit board land pattern. There were
many major compromises made before things settled
down to square formats with an odd number of leads per
side and the general lead pattern configuration shown
in Figure 11.
COMPUTER
SEALED PACKAGE
ELL0
;f05
wIS
j_;;;i'X:ff00 00 ;00 0RCUlT PATTERN F T O\ REEL
LOOSE PIECE VERS ON
Figure 8. Processing steps for AMP package.
1-1
Figure 9. Open package assembly.
December 1977
63
The family concept
What evolved from these series of meetings was the
concept of a family of chip carrier packages made of
different materials, having different leads, having different
advantages and disadvantages, but all compatible with
the same layout on a printed circuit board.5 This family
is shown in Figure 12.
At this stage, however, that compatibility is more
apparent than real. Only the GI Mini-Pak and the two
compliant lead devices can connect directly to the printed
circuit board without some interface means. The two
styles of the ceramic packages require a socket or a
similar interface member using elastomeric connection
means in order to be useful. Accordingly, the group of
cooperating companies that had been the task force for
package standardization had a second task: that of also
participating in a standardization activity for sockets.
Figure 1O. Edge-clip leaded assembly.
Socket considerations
Table 2. LSI package family.
MAXIMUM I/O
CAPABILITY
28
44
52
68
84
100
124
156
NOMINAL PACKAGE
SIZE
.450" SQUARE
.650" SQUARE
.750" SQUARE
.950" SQUARE
1.150'" SQUARE
1.350" SQUARE
1.650" SQUARE
2.050'' SQUARE
MINIMUM MOUNTING
AREA
0.6" SQUARE
0.8" SQUARE
0.9" SQUARE
1.1" SQUARE
1.3'" SQUARE
1.5" SQUARE
1.8" SQUARE
2.2'' SQUARE
EXISTING PACKAGE COMPARISONS TO NEW DEVICE SIZES:
I/O LEADS
28
44
52
EXISTING DEVICES
24 PIN MSI
24 PIN SUB-NANOSECOND ECL
GENERAL INSTRUMENT 28 LEAD MINI-PAK
24/28 LEAD 3M TYPE CHIP CARRIER
40 PIN DIP MICROPROCESSORS
42 PIN ROCKWELL QUIP
48 PIN QUIL (MOTOROLA MC10800)
PROPOSED 52 PIN QUIP AND DIP PACKAGES
CURRENT NEEDS FOR 48/52 LEAD HIGH PERFORMANCE
PACKAGES
64 PIN DIP
68
PROPOSED QUIP AND QUAD PACKAGES
CURRENT NEED FOR HIGH PERFORMANCE PACKAGES
AMDAHL ECL PACKAGE
84
Table 3. Chip carrier packaging standardization.
JEDEC TASK FORCE JC1 1.3.1
TASK FORCE CHAIRMAN: DANIEL I. AMEY, SPERRY UNIVAC
PARTICI PANTS
BTL, BURROUGHS, HONEYWELL, IBM, RCA,
USERS:
ROCKWELL, SPERRY GYROSCOPE, WESTERN
ELECTRIC, XEROX
PACKAGE SUPPLIERS: AMP, BERG, COORS, KYOCERA, 3M
SOCKET SUPPLIERS: AMP, BERG, BURNDY, TECKNIT, TI, TRW CINCH
SEMICONDUCTOR
MANUFACTURERS:
EQUIPMENT
MANUFACTURERS:
64
FAIRCHILD, GENERAL INSTRUMENT, INTEL,
MOTOROLA, RCA, SIGNETICS, TI
JADE, KULICKE & SOFFA, USM
Socket standardization is an activity of the Electronic
Industries Association rather than of JEDEC, and one
of the members of the package standardization task force
was Max Peel, who had been active as a standardization
task force chairman for EIA. A socket standardization
task force was then set up after the package standardization task force had begun to reach its conclusions. One
possible socket type is shown in Figure 13.
The one important concept that is being advocated
with respect to the chip carrier sockets is that they
also may be attached to the underlying printed circuit
board by reflow soldering to surface lands.6 The sockets
attach to if it did not have a socket; this opens some
very interesting manufacturing choices. Just as in the
case of the dual in-line package where it is possible to
mount the DIP directly to the printed circuit board or
to use a socket without changing the board configuration,
that choice of plastic or ceramic packages with or without
sockets is also possible for chip carriers.
Advantages of leadless packages and
leadless sockets
One of the reasons for going to the chip carrier format
is to reduce the physical size of the package and its
required real estate area on the circutit board. This
reduction in size and board area is important for electrical
reasons because of the reduced lead inductance and the
improved high frequency limit. It is- also important
because of the savings in board real estate costs. Even
more significant is the savings in a system that may
require only half as many boards installed in half as many
cabinets. In fact, it is this reduction in cabinet cost and
cabinet wiring that is the single most important economic
factor in the use of chip carriers.
None of this reduction in cost through reduction in
occupied space on the printed circuit board can be realized
unless there is the ability to interconnect the chip carriers
in that reduced real estate. If the packing density of chip
carriers is determined by the maximum achievable circuit
density with a double-sided printed circuit board or a
multilayer board, a great deal of the possible cost savings
may be cancelled. Fortunately, however, the 50-mil spaced
reflow land pattern can be so arranged as to result in
board configurations that have increased routing capability
commensurate with the increased packing density. Consider the circuit board configuration of Figure 14. Here
COMPUTER
CERAMIC
COVER
. LEADLESS
TYPE A
TOP
PLASTIC
CAP
METAL
LEADLESS
TYPE B
HANDLING
SINGLE OR
MULTICHIP
HYBRID
EPOXY DROP
LEADED
TYPE B
LEADED
TYPE A
MINI-PAK
.-
BOTTOM
METALLIZED
PADS OPTIONAL
EDGE
CONDUCTORS
IN GROOVES
SOLDER
REFLOW
FEET
Figure 11. 0.050-inch center LSI package standards.
LEADLESS TYPE A
MINI-PAK
TED PADS
,HOLES
1
F
REQUIRES
<
MAY USE INTERCONNECTING
INTERCONNECTING-ELEMEN2I
ELEMENT OR BE SOLDERED
_'
-MUST BE SOLDERED
)
COMMON PC LAND CONFIGURATION
Figure 12. Mounting compatibility.
December 1977
65
the 50-mil lands are extended either inboard or outboard
in order to connect to a grid of via holes at 100-mil
centers that are in two concentric squares around the
edges of the chip carrier package footprint. These via
holes connected to the lands do not need to be large
enough to accept pins or DIP leads but may be 20-mil
diameter holes in a 30-mil-square pad. This reduced pad
size makes for larger spacing between pads that can
provide spaces for three conducting circuits instead of
two for high-density multilayer boards using 10-mil line
and space (Figure 15). Furthermore, it can also provide
two wiring channels instead of one for low-density conservative tolerance and double-sided printed circuit board
often used for memory circuits and consumer devices.
In either case, the achievable routing density is almost
doubled. Realistic circuit layouts using chip carriers can,
therefore, be designed so that the increase in packing
density can be realized in the circuit layout.
To achieve the maximum wiring and routing capability,
one must use a two-signal layer multilayer board with a
surface pad layer. This hollow square arrangement that
has many of its vias internal to the square can only be
utilized if it is possible for the leads to get into the square
through the solid phalanx of 50-mil center stripes around
the square. For logic circuits in a computer central
processor, such a multilayer board may be expected in
any event and its use would pose no hardship. But what
of memory boards? Memory boards have been two-sided
in the past, and it has been possible to route many of the
leads through the central channel of a DIP. If a solid array
of contacts on a chip carrier is substituted for the DIP,
these wiring pads are blocked. But there is a solution to
that problem. The chip carrier format only indicates the
possible lead and pad locations; it does not require that
all of them be occupied. For a memory circuit, therefore,
Figure 13. Possible socket assembly.
TOP LAYER LAYOUT
INTERNAL OR BOTTOM LAYOUT
n a a a a 0 n
W=
adi Lj t6di
-qv`.
a
n
rn'
X1 X X X X X
.1
.I
c
a
El
a
a
0
a
9
0 0
)
Q@
cm
__
9
)Q
a
_
.
.
.
0
. 9
lI . im
. a
18
im
EM
lm
©
©m a
1
.
_© ©
_
_
_
_
_
_
_
lI
IZ
NON-DEVICE CONNECTIONS
© DEVICE CONNECTIONS
Figure 14. Typical PC patterns for 68 leaded device.
66
COMPUTER
LOW DENSITY CONSERVATIVE TOLERANCES
HIGH DENSITY STRINGENT TOLERANCES
CONVENTIONAL "THRU HOLE" MOUNTING
.040" HOLE
i.-
CONVENTIONAL "THRU HOLE" MOUNTING
1
-0.1"
.040" HOLE
1.
.7.1.
|
.1
I-0
H
E0.1"
I
li,,-
Iw-.060" PAD-----
ONE .015" LINE WITH
.0125" SPACES IN
0.1 " CHANNEL
SURFACE MOUNTING
SURFACE MOUNTING
i'
'
TWO .015" LINES WITH
.010" SPACE IN 0.1" CHANNEL.
X,' $t .,$
0.1"
_-
THREE .010" LINES WITH
010" SPACE IN 0.1" CHANNEL.
-.020" HOLE
l-.030" PAD
Figure 15. PC board routing densities.
or any circuit using a two-sided printed circuit board,
one would use a chip carrier Wvhich has half of all its
leads omitted on the east and west sides. Figure 16 makes
it clear that the resultant open wiring channels are more
than adequate to make the necessary connections to the
chip carrier pads for such circuits. A 450-mil square
28-lead chip carrier can still provide 22 leads in this application and occupy a board area of 600 mils x 600 mils,
or 0.36 square inch. An equivalent DIP is typically 400
by 1100 mils occupying a board area of 500 by 1200, or
0.6 square inch-66 percent larger in board area requirements.
boards. For packages 80 leads and above, the chip carrier
packaging style offers an alternative to the staked pins
in the ceramic approach of IBM and others that was the
outgrowth of the IBM SLT technology. In fact, comparisons with such large packages indicate comparable
board area with, of course, the much greater availability
of sockets and interchangeable packaging types that are
the hallmark of this chip carrier concept. U
Status
The developments being reported in this paper have
been presented at Nepcon 77, and the individual papers
describing these developmments in greater detail are
listed in the references. The exciting thing about this
development has been the cooperation from more than
200 companies that have been assembled as a task force
to develop the standards by which all of these devices
and sockets can be made interchangeable. No new packaging concept will totally replace prior standard ways
of assembling electronic equipment, and this set of
package styles is no exception. In fact, it seems quite
likely that the 16-pin DIP package is here to stay and
is clearly more economical for the interconnection of LSI
circuits that can and do have 16 pins or fewer connections
to the circuit board. For 48- and 64-leaded chips, however,
the chip carrier seems to be a viable alternative to the
QUIP and DIP packages, especially in those circuits
that will use large numbers of such chips on single
December 1977
Figure16. Possible surface routing connections for reduced
110 packages.
67
Acknowledgments
References
The work of this chip carrier coordination has been
coordinated by Dan Amey of Sperry Univac, who heads
the package standard task force (JEDEC JC11.3.1), Max
Peel of Texas Instruments, who heads an EIA task force
(P5.2.6), and Jack Balde of Western Electric, who provided
the coordination with the Computer Packaging Committee.
Other major contributors included Bob Moore, Dave
Walker, Bill Hargis, John Bauer, Sal Acello, and Dimitry
Grabbe, all of whom were particularly active in the committee or were the authors of papers listed in the references. Many others were also involved but the particular
contributions of Bob White of Coors Corporation, Jim
Dillaplane of Berg, George Fujimoto from Kyocera, and
Bill Olsson and others from AMP were particuarly
helpful in developing the dimensional standards; Wolf
Knausenberger and Tony Close of Bell Telephone Laboratories and Don Franck of IBM made useful contributions
to the requirements and the considerations for the printed
circuit board routing.
1.
M. L. Burch and W. M. Hargis, "Ceramic Chip CarrierThe New Standard in Packaging?" Proc., Nepcon, 1977
2.
J. A. Bauer, "Use of Chip Carriers for High Reliability,
High Performance Product," Ibid.
I
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3.
S. Acello, "Mini-Pak-A Cost Effective Leadless Flat Pack,"
Ibid.
4.
D. G. Grabbe, "A Premolded Chip Carrier with Compliant
Leads," Ibid
5.
D. I. Amey and R. P. Moore, "AAn LSI Package Standard
and its Interconnection Variations," Ibid
6.
M. Peel, "Chip Carrier Sockets-What are the Options?"
Ibid.
John W. Balde is a research leader in interconnection technology development at the
Western Electric Engineering Research
Center in Princeton, New Jersey. He has
been active and holds patents in graphic display, tantalum thin film technology, and flat
cable technology. He has a BSEE from Rensselaer Polytechnic Institute and is a member
of Sigma Xi and a Senior Member of IEEE.
Balde was Chairman of the IEEE Computer
Society Computer Packaging Technical Committee at the time
the chip carrier standardization activity began and has served
as chairman of many chip carrier seminars as well as other packaging or systems interconnection conferences.
JANUARY 13-15,1978
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Daniel I. Amey is engineering manager of the
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5f
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Lehigh University in January 1977. He serves
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Group. He is also active in the IEEE Computer Society Packaging Committee and various EIA sponsored committees, and
is chairman of the JEDEC JC11.3.1 Task Group for standardization of LSI packages.
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