A 3V Rail-to-Rail CMOS Operational Amplifier
Oscar Calderón Prager, Francisco Javier Ramírez
Grupo de Sensores Integráveis e Microestruturas
Laboratório de Microeletrônica
Escola Politécnica - Universidade de São Paulo
Caixa Postal 61548, CEP 05424-970, São Paulo-SP
Fax : (55 11) 818 - 5585
http://www.lme.usp.br/sim
ocprager@lme.usp.br
jramirez@lme.usp.br
ABSTRACT
This work presents a compact two stage CMOS opamp with rail-to-rail input and output range.
The amplifier consists of a constant transconductance (gm) input stage and a class AB output stage
with its control shifted into the summing circuit. A floating current source biases the summing circuit
and the class AB control. This current source has the same power supply voltage dependency as the
class AB control, providing therefore a power supply independent quiescent current. The opamp was
designed to work with a 3 V power supply using the design rules of a conventional CMOS digital
0.7um techonology. Using a conventional Miller frequency compensation technique, its unity gain
frequency is 3.5 MHz and its open loop gain is 100dB.
INTRODUCTION
With the continuing trend towards supply voltages reduction, the design of compact
analog cells suitable for mixed mode VLSI systems becomes a difficult task, due to the
increasing problems inherent to minimum supply currents and voltages such as reduced
bandwidth, dynamic range and gain [1]. Also, the raising demand for portable equipment due
to the high density integration offered by new technologies, adds a special requirement for
high performance compact designs. In contrast with digital cells, analog circuits cannot
usually be designed with minimum lengths, for reasons of gain, offset, etc., so special
architectures and design techniques must be used. This work presents some ways of
overcoming these and other problems such as signal-to-noise ratio and frequency
compensation.
INPUT STAGE
In Fig. 1, the schematic diagram of the opamp is presented. The input stage has two
differential pairs in parallel. The P-channel input pair (M1-M2) can reach the negative supply
rail while the N-channel input pair (M3-M4) can reach the positive supply rail. This is made to
achieve rail-to-rail common mode input voltages, so a reasonable signal to noise ratio can be
obtained while operating at low voltages [2].
The operation requirement for this input stage is that the supply voltage must be of at
least:
Vsup,min = Vgsp + Vgsn + 2Vdsat
(1)
where Vgsp and Vgsn are the gate-source voltage of a p-channel and n-channel transistor
respectively, and Vdsat is the voltage across a current source which is necessary to ensure
that it operates as a current source.
Fig 1. Schematic diagram of the rail-to-rail opamp
This architecture, however, has a drawback in that the gm varies by a factor of two
over its common mode input range [3], which impedes an optimal frequency compensation
[4]. To overcome this problem, a control circuit that mantains the gm constant is included in
the input stage. It consists of two switches (M5, M8) that take away the tail current (It) of the
non-operating input pair when low (VSS + 1V) and high (VDD - 1V) common mode input
voltages are applied. This current is multiplied by a factor of three (by means of the current
mirrors M6-M7 and M9-M10 which have a gain of three) and added to the tail current of the
operating pair. If both tail currents are equal, a constant tail current 4It polarizes both input
pairs, guaranteeing a constant gm, since it is proportional to the root square of the drain
current of a transistor, when it is operating on strong inversion. At intermediate common
mode input voltages (between VSS + 1V and VDD - 1V) both input pairs operate and both
switches are off, so each input pair is polarized by a constant tail current equal to It. The
drain currents of the input transistors are fed into a summing circuit that at the same time
implements the class AB control for the output stage, as explained in the next section.
OUTPUT STAGE
A class AB biasing is used for the common source connected output transistors (M25M26). This is done to make an efficient use of the supply voltage and supply current [5]. The
floating class AB control keeps the voltage between the gates of the output transistors
constant and it is formed by transistors M19 and M20. It uses two loops: M20-M21-M22-M25
and M19-M23-M24-M26 to achieve this. The class AB control is implemented within the
summing circuit, saving die area and avoiding a unity gain frequency decrease due to an
extra stage. In order to make the quiescent current of the output transistors insensitive to
supply voltage variations, the summing circuit current mirrors (M11-M14 and M15-M18) are
biased by a floating current source (M27-M28) that has the same supply voltage dependency
as the class AB control. This also contributes to the reduction of the noise and offset of the
opamp. A conventional Miller frequency compensation technique is used with two capacitors
CM1 and CM2 connected to the output transistors.
SIMULATION RESULTS
The opamp showed a good performance after simulations. It has an open loop gain of
100 dB and a unity gain frequency of 3,5 MHz, as shown in Fig. 2. The unity gain phase
margin is 40°. Its slew rate is 2 V/µs aproximately, and its CMRR is 90 dB. The input gm is
approximately constant over its common mode input range, except at the points where the
current through the current switches (M5, M8) changes. At this point the variation is only
15%. Due to its compact design, its power consumption is 160 µW, making it possible to use
this circuit in low-power portable systems. The final layout of the opamp is shown in Fig. 3. It
occupies a total die area of 0.4 mm2 without pads. The circuit is being manufactured.
Fig. 2. Frequency response
Fig.3 Layout of the opamp
ACKNOWLEDGMENTS
This research is sponsored by FAPESP, under its 95/1358-6 process.
REFERENCES
[1]
[2]
[3]
[4]
[5]
SETTY, S; TOUMAZOU, C. +/- 1 V CMOS rail to rail op amp. Proceedings of the
1995 IEEE Symposium of Circuits and Systems.
HOGERVORST, R.; TERO, J. P.; ESCHAUZIER, R. G. H.; HUIJSING, J. H. A
compact power-efficient rail-to-rail input/output operational amplifier for VLSI cells
libraries. IEEE journal of solid-state circuits, vol. 29, no. 6, Dec 1994.
NAGARAJ, K. Constant transconductance CMOS amplifier input stage with rail-to-rail
input common mode voltage range. IEEE transactions on circuits and systems-II:
analog and digital signal processing, vol. 42, no. 5, May 1995.
HUIJSING, J. H.; LINEBARGER, D. Low-voltage operational amplifier with rail-to-rail
input and output ranges. IEEE journal of solid-state circuits, vol. SC-20, Dec 1985.
GRADINARIU, I.; GONTRAND, C. A fast settling 3 V CMOS buffer amplifier. IEEE
transactions on circuits and systems-I: fundamental theory and applications, vol. 43,
no. 6, June 1996.