Introduction to HW/SW Co-Design of Embedded Systems Prof. Cristina SILVANO Politecnico di Milano Dipartimento di Elettronica e Informazione P.za L. Da Vinci 32, I-20133 Milano (Italy) Ph.: +39-02-2399-3692 e-mail: silvano@elet.polimi.it Web site: http://www.elet.polimi.it/~silvano Prof. C. SILVANO, Politecnico di Milano, 2004 - 1- Outline •• Embedded Embedded Systems Systems Overview Overview •• Design Design Methodologies Methodologies •• Hardware-Software Hardware-Software Co-Design Co-Design Flow Flow •• Optimizing Optimizing Design Design Metrics Metrics •• Design Design Technologies Technologies •• Design Design Productivity Productivity Gap Gap Prof. C. SILVANO, Politecnico di Milano, 2004 - 2- 1 Embedded Systems Overview Prof. C. SILVANO, Politecnico di Milano, 2004 - 3- Embedded Systems Overview •• •• Computing Computing systems systems are are everywhere everywhere Most of us think of “desktop” Most of us think of “desktop” computers computers –– PC’s PC’s –– Laptops Laptops –– Mainframes Mainframes –– Servers Servers •• But But there’s there’s another another type type of of computing computing system system –– Far Far more more common... common... Prof. C. SILVANO, Politecnico di Milano, 2004 - 4- 2 Embedded Systems Overview •• Embedded Embedded computing computing systems systems –– Computing Computing systems systems embedded embedded within within electronic electronic devices devices –– Hard Hard to to define. define. Nearly Nearly any any computing system computing system other other than than aa desktop computer desktop computer –– Billions Billions of of units units produced produced yearly, yearly, versus versus millions millions of of desktop desktop units units –– Perhaps Perhaps 50 50 per per household household and and per automobile per automobile Embedded systems are in here... and here... and even here... Prof. C. SILVANO, Politecnico di Milano, 2004 - 5- Embedded Systems Embedded systems (ES) = information processing systems embedded into a larger product Examples: Main reason for buying is not information processing Prof. C. SILVANO, Politecnico di Milano, 2004 - 6- 3 Application Areas (1) •• Automotive Automotive electronics electronics •• Aircraft Aircraft electronics electronics •• Trains Trains •• Telecommunication Telecommunication Prof. C. SILVANO, Politecnico di Milano, 2004 - 7- Application Areas (2) •• Medical Medical systems systems •• Military Military applications applications •• Authentication Authentication Prof. C. SILVANO, Politecnico di Milano, 2004 - 8- 4 Application Areas (3) •• Consumer Consumer electronics electronics •• Fabrication Fabrication equipment equipment •• Smart Smartbuildings buildings Prof. C. SILVANO, Politecnico di Milano, 2004 - 9- Application Areas (4) ••Robotics Robotics Robot „Johnnie“ (Courtesy and ©: H.Ulbrich, F. Pfeiffer, TU München) Prof. C. SILVANO, Politecnico di Milano, 2004 - 10 - 5 A “short list” of embedded systems Anti-lock brakes Auto-focus cameras Automatic teller machines Automatic toll systems Automatic transmission Avionic systems Battery chargers Camcorders Cell phones Cell-phone base stations Cordless phones Cruise control Curbside check-in systems Digital cameras Disk drives Electronic card readers Electronic instruments Electronic toys/games Factory control Fax machines Fingerprint identifiers Home security systems Life-support systems Medical testing systems Modems MPEG decoders Network cards Network switches/routers On-board navigation Pagers Photocopiers Point-of-sale systems Portable video games Printers Satellite phones Scanners Smart ovens/dishwashers Speech recognizers Stereo systems Teleconferencing systems Televisions Temperature controllers Theft tracking systems TV set-top boxes VCR’s, DVD players Video game consoles Video phones Washers and dryers - 11 - Prof. C. SILVANO, Politecnico di Milano, 2004 An embedded system example: Digital camera Digital camera chip CCD A2D CCD preprocessor Pixel coprocessor D2A lens JPEG codec Microcontroller Multiplier/Accum DMA controller Memory controller Display ctrl ISA bus interface UART LCD ctrl • Single-functioned: Always a digital camera • Tightly-constrained: Low cost, low power, small, fast • Reactive and real-time: Only to a small extent Prof. C. SILVANO, Politecnico di Milano, 2004 - 12 - 6 Some common characteristics of embedded systems •• Single-functioned Single-functioned –– Executes Executes aa single single program, program, repeatedly repeatedly •• Tightly-constrained Tightly-constrained –– Low Low cost, cost, low low power, power, small, small, fast, fast, etc. etc. •• Reactive Reactive and and real-time real-time –– Continually Continually reacts reacts to to changes changes in in the the system’s system’s environment environment –– Must Must compute compute certain certain results results in in real-time real-time without delay without delay Prof. C. SILVANO, Politecnico di Milano, 2004 - 13 - Characteristics of Embedded Systems (1) ••Must Must be bedependable, dependable, •• Reliability ReliabilityR(t) R(t) == probability probability of of system system working working correctly provided that is was working at correctly provided that is was working att=0 t=0 •• Maintainability MaintainabilityM(d) M(d) == probability probabilityof ofsystem systemworking working correctly d time units after error occurred. correctly d time units after error occurred. •• Availability: Availability: probability probability of of system system working workingat attime timett •• Safety: no harm to be caused Safety: no harm to be caused •• Security: Security: confidential confidential and and authentic authentic communication communication •• Even perfectly designed systems Even perfectly designed systemscan canfail failififthe the assumptions about the workload and possible assumptions about the workload and possible errors errors turn turnout outto tobe bewrong. wrong. •• Making Making the the system system dependable dependablemust mustnot notbe bean anafterafterthought, it must be considered from the very beginning thought, it must be considered from the very beginning Prof. C. SILVANO, Politecnico di Milano, 2004 - 14 - 7 Characteristics of Embedded Systems (2) •• Must Must be be efficient efficient –– Energy Energy efficient efficient –– Code-size Code-size efficient efficient (especially (especially for for systems systems on on aa chip) chip) –– Run-time Run-time efficient efficient –– Weight Weight efficient efficient –– Cost Cost efficient efficient •• Dedicated Dedicated towards towards aa certain certain application application •• Dedicated Dedicated user user interface interface (no mouse, keyboard (no mouse, keyboard and and screen) screen) Prof. C. SILVANO, Politecnico di Milano, 2004 - 15 - Characteristics of Embedded Systems (3) •• Many Many ES ES must must meet meet real-time real-time constraints constraints –– AA real-time system must react real-time system must react to to stimuli stimuli from from the the controlled controlled object object (or (or the the operator) operator) within within the the time interval dictated by the environment. time interval dictated by the environment. –– For For real-time real-time systems, systems, right right answers answers arriving arriving too too late are wrong. late are wrong. –– „A „A real-time real-time constraint constraint is is called called hard, hard, ifif not not meeting that constraint could result in a meeting that constraint could result in a catastrophe“ catastrophe“ [Kopetz, [Kopetz, 1997]. 1997]. –– All All other other time-constraints time-constraints are are called called soft. soft. Prof. C. SILVANO, Politecnico di Milano, 2004 - 16 - 8 Characteristics of Embedded Systems (4) •• Frequently Frequently connected connected to to physical physical environment environment through sensors and actuators, through sensors and actuators, •• Hybrid Hybrid systems systems (analog (analog + + digital digital parts). parts). •• Typically, Typically, ES ES are are reactive reactive systems: systems: „A „A reactive reactive system system isis one one which which isis in in continual continual interaction interaction with with isis environment environment and and executes executes at at aa pace pace determined determined by by that environment“ [Bergé, 1995] that environment“ [Bergé, 1995] Behavior Behavior depends depends on on input input and and current current state. state. ) ) Automata Automata model model appropriate, appropriate, model model of of computable computable functions functions inappropriate. inappropriate. Prof. C. SILVANO, Politecnico di Milano, 2004 - 17 - Characteristics of Embedded Systems (5) Not Not every every ES ES has has all all of of the the above above characteristics. characteristics. Def.: Def.: Information Information processing processing systems systems having having most of the above characteristics are called most of the above characteristics are called embedded embedded systems. systems. Methodologies Methodologies for for embedded embedded systems systems design design makes makes sense sense because because of of the the number number of of common common characteristics. characteristics. Prof. C. SILVANO, Politecnico di Milano, 2004 - 18 - 9 IC Technology towards the System-On-Chip Approach - 19 - Prof. C. SILVANO, Politecnico di Milano, 2004 IC Technology towards the System-On-Chip Approach • Evolution of microelectronic technology, design methodology and EDA tool enables the System-On-Chip (SOC) approach. Satellite (DVB) Video Broadcasting Multimedia Game System Prof. C. SILVANO, Politecnico di Milano, 2004 Wireless GSM Pocket Communicator - 20 - 10 System-On-Chip Approach •• The The evolution evolution of of SOC SOC approach approach opens opens new new perspectives to HW/SW codesign. perspectives to HW/SW codesign. •• Specification Specification languages languages and and system-level system-level modelling assume fundamental modelling assume fundamental importance importance to to support support mixed mixed HW/SW HW/SW descriptions. descriptions. •• Based Based on on integration integration of of off-the-shelf off-the-shelf blocks as core processors blocks as core processors and and reuse reuse of of IP IP (Intellectual Property) blocks and cells. (Intellectual Property) blocks and cells. Prof. C. SILVANO, Politecnico di Milano, 2004 - 21 - Embedded systems and ubiquitous computing Ubiquitous Ubiquitous (or (or pervasive) pervasive) computing: computing: Information Information available available anytime, anytime, anywhere. anywhere. Embedded Embedded systems systems provide provide fundamental fundamental technology. technology. Ist.gif UMTS, Prof. C. SILVANO, Politecnico di Milano, 2004 - 22 - 11 Embedded Systems Market •• Growing Growing economical economical importance importance of of embedded embedded systems systems –– .... but but embedded embedded chips chips form form the the backbone backbone of of the the electronics driven world in which we live ... electronics driven world in which we live ... they they are are part part of almost everything that runs on electricity of almost everything that runs on electricity [Mary [Mary Ryan, Ryan, EEDesign, EEDesign, 1995] 1995] –– 79% 79% of of all all high-end high-end processors processors are are used used in in embedded systems embedded systems –– THE THE growing growing area, area, according according to to all all forecasts forecasts Prof. C. SILVANO, Politecnico di Milano, 2004 - 23 - Importance of Embedded Software and Embedded Processors “... the New York Times has estimated that the average American comes into contact with about 60 micro-processors every day....” [Camposano, 1996] Latest top-level BMWs contain over 100 micro-processors ... it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development [A. Sangiovanni-Vincentelli, 1999] Most of the functionality of embedded systems will be implemented in software! Prof. C. SILVANO, Politecnico di Milano, 2004 - 24 - 12 Importance of Embedded Software and Embedded Processors ... ...dramatic dramatic growth growthof ofthe thenumber numberof ofembedded embeddedapplications applications and the size and the complexity of the and the size and the complexity of thesoftware softwareused usedin in these applications. these applications. For For many many products products in in the the area areaof ofconsumer consumerelectronics electronicsthe the amount of code is doubling every two years. amount of code is doubling every two years. [Fritz Vaandrager in: Rozenberg, Vaandrager (eds.): Lectures on Embedded Systems, LNCS, Vol. 1494, 1998] Prof. C. SILVANO, Politecnico di Milano, 2004 - 25 - Views on embedded software •• It It isis estimated estimated that that each each year year embedded embedded software software isis written written five five times times as as much much as as 'regular' 'regular' software software •• The The vast vast majority majority of of CPU-chips CPU-chips produced produced world-wide world-wide today today are used in the embedded market ... ; are used in the embedded market ... ; only only aa small small portion portion of of CPU's CPU's isis applied applied in in PC's PC's •• ... ... the the number number of of software-constructors software-constructors of of Embedded Embedded Systems Systems will will rise rise from from 22 million million in in 1994 1994 to to 10 10 million million in in 2010; 2010; ... ... the the number number of of constructors constructors employed employed by by softwaresoftwareproducers producers 'merely' 'merely' rises rises from from 0.6 0.6 million million to to 1.1 1.1 million. million. [Department of Trade and Industry/ IDC Benelux BV: Embedded software research in the Netherlands. Analysis and results, 1997 (according to: www.scintilla.utwente.nl/shintabi/engels/thema_text.html)] Prof. C. SILVANO, Politecnico di Milano, 2004 - 26 - 13 Cost of Software in Embedded Systems Prof. C. SILVANO, Politecnico di Milano, 2004 - 27 - What‘s the problem? If embedded systems will be implemented mostly in software, then why don‘t we just use what software engineers have come up with? Prof. C. SILVANO, Politecnico di Milano, 2004 - 28 - 14 Some open problems ••How How can can we we capture capture the therequired required behavior behavior of of complex complex systems ? systems ? ••How How do do we we validate validate specifications? specifications? ••How How do do we we translate translate specifications specifications efficiently efficiently into into implementation? implementation? ••Do Dosoftware softwareengineers engineersever everconsider consider power power dissipation? dissipation? ••How How can can we we check check that that we wemeet meet real-time real-time constraints? constraints? ••Which Which programming programming language language provides providesreal-time real-timefeatures? features? ••How Howdo dowe wevalidate validateembedded embedded real-time real-time software? software? (large volumes of data, testing may (large volumes of data, testing maybe besafety-critical) safety-critical) - 29 - Prof. C. SILVANO, Politecnico di Milano, 2004 The co-design ladder •• In Inthe thepast: past: –– Hardware Hardwareand andsoftware software design technologies design technologies were werevery verydifferent different –– Recent maturation Recent maturationof of synthesis synthesisenables enablesaa unified unifiedview viewof of hardware hardwareand andsoftware software Sequential program code (e.g., C, VHDL) Behavioral synthesis (1990's) Compilers (1960's,1970's) Register transfers Assembly instructions Assemblers, linkers (1950's, 1960's) RT synthesis (1980's, 1990's) Logic equations / FSM's Logic synthesis (1970's, 1980's) Machine instructions Logic gates •• Now: Now: –– Hardware/software Hardware/software “codesign” “codesign” Microprocessor plus program bits: “software” Implementation VLSI, ASIC, or PLD implementation: “hardware” The choice of hardware versus software for a particular function is simply a tradeoff among various design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no fundamental difference between what hardware or software can implement. Prof. C. SILVANO, Politecnico di Milano, 2004 - 30 - 15 Design Methodologies Prof. C. SILVANO, Politecnico di Milano, 2004 - 31 - Design Methodologies •• •• A A procedure procedure for for designing designing aa system system Many systems are complex and Many systems are complex and pose pose many many design challenges: Large specifications, design challenges: Large specifications, short short time-to-market, time-to-market, high high performance, performance, multiple multiple designers, designers, interface interface to to manufacturing. manufacturing. •• Proper design methodology Proper design methodology helps helps to to manage manage the design process and improves quality, the design process and improves quality, performance performance and and design design costs costs Prof. C. SILVANO, Politecnico di Milano, 2004 - 32 - 16 Design Flow •• A A sequence sequence of of design design steps steps in in aa design design methodology methodology •• The The design design flow flow can can be be partially partially or or fully fully automated automated •• A A set set or or tools tools can can be be used used to to automate automate the the methodology steps: methodology steps: –– Software Software engineering engineering tools, tools, –– Compilers, Compilers, –– Computer-Aided Computer-Aided Design Design tools, tools, –– etc. etc. Prof. C. SILVANO, Politecnico di Milano, 2004 - 33 - Design goals •• To To provide provide the the target target functionality functionality and and user user interface interface meeting meeting the the system system level level requirements requirements in in terms terms of: of: –– Performance Performance (latency (latency and and throughput) throughput) –– Power Power consumption consumption –– Design Design and and manufacturing manufacturing costs costs –– Other requirements (physical Other requirements (physical size, size, weight, weight, etc.) etc.) Prof. C. SILVANO, Politecnico di Milano, 2004 - 34 - 17 A simplified design flow System-Level Requirements System-Level Specification Architecture Definition HW Design SW Design System Integration and Validation Prof. C. SILVANO, Politecnico di Milano, 2004 - 35 - System-Level Requirements •• Plain Plain language language description description of of what what the the user user wants wants and and expects expects to to gets gets •• May May be be developed developed in in several several ways: ways: talking talking directly directly to to customers, customers, talking talking to to marketing marketing representative, representative, etc. etc. •• Functional requirements: Functional requirements: –– To To describe describe outputs outputs as as aa function function of of inputs inputs •• Non-functional Non-functional requirements: requirements: –– Performance (latency Performance (latency and and throughput), throughput), power consumption, reliability, power consumption, reliability, sizes, sizes, weight, weight, reliability, reliability, etc. etc. Prof. C. SILVANO, Politecnico di Milano, 2004 - 36 - 18 System-Level Specification •• A A more more precise precise description description of of the the system system behavior behavior –– Should Should not not yet yet imply imply aa target target architecture architecture –– Provides Provides inputs inputs to to the the architecture architecture design design process process •• May May include include functional functional and and non-functional non-functional requirements requirements •• May May be be executable executable for for simulation simulation or or may may be be in mathematical form for formal verification. in mathematical form for formal verification. Prof. C. SILVANO, Politecnico di Milano, 2004 - 37 - Architecture Design •• How How HW HW and and SW SW components components can can satisfy satisfy the the specification? specification? •• HW HW Components: Components: –– Processor, Processor, Memory, Memory, Peripherals, Peripherals, etc. etc. •• SW SW Components: Components: –– Programs Programs and and their their operations operations •• Some Some components components are are already already available available (design reuse), some can be modified (design reuse), some can be modified from from existing existing designs, designs, some some others others must must be be designed designed from from scratch scratch Prof. C. SILVANO, Politecnico di Milano, 2004 - 38 - 19 System Integration •• Put Put together together the the HW HW and and SW SW components components of of the system the system •• The The components components can can be: be: –– Executable Executable models models –– Physical Physical prototypes prototypes •• The system The system integration integration phase phase is is crucial crucial to to validate the interaction among the different validate the interaction among the different system system components. components. •• Many Many system-level system-level bugs bugs can can be be discovered discovered only at this stage only at this stage •• It It would would be be convenient convenient to to validate validate system system integration as early as possible! integration as early as possible! Prof. C. SILVANO, Politecnico di Milano, 2004 - 39 - Levels of Abstraction • Define the levels of detail in the description of the component and system models: –System Level –Behavioral Level –Architectural or RT (Register Transfer) Level –Logic Level –Layout Level Prof. C. SILVANO, Politecnico di Milano, 2004 - 40 - 20 Top-down Design Approach •• Top-down Top-down design design approach: approach: –– Start Start from from the the most most abstract abstract description description down to the most detailed low-level down to the most detailed low-level description description –– Stepwise Stepwise refinement refinement process: process: ••At At each each level level of of abstraction, abstraction, we we must must analyze the design to determine analyze the design to determine the the characteristics characteristics of of the the current current state state of of the design the design ••To To refine refine the the design design descriptions descriptions by by adding details. adding details. Prof. C. SILVANO, Politecnico di Milano, 2004 - 41 - Bottom-up Design Approach •• Bottom-up Bottom-up design design approach: approach: –– Start from small Start from small component component design design to to system integration system integration –– Based Based on on the the Reuse Reuse of of Intellectual Intellectual Property (IP) components Property (IP) components Prof. C. SILVANO, Politecnico di Milano, 2004 - 42 - 21 HW/SW Co-design Flow Prof. C. SILVANO, Politecnico di Milano, 2004 - 43 - What is HW/SW Co-design? •• HW/SW HW/SW Co-design Co-design is is the the field field that that emphasizes emphasizes aa unified unified view view of of HW HW and and SW SW and and develops synthesis tools and simulators that develops synthesis tools and simulators that enable enable the the co-development co-development of of systems systems by by using both hardware and software. using both hardware and software. •• Main Main goal: goal: To To meet meet the the design design goals goals at at the the system-level system-level exploiting exploiting the the synergy synergy of of HW HW and and SW SW parts parts through through their their concurrent concurrent design. design. Prof. C. SILVANO, Politecnico di Milano, 2004 - 44 - 22 HW/SW Co-design: Main Advantages •• •• •• •• •• •• To To explore explore different different design design alternatives. alternatives. To To evaluate evaluate cost-performance cost-performance trade-offs trade-offs To reduce system design time ⇒ To reduce system design time ⇒ Reduction Reduction of product time-to-market and cost of product time-to-market and cost To To improve improve product product quality quality through through design design process optimization process optimization To To support support system-level system-level specifications specifications ⇒ ⇒ To To facilitate facilitate the the reuse reuse of of hardware hardware and and software parts. software parts. To To provide provide an an integrated integrated framework framework for for the the synthesis and validation of hardware and synthesis and validation of hardware and software software components. components. Prof. C. SILVANO, Politecnico di Milano, 2004 - 45 - HW/SW Co-design Flow Prof. C. SILVANO, Politecnico di Milano, 2004 - 46 - 23 Main phases of HW/SW co-design process •• •• •• •• •• •• •• •• •• Requirements Requirements Analysis Analysis Functional Functional Specification Specification (System (System Modelling) Modelling) Task Task Concurrency Concurrency Management Management High-level Transformations High-level Transformations Design Design Space Space Exploration Exploration HW/SW HW/SW Partitioning Partitioning Compilation Compilation and and Scheduling Scheduling Co-synthesis Co-synthesis Co-simulation Co-simulation and and co-verification co-verification Prof. C. SILVANO, Politecnico di Milano, 2004 - 47 - Overview of co-design phases •• Functional Functional Specification Specification (System-Level (System-Level Modelling): Modelling): to to capture capture the the system system functionality in a formal language. functionality in a formal language. •• Task Task Concurrency Concurrency Management: Management: To To identify identify and and to to manage manage tasks tasks in in the the system; system; To define tasks granularity (size of tasks) To define tasks granularity (size of tasks) •• High-level High-level Transformations: Transformations: To To apply apply some some optimizing optimizing high-level high-level transformations transformations (that (that are are outside outside the the scope scope of of traditional traditional compilers). For example: Loops compilers). For example: Loops can can be be interchanged so that accesses to interchanged so that accesses to arrays arrays in in memory can exploit more locality. memory can exploit more locality. Prof. C. SILVANO, Politecnico di Milano, 2004 - 48 - 24 Overview of co-design phases •• Design Design Space Space Exploration: Exploration: To To evaluate evaluate different different design design alternatives alternatives in in terms terms of of power-performance trade-offs power-performance trade-offs •• HW/SW HW/SW Partitioning: Partitioning: To To map map system system functionalities to either hardware functionalities to either hardware or or software. software. •• Compilation Compilation and and Scheduling: Scheduling: HardwareHardwareaware aware compilation compilation (for (for example example energy-aware energy-aware compilation) compilation) and and scheduling scheduling (mapping (mapping of of operations to control steps). operations to control steps). Prof. C. SILVANO, Politecnico di Milano, 2004 - 49 - Overview of co-design phases •• Co-synthesis: Co-synthesis: To To automatically automatically derive derive aa system system implementation implementation –– Hardware Hardware synthesis synthesis of of dedicated dedicated units units –– Software synthesis for processors Software synthesis for processors (Specialized (Specialized compiling compiling techniques) techniques) –– Interface Interface synthesis synthesis to to support support HW/SW HW/SW interface interface and and synchronization synchronization •• Co-simulation Co-simulation and and co-verification: co-verification: To To validate validate the the design design descriptions descriptions with with respect to system-level requirements. respect to system-level requirements. Prof. C. SILVANO, Politecnico di Milano, 2004 - 50 - 25 HW/SW Partitioning To To map map system system functionalities functionalities to to either either dedicated HW components or SW dedicated HW components or SW (processors). (processors). •• One One extreme: extreme: Fully Fully HW HW solution solution –– High performance due High performance due to to parallelism parallelism –– High High cost cost and and long long design design time time •• Other Other extreme: extreme: Fully Fully SW SW solution solution –– High-performance low-cost High-performance low-cost processors processors –– Operations serialization Operations serialization –– Lack Lack of of support support for for specific specific tasks tasks •• Best solution: Mix of HW and SW Best solution: Mix of HW and SW components components based based on on cost-performance cost-performance trade-offs trade-offs Prof. C. SILVANO, Politecnico di Milano, 2004 - 51 - HW/SW Partitioning Goals •• To To speed-up speed-up software software execution execution –– By migrating critical By migrating critical SW SW functions functions to to dedicated HW dedicated HW •• To To reduce reduce the the cost cost of of hardware hardware implementation implementation –– By By migrating migrating non-critical non-critical hardware hardware functions functions to to software software running running on on processor processor core core •• To To achieve achieve system system prototypes prototypes –– By By migrating migrating functions functions to to the the prototype prototype medium medium Prof. C. SILVANO, Politecnico di Milano, 2004 - 52 - 26 Open issues in HW/SW partitioning •• Object Object granularity granularity in in partitioning partitioning •• Estimation Estimation of of performance performance and and cost cost metrics metrics from graph model of the system from graph model of the system •• Integrate Integrate the the designer’s designer’s experience experience in in biasing a partition biasing a partition Prof. C. SILVANO, Politecnico di Milano, 2004 - 53 - Co-synthesis after partitioning •• To To automatically automatically derive derive aa system system implementation implementation –– Hardware Hardware synthesis synthesis of of dedicated dedicated units units –– Software synthesis for processors Software synthesis for processors (Specialized (Specialized compiling compiling techniques) techniques) –– Interface synthesis to support Interface synthesis to support HW/SW HW/SW interface interface and and synchronization synchronization of of SW SW functions functions identified identified by by program program threads threads •• A A single single processor processor requires requires threads threads serialization serialization or or interleaving interleaving •• Scheduling Scheduling of of threads threads and and instructions instructions –– Satisfying Satisfying performance performance constraints constraints •• System-level System-level run-time run-time scheduler scheduler to to synchronize SW and HW functions synchronize SW and HW functions Prof. C. SILVANO, Politecnico di Milano, 2004 - 54 - 27 HW Synthesis •• After After partitioning, partitioning, HW HW behavior behavior is is still still described at high-level of abstraction described at high-level of abstraction (behavioral (behavioral level) level) •• High-level High-level synthesis synthesis alternatives: alternatives: –– Manual translation Manual translation to to RTL RTL (Register (Register Transfer Level) description Transfer Level) description –– Use Use behavioral behavioral synthesis synthesis tools tools Prof. C. SILVANO, Politecnico di Milano, 2004 - 55 - SW Synthesis •• SW SW synthesis synthesis for for processors processors is is based based on on specialized specialized compiling compiling techniques techniques •• SW SW synthesis synthesis may may be be preceded preceded by by automatic automatic SW SW generation generation steps steps •• Compilation Compilation characteristics characteristics in in embedded embedded systems systems –– Code Code is is compiled compiled once once ⇒ ⇒ Compilation Compilation time time is not important, maximum optimization is not important, maximum optimization is is desired desired –– Performance Performance constraints constraints ⇒ ⇒ Code Code must must be be tight and fast ⇒ Assembly code tight and fast ⇒ Assembly code –– Energy-aware Energy-aware compilation compilation for for low-power low-power portable embedded systems portable embedded systems Prof. C. SILVANO, Politecnico di Milano, 2004 - 56 - 28 Interface Synthesis •• Interfacing Interfacing processors processors to to ASICs ASICs and and peripheral devices peripheral devices •• Device Device drivers drivers may may be be in in SW SW or or in in HW HW •• Define Define models models for for communication communication mechanisms mechanisms •• Scheduling Scheduling the the processor processor communication communication - 57 - Prof. C. SILVANO, Politecnico di Milano, 2004 HW/SW Co-design at System-Level System Soft IP Physical System Level IP RTL HW Implementation Verification & Analysis SW Implementation System Level Design RTL to GDS II Synthesis Flow C Compiler Assembler Link Editor (IDE) Hard IP Prof. C. SILVANO, Politecnico di Milano, 2004 - 58 - 29 HW/SW Co-Design Architectural Design C/C++ Functional Design C/C++ HW/SW Integration + a.out - 59 - Prof. C. SILVANO, Politecnico di Milano, 2004 System-Level Design Flow Based on a Common HW/SW Language Algorithm C/C++ Architecture Application Executable Specification Hardware Synthesis C/C++ Software Synthesis Application RTOS, Protocols Device Drivers Prof. C. SILVANO, Politecnico di Milano, 2004 - 60 - 30 Optimizing Design Metrics Prof. C. SILVANO, Politecnico di Milano, 2004 - 61 - Design goals: Optimizing design metrics •• Obvious Obvious design design goal: goal: –– Design an implementation Design an implementation with with desired desired functionality functionality •• Key Key design design challenge: challenge: –– Simultaneously Simultaneously optimize optimize several several design design metrics metrics •• Design Design metric metric –– A A measurable measurable feature feature of of aa system’s system’s implementation implementation –– Optimizing Optimizing design design metrics metrics is is aa key key challenge challenge Prof. C. SILVANO, Politecnico di Milano, 2004 - 62 - 31 Design goals: Optimizing design metrics •• Common Common metrics metrics ––Unit Unit cost: cost: Monetary Monetary cost cost of of manufacturing manufacturing each each copy copy of of the the system, system, excluding excluding NRE NRE cost cost ––NRE NRE cost cost (Non-Recurring (Non-Recurring Engineering Engineering cost): cost): One-time One-time monetary monetary cost cost of of designing designing the the system system ––Size: Size: Physical Physical space space required required by by the the system system ––Performance: Performance: Execution Execution time time or or throughput throughput of of the the system system ––Power: Power: Amount Amount of of power power consumed consumed by by the the system system ––Flexibility: Flexibility: Ability Ability to to change change the the functionality functionality of of the the system system without without incurring incurring heavy heavy NRE NRE cost cost Prof. C. SILVANO, Politecnico di Milano, 2004 - 63 - Design goals: Optimizing design metrics Common Common metrics metrics (continued) (continued) –– Time-to-prototype: Time-to-prototype: Time Timeneeded neededto tobuild buildaaworking working version versionof ofthe thesystem system –– Time-to-market: Time-to-market: Time Timerequired requiredto todevelop develop aasystem systemto to the thepoint pointthat thatititcan canbe bereleased releasedand andsold soldto tocustomers customers –– Maintainability: Maintainability: Ability Abilityto tomodify modifythe thesystem systemafter afterits its initial initialrelease release –– Correctness: Correctness: Confidence Confidence to to have have implemented implemented the the system’s system’s functionality functionality correctly correctly –– Safety: Safety: Probability Probability that that the the system system will will no no cause cause harm harm –– Many Many more… more… Prof. C. SILVANO, Politecnico di Milano, 2004 - 64 - 32 Design metric competition: Improving one may worsen others Power Performance Size NRE cost Expertise Expertise with with both both software software and and hardware hardware is is needed to optimize design metrics needed to optimize design metrics –Not –Not just just aa hardware hardware or or software software expert, expert, as as is is common common –The –The designer designer must must be be able able to to migrate migrate from from one one technology to another in order to find the technology to another in order to find the best best implementation implementation for for aa given given application application and and constraints constraints - 65 Prof. C. SILVANO, Politecnico di Milano, 2004 Revenues ($) Time-to-market: A demanding design metric Time (months) Prof. C. SILVANO, Politecnico di Milano, 2004 •Time •Time required required to to develop develop aa product product to to the the point point itit can can be be sold sold to to customers customers •Market window •Market window –Period –Period during during which which the the product product would would have have highest highest sales sales •Average •Average time-to-market time-to-market constraint constraint is is about about 88 months months •Delays •Delays can can be be costly costly - 66 - 33 Losses due to delayed market entry •Simplified •Simplified revenue revenue model model –Product –Product life life = = 2W, 2W, peak peak at at W W –Time of –Time of market market entry entry defines a triangle, defines a triangle, representing representing market market penetration penetration –Triangle –Triangle area area equals equals revenue revenue •Loss •Loss –The –The difference difference between between the on-time the on-time and and delayed delayed triangle triangle areas areas Peak revenue Revenues ($) Peak revenue from delayed entry On-time Market fall Market rise Delayed D On-time entry W 2W Time Delayed entry Prof. C. SILVANO, Politecnico di Milano, 2004 - 67 - Revenues ($) Losses due to delayed market entry (cont.) On-time Market rise Delayed D On-time entry Delayed entry •Area •Area = = 1/2 1/2 ** base base ** height height –On-time = 1/2 * 2W –On-time = 1/2 * 2W ** W W= = 22 W W Peak revenue –Delayed –Delayed = = 1/2 1/2 ** (W-D+W)*(W-D) (W-D+W)*(W-D) Peak revenue from delayed entry •Percentage •Percentage revenue revenue loss loss = = 22)*100% (D(3W-D)/2W (D(3W-D)/2W )*100% Market fall •Try •Try some some examples examples 2W W Time – – – – – Lifetime 2W=52 wks, delay D=4 wks (4*(3*26 –4)/2*26^2) = 22% Lifetime 2W=52 wks, delay D=10 wks (10*(3*26 –10)/2*26^2) = 50% Delays are costly! Prof. C. SILVANO, Politecnico di Milano, 2004 - 68 - 34 NRE and unit cost metrics Costs: Costs: Unit Unit cost: cost: the the monetary monetary cost cost of of manufacturing manufacturing each each copy of the system, excluding copy of the system, excluding NRE NRE cost cost NRE NRE cost cost (Non-Recurring (Non-Recurring Engineering Engineering cost): cost): The The oneonetime time monetary monetary cost cost of of designing designing the the system system total total cost cost = = NRE NRE cost cost + + unit unit cost cost ** # # of of units units per-product per-product cost cost = = total total cost cost // # # of of units units = = (NRE (NRE cost cost // # # of of units) units) + + unit unit cost cost • Example – NRE Cost = $2000, Unit Cost = $100 – For 10 units – total cost = $2000 + 10*$100 = $3000 – per-product cost = $2000/10 + $100 = $300 Amortizing NRE cost over the units results in an additional $200 per unit - 69 - Prof. C. SILVANO, Politecnico di Milano, 2004 NRE and unit cost metrics Compare Compare technologies technologies by by costs costs --- best best depends depends on on quantity quantity Technology Technology A: A: NRE=$2,000, NRE=$2,000, unit=$100 unit=$100 Technology B: NRE=$30,000, Technology B: NRE=$30,000, unit=$30 unit=$30 Technology Technology C: C: NRE=$100,000, NRE=$100,000, unit=$2 unit=$2 $200,000 $120,000 $80,000 $160 p e r p ro d u c t c o st C A B B $160,000 to ta l c o st (x1000) $200 A $40,000 C $120 $80 $40 $0 $0 0 800 1600 2400 0 Nu m b e r o f u nits (vo lu m e ) 800 1600 2400 Nu m b e r o f un its (vo lu m e ) • But, must also consider time-to-market Prof. C. SILVANO, Politecnico di Milano, 2004 - 70 - 35 NRE and unit cost metrics The The best best technology technology choice choice will will depend depend on on the the number number of of units units we we plan plan to to produce. produce. •• Larger Larger volumes volumes allow allow us us to to amortize amortize NRE NRE costs costs such such that that lower lower per-product per-product costs costs result result •• Larger Larger volumes volumes ⇒ ⇒ Lower Lower per-product per-product cost cost since NRE cost can be distributed over since NRE cost can be distributed over more more products. products. Prof. C. SILVANO, Politecnico di Milano, 2004 - 71 - The performance design metric •• Widely-used Widely-used measure measure of of system, system, widelywidelyabused abused –– Clock Clock frequency, frequency, instructions instructions per per second second –– not not good measures good measures –– Digital Digital camera camera example example –– aa user user cares cares about about how how fast it processes images, not clock speed fast it processes images, not clock speed or or instructions instructions per per second second •• Latency Latency (response (response time) time) –– Time Time between between task task start start and and end end –– e.g., Camera’s A and B process e.g., Camera’s A and B process images images in in 0.25 0.25 seconds seconds Prof. C. SILVANO, Politecnico di Milano, 2004 - 72 - 36 The performance design metric •• Throughput Throughput (Number (Number of of tasks tasks that that can can be be processed per unit time) processed per unit time) –– Tasks Tasks per per second, second, e.g. e.g. Camera Camera AA processes processes 44 images images per per second second –– Throughput Throughput can can be be more more than than latency latency seems seems to to imply due to concurrency, e.g. Camera imply due to concurrency, e.g. Camera BB may may process process 88 images images per per second second (by (by capturing capturing aa new new image while previous image is being image while previous image is being stored). stored). •• To To compare compare the the performance performance of of 22 systems: systems: Speedup of B over A = B’s performance Speedup of B over A = B’s performance // A’s A’s performance performance –– Throughput Throughput speedup speedup = = 8/4 8/4 = = 22 Prof. C. SILVANO, Politecnico di Milano, 2004 - 73 - Design Technologies Prof. C. SILVANO, Politecnico di Milano, 2004 - 74 - 37 Three key technologies Technology Technology A A manner manner of of accomplishing accomplishing aa task, task, especially using technical processes, especially using technical processes, methods, methods, or or knowledge knowledge Three key technologies Three key technologies for for embedded embedded systems systems 1. 1. Processor Processor technology technology 2. IC technology 2. IC technology 3. 3. Design Design technology technology - 75 - Prof. C. SILVANO, Politecnico di Milano, 2004 1) Processor technology •• The The architecture architecture of of the the computation computation engine engine used used to to implement implement aa system’s system’s desired desired functionality functionality •• “Processor” “Processor” not not necessarily necessarily equal equal to to general-purpose general-purpose processor processor Controller Control logic and State register IR PC Datapath Register file General ALU Controller Control logic and State register IR Datapath Controller Datapath Registers Control logic index Custom ALU State register Data memory total = 0 for i =1 to … General-purpose (“software”) + PC Data memory Program memory Assembly code for: total Data memory Program memory Assembly code for: total = 0 for i =1 to … Application-specific Prof. C. SILVANO, Politecnico di Milano, 2004 Single-purpose (“hardware”) - 76 - 38 Processor technology Processors Processorsvary varyin intheir theircustomization customizationfor forthe theproblem problemat athand hand total = 0 for i = 1 to N loop total += M[i] end loop General-purpose processor (SW) Desired functionality It represents the exact fit of the desired functionality Application-specific processor (HW/SW) Single-purpose processor (HW) - 77 - Prof. C. SILVANO, Politecnico di Milano, 2004 General-purpose processors (SW) •• Programmable Programmable device device used used in in aa variety of applications variety of applications –– Also Also known known as as “microprocessor” “microprocessor” •• Features Features –– Program Program memory memory –– General General data-path data-path with with large large register file and general register file and general ALU ALU •• User benefits User benefits –– Low Low time-to-market time-to-market and and NRE NRE costs costs –– High High flexibility flexibility •• “Pentium” “Pentium” the the most most well-known, well-known, but there are hundreds but there are hundreds of of others others Prof. C. SILVANO, Politecnico di Milano, 2004 Controller Datapath Control logic and State register Register file IR PC Program memory General ALU Data memory Assembly code for: total = 0 for i =1 to … - 78 - 39 Single-purpose processors (HW) •• Digital Digital circuit circuit designed designed to to execute execute exactly one program exactly one program –– a.k.a. a.k.a. coprocessor, coprocessor, accelerator accelerator or or peripheral peripheral •• Features Features –– Contains Contains only only the the components components needed needed to to execute execute aa single single application application program program –– No No program program memory memory •• Benefits Benefits –– Fast Fast –– Low Low power power –– Small Small size size Controller Datapath Control logic index total State register + Data memory - 79 - Prof. C. SILVANO, Politecnico di Milano, 2004 Application-specific processors (HW/SW) •• Programmable Programmable processor processor optimized optimized for for aa particular particular class class of of applications applications having having common common characteristics characteristics –– Compromise between Compromise between generalgeneralpurpose purpose and and single-purpose single-purpose processors processors •• Features Features –– Program Program memory memory –– Optimized Optimized data-path data-path –– Special Special functional functional units units •• Benefits Benefits –– Some Some flexibility, flexibility, good good performance, performance, size size and and power power Prof. C. SILVANO, Politecnico di Milano, 2004 Controller Datapath Control logic and State register Registers IR Custom ALU PC Program memory Data memory Assembly code for: total = 0 for i =1 to … - 80 - 40 Application-specific processors ASIPS ASIPS can can require require large large NRE NRE costs costs to to build build the the processor and the compiler processor and the compiler ⇒ Current ⇒ Current research research focuses focuses on on automatically automatically generating ASIPs and their associated generating ASIPs and their associated compile compile and and debug debug environment. environment. - 81 - Prof. C. SILVANO, Politecnico di Milano, 2004 2) IC technology •• The The manner manner in in which which aa digital digital (gate-level) (gate-level) implementation implementation is is mapped mapped onto onto an an IC IC –– IC: Integrated circuit, or “chip” IC: Integrated circuit, or “chip” –– IC IC technologies technologies differ differ in in their their customization customization to to aa design design –– IC’s IC’s consist consist of of numerous numerous layers layers (perhaps (perhaps 10 10 or or more) more) •• IC IC technologies technologies differ differ with with respect respect to to who who builds builds each layer and when each layer and when IC package IC source gate oxide channel drain Silicon substrate Prof. C. SILVANO, Politecnico di Milano, 2004 - 82 - 41 IC technology Three Three types types of of IC IC technologies technologies a) a) Full-custom/VLSI Full-custom/VLSI b) b)Semi-custom Semi-custom ASIC ASIC (gate (gate array array and and standard standard cell) cell) c) c) PLD PLD (Programmable (Programmable Logic Logic Device) Device) Prof. C. SILVANO, Politecnico di Milano, 2004 - 83 - a) Full-custom/VLSI •• All All layers layers are are optimized optimized for for an an embedded embedded system’s particular digital implementation system’s particular digital implementation –– Placing Placing transistors transistors –– Sizing Sizing transistors transistors –– Routing Routing wires wires •• Benefits Benefits –– Excellent Excellent performance, performance, small small size, size, low low power power •• Drawbacks Drawbacks –– High High NRE NRE cost cost (e.g., (e.g., $300k), $300k), long long time-totime-tomarket market Prof. C. SILVANO, Politecnico di Milano, 2004 - 84 - 42 b) Semi-custom •• Lower Lower layers layers are are fully fully or or partially partially built built –– Designers Designers are are left left with with routing routing of of wires wires and maybe placing some blocks and maybe placing some blocks •• Benefits Benefits –– Good Good performance, performance, good good size, size, less less NRE NRE cost cost than than aa full-custom full-custom implementation implementation (perhaps (perhaps $10k $10k to to $100k) $100k) •• Drawbacks Drawbacks –– Still Still require require weeks weeks to to months months to to develop develop Prof. C. SILVANO, Politecnico di Milano, 2004 - 85 - c) PLD (Programmable Logic Device) •• All All layers layers already already exist exist –– Designers can purchase Designers can purchase an an IC IC –– Connections Connections on on the the IC IC are are either either created created or or destroyed destroyed to to implement implement desired desired functionality functionality –– Field-Programmable Field-Programmable Gate Gate Array Array (FPGA) (FPGA) very very popular popular •• Benefits Benefits –– Low Low NRE NRE costs, costs, almost almost instant instant IC IC availability availability •• Drawbacks Drawbacks –– Bigger, Bigger, expensive expensive (perhaps (perhaps $30 $30 per per unit), unit), power power hungry, hungry, slower slower Prof. C. SILVANO, Politecnico di Milano, 2004 - 86 - 43 Independence of processor and IC technologies •• Basic Basictradeoff tradeoff –– General Generalvs. vs.custom custom –– With respect With respectto toprocessor processortechnology technologyor orIC ICtechnology technology –– The two technologies are independent The two technologies are independent Generalpurpose processor General, providing improved: Singlepurpose processor ASIP Customized, providing improved: Flexibility Maintainability NRE cost Time- to-prototype Time-to-market Cost (low volume) Power efficiency Performance Size Cost (high volume) PLD Semi-custom Full-custom - 87 - Prof. C. SILVANO, Politecnico di Milano, 2004 Embedded Hardware: Moore’s law •• The The most most important important trend trend in in embedded embedded systems systems [Predicted [Predicted in in 1965 1965 by by Intel Intel co-founder co-founder Gordon Gordon Moore] Moore] “IC transistor capacity has doubled roughly “IC transistor capacity has doubled roughly every every 18 18 months for the past several decades” months for the past several decades” 10,000 1,000 Logic transistors per chip (in millions) 100 10 1 0.1 Note: logarithmic scale 0.01 Prof. C. SILVANO, Politecnico di Milano, 2004 2009 2007 2005 2003 1999 2001 1995 1997 1991 1993 1989 1985 1987 1983 1981 0.001 - 88 - 44 Embedded Hardware: Moore’s law •• This This trend trend is is mainly mainly caused caused by by improvements improvements in IC manufacturing in IC manufacturing •• Minimum Minimum feature feature size size for for CMOS CMOS IC IC technology in 2002 is approximately technology in 2002 is approximately 130 130 nm. nm. - 89 - Prof. C. SILVANO, Politecnico di Milano, 2004 Graphical illustration of Moore’s law 1981 1984 1987 1990 1993 1996 1999 2002 10,000 transistors 150,000,000 transistors Leading edge chip in 1981 Leading edge chip in 2002 • Something that doubles frequently grows more quickly than most people realize! – A 2002 chip can hold about 15,000 1981-chips inside itself Prof. C. SILVANO, Politecnico di Milano, 2004 - 90 - 45 STMicroelectronics Roadmap - 91 - Prof. C. SILVANO, Politecnico di Milano, 2004 3) Design Technology The The manner manner in in which which we we convert convert our our concept concept of of desired desired system system functionality functionality into into an an implementation implementation Compilation/ Synthesis Compilation/Synthesis: Automates exploration and insertion of implementation details for lower level. Libraries/IP: Incorporates predesigned implementation from lower abstraction level into higher level. Test/Verification: Ensures correct functionality at each level, thus reducing costly iterations between levels. Libraries/ IP Test/ Verification System specification System synthesis Hw/Sw/ OS Model simulat./ checkers Behavioral specification Behavior synthesis Cores Hw-Sw cosimulators RT specification RT synthesis RT components HDL simulators Logic specification Logic synthesis Gates/ Cells Gate simulators To final implementation Prof. C. SILVANO, Politecnico di Milano, 2004 - 92 - 46 Design Technology The The designer designer must must be be able able to to produce produce larger larger number of transistors per year to keep number of transistors per year to keep pace pace with with IC IC technology. technology. Prof. C. SILVANO, Politecnico di Milano, 2004 - 93 - Design Productivity Gap Prof. C. SILVANO, Politecnico di Milano, 2004 - 94 - 47 Design productivity exponential increase 100,000 1,000 100 10 1 Productivity (K) Trans./Staff – Mo. 10,000 0.01 2009 2007 2005 2003 2001 1999 1997 1995 1993 1991 1989 1987 1985 1983 1981 0.1 Exponential Exponential increase increase over over the the past past few few decades decades - 95 - Prof. C. SILVANO, Politecnico di Milano, 2004 Design productivity gap •• While While designer designer productivity productivity has has grown grown at at an an impressive impressive rate rate over over the the past past decades, decades, the the rate rate of of improvement improvement has has not not kept kept pace pace with with chip chip capacity capacity Logic transistors per chip (in millions) 10,000 100,000 1,000 10,000 100 1000 Gap 10 100 IC capacity 1 10 0.1 Productivity (K) Trans./Staff-Mo. 1 productivity 0.01 0.1 0.001 Prof. C. SILVANO, Politecnico di Milano, 2004 2009 2007 2005 2003 1999 2001 1997 1993 1995 1991 1987 1989 1985 1983 1981 0.01 - 96 - 48 Design productivity gap •• 1981 1981 leading leading edge edge chip chip required required 100 100 designer designer months months –– 10,000 transistors / 100 transistors/month 10,000 transistors / 100 transistors/month •• 2002 2002 leading leading edge edge chip chip requires requires 30,000 30,000 designer designer months months –– 150,000,000 150,000,000 // 5000 5000 transistors/month transistors/month •• Designer cost increases from Designer cost increases from $1M $1M to to $300M $300M Logic transistors per chip (in millions) 10,000 100,000 1,000 10,000 100 10 1000 100 Gap IC capacity 1 0.1 10 1 productivity 0.01 Productivity (K) Trans./Staff-Mo. 0.1 0.001 2009 2007 2003 2005 2001 1999 1995 1997 1993 1991 1987 1989 1985 1981 1983 0.01 - 97 - Prof. C. SILVANO, Politecnico di Milano, 2004 The mythical man-month •• The Thesituation situationis iseven evenworse worsethan thanthe theproductivity productivitygap gapindicates indicates •• In theory, adding designers to team reduces project In theory, adding designers to team reduces projectcompletion completiontime time •• In Inreality, reality,productivity productivityper perdesigner designerdecreases decreasesdue dueto tocomplexities complexitiesof of team teammanagement managementand andcommunication communication •• In Inthe thesoftware softwarecommunity, community,known knownas as“the “themythical mythicalman-month” man-month” (Brooks (Brooks1975) 1975) •• At Atsome somepoint, point,can canactually actuallylengthen lengthenproject projectcompletion completiontime! time!(“Too (“Too many manycooks”) cooks”) 1M transistors, 1 designer=5000 trans/month Each additional designer reduces for 100 trans/month So 2 designers produce 4900 trans/month each 60000 50000 40000 30000 20000 10000 16 Team 15 16 19 18 23 24 Months until completion 43 Individual 0 Prof. C. SILVANO, Politecnico di Milano, 2004 10 20 30 Number of designers 40 - 98 - 49 Managing the design productivity crisis •• IP IP (Intellectual (Intellectual Property) Property) Reuse Reuse •• System-Level System-Level Design Design •• Software Software Design Design Prof. C. SILVANO, Politecnico di Milano, 2004 - 99 - IP-reuse •• Assembly Assembly of of predesigned predesigned Intellectual Intellectual Property Property components, components, often often from from external external vendors vendors •• Soft Soft and and Hard Hard IPs IPs Prof. C. SILVANO, Politecnico di Milano, 2004 - 100 - 50 System-Level Design •• Design Design and and verification verification at at the the system-level system-level –– Rather Rather than than at at the the RTL RTL or or gate-level gate-level –– Focus Focus on on Interface Interface and and Communication Communication Prof. C. SILVANO, Politecnico di Milano, 2004 - 101 - Software Design Great Great importance importance of of software software Prof. C. SILVANO, Politecnico di Milano, 2004 - 102 - 51 Summary •• Embedded Embedded systems systems are are everywhere everywhere •• Key Key challenge: challenge: optimization optimization of of design design metrics metrics –– Design Design metrics metrics compete compete with with one one another another •• A unified view of hardware and software A unified view of hardware and software is is necessary to improve productivity necessary to improve productivity •• Three Three key key technologies technologies –– Processor: Processor: general-purpose, general-purpose, applicationapplicationspecific, single-purpose specific, single-purpose –– IC: IC: Full-custom, Full-custom, semi-custom, semi-custom, PLD PLD –– Design: Design: Compilation/synthesis, Compilation/synthesis, libraries/IP, libraries/IP, test/verification test/verification Prof. C. SILVANO, Politecnico di Milano, 2004 - 103 - Note •• Part Part of of the the material material presented presented was was derived derived from from the the books: books: –– “Embedded System Design” by Peter Marwedel, Kluwer “Embedded System Design” by Peter Marwedel, Kluwer Academic Academic Publishers, Publishers, ISBN: ISBN: 1-4020-7690-8, 1-4020-7690-8, October October 2003 2003 –– “Embedded “Embedded System System Design: Design: AA Unified Unified Hardware/ Hardware/ Software Software Introduction” Introduction” by by Frank Frank Vahid, Vahid, Tony Tony Givargis, Givargis, John John Wiley Wiley && Sons Sons Inc., Inc., ISBN:0-471-38678-2, ISBN:0-471-38678-2, 2002. 2002. –– “Computers as Components: Principles of Embedded “Computers as Components: Principles of Embedded Computer Computer Systems Systems Design Design (With (With CD-ROM)” CD-ROM)” by by Wayne Wayne Wolf, Morgan Kaufmann Publishers, Wolf, Morgan Kaufmann Publishers, ISBN: ISBN: 1-55860-541-X, 1-55860-541-X, 2001 2001 Prof. C. SILVANO, Politecnico di Milano, 2004 - 104 - 52