1
Design of a low power CMOS operational amplifier with common mode feedback
2
for pipeline analog-to-digital converter applications
3
Sohiful Anuar ZAINOL MURAD1,*, Izatul Syafina ISHAK1 , Mohd Fairus AHMAD1
4
and Shaiful Nizam MOHYAR1
1
5
School of Microelectronic Engineering, Universiti Malaysia Perlis,
6
Pauh Putra Campus, 02600 Arau, Perlis, Malaysia
7
*Correspondence: sohiful@unimap.edu.my
8
Abstract: This paper proposes the design of a low-power operational amplifier (op-
9
amp) for pipeline analog-to-digital converter (ADC) applications using 0.13-µm CMOS
10
process. The folded cascode topology with NMOS input types is employed for the op-
11
amp design due to a larger output gain as compared to the PMOS input types.
12
Furthermore, the op-amp is d with designed double detection structure of a common
13
mode feedback circuit to provide a stable feedback voltage. The simulation results show
14
that the proposed op-amp has achieved gain of 64.5 dB and a unity gain bandwidth of
15
695.1 MHz with a low power consumption of 0.14 mW. In addition, by applying ± 1.2
16
V input voltage, the output voltage, which is generated by the proposed op-amp design,
17
fixes at 1.2 V with a constant feedback voltage of 1.3 V. Moreover, the proposed circuit
18
has been implemented and simulated successfully in a 1.5-bit per stage pipeline ADC.
19
Key words: Analog-to-digital converter, fully differential op-amp, low power, low
20
voltage, pipeline
21
22
1.
Introduction
23
A Pipeline is an eminent architecture of Analog-to-Digital Converter (ADC) and plays
24
an essential role in applications which require the interface between analog and digital
1
1
domain. The pipeline architecture covers numerous signals processing applications such
2
as in communications, instrumentations, and also imaging systems since the architecture
3
has been classified as a high-speed and high-accuracy architecture [1]. Commonly, this
4
architecture is extensively designed for a power-efficient high-speed conversion of wide
5
bandwidth input signals in the range of 10 to 100 mega samples per second (MSPS)
6
with medium to high resolution bits, around 8 to 14 bits resolution [2]. As discussed in
7
[3], the pipeline ADC is open-loop architecture with a small inherent latency; from 4 to
8
6 clock cycles and possesses a direct relationship between the input signal and the
9
output code. Figure 1 illustrates the architecture of a pipeline ADC which consists of
10
individual stages such as a low resolution ADC, digital-to-analog converter (DAC),
11
sample and hold circuit and an amplifier circuit that successively alter the analog signal
12
into the digital signal by converting the data in pipe-lined manner [1].
13
14
Figure 1. Pipeline ADC architecture [1].
15
16
An operational amplifier (op-amp) is a core element and the most important integral
17
part in pipeline architecture. Basically, the op-amp has high input and low output
18
impedance that are used with a single-loop and negative feedback in order to achieve
19
the precision signal processing. Generally, the op-amp is divided into several types of
20
topologies such as a telescopic op-amp, folded cascode op-amp, two-stage op-amp and
21
gain boosted op-amp as shown in Figure 2 [4]. In brief, a telescopic op-amp is a simple
22
topology compared to the other topologies. Traditionally, the telescopic topology as
23
shown in Figure 2 (a) is constructed from only one type of transistor in the signal path
24
which is NMOS type. This topology provides a faster performance with high gain and
2
1
in addition shows less power consumption and low noise. However, it requires a higher
2
supply voltage in order to control and to ensure the input and output of common-mode
3
to be at the same level (equal value of input and output). Meanwhile, for folded cascode
4
topology as shown in Figure 2 (b), the structure is naturally modified from the
5
telescopic op-amp. Based on the rule of this topology the folded cascode can be
6
constructed by two types of transistor in the signal path either in NMOS type or PMOS
7
type. This signal path will produce a different op-amp circuit performance. Commonly,
8
the folded cascode op-amp produces a higher gain, yet shows high power consumption
9
and also high noise compared to the telescopic op-amp. Yet, the folded cascode op-amp
10
easily controls the input and output of common-mode to be equal and potentially
11
operates in a low power voltage supply. Figure 2 (c) shows the topology of a two-stage
12
op-amp that yields more gain and swing. Essentially, the first stage contains a
13
differential input, which converts the input voltage to current and provides a high gain
14
while for the second stage is configured with a simple common-source stage, which
15
converts the current to the voltage output and provides a high swing. For gain-boosted
16
op-amp as shown in Figure 2 (d), is typically utilized to maximize the output
17
impedances as well as to attain a high gain [4]. Basically, this topology is employed in
18
order to reduce the problems stacking among the transistors. However, it has high
19
power consumption, noise and also requires a high voltage supply to conduct the op-
20
amp circuit.
(a)
21
22
(c)
(b)
(d)
23
Figure 2. Op-amp topologies [4] (a) telescopic, (b) folded cascode with PMOS input,
24
(c) two-stage and (d) gain-boosted.
3
1
2.
Circuit Implementation
2
2.1
Design Specifications
3
Based on the requirement of high-speed and high-accuracy pipeline ADC, the op-amp
4
becomes a primary and sensitive design. Thus, the specifications of the op-amp for 10
5
to 12-bits ADC applications are designated in Table 1.
Table 1 Op-amp design specification for pipeline ADC
6
7
8
2.2
The Proposed Circuit Design
9
Based on the design specifications in Table 1, a suitable op-amp topology is taken into
10
consideration in order to meet all requirements of the design specifications. As
11
mentioned in [4] a comparable performance of op-amp topologies which represents the
12
folded cascode topology produces a high gain and high speed even though the topology
13
can be operated in a low voltage supply. Besides that, this topology has also been used
14
to obtain a high DC and fast settling with high unity high gain apart from low power
15
consumption [5-7]. In addition, a common-mode feedback circuit is vital in this op-amp
16
design consecutively to stabilize the output that is generated by the op-amp circuit as
17
well as to ensure a proper operation of a fully-differential op-amp as discussed in [8-
18
10].
19
20
2.2.1 Folded Cascode Op-Amp
21
The folded cascode topology with NMOS input types is preferable to be the main op-
22
amp design due to the limitation of op-amp specifications as this input type gives a
23
larger output gain compared to the PMOS input types. Figure 3 illustrates the folded
4
1
cascode op-amp with NMOS topology and the details of this op-amp design is discussed
2
as follows.
3
(a)
4
(b)
5
Figure 3. Folded cascode with NMOS input structure (a) complete circuit, (b) half
6
circuit.
7
8
Referring to Figure 3 (b), the proposed folded cascode is constructed by considering to
9
the half circuit. The essential property of a small-signal analysis, the gain (Av) is
10
11
obtained as:
Av = G m × Rout
(1)
12
where Gm ≈ gm1 and gm1 is a transconductance of the input transistor of M1.
13
By using the equation (2), gm is equal to 816.81 × 106 S with 1pF of capacitive load,
14
CL. Meanwhile Rout is shown in the equation (3).
15
GBW =
16
where GBW is a gain bandwidth product of the op-amp.
17
Rout = [g m5 .ro5 .(ro1 || ro3 )] || [g m7 .ro7 .ro9 ]
18
When the gm is obtained, the current, ID across the op- amp can be calculated as:
19
ID =
20
where VGS is a gate-source voltage and Vth is a threshold voltage.
21
Therefore, the sizing of transistors can be calculated by using the equation (5) for
22
NMOS transistor and the equation (6) for PMOS transistor.
gm
CL
g m  (VGS -Vth )
2
(2)
(3)
(4)
5
1
( g m )2
W
=
L 2 × I D × μ n c ox
(5)
2
( g m )2
W
=
L 2 × I D × μ p cox
(6)
3
where µn is the n-type channel mobility, µp is the p-type channel mobility and Cox is the
4
capacitance per gate unit area.
5
Table 2 summarized the transistor ratio result that obtained through the ‘first-cut’
6
method. Noted that, the minimum length of thickness oxide transistor is 0.13-µm and to
7
minimize the channel length modulation, the length of transistor is set to 3 times of the
8
minimum channel length.
9
Table 2: Calculated transistor ratio of folded cascode.
10
11
2.2.2 Biasing Circuit
12
A biasing circuit is an important block with its function to bias a proper voltage in the
13
op-amp structure. As can be seen in Figure 3 (a), the voltage bias in the folded cascode
14
architecture are Vbias1, Vbias2 and Vbias3, which are generated from the biasing circuit that
15
has been designed from the wide swing current mirror as shown in Figure 4. The current
16
of 20 µA flows across the transistor of Vbias1, Vbias2 and Vbias3 as a reference current
17
(Iref). Therefore, the development of this circuit is done by twining the W/L ratio with
18
respect to Iref and checks each node voltages at cascode stage. Noted that, the resistor
19
(R) is needed as it functions to bias the current and commonly it is a passive component
20
in biasing circuit. Table 3 presents the W/L ratio of each transistor with the related
21
voltage bias (Vbias).
6
1
2
Figure 4. Biasing circuit.
3
Table 3: Biasing circuit performances.
4
2.2.3 Common-mode Feedback Circuit
5
Figure 5 (a) shows a conventioanl differential difference amplifier (DDA) structure. The
6
transistor of M1(a) and M1(b) is modified to be a double detection of Vfeedback voltage
7
node [11]. A common-mode feedback circuit with a modification of a conventional
8
differential difference amplifier (DDA) structure as illustrated in Figure 5 (b) has been
9
utilized in this op-amp design. Therefore, the double detection structure provides a
10
stable feedback voltage of 1.3 V with 1.2 V input voltage. Moreover, the CMFB
11
structure can also stabilize the 1.2 V output voltage which is generated by this op-amp
12
circuit. The sizing of each transistor of CMFB circuit is shown as in Table 4.
13
14
15
16
(a)
(b)
Figure 5. (a) Conventional DDA structure [10], (b) The proposed CMFB circuit.
Table 4: Transistor sizing in CMFB circuit.
17
The completed circuit consists of biasing and a common mode feedback of the proposed
18
fully differential folded cascode op-amp is show in Figure 6. Further, this circuit will be
19
implemented in a 1.5-bit per stage pipeline ADC for performance verification.
20
21
Figure 6. The proposed design of fully differential folded cascode op-amp.
7
1
2.2.3 Integration of Folded Cascode Op-Amp with CMFB Circuit in 1.5-bit per
stage ADC.
2
3
Figure 7 shows the integration of 1.5-bit per stage pipeline ADC with three main circuit
4
blocks which are the comparator (block A), logic switch (block B) and also a residue
5
amplifier (block C). The proposed circuit of folded cascode and CMFB is implemented
6
in the residue amplifier as represented by block C in order to analyze the circuit
7
performances. The complete circuit of the residue amplifier is depicted in Figure 8.
8
Figure 7. Design implementation of 1.5-bit per stage pipeline ADC.
9
10
Figure 8. Residue amplifier circuit block.
11
12
13
3.
Results and Discussions
14
The performances of the proposed circuit design have been simulated using Cadence
15
Virtuoso spectre. The process technology is CMOS 0.13-µm process and it is powered
16
at 1.8 V voltage supply. The performances of the folded cascode op-amp are
17
demonstrated based on AC and a transient response. From the AC analysis as shown in
18
Figure 9 (a), the DC gain of the folded cascode of 64.5 dB is obtained with 695.1 MHz
19
unity gain bandwidth (UGB) along 52.5 kHz cut-off frequency. Meanwhile the phase
20
margin as plotted in Figure 9 (b) is achieved at 68.4º with a 1 pF load capacitor.
21
22
(a)
23
(b)
24
Figure 9. AC analysis (a) DC gain, (b) Phase Margin.
8
1
Since the parameter of DC gain, unity gain bandwidth and phase margin becomes
2
critical parameters in this design, the corner analysis has been simulated as shown in
3
Figure 10 for three possible corners; typical-typical (TT), the fast-fast (FF) and slow-
4
slow (SS). As can be seen in Figure 10 (a), the DC gain indicates 4 % (SS corner) and 7
5
% (FF corner) chages from TT value while the unity gain bandwidth shows different
6
changes between FF and SS corner among TT value which is 42.7 % (SS corner) and
7
0.7 % (FF corner). Therefore, the SS corner of the unity gain bandwidth can be
8
considered as a worst-case for this design. Meanwhile for the phase margin as depicted
9
in Figure 10 (b), the value of FF and SS corner is slightly changes from the TT value
10
which is 4 % (SS corner) and 1.6 % (FF corner).
11
12
(a)
13
(b)
14
Figure 10. Corner analysis results for the proposed folded cascdoe op-amp design, (a)
15
DC gain, unity gain bandwidth; (b) phase margin.
16
17
As depicted in Figure 11, the simulated transient analysis result shows that a slew rate
18
of 22.6 V/µs with 72.4 ns settling time is obtained.
19
20
Figure 11. Transient analysis result.
21
Figure 12 shows the result of a Common Mode Rejection Ratio (CMRR). The CMRR is
22
important parameter to determine the tendency of op-amp to reject or cancel out the
23
input common signals to both inputs. As can be seen, the simulation result indicated that
24
the CMRR of 41.48 dB is achieved.
9
1
Figure 12: Common Mode Rejection Ratio result.
2
The main characteristics of the proposed folded cascode op-amp design are summarized
3
in Table 5. From the results, the obtained DC gain is a medium gain, which is near to
4
the 70 dB. However, the DC gain has less effect to the desired op-amp design because
5
the unity gain bandwidth and the phase margin are still in a range of op-amp design
6
specifications.
7
Table 5 Folded Casode Op-Amp Performances
8
9
10
Figure 13 (a) presents the test setup for CMFB circuit in order to analyze the circuit
11
performances. The performances of the circuit is illustrated in Figure 13 (b). From
12
the simulation results, by applying a ± 1.2 V input voltage at In1 and In2, the output
13
voltage that is generated by the proposed op-amp design meets 1.2 V with a constant
14
value of 1.3 V of feedback voltage.
15
(a)
16
(b)
17
Figure 13. (a) Test setup of CMFB circuit, (b) CMFB circuit performances result.
18
The implementation results of the folded cascode op-amp with CMFB circuit are
19
demonstrated by comparing the simulation results with the process information in Table
20
6.
21
Table 6 Process Information
22
23
The comparison process is performed by feeding the comparator with the differentiate
24
voltage (vdiff) of (vdiff = vin+  vin-) where the value of Vin is between the range of  1.8
10
1
V to 1.8 V. Later, the vdiff is compared to the  Vref/4 in order to perform the 2-bit signal
2
of COM1 and COM0 (refer to Figure 7). However, the value of Vref should be noted as
3
1.2 V. Thus, simulation results are presented in Figure 14 and then are compared to the
4
ideal case as shown in the same Figure 14. From the transfer function, it shows the
5
switch value between the positive and negative value which at the input difference of +
6
0.3 V and  0.3 V. As knowledge, the data of output voltage are only sampled at
7
increment or decrement value of ± 0.1 V on both inputs of Vin + and also Vin –.
8
However, to perform the value transition at ± 0.3 V, the sampling of value should be
9
small enough which close to ± 0.3 V for example ± 0.32 V and ± 0.28 V. Therefore, this
10
integration is applied in order to ensure the folded cascode and CMFB circuit can
11
provide a comprehensive design for high speed and high gain of pipeline ADC.
12
13
Figure 14. (a) Transfer function of residue output.
14
15
Table 7 summarizes the performance comparison of the op-amp circuit with a
16
previously published work for the pipeline ADC applications. Referring to [12], the op-
17
amp circuit with a folded regulated cascode topology obtains a 90.39 dB of DC gain
18
along 700.7 MHz unity gain bandwidth and has been utilized in 10-bit pipeline ADC.
19
However, the higher gain is not required for 10-bit pipeline ADC thus the op-amp
20
circuit shows higher power consumption, 3.24 mW. Meanwhile, in [15] the op-amp
21
circuit has been utilized in 14-bit ADC application with folded cascode topology. The
22
op-amp circuit achieves 92.0 dB of DC gain with 1600.0 MHz unity gain bandwidth,
23
but the op-amp circuit shows higher power consumption compared to [12] which is 7.8
24
mW with a voltage supply of 1.8 V. The gain band-width product for [12]-[16] are
11
1
higher than the proposed work due to the higher gain and their design targeted for
2
higher resolution (bits). As can be seen in this work, the proposed op-amp circuit
3
demonstrates the lowest power consumption as compared to previous works with other
4
parameters are comparable. In addition, the proposed op-amp circuit has been
5
implemented in 10-bit pipeline ADC.
6
7
4.
Conclusion
8
This work describes the design of op-amp circuit using a folded cascode topology with
9
NMOS input types for pipeline ADC applications. The proposed op-amp with designed
10
a common-mode feedback is implemented in a 0.13-µm CMOS technology. The
11
simulated results show that the op-amp achieves 64.5 dB gain, 695.1 MHz of unity gain
12
bandwidth and phase margin of 68.4º at 1 pF load capacitor. In addition, the op-amp
13
also provides a 22.6 µs/V of slew rate with 72.4 ns settling time and in addition shows
14
less power consumption which is 0.14 mW at 1.8 V voltage supply. A common mode
15
feedback circuit with double-detection structure is capable to fix the output voltage
16
which is generated by the op-amp at 1.2 V for a constant feedback voltage of 1.3 V.
17
Therefore, the proposed folded cascode op-amp with CMFB is able to be implemented
18
in pipeline ADC applications.
19
20
Table 7 Comparison performances of proposed Folded Cascode Op-Amp with
21
previously published work
22
23
24
12
1
Acknowledgement
2
The authors wish to express their appreciation and gratitute for the unconditional as well
3
as continuous support, contributions and assisstance especially the Fundamental
4
Reserach Grant Scheme (FRGS) grant awarded (9003-00387) that helps to materialize
5
the production of this article.
6
7
References
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1
Figure 1. Pipeline ADC architecture [1].
2
3
4
(a)
(b)
(c)
(d)
5
6
7
Figure 2. Op-amp topologies [4] (a) telescopic, (b) folded cascode with PMOS input,
8
(c) two-stage and (d) gain-boosted.
16
1
2
3
(a)
(b)
4
Figure 3. Folded cascode with NMOS input structure (a) complete circuit, (b) half
5
circuit.
6
7
8
Figure 4. Biasing circuit.
9
10
11
17
1
2
3
4
(a)
(b)
Figure 5. (a) Conventional DDA structure [10], (b) The proposed CMFB circuit.
5
6
7
8
Figure 6. The proposed design of fully differential folded cascode op-amp.
9
10
18
1
2
Figure 7. Design implementation of 1.5-bit per stage pipeline ADC.
3
4
Figure 8. Residue amplifier circuit block.
5
6
19
1
2
(a)
3
4
(b)
5
Figure 9. AC analysis (a) DC gain, (b) Phase Margin.
6
7
8
9
10
11
12
20
1
TT
2
3
FF
SS
4
5
6
7
8
(a)
9
10
11
TT
FF
12
SS
13
14
15
16
17
(b)
18
Figure 10. Corner analysis results for the proposed folded cascdoe op-amp design, (a)
19
DC gain, unity gain bandwidth; (b) phase margin.
20
.
21
1
2
Figure 11. Transient analysis result.
3
4
5
Figure 12: Common Mode Rejection Ratio result.
6
7
22
1
2
3
(a)
(b)
Figure 13. (a) Test setup of CMFB circuit, (b) CMFB circuit performances result.
4
5
6
7
8
9
10
11
Residue output idea case
12
13
14
15
16
17
18
Figure 14. (a) Transfer function of residue output.
19
23
Table 1 Op-amp design specification for pipeline ADC
1
Parameter
Value
Voltage supply
± 1.8 V
Vin
± 1.2 V
Vout
1.2 V
DC gain
> 70 dB
Phase Margin
> 50º
Unity gain bandwidth
> 130MHz
2
Table 2: Calculated transistor ratio of folded cascode.
3
Transistor
M1-M2
M3-M4
M5-M6
M7-M8
M9-M10
M11
Aspect
ratio
44
13
27
12
12
6
Width / W
(µm)
1.599
1.755
14.04
1.599
31.98
7.995
Length /L
(µm)
0.39
0.39
0.39
0.39
0.39
0.39
IDsat
(µA)
20
40
20
20
20
40
4
Table 3: Biasing circuit performances.
5
Voltage bias
Transistor
Vbias1
Vbias2
Vbias3
M1-M2
M5
M8-M9
(W/L) ratio
Width Length
9.35µm 300 nm
705 nm 300 nm
150 nm 300 nm
Voltage (V)
Iref (µA)
1.00007
0.90019
0.50012
20.0003
20.0021
20.0021
6
7
8
9
24
Table 4: Transistor sizing in CMFB circuit.
1
Transistor
M1
M2-M3
M4
M5
Width (W)
1.0 µm
785 nm
800 nm
2.5 µm
Length (L)
150 nm
150 nm
130 nm
130 nm
IDsat
1.00021 µA
1.00096 µA
1.00108 µA
1.0077 µA
2
3
4
Table 5 Folded Casode Op-Amp Performances
Parameter
Value
DC gain
64.5 dB
Unity gain bandwidth
695.1 MHz
Cut-off frequency
52.5 kHz
Phase margin
68.4º
CMRR
41.48 dB
ICMRR
0.5 V
PSRR
73.15 dB
Slew rate
22.6 V/µs
Settling time
72.4 ns
Output voltage swing
0.4 V – 1.65 V
Power consumption
0.14 mW
5
6
7
8
9
25
Table 6 Process Information
1
No Vin
B1
B0
DAC
Residue output
Output
1.
Vin > Vref/4
1
0
+ Vref
2Vin – Vref
2.
 Vref/4 < Vin < Vref/4
0
1
0
2Vin
3.
Vin <  Vref/4
0
0
 Vref
2Vin + Vref
2
3
Table 7 Comparison performances of proposed Folded Cascode Op-Amp with
4
previously published work
References
[12]
[13]
[14]
[15]
[16]
This
work
Technology (µm)
0.18
0.13
0.13
0.18
0.18
0.13
Voltage supply (V)
1.8
3.0
1.8
1.8
1.8
1.8
DC gain (dB)
90.39
94.9
91.5
92.0
103.94
64.5
Unity gain bandwidth
700.7
414
714.5
1600.0
344.5
695.1
Phase margin (º)
63.85
82.3
62.0
76.0
61.06
68.4
Slew rate (V/µs)
N/A
N/A
N/A
N/A
2883.5
22.6
Settling time (ns)
N/A
6.17
40.0
7.0
N/A
72.4
Power consumption
3.24
11.0
9.0
7.8
1.0
0.14
Load capacitance (pF)
0.5
2.0
7.5
0.15
1.0
1.0
Resolution(bits)
10
12
14
14
3
10
(MHz)
(mW)
5
26