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Transactions on Power Electronics
Model-Based Fault Detection and Identification for
Switching Power Converters
Jason Poon, Student Member, IEEE, Palak Jain, Ioannis C. Konstantakopoulos, Costas Spanos, Fellow, IEEE,
Sanjib Kumar Panda, Senior Member, IEEE, Seth R. Sanders, Fellow, IEEE
Abstract—We present the analysis, design, and experimental
validation of a model-based fault detection and identification
(FDI) method for switching power converters using a modelbased state estimator approach. The proposed FDI approach is
general in that it can be used to detect and identify arbitrary
faults in components and sensors in a broad class of switching
power converters. The FDI approach is experimentally demonstrated on a nanogrid prototype with a 380 V DC distribution
bus. The nanogrid consists of four different switching power
converters, including a buck converter, an interleaved boost
converter, a single-phase rectifier, and a three-phase inverter. We
construct a library of fault signatures for possible component
and sensor faults in all four converters. The FDI algorithm
successfully achieves fault detection in under 400 µs and fault
identification in under 10 ms for faults in each converter. The
proposed FDI approach enables a flexible and scalable solution
for improving fault tolerance and awareness in power electronics
systems.
Index Terms—Fault detection, fault diagnosis, state estimation,
fault location, microgrid
I. I NTRODUCTION
Commercial buildings consume nearly one-fifth of the
primary energy in the United States. In recent years, the
concept of a zero-energy building has emerged as an important
industrial effort towards realizing significant improvements in
building energy efficiency, user comfort, and intelligence [1],
[2]. Integral to the concept of a zero-energy building is its
power distribution network, or nanogrid, as shown in Fig. 1.
As opposed to buildings that purely consume energy, these
nanogrids can contain on-site microgeneration resources, such
as rooftop photovoltaics or wind turbines. Energy storage
buffers, such as batteries or mechanical flywheels, store excess
generated energy, which can be used for building loads or
sold back to the utility. Additionally, electrical loads can be
scheduled based on dynamic energy pricing, enabling demand
This work is supported in part by the NSF through the Graduate Research
Fellowship program, in part by Republic of Singapore’s National Research
Foundation through a grant to the Berkeley Education Alliance for Research
in Singapore (BEARS) for the Singapore-Berkeley Building Efficiency and
Sustainability in the Tropics (SinBerBEST) Program, and in part by the
Alexander S. Onassis Public Benefit Foundation. This paper was presented in
part at the 2015 IEEE Applied Power Electronics Conference on March 16,
2015.
J. Poon, I. Konstantakopoulos, C. Spanos, and S. Sanders are with the
Department of Electrical Engineering and Computer Sciences at the University
of California, Berkeley, CA 94720 USA (email: {jason, ioanniskon, spanos,
seth.sanders}@berkeley.edu).
P. Jain and S. Panda are with the Department of Electrical and Computer
Engineering at the National University of Singapore, Singapore 119077
(email: {palakjain, sanjib.kumar.panda}@nus.edu.sg.
response. Indeed, zero-energy building nanogrids introduce a
new paradigm of how buildings consume, generate, and store
energy.
However, the confluence of power electronics systems and
buildings in these nanogrids has introduced new challenges,
particularly with respect to availability, reliability, and system
security and safety [3]. Switching power converters introduce
new failure points in a power distribution network. Moreover,
the interactions between converters and the propagation or
cascading effect of faults through a nanogrid remain open
research questions.
In general, systems with critical dependability requirements
are designed with mechanisms for fault tolerance. Fault tolerance is the ability of a system to adapt and compensate, in
a systematic way, to faults in components, sensors, or inputs,
while providing completely or partially its intended functionality. There are three key elements to any fault tolerant system
design: (1) component redundancy, (2) a fault detection and
identification (FDI) system [4]–[6], and (3) a remediation or
reconfiguration system that, once a fault has been detected and
identified, substitutes the faulty component with a redundant
one, or reconfigures the control to compensate for the fault.
An FDI system is advantageous in that it can contribute
to the fault tolerance of a system with minimal additional
cost and system complexity (as opposed to an approach using
component redundancy). An FDI system executes two tasks:
(1) detection, which makes a binary decision whether or not a
fault has occurred, and (2) identification, which determines the
location of the faulty component [4]. It is important to note
that an FDI system, in general, does not replace hardwarebased fault protection devices, such as fuses, circuit breakers,
and internal semiconductor module protection. Instead, an
FDI system provides on-line granular information about the
converter state and health, which can be used for monitoring,
prognosis, and automated fault remediation.
Fault detection and identification for power electronics
systems has been explored in literature before (see Table I),
primarily for specific converter topologies and for specific
converter faults. For instance, in [13], [15]–[19], [22], [25]–
[27], [33], [35], [36], [39], [43], [44], [47]–[50], [54], [58],
[59], the authors investigate FDI techniques specifically for
three-phase drives in electric vehicles. In other works, authors
have focused on detecting and identifying specific component
faults (e.g. open- and short-circuit switch faults, gate driver
faults, capacitor faults) in DC-DC converters [10]–[12], [34],
[41], grid-connected AC-DC converters and DC-AC converters [8], [14], [21], [32], [40], [42], [45], [46], [52], and in
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Transactions on Power Electronics
380 VDC Distribution Bus
Interleaved Boost Converter
R1
L1
R2
L2
SW1
Buck Converter
SW5
SW3
SW1
SW5
R
L
SW6
SW4
SW2
Switching Node
SW4
SW6
Switching Node
1ϕ Rectifier
L
Rdc
C
C
SW2
R
SW3
3ϕ Inverter
SW1
SW5
SW3
SW1
C
SW2
SW4
SW6
Switching Node
SW3
SW5
C
SW2
SW4
Ra
La
Rl
Ll
Rb
Lb
Rl
Ll
Rc
Lc
Rl
Ll
SW6
Switching Node
Fig. 1: A DC-based power distribution nanogrid.
TABLE I: A review of existing literature in FDI methods for power electronics systems.
Hardware-based (analog circuits)
Model-based
Signal processing (time domain)
Signal processing (frequency domain)
Statistical
Machine learning
Hidden Markov model
Switch fault
[7]–[13]
[14]–[24]
[32]–[34]
[42]–[47]
[44], [48]
[13], [43], [47], [49]–[53]
[56]
modular multilevel converters [20], [24], [60]. Some literature
has focused on detecting faults in current and voltage sensors
in converter systems [27], [45].
However, to the best knowledge of the authors, no work has
been reported towards a generalized FDI approach for components and sensors that is suitable for an arbitrary switching
power converter. The majority of the existing FDI techniques
are specialized for a specific converter topology and cannot
be easily ported from one converter to another. Indeed, such a
generalized FDI approach would be particularly beneficial in
a nanogrid setting, which could feature an array of DC-DC,
DC-AC, or AC-DC converters.
Methodologies used for fault detection and identification
can be broadly classified into model-based and model-free
approaches. Model-based approaches use analytical knowledge of the system and are generally based on residual
generation using parameter estimation, parity equations, or
state observers [14]–[23], [25]–[31]. Signal processing techniques, which are a subset of model-based methods, monitor
the difference between nominal and faulty states of signals
to indicate abnormalities. Signal processing FDI approaches
can either be in the time domain (see e.g. [32]–[41]) or in
the frequency domain (see e.g. [22], [42]–[47]). However,
in general, signal processing techniques require a relatively
long time (10 to 20 ms) to identify faults depending on the
computational complexity of the algorithm and the latency of
the computing platform.
Multiple switch fault
[10]
[25], [26]
[35]–[40]
[22]
[22], [40], [54]
[57]
Open-phase
[8]
[18]
[41]
[44]
[44]
[55]
-
Sensor fault
[27]
[45]
-
Passive element fault
[28]–[31]
-
Model-free approaches rely on artificial intelligence-based
techniques, such as machine learning, artificial neural networks, or fuzzy logic, to develop an expert system that once
trained, can identify specific faults [13], [22], [40], [43], [44],
[47]–[55]. Drawbacks of these approaches are the excessive
computational requirements and large data sets required to
train the algorithms.
Finally, the FDI techniques can be further classified into
analog or digital implementation. It is evident that analog
implementations can identify faults relatively fast (around
1-100 µs) (see e.g. [7]–[13]). However, the analog implementations are both converter and fault specific. Digital implementations generally provide more flexibility in terms of
reconfigurability (see e.g. [14], [17]–[19], [22], [23], [32],
[33], [35], [39], [41]). Additionally, field-programmable gate
array (FPGA) implementations have demonstrated fault identification at speeds comparable to analog implementations in
some applications [14], [22], [32].
In this paper, we present a generalized model-based methodology for fault detection and identification in switching power
converters. The proposed FDI approach is general in that it can
be used to detect and identify arbitrary faults in components
and sensors in a broad class of switching power converters.
More importantly, the modeling and implementation of the
proposed FDI approach is flexible for both the converter
topology and faults of interest; that is, one would require
minimal effort to reconfigure an existing FDI implementation
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Transactions on Power Electronics
for a different converter topology or fault type. The proposed
FDI method can be integrated with the existing control system
of the switching power converter, requiring no additional electrical or computation hardware. In essence, the FDI method
enables a layer of intelligence on top of existing hardware
protection such as fuses and circuit breakers.
The proposed FDI approach uses switched linear state
estimator to generate a real-time error residual which captures
the difference between the measured and estimator outputs
(i.e. voltages and currents) of an arbitrary switching power
converter. When a fault occurs in the converter, the error
residual becomes non-zero, which enables fault detection. We
show that the dynamics of the error residual can be used to
achieve fault identification.
We present an experimental demonstration of the FDI approach on a nanogrid prototype with a 380 V DC distribution
bus. The FDI algorithm is implemented on four different
switching power converters–a buck converter, an interleaved
boost converter, a single-phase rectifier, and a three-phase
inverter. We validate the performance and speed of the FDI
algorithm for a variety of component and sensor faults for
each converter. We show that the FDI approach enables fast
fault detection and fault identification with speed on the order
of application-specific implementations in literature, but with
the advantage of being converter- and fault-agnostic in terms
of modeling and implementation.
The remainder of the paper is organized as follows. Section II presents the switched linear modeling framework used
to model the nominal and faulted dynamics of a general
switching power converter. Section III presents the proposed
algorithm for fault detection and identification. Section IV
presents a simulation of the proposed FDI algorithm, and
demonstrates its robustness in the presence of converter nonidealities such as switch and passive component parasitics and
component parameter variations due to aging and degradation.
In Section V, we describe the nanogrid testbed used to
experimentally validate the FDI algorithm. We present the
techniques used to implement the FDI algorithm in realtime. Section VI presents experimental results that verify the
FDI algorithm on four different switching power converters.
Section VII concludes the paper.
II. C ONVERTER
AND
R1
SW1
SW3
SW5
vin (t)
C
SW2
SW4
iload (t)
SW6
Switching Node
Fig. 2: Boost converter topology.
TABLE II: Possible open/close switch positions for the boost converter in
continous conduction mode.
σ(t)
s1
s2
1
0
1
2
1
0
open/closed position for the switches in a converter (e.g.
diodes, IGBTs, MOSFETs, etc.) and applying Kirchhoff’s
circuit laws for the resulting linear circuit. The switching
signal can be obtained by considering a logical union of
the dynamics of ‘controlled’ switches (e.g. PWM applied to
IGBTs or MOSFETs) and the dynamics of ‘uncontrolled’
switches (e.g. diodes) whose open/closed position depends on
the state of the system (e.g. the polarity of current flowing
through a diode). In general, the dynamics of an arbitrary
switching power converter can be modeled as a switched linear
system of the form [61]:
ẋ(t) = Aσ(t) x(t) + Bσ(t) u(t)
y(t) = Cx(t)
(1)
(2)
where Aσ(t) , Bσ(t) , and C are the collection of linear state
space models, and σ(t) is the continuous-time switching signal
that indicates the active mode.
Example 1. Consider the boost converter topology in Fig. 2.
In the continuous conduction mode of operation, the mode of
the system is determined explicitly by the PWM applied to
SW2 . It follows that:
iL1 (t)
vin (t)
x(t) = y(t) =
, u(t) =
vC (t)
iload (t)
FAULT M ODELING F RAMEWORK
In this section, we present the modeling framework used
to describe the dynamics of a switching power converter in
nominal and faulted operating conditions. We use the boost
converter topology shown in Fig. 2 as an illustrating example,
but the modeling framework and formalisms are applicable to
a broad class of switching power converters.
L1
Aσ(t) =
−R
L
s1
C
1
− sL1
, Bσ(t) = L
0
0
0
1
, C=
− C1
0
0
1
The possible values for the switching signal σ(t) are given
in Table II, where sk = 0 indicates switch SWk is open, and
sk = 1 indicates switch SWk is closed.
B. Post-Fault System Model
A. Nominal System Model
The switching power converters under consideration are
those that can be modeled as a switched linear system, that
is, a collection of linear state space models (modes) and a
continuous-time switching signal, which indicates the active
mode of the system at every time instant. The state space
model for each mode can be obtained by considering every
We consider two types of converter faults—(1) components
faults, that is, faults that manifest in passive or switching
elements, and (2) sensors faults, that is, faults that cause the
measured values in y(t) to deviate from the actual values of
x(t).
1) Component faults: Generally, component faults that
affect passive or switching elements manifest as additive
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Transactions on Power Electronics
deviations ∆A(t) and ∆B(t) from the nominal Aσ(t) and
Bσ(t) , respectively, in (1). Thus, the state dynamics in the
faulted condition can be modeled as:
ẋ(t) = Ãσ(t) x(t) + B̃σ(t) u(t)
(3)
where Ãσ(t) , Aσ(t) + ∆A(t) and B̃σ(t) , Bσ(t) + ∆B(t).
With algebraic manipulation, we can rewrite (3) as the sum
of (1) and the product of a time-varying scalar component
fault magnitude function φi (x, u) and a time-invariant vector
component fault signature fi , that is:
ẋ(t) = Aσ(t) x(t) + Bσ(t) u(t) + φi (x, u)fi
(4)
where i = 1, ..., I and I is the number of possible types of
component faults.
Example 2. Consider a fault in the output capacitor C of
the boost converter in Fig. 2 that causes the value of the
capacitance to change by a quantity ∆C. Thus, the dynamics
of the converter in the presence of this fault are:
R1
1
0
−L
− sL1
L
Ãσ(t) =
,
B̃
=
1
s1
σ(t)
0 − C+∆C
0
C+∆C
The fault magnitude function φ1 (x, u) and component fault
signature f1 from (4) are as follows:
∆C
(iload − s1 iL ),
C(C + ∆C)
f1 = [0, 1]T
φ1 (x, u) =
2) Sensor faults: Sensor faults manifest as affine deviations
in the output readout map in (2). That is, the output readout
map in the faulted condition can be modeled as:
y(t) = (C + ∆C(t))x(t) + ∆E(t)
(5)
where ∆C(t) and ∆E(t) capture the affine dynamics of the
sensor fault. Similar to the steps performed for the component
fault model in Section II-B1, we can rewrite (5) as the sum of
(2) and the product of a scalar sensor fault magnitude function
θj (x) and a vector sensor fault signature gj , that is:
y(t) = Cx(t) + θj (x)gj
(6)
where j = 1, ..., J and J is the number of possible types of
sensor faults.
Example 3. Consider a fault in the input inductor L1 current
sensor of the boost converter in Fig. 2 that causes a perturbation in the sensor gain c1 (t) and in the sensor offset e1 (t).
This perturbation can be modeled as:
c (t) 0
e (t)
∆C(t) = 1
, ∆E(t) = 1
0
0
0
III. FDI A LGORITHM D ESIGN
In this section, we present the proposed algorithm design
for fault detection and identification. The objectives of the
algorithm are two-fold—(1) make a binary decision as to
whether a component or sensor fault has occurred or not, and
(2) if a fault has been detected, identify precisely the type and
location of the faulted component or sensor.
Fundamentally, the proposed FDI algorithm consists of
a switched linear state estimator that calculates an error
residual between the measured output of the converter and
the estimated output. In the fault-free (nominal) condition,
the residual approaches zero. However, when a component or
sensor fault occurs, the residual becomes non-zero, enabling
fault detection. Moreover, we show that for different faults, the
residual evolves in a deterministic direction in vector space,
which enables fault identification.
A. Fault detection
We can build a switched linear state estimator of the system
from (1) as follows:
ż(t) = Aσ(t) z(t) + Bσ(t) u(t)
(7)
γ(t) = y(t) − Cz(t),
(8)
where z(t) is an estimate of the state vector x(t) from (1), and
γ(t) is the residual of the difference between the measured
output y(t) and the estimated output Cz(t). Fault detection is
achieved by monitoring the norm of the residual γ(t) at each
time step and comparing it with a predefined fault detection
threshold Γ; the value of Γ is determined empirically. When
kγ(t)k2 > Γ, the algorithm detects a fault.
1) Fault-free (nominal) condition: Let e(t) , z(t) − x(t).
In the fault-free (nominal) condition, the dynamics of e(t) are
governed by:
ė(t) = Aσ(t) e(t)
γ(t) = Ce(t)
(9)
(10)
The open-loop error dynamics of the state estimator are
stable (see [62]). Moreover, due to losses in the converter and
corresponding model, the error residual is zero in the steady
state for a fault-free system. Thus, γ(t) → 0 as t → ∞, and
no fault will be detected.
2) Component faults: When the ith component fault occurs,
the dynamics of the faulted converter can be modeled as in
(4). Thus, in this case, the dynamics of e(t) are governed by:
ė(t) = Aσ(t) e(t) − φi (x, u)fi
(11)
−Aσ(t) t
γ(t) = Ce(t) = Ce
e(0) + ...
Z t
... + C fi
e−Aσ(t) (t−τ ) φi (x, u)dτ
(12)
0
The fault magnitude function θ1 (x) and sensor fault signature
g1 from (6) are as follows:
θ1 (x) = c1 (t)iL1 (t) + e1 (t),
g1 = [1, 0]T
−Aσ(t) t
The term Ce
vanishes as t → ∞. However, the
Re(0)
t
(scalar) integral term 0 e−Aσ(t) (t−τ ) φi (x, u)dτ will become
non-zero depending on the dynamics of φi (x, u). Thus, when
the magnitude of this term causes kγ(t)k2 > Γ, the algorithm
will detect a fault.
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Transactions on Power Electronics
TABLE III: Component fault signature library.
Library element
Buck converter
i=1
i=2
Fault event
Change in capacitance by ∆C
Open circuit fault in SW1
Interleaved boost converter
i=3
Change in capacitance by ∆C
φi (x, u)
fi
∆C
(i
(t) − iL (t))
C(C+∆C) load
s1
− L vin (t)
[0, 1]T
∆C
(i
− s2 iL1
C(C+∆C) load
1
− ∆R
iL1 (t)
L
∆R2
− L iL2 (t)
i=4
Change in phase 1 series resistance by ∆R1
i=5
Change in phase 2 series resistance by ∆R2
i=6
Open circuit fault in SW2
s2
i=7
Open circuit fault in SW4
s4
Single-phase rectifier
i=8
Change in capacitance by ∆C
∆C
(i
(t)
C(C+∆C) load
Three-phase inverter
i=9
Change in phase a series resistance by ∆Ra
i = 10
Change in phase b series resistance by ∆Rb
i = 11
Change in phase c series resistance by ∆Rc
[1, 0]T
[0, 0, 1]T
− s4 iL2 )
[1, 0, 0]T
[0, 1, 0]T
iL
vC (t)
, 0, − C1 ]T
L1
i 2 T
(t)
,− L
]
[0, vC
L2
C
[
− iL (t))
∆Ra
i (t)
3L a
∆Rb
i (t)
3L b
∆Rc
i (t)
3L c
[0, 1]T
[−2, 1, 1]T
[1, −2, 1]T
[1, 1, −2]T
TABLE IV: Sensor fault signature library.
Library element
Fault event
Buck converter
j=1
Fault in iL (t) sensor
j=2
Fault in vC (t) sensor
Interleaved boost converter
j=3
Fault in iL1 (t) sensor
j=4
Fault in iL2 (t) sensor
j=5
Fault in vC (t) sensor
Single-phase rectifier
j=6
Fault in iL (t) sensor
j=7
Fault in vC (t) sensor
Three-phase inverter
j=8
Fault in iLa (t) sensor
j=9
Fault in iLb (t) sensor
j = 10
Fault in iLc (t) sensor
3) Sensor faults: When the j th sensor fault occurs, the
dynamics of the faulted converter can be modeled as in (6).
Thus, the dynamics of e(t) are governed by:
ė(t) = Aσ(t) e(t)
(13)
γ(t) = Ce(t) − θj (x)gj
(14)
The term Ce(t) vanishes as t → ∞. However, the term
θj (x) will become non-zero depending on the dynamics
of θj (x). Thus, when the magnitude of this term causes
kγ(t)k2 > Γ, the algorithm will detect a fault.
B. Fault identification
Fault identification is achieved via a two step process. First,
prior to running the FDI algorithm, a collection of component
fault signatures fi and sensor fault signatures gj are assembled
into a fault signature library, as shown in Tables III and IV.
The fault signatures are obtained by modeling faults of interest
and extracting fi and gj mathematically via (4) and (6).
Second, in real-time, an L2 -inner product is computed
between the residual γ(t) and every element of the fault
signature library. Intuitively, the L2 -inner product will reveal
θj (x)
gj
∆c1 (t)iL (t) + ∆e1 (t)
∆c2 (t)vC (t) + ∆e2 (t)
[1, 0]T
[0, 1]T
∆c3 (t)iL1 (t) + ∆e3 (t)
∆c4 (t)iL2 (t) + ∆e4 (t)
∆c5 (t)vC (t) + ∆e5 (t)
[1, 0, 0]T
[0, 1, 0]T
[0, 0, 1]T
∆c6 (t)iL (t) + ∆e6 (t)
∆c7 (t)vC (t) + ∆e7 (t)
[1, 0]T
[0, 1]T
∆c8 (t)iLa (t) + ∆e8 (t)
∆c9 (t)iLb (t) + ∆e9 (t)
∆c10 (t)iLc (t) + ∆e10 (t)
[1, 0, 0]T
[0, 1, 0]T
[0, 0, 1]T
which fault signature the residual most closely aligns with in
vector space.
In the case of the ith component fault, we see from (12)
that γ(t) will align with C fi . Mathematically, the L2 -inner
product is calculated as follows:
Z t
hγ(t), C fi iL2 =
γ T (t − τ )C fi (τ ) dτ
(15)
t−W
where W is the window size of the inner product calculation.
Similarly, for the j th sensor fault, we see from (14) that γ(t)
will align with gj . Mathematically, the L2 -inner product is
calculated as follows:
Z t
hγ(t), gj iL2 =
γ T (t − τ )gj (τ ) dτ
(16)
t−W
When the magnitude of an inner product calculation result
exceeds the predefined fault identification threshold Λ, the
algorithm identifies the fault as the one associated with the
appropriate fault signature.
In the instances when a component fault signature or sensor
fault signature is not unique, the magnitude of the L2 -inner
product can be used to identify the appropriate fault. Moreover,
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Transactions on Power Electronics
L1
Rpar1 Cpar1
vin (t)
15
SW1
C
Cpar2
Rpar2
SW2
Ron
Resr
Lpar2
Lpar1
iload (t)
iL1 (t) [A]
R1
10
5
0
Rpar3
0.5
1
1.5
Time [s]
2
-3
×10
(a) Inductor current iL1 (t).
Fig. 3: Boost converter model with switch and passive component parasitics.
Component parameters
C
L1
R
Parasitic parameters
Resr
Ron
Rpar1,2
Rpar3
Cpar1
Cpar2
Lpar1
Lpar2
Operating point
vin (t)
iload (t)
Switching frequency
Vbase
Ibase
2200 µF ±20%
5.00 mH ±20%
25 mΩ
AND
400
350
300
0
38 mΩ ±50%
1 mΩ
100 Ω
5Ω
1 pF
1 nF
5.00 nH
1 nH
190 V
5A
10 kHz
380 V
10 A
a frequency domain analysis of the residual γ(t) can also be
used in order to identify the fault (as shown in [14]). However,
the fault detection method remains unchanged.
IV. S IMULATION
vC (t) [V]
TABLE V: Simulation parameters for boost converter.
450
ROBUSTNESS A NALYSIS
In this section, we present a simulation of the FDI algorithm
using the boost converter as an illustrating example. The
FDI algorithm uses the ‘ideal’ model shown in Fig. 2 and
developed in Example 1. However, the boost converter plant is
simulated using the model shown in Fig. 3, which accounts for
switch and passive component parasitics and also component
parameter variations in the output capacitance C, the input
inductance L1 , and the ESR of the output capacitance Resr .
These parasitics and parameter variations are used to test the
robustness of both the fault detection and fault identification
algorithms in the presence of such converter non-idealities.
Fig. 4 shows the dyanmics of the parasitic model in steady
state with nominal component parameters. Variations in the
input voltage vin (t) and the load current iload (t) do not
influence the FDI algorithm as these variables are explicitly
measured from the plant and fed into the state estimator via
the input vector u(t).
The implementation details of the simulation are as follows.
The converter and FDI algorithm are co-simulated at the
minimum and maximum of each parameter variation, that is, at
the corners of the accepted parameter space of (L1 , C, Resr ).
The residual γ(t) is normalized to the appropriate Vbase and
Ibase shown in Table V. The fault detection threshold Γ is
selected such that the worst-case voltage and current transients
0.5
1
1.5
Time [s]
2
×10-3
(b) Capacitor voltage vC (t).
Fig. 4: Steady state dynamics of boost converter model with switch and passive
component parasitics (Fig. 3) with nominal component parameters.
related to circuit parasitics do not cause kγ(t)k2 to exceed
the fault detection threshold Γ. Similar design considerations
are used to select the fault identification threshold Λ. For the
simulations, we select Γ = 0.5 and Λ = 0.1. Of the eight
corners of the accepted parameter space that are simulated,
the worst-case scenario with respect to dynamics adversely
affecting γ(t) occurs at (min(L1 ), max(C), max(Resr ). Our
selection of Γ and Λ provide sufficient tolerance to prevent
false positives while still ensuring minimal time to fault
detection and identification.
The fault signature library for the simulation contains two
fault signatures: (1) f1 , the component fault signature for a
fault in the output capacitor C, as derived in Example 2,
and (2) g1 , the sensor fault signature for a fault in the input
inductor L1 current sensor, as derived in Example 3.
First, we simulate a fault in the output capacitor causing
C → 0. The fault emulates the dynamics of a capacitor open
circuit fault, which can be caused by a rapid increase of Resr .
As shown in Fig. 5a, fault detection occurs essentially instantaneously as kγ(t)k2 exceeds the fault detection threshold Γ
at t = 0. Fig. 5b shows the L2 -inner product between γ(t)
and C f1 and g1 . As shown, the residual correctly aligns with
C f1 , and exceeds the fault identification threshold Λ in 0.20.3 ms.
Second, we simulate a fault in the input inductor L1
current sensor causing the sensor gain c1 (t) → 0. Again,
fault detection occurs essentially instantaneously as shown in
Fig. 6a. Fault identification occurs in 0.1 ms, as the residual
correctly aligns with g1 as shown in Fig. 6b.
In both fault cases, the FDI algorithm is able to correctly detect and identify the appropriate fault even in the preswence of
the non-ideal plant dynamics. For fault detection, the threshold
Γ prevents any dynamics caused by parasitics or component
parameter variation from raising a false fault detection flag.
For fault identification, the moving window W of the L2 -inner
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kγ(t)k2 [p.u.]
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Transactions on Power Electronics
TABLE VI: Specifications and ratings for nanogrid testbed.
1
0.5
Γ
0
-2
-1
0
1
Time [s]
2
×10
-3
(a) Plot of kγ(t)k2 and the fault detection threshold Γ.
[p.u.]
1
hγ(t), C f1 iL2
0.5
Λ
0
-2
hγ(t), g1 iL2
-1
0
1
Time [s]
2
×10
-3
(b) Plot of hγ(t), C f1 iL2 , hγ(t), g1 iL2 , and the fault
identification threshold Λ.
kγ(t)k2 [p.u.]
Fig. 5: Simulation of the FDI algorithm for a capacitor fault injected at t =
0 causing C → 0. Shown is the worst-case scenario caused by parameter
variation (min(L1 ), max(C), max(Resr ).
Γ
-1
0
1
Time [s]
2
×10
-3
(a) Plot of kγ(t)k2 and the fault detection threshold Γ.
1
[p.u.]
5.00 mH
0.82 Ω
2200 µF
5.00 mH
25 mΩ
2200 µF
dSPACE DS1103 controller
100 µs
10 to 20 kHz
Typhoon HIL602
500 ns
20 ns
1 MHz
A. Nanogrid testbed
0
-2
hγ(t), g1 iL2
0.5
hγ(t), C f1 iL2
Λ
0
-2
150 V, 40 A, 2 kW
305 Vrms , 11 Arms , 1 kVA
150 V, 33 A, 165 W
220 Vrms , 8.7 Arms , 3.3 kW
1200 V, 25 A, IP67 enclosure
Infineon FS25R12W1T4
Semikron SKHI 61R
LEM LA25-NP
LEM LV25-P
Fig. 7. The complete specifications and ratings are presented
in Table VI.
1
0.5
PV emulator ratings
AC grid emulator ratings
Controlled DC load
Three-phase AC load
Switching node ratings
IGBT module
Gate driver
Current sensors
Voltage sensors
Buck and interleaved boost converter
L, per phase
R, per phase
C
Rectifier and three-phase inverter
L, per phase
R, per phase
C
FDI computing platform
Model
Controller time step
Converter switching frequency
Real-time model-based estimator
Model
Simulation time step
PWM sampling interval
ADC/DAC sampling rate
-1
0
Time [s]
1
2
×10-3
(b) Plot of hγ(t), C f1 iL2 , hγ(t), g1 iL2 , and the fault
identification threshold Λ.
Fig. 6: Simulation of the FDI algorithm for a fault in the input inductor L1
current sensor injected at t = 0. Shown is the worst-case scenario caused by
parameter variation (min(L1 ), max(C), max(Resr ).
product provides an added benefit as a natural low-pass filter
that removes the effects of parasitic ringing and transients. The
fault identification threshold Λ accounts for dynamics caused
by variations in component parameters.
The prototype nanogrid testbed consists of four converters
that interface two sources—a PV emulator and a single phase
AC grid emulator—with two loads—a controlled DC load
and a resistive three-phase load—through an intermediate
380 VDC distribution bus. The circuit schematics of all
four converters are shown in Fig. 1. An MPPT-controlled
interleaved boost converter interfaces the PV emulator with the
DC distribution bus. A single-phase rectifier interfaces the AC
grid emulator to the DC bus. A buck converter and three-phase
inverter are used to interface the DC load and three-phase AC
load, respectively.
The design of each converter is modularized by using a
standardized switching node. A switching node consists of a
sixpack IGBT module configured as three half-bridges, a gate
driver module, and four current and four voltage sensors all
enclosed in an IP67 rated enclosure. The implementation of
the switching node is shown in Fig. 8. A switching node is
configured with appropriate passive elements to form each of
the four converters.
Finally, two dSPACE D1103 controller boards implement
the closed-loop control for each converter. It is worth noting
that the converters are controlled individually, that is, there is
no supervisory controller for the entire nanogrid testbed.
V. I MPLEMENTATION AND NANOGRID T ESTBED
In this section, we present a prototype nanogrid used to
validate the FDI algorithm on four switching power converters.
Moreover, we discuss the real-time implementation of the
FDI algorithm proposed in Section III. A photograph of the
prototype nanogrid and FDI computing platform is shown in
B. FDI computing platform
The FDI algorithm is implemented on two separate realtime computing devices. First, the state estimator discussed
in Section III is implemented on a Typhoon HIL602. The
FPGA processor architecture of this device is tailored for
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Transactions on Power Electronics
Typhoon HIL602
280 mm
Current and voltage sensor boards
PV emulator
dSpace DS1103 Controllers
380 mm
AC grid emulator
Interleaved boost converter
Buck converter and controlled DC load
Gate driver
IGBT module
380 VDC bus
Single-phase rectifier
Inverter and three-phase AC load
DC connection
AC connection
Fig. 8: Switching node implementation.
Fig. 7: Photograph of the FDI computing platform and prototype nanogrid testbed.
solving switched linear state space models of power electronics systems with a fixed simulation time step of 500 ns,
including input-output latency [63]. Moreover, the multi-core
architecture enables multiple state estimators of independent
converters to be solved simultaneously. This allows us to run
the state estimation algorithm for each of the four converters
in parallel on a single device.
Second, the fault detection and identification algorithms
are implemented on the dSPACE DS1103 controller boards.
These devices, in addition to operating the closed-loop control
for each converter, execute the FDI algorithm discussed in
Sections III-A and III-B. That is, for each converter, the
DS1103 performs the following tasks: (1) stores the fault
signature library, (2) generates an error residual based on
signals from the converter sensors and the state estimator
output, and (3) generates fault detection and fault identification
flags based on the magnitude of the error residual and the L2 inner product calculation.
VI. E XPERIMENTAL R ESULTS
In this section, we present experimental results of the
proposed FDI algorithm on the testbed presented in Section V.
Figs. 9, 10, 11, and 12 show the dynamics of various faults and
load changes in four different converters, where fd indicates
the instance of fault detection, and fi indicate the instance
of fault identification. For each converter, we choose the
fault detection threshold Γ = 0.5 and the fault identification
threshold Λ = 0.1. In every test case, these values provide
sufficient tolerance to dynamics caused by converter nonidealities, such as parasitics and parameter variation.
Table VII presents the experimentally measured time to fault
detection (td ) and time to fault identification (ti ) for each
fault. For most faults, the time to fault detection is one or
two time steps of the real-time FDI computing platform (in
this case, fixed time step is 100 µs for the dSPACE DS1103
controller). The time to fault identification generally depends
on the dynamics of the particular fault and how fast the fault
signature evolves.
TABLE VII: Experimentally measured time to fault detection (td ) and time
to fault identification (ti ).
Buck converter
Current sensor fault
Open circuit fault
Load change
Interleaved boost converter
Current sensor fault
Phase open circuit fault
Load change
Single-phase rectifier
Current sensor fault
Capacitor fault
Load change
Three-phase inverter
Current sensor fault
Phase open circuit fault
Load change
td
ti
Fig. 9a
Fig. 9b
Fig. 9c
280 µs
132 µs
-
880 µs
113 ms
-
Fig. 10a
Fig. 10b
Fig. 10c
360 µs
340 µs
-
4.4 ms
8.65 ms
-
Fig. 11a
Fig. 11b
Fig. 11c
146 µs
400 µs
-
456 µs
9.3 ms
-
Fig. 12a
Fig. 12b
Fig. 12c
220 µs
170 µs
-
2.90 ms
3.45 ms
-
Additionally, for each converter, we test load changes in
order to demonstrate that the FDI algorithm is immune to
events external to the switching power converter, such as
changes in load or input power, or faults in elements external
to the converter. In this way, fault or events in one converter
will not influence the FDI algorithm in a separate converter.
A. Buck converter (Fig. 9)
The dynamics of a fault in the current sensor (iL (t)) that
force the sensor gain to zero are shown in Fig. 9a. As shown,
when the fault is injected, the measured iL (t) begins to
exponentially decay, while the dynamics of vC (t) and iload (t)
remain unchanged. The FDI algorithm detects the current
sensor fault in 280 µs, and correctly identifies the fault in
880 µs.
Fig. 9b shows the dynamics of an open switch fault in SW1 .
The current in the inductor iL (t) immediately becomes zero,
while the capacitor begins discharging across the output load.
This fault is detected in 360 µs. The time to fault identification
depends on the RC time constant of the output capacitor
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Fault injected
fd
fi
Fault injected
fd
fi
Load change
vC(t)
vC(t)
vC(t)
iL(t)
iL(t)
iL(t)
iload(t)
iload(t)
iload(t)
500 us/div
5 ms/div
50 ms/div
(a) Sensor fault in iL (t) sensor.
(c) Load step change in iload (t).
(b) Open switch fault in SW1 .
Fig. 9: Buck converter FDI experimental results.
Fault injected fd
fi
Fault injected
vC(t)
fd
fi
Load change
vC(t)
iL (t)
iload(t)
iL (t)
1
iL (t)
1
1
iL (t)
2
5 ms/div
(a) Sensor fault in iL2 (t) sensor.
iL (t)
iL (t)
2
2
20 ms/div
5 ms/div
(c) Load step change in iload (t).
(b) Open phase fault in phase 1.
Fig. 10: Interleaved boost converter FDI experimental results.
Fault injected fi
Fault injected fd
fi
Load change
vC(t)
vC(t)
vC(t)
iL(t)
iL(t)
iL(t)
iload(t)
iload(t)
10 ms/div
(a) Sensor fault in iL (t) sensor.
iload(t)
10 ms/div
(b) Capacitor fault causing C → 0.
10 ms/div
(c) Load step change in iload (t).
Fig. 11: Single-phase rectifier FDI experimental results.
and resistive load, as this will determine how fast the fault
signature evolves. In this case, fault identification requires
113 ms.
Finally, Fig. 9c shows the response of the system to a
step change in the load current. As shown, the step change
causes the inductor current iL (t) to increase. However, the FDI
algorithm recognizes this as an external event to the switching
power converter, and does not raise a fault flag.
B. Interleaved boost converter (Fig. 10)
Fig. 10a shows the dynamics of a sensor fault in iL2 (t) that
force the sensor gain to zero. The measured current in iL2 (t)
becomes zero, while vC (t) and iL1 (t) remain unchanged. The
fault is detected in 360 µs, and is identified in 4.4 ms.
The dynamics of an open phase 1 fault are shown in
Fig. 10b. As shown, the current iL1 (t) immediately becomes
zero, and the current iL2 (t) increases in order to compensate for the lost phase. The output voltage vC (t) remains
unchanged. The FDI algorithm detects this fault in 340 µs,
and identifies it in 8.65 ms.
Fig. 10c shows the response of the system to a step
change in the load current iload (t). The load increase causes a
balanced increase in the currents flowing through both phases
(iL1 (t) and iL2 (t)). Again, since this is a normal external
event, the FDI algorithm does not detect it as a fault.
C. Single-phase rectifier (Fig. 11)
The dynamics of a current sensor fault (iL (t)) are shown in
Fig. 11a. As shown, the measured current becomes zero, while
the remaining measured outputs (vC (t) and iload (t)) remain
unchanged. This fault is detected in 146 µs, and identified in
456 µs.
Fig. 11b shows the response of the system when the output
capacitance C of the rectifier becomes 0. As shown, the fault
causes a large periodic ripple in the output voltage vC (t), while
subsequently causing a distorted waveform in the inductor
current iL (t). The FDI algorithm detects the capacitor fault
in 400 µs, and correctly identifies the fault in 9.3 ms.
Finally, Fig. 11c shows the response of the system to a
step change in the output load. As shown, the periodic current
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Fault injected fd fi
Fault injected fd fi
Load change
ia(t)
ia(t)
ia(t)
ib(t)
ib(t)
ib(t)
ic(t)
ic(t)
5 ms/div
5 ms/div
(a) Sensor fault in ia (t) sensor.
(b) Open phase fault in phase b.
ic(t)
10 ms/div
(c) Balanced load step change in Rl .
Fig. 12: Three-phase inverter FDI experimental results.
pulses in iL (t) become larger, while the output voltage vC (t)
remains unchanged. The FDI algorithm does not raise a fault
flag for this external event.
D. Three-phase inverter (Fig. 12)
Fig. 12a shows the dynamics of a current sensor fault in
phase a of the three-phase inverter. As shown, the measured
current ia (t) immediately becomes zero, while the current in
the remaining two phases are unchanged. The FDI algorithm
detects the fault in 220 µs, and identifies it in 2.90 ms.
Next, Fig. 12b shows the response of the system during
the phase b open circuit fault. This fault can be modeled as a
sharp increase in the series resistance Rb . The current in phase
b immediately becomes zero, while the currents in phase a and
c become 180 degrees out of phase. The fault is detected in
170 µs, and is correctly identified in 3.45 ms.
Lastly, the dynamics of a balanced load change are shown
in Fig. 12c. As shown, the load change causes a balanced
increase in the currents in all three phases of the inverter.
Again, the FDI algorithm does not raise a fault flag for this
external event.
VII. C ONCLUSIONS
This paper has demonstrated an approach to model-based
fault detection and identification for arbitrary switching power
converters. The approach is experimentally implemented and
validated for four different converter topologies that demonstrate the applicability of the FDI method for a nanogrid
setting. The experimental results show the efficacy of the
proposed approach for fast fault detection and identification
for a variety of common fault events in switching power
converters. In this way, the proposed fault FDI method enables
a flexible solution for improving reliability and fault tolerance
in an array of power electronics applications.
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Transactions on Power Electronics
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2541342, IEEE
Transactions on Power Electronics
Jason Poon (S’11) received the B.S. degree from
Olin College in 2012 and the M.S. degree from
the University of California, Berkeley in 2015, all
in electrical engineering. He is currently working
towards the Ph.D. degree in electrical engineering
at UC Berkeley. He has previously held research
positions at ABB Corporate Research Center in
Baden-Dättwil, Switzerland and at MIT in Cambridge, Mass. His research interests include power
electronics, digital control, and embedded and cyberphysical systems theory.
Palak Jain received her B.E. degree (2012) in
electrical engineering from Delhi College of Engineering, D.U., Delhi, India. She is currently working
on her Ph.D in electrical engineering at National
University of Singapore, Singapore. Her research
interests include the areas of system reliability theory and their application to energy systems, cyberphysical systems theory and real time simulation.
Ioannis C. Konstantakopoulos received the
Diploma Engineering degree in Electrical and Computer Engineering in 2012 from the University of Patras, Greece and the Master of Science in Electrical
Engineering and Computer Sciences in 2014 from
University of California, Berkeley. He is currently
working toward the Ph.D. degree in the Department
of Electrical Engineering and Computer Sciences at
UC Berkeley. His current research interests include
statistical learning theory, machine learning, game
theory, and optimization theory.
Costas Spanos (M’87–SM’92–F’98) received the
EE Diploma from the National Technical University
of Athens, Greece in 1980 and the M.S. and Ph.D.
degrees in ECE from Carnegie Mellon University
in 1981 and 1985, respectively. In 1988 he joined
the Faculty at the department of Electrical Engineering and Computer Sciences of the University of
California, Berkeley. He has served as the Director
of the Berkeley Microlab, the Associate Dean for
Research in the College of Engineering and as the
Chair of the Department of EECS. He works in
statistical analysis in the design and fabrication of integrated circuits, and on
novel sensors and computer-aided techniques in semiconductor manufacturing.
He also works on statistical data mining techniques for energy efficiency
applications. He has participated in two successful startup companies, Timbre
Tech, (acquired by Tokyo Electron) and OnWafer Technologies (acquired
by KLA-Tencor). He is presently the Director of the Center of Information
Technology Research in the Interest of Society (CITRIS) and the Chief
Technical Officer for the Berkeley Educational Alliance for Research in
Singapore (BEARS).
Sanjib Kumar Panda (S’86–M’91–SM’01) received B. Eng. Degree from the South Gujarat
University, India, in 1983, M.Tech. degree from
the Indian Institute of Technology, Banaras Hindu
University, Varanasi, India, in 1987, and the Ph.D.
degree from the University of Cambridge, U.K., in
1991, all in electrical engineering. Since 1992, he
has been holding a faculty position in the Department of Electrical and Computer Engineering, National University of Singapore and currently serving
as an Associate Professor and Director of the Power
& Energy Research Area. Dr. Panda has published more than 200 peerreviewed research papers, co-authored one book and contributed to several
book chapters and six patents. His research interests include high-performance
control of motor drives and power electronic converters, condition monitoring
and condition based maintenance, building energy efficiency etc. He was
the recipient of the Cambridge-Nehru Scholarship and M. T. Mayer Graduate Scholarship during his PhD study (1987-1991). He is serving as an
Associate Editor of several IEEE Transactions and Editor of the Journal
of Power Electronics, South Korea. He has served in various capacities
for the two key conferences IEEE Power Electronics and Drive Systems
(PEDS) Conference and IEEE International Conference on Sustainable Energy
Technologies (ICSET) Conference series organized and managed by the IEEE
Joint IAS/PELS Society Chapter, Singapore Section. Dr. Panda has received
the IEEE Third Millennium Medal. He is serving as the IEEE R-10 AsiaPacific Liaison Officer for the IEEE PELS. He is also the recipient of the
IEEE Singapore Section Outstanding Volunteer Award in 2010 and the IEEE
Region-10 Outstanding Volunteer Award in 2014. He has served the IEEE
Section Congress 2014 as a Member of the Program Committee.
Seth R. Sanders (S’88–M’88–SM’08–F’10) is Professor in the Department of Electrical Engineering
and Computer Sciences at the University of California, Berkeley. He received S.B. degrees (1981)
in Electrical Engineering and Physics, and the S.M.
(1985) and Ph.D. (1989) degrees in Electrical Engineering from the Massachusetts Institute of Technology, Cambridge. Following an early experience as a
Design Engineer at the Honeywell Test Instruments
Division in 1981-83, he joined the UC Berkeley
faculty in 1989. Dr. Sanders technical interests are
in electrical energy and power conversion systems . Dr. Sanders is presently
or has recently been active in supervising research projects in the areas of
flywheel energy storage, electric machine design, renewable energy systems,
integrated power conversion circuits, and IC designs for power conversion
applications. Dr. Sanders is co-founder and CTO of Amber Kinetics, Inc.,
a technology developer, manufacturer, and project developer of utility scale
flywheel energy storage systems. During the 1992-1993 academic year, he
was on industrial leave with National Semiconductor, Santa Clara, CA. Dr.
Sanders received the NSF Young Investigator Award and multiple Best Paper
Awards from the IEEE Power Electronics and the IEEE Industry Applications
Societies. He has served as Chair of the IEEE PELS Technical Committee
on Computers in Power Electronics, Chair of the IEEE PELS Technical
Committee on Power Conversion Components and Systems, and as MemberAt-Large of the IEEE PELS Adcom. He is an IEEE Fellow, a Distinguished
Lecturer of the IEEE PELS and IAS societies, and recipient of the IEEE PELS
Modeling and Control Technical Achievement Award.
0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.