Design and Development of Organically Packaged
Components and Modules for Microwave and MillimeterWave Applications
A Ph.D. Dissertation
Presented to
The Academic Faculty
by
Wasif Tanveer Khan
In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in
Electrical and Computer Engineering
School of Electrical and Computer Engineering
Georgia Institute of Technology
December 2014
Copyright © 2014 by Wasif Tanveer Khan
Design and Development of Organically Packaged
Components and Modules for Microwave and
Millimeter wave Applications
Approved By:
Professor John Papapolymerou, Advisor
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor Madhavan Swaminathan
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor Andrew Peterson
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor John Zhang
School of Chemistry and
Bio-Chemistry
Georgia Institute of Technology
Professor John Cressler
School of Electrical and Computer
Engineering Georgia Institute of
Technology
Date Approved: November 12th, 2014
II
To my beloved wife (Saira), daughter (Areebah), brother (Atif), and parents (Tanvir and
Mah Jabeen) for their unswerving faith and support
III
ACKNOWLEDGEMENTS
First of all, I would like to thank Allah Almighty for blessing me with such a
great opportunity and granting me courage and strength to achieve this milestone in my
life.
My deepest gratitude goes to my Ph.D. advisor Prof. Dr. John Papapolymerou
who, despite my rudimentary knowledge about EM tools and absolutely no experience in
cleanroom fabrication, provided me with an opportunity to work in his microwave circuit
technology (MircTech) research group in my first semester at Georgia Tech. I thank him
for showing unflinching trust in me, giving me time to learn EM tools and fabrication,
and providing me with many opportunities to work on good problems and develop some
great mm-wave components and modules. His support and guidance has helped me
become a good researcher. I have learnt a lot (design, fabrication, assembly and
measurement of mm-wave on-chip and on-package components and modules) during the
last few years.
I would like to extend my sincere thanks to my Ph.D. defense committee
Professor John D. Cressler, Professor Andrew F. Peterson, Professor Madhawan
Swaminathan and Professor John Zhan for serving on my Ph.D. defense committee and
providing me with their worthy guidance and feedback.
During my Ph.D., I was fortunate enough to collaborate with research groups
(SiGe Research group, GEMS, mixed signal design group), supervised by other
professors, which provided me some excellent opportunities to extend the horizon of my
research. I thank my advisor, Dr. John Papapolymerou, research engineer Dr. Cagri
Ulusoy, and other professors Dr. John Cressler, Dr. Hua Wang, Dr. Madhawan
IV
Swaminathan, Dr. Alenka Zajic, and research engineer Dr. Venky Sundaram for
providing me with opportunities to work on such interesting projects. While working on
these projects, I developed great working relationship with the members of SiGe, GEMS
and mixed signal design group. I would like to thank, Rob Schmid, Peter Song, Steve
Horst, Saeed Zeinolabedinzadeh, Farzad Inanlou, Seunghwan Kim, Song Hu, Taiyun Chi,
Jong Seok Park, Kyuhwan Han, Nelson Lourenco, and Srikrishna Sitaraman for their
help and collaborative work.
How can I forget my own MircTech research group members! I owe special
thanks and gratitude to all of them. I had a great time working with every one of them. I
owe a debt of gratitude to graduated members, Dr. David Chung, Dr. Arnaud Amadjikpe,
Dr. Negar Tavassolian, Dr. Yuan Li, Dr. Carlos Donado, Dr. Benjamin Lacroix, Dr.
Swapan Bhattachariya, and last but not the least Dr. Chad Patterson from whom I learnt a
whole lot about fabrication and EM tools. I would like to especially thank Dr. Chad
Patterson for taking out time and train me on cleanroom and laboratory equipment.
I would like to deeply acknowledge my current group members (Dr. Cagri
Ulusoy, Spyridon Pavlidis, Outname Lemtiri Chlieh, Aida Vera, Fan Cai, Christopher
Barisich, Sensen Li, George Alexopolis) and visiting student from France, Gaetan
Dufour, with whom I enjoyed good friendship and excellent working relationship. Their
new ideas and problems helped me reinforce my knowledge and further explore new
interesting topics. They helped me during the time of distress and made my journey
through Ph.D. a lot easier. I would cherish all my life those amazing last moments of IMS
submission deadline almost every year 5:00 am in the morning and all group lunches. I
V
would like to especially thank Dr.Cagri Ulusoy for having great discussions, ideas and
guidance.
I wish to acknowledge my sponsors Higher Education Commission Pakistan,
United States Educational Foundation in Pakistan for granting me MS leading to Ph.D.
Fulbright scholarship. It was indeed a generous award from my homeland. I would also
like to thank other sponsors of my research; Sony corporation, National Science
Foundation, and Intel Corporation. I also want to extend my sincere thanks to Dr.Anjum
Ali and Irfan Iqbal. Their worthy guidance and suggestions were very helpful in
preparing my application for graduate studies and Fulbright Scholarship.
I want to recognize the efforts of Liza Salter and Scott Sladek for taking care of
all administrative needs and cleanroom staff (especially Gary Spinner, Charlie Suh, Vinh
Tran, and Richard Shafer) for keeping cleanroom equipment up and running so we can
meet our deadlines and finish our Ph.D in a timely fashion.
I am grateful to my friends Muqarrab, Ubaid, Hassan, Minhaj, Shoaib, Ahmad
Usman, Naveed, Umar Tariq, Samee Ullah and Waseem whom company made my life
here at Georgia Tech full of life and excitement. I would never forget many east coast
and west coast trips which some of us enjoyed together.
Finally and most importantly, I would like to thank my family (wife Saira,
daughter (Areebah), brother (Atif) and my parents (Tanvirr and Mah Jabeen) for their
endless prayers and unswerving support through thick and thin. I am forever indebted to
my mother and father for their unwavering support, love and affection. On many
occasions, only my parents’ prayers gave me enough strength and confidence to
overcome obstacles. I would also like to thank my in-laws for their support and love. I
VI
highly appreciate my beloved wife’s support who endured happily all my deadlines and
sometimes odd and unusual working hours. She really was a true strength behind me.
Since I got married to her, my life has been more organized and productive. Thanks a lot
Saira for your unswerving support and unending love. During my Ph.D., Allah also
blessed us with a beautiful daughter Areebah, whose presence at home always relieved
me of my day-long tiredness and fatigue.
Without the contribution of each and every body mentioned above, it would have
been a much difficult journey. I would remember and miss all cherished moments which
I enjoyed during my Ph.D. I wish everybody best of luck for their future endeavors.
VII
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS..……………………………………………………………
IV
LIST OF TABLES………………………………………………………………………
XII
LIST OF FIGURES……………………………………………………………………..
XIII
SUMMARY…………………………………………………………………………….
XIX
CHAPTER
1
INTRODUCTION……………………………………………………………....
1
1.1 Overview and Potential of mm-Wave Applications and Market ……...
1
1.2 Organization of the Dissertation ……………………………………....
4
PART - I
Characterization of Liquid Crystal Polymer from 110 GHz to 170 GHz
2
REVIEW OF RF SUBSTRATES AND THIER CHARACTERIZATION METHODS. 7
2.1 RF Substrates for mm-Wave Modules…………………………………...
7
2.2 Characterization of Electrical Parameters of Dielectric Materials ………
10
2.3 Material Characterization Methods………………………………………
12
2.3.1 Capacitance or Parallel Plate Method (DC to 30 MHz)………......
14
2.3.2 Free Space Method………………………………………………..
15
2.3.3 Cavity Resonators..………………………………………………..
15
2.3.4 Transmission Line Techniques..…………………………………..
16
2.3.5 Fourier Transforms Infrared Spectroscopy (1 to 100 THz)…...…..
17
2.3.6 THz Time Domain Spectroscopy (TDS) (0.1 THz to 10 THz)…...
17
2.4 Challenges in the Characterization of LCP in the D-band and
3
Proposed Method………………………………………………………….
17
CHARACTERIZATION OF LCP FROM 110 TO 170 GHZ……………………..
19
3.1 Extraction of the Relative Permittivity……………………………………
20
3.2 Extraction of the Loss Tangent and Investigation of the Radiation Loss…
22
3.2.1 Total Loss Calculation……………………………………………...
24
3.2.2 Conductor Loss Calculation………………………………………..
24
3.3 Fabrication and Measurements…………………………………………….
27
SUMMARY PART I………………………………………...……………………
31
VIII
PART - II
Design and Development of on-chip and Antenna-in-Package Solutions
for mm-wave Applications
4
DEVELOPMENT OF ANTENNA-IN-PACKAGE SOLUTIONS ON ORGANIC
SUBSTRATES………………………………….…………………………………….
33
4.1 Background and Prior Art of AiP Solutions………………………………….
33
4.2 An Ultra-Wide-band W-band End-fire Antenna……………………………..
36
4.2.1 Tapered Slot Antenna (TSA) Design Theory………...………...….....
37
4.2.2 TSA Design on LCP………...………...….....…...………...…............
38
4.2.3 Fabrication and Measurements of TSA..….....…...………...…............
42
4.3 Integration of V-band and W-band Antennas with SPDT Switch on Organic
Substrate………...………...….....…...………...…...............….......................
44
4.3.1 Dipole Antenna Design Theory………...………...….....…...…..........
45
4.3.2 Integration of V- and W- Band Antenna Arrays on Organic Substrate.. 47
5
DEVELOPMENT OF AN ON-CHIP ANTENNA.. ……………………………..…..
50
5.1 Background and Prior Art …………………………………....………...….....
50
5.2 Antenna Design …………………………………....………...…......…..........
54
5.2.1 On-chip Antenna Design using Localized Back-side Etching…..........
57
5.2.2 Antenna Design on LCP…..........…………....………...…......…..........
67
5.3 Fabrication …………………………………....………...…......…..................
68
5.4 Measurement Results and Discussion………....………...…......….................
69
5.4.1 On-chip Antenna Measurements…..........……...…......…....................
71
5.4.2 On-package Antenna Measurements…..........……...…......…..............
76
SUMMARY PART II…………………....………...….....…......…............................
79
PART - III
Design and Development of K-, V-, W, and D-band Front-end
Component sand Modules for Microwave
and Mm-wave Applications
6
BACKGROUND/LITERATURE SURVEY.. ……………………………..…..…....
82
6.1 Advanced Packaging Solutions for the Development of Mm-wave Modules... 82
IX
7
DEVELOPMENT OF K- AND V-BAND MODULES ON LCP…………...…..…....
90
7.1 Low Phase Noise K-Band Oscillator on Organic LCP Substrate………….....
90
7.2 Low Cost 60 GHz RF Front-end Transceiver Integrated on Organic
Substrate……………………………………………………………………..
99
7.2.1 Antenna Design…..........……...…......….............................................
99
7.2.2 Fabrication…..........……...…......…..................................................... 101
7.2.3 Measurements and Results..……...…......….......................................... 104
8
DEVELOPMENT OF W-BAND MODULES ON LCP…………...…..….................. 107
8.1 LNA Design…………......……...…......…........................................................ 108
8.2 Flip-chip Package Design...……...…......…....................................................... 109
8.3 Antenna Design…………...……...…......…..................................................... 119
8.4 Fabrication of Packaged LNA and Receive Module......................................... 121
8.5 Results and Measurements of Packaged LNA……........................................... 123
8.6 Results and Measurements of W-Band Packaged Receive Module...….........
125
8.7 Recommended Guidelines…………………………………………...…........... 129
9
DEVELOPMENT OF D-BAND MODULES ON LCP…………...…..….................. 103
9.1 D-band Indoor Path-loss Mesurements....…..................................................... 130
9.1.1 Measurement Setup…..........……...…......…......................................... 131
9.1.2 Path loss Mesurements........……...…......….......................................... 131
9.2 D-band Characterization of Co-planar Wave-guide and Microstrip
Transmission Lines and SIW on LCP ……………………………………… 135
9.2.1 Design of CB-CPWs….......……...…......…........................................
136
9.2.1.1 Design of Via-less 60 ohms CB-CPWs and 80 ohms Microstrip
Line……………………………..……………………….……… 137
9.2.1.2 Design of CB-CPW to Microstrip Transition Line………….....
138
9.2.1.3 Design of TRL Lines for Microstrip Loss Extraction……...….. 139
9.2.2 Fabrication…………………………….….......……...…......…............ 140
9.2.2.1 Additional Fabrication Considerations……………………... …. 141
9.2.3 Measurements………..……………….….......……...…......…............. 146
9.2.3.1 80 ohms Microstrip Loss Extraction with TRL Calibration….. .. 149
9.2.3.2 Via-Less 60 ohms CB-CPWs Measurements after LRRM
Calibration……………………………………………….…... … 150
9.2.3.3 Comparative Study Between CPWs Fabricated using 2 µm
and 9µm Cu…………………………………………..……......... 152
X
9.2.3.4 CPW to Microstrip Line Transition and Substrate Integrated
Waveguide (SIW)………..…………………………..…….......... 153
9.3 Characterization of a Low-loss and Wide-band (DC to 170 GHz)
Flip-chip Interconnect on an Organic Substrate………………………........... 155
9.3.1 The Design of a Flip-chip Interconnet….......……...…......….............. 156
9.3.2 Fabrication and Flip-chip Bonding……………………………............ 159
9.3.3 Measurements and Results……….……………………………............ 161
SUMMARY PART III…………………....………...….....…......….................... 165
10 CONTRIBUTIONS…………….……….………………………...…..….................... 168
11 FUTURE WORK...…………….……….………………………...…..….................... 170
APPENDIX A Facilities Used…….….………………………...…..…............................
171
LIST OF AUTHOR’S PUBLICATIONS………………………...…..….......................... 173
REFERENCES………………………….………………………...…..….........................
178
VITA………………………….………………………...…..…........................................... 200
XI
LIST OF TABLES
Page
Table 3.1: Dimensions of Ring Resonators and Transmission Lines (mm)…………
28
Table 5.1: On-chip Antenna Design Parameters…………………………………….
59
Table 5.2: On-package Antenna Design Parameters……………………………….
68
Table 5.3: Comparison between State-of-the-art On-chip Antennas…….…………..
78
Table 7.1: Comparison of Oscillators’ Phase Noise and Output Power….…………..
99
Table 7.2: Tx/Rx Total Gain Calculation……………………………...….………….. 106
Table 8.1: Antenna Design and Chip-Model Parameters………………….…………. 110
Table 8.2: RLC Values vs bump_h for Interconnect Eq.Model………..….…………. 119
Table 9.1: Measurement Parameters…………………………………....….…………. 132
Table 9.2: Design Parameters of CB-CPW Lines…………………….….…………… 138
Table 9.3: Design Parameters of Microstrip Lines……………………….…………… 139
Table 9.4: TRL Line Lengths…………………………………………….…………… 140
Table 9.5: LCP Package-and Chip- Model Parameters………………….…………… 158
Table 9.6: Comparison between State-of-the-art Flip-chip and Wirebond Interconnect 164
Table 9.7: Comparison of Flip-chip with other Interconnects……………………….
XII
164
LIST OF FIGURES
Page
Figure 1.1: Wireless technologies and applications in operation …………………………..
2
Figure 1.2: Some future potential applications at mm-wave and terahertz frequencies ……
2
Figure 2.1: (a) Free space measurement setup [16] (b) open resonator method
measurement setup, (c) cavity resonator [17], (d) ring resonator, (e)
Terahertz Time domain spectroscopy (TDS) method, (f) filled
waveguide method ……………………………………………………………
13
Figure 3.1: (a) open-gap-MRR-gap-open structure, (b) open-gap-open, (c) simple microstrip
(d) CBCPW cross-section …………………………………………………….
Figure 3.2: Radiation loss simulation results for microstirp, open-gap-open and open-gap-MRR-gap-open structures ……………………………………………….
26
27
Figure 3.3: (a) TRL lines standards, (b) ring resonator, (c) coupling gap between
the feed line and MRR ………………………………………………………..
29
Figure 3.4: Measured S21 of Ring Resonator ……………………………………………..
29
Figure 3.5: Measured/extracted relative permittivity using ring resonator dielectric
characterization method ………………………………………………………
30
Figure 3.6: Measured/extracted loss tangent using ring resonator dielectric
characterization method ……………………………………………………….
30
Figure 4.1: HFSS model with dimensions ………………………………………………….
39
Figure 4.2: Conventional microstrip-to-slot transition...……………………………………
39
Figure 4.3: Simulated S11 showing difficulty to realize slot width of (10um) for
50 ohms ………………………………………………………………………..
40
Figure 4.4: Current flow on the transition [68] ....................……………………………….
41
Figure 4.5: Equivalent circuit model of the microstrip-to-slot transition [68]……………..
41
Figure 4.6: Fabricated back to back transition …………………………………………….
42
Figure 4.7: Measured S-Parameters of the new transition …………………………………
42
Figure 4.8: Fabricated antenna and measurement setup: (a) measurement setup; (b) backside
of substrate (ground having TSA profile; (c) µstrip-to-slot transition with slow
wave structure (d) top side of substrate with CPW line…………………………
43
Figure 4.9: (a) Measured and simulated gain and S11 and (b) H plane co and cross polarization
measured and simulated results ..………………………………………………..
XIII
44
Figure 4.10: (a) HFSS model of integration of switch with antenna, (b)snapshot of fabricated
module, (c) wide-band wire-bond transition with compensation stub, (d)
measurements underway, and (e) cross-sectional view of integrated module
…………………………………………………………………………………… 48
Figure 4.11: (a) Measured and simulated gain and S-parameters and (b) H plane Co and
Cross polarization measured and simulated results …………………………….
49
Figure 5.1: Schematic view of a Yagi-Uda antenna including measurement pads ………….
55
Figure 5.2: On-chip Yagi-Uda antenna HFSS EM-model …………………………………..
58
Figure 5.3: Cross-sectional view of on-chip end-fire Yagi-Uda antenna with LBE ………..
58
Figure 5.4: Simulated insertion loss of back-to-back balun structure ………………...…….
60
Figure 5.5: Simulated effect of the silicon wall in front of the antenna (Si_f) on the
E-plane radiation pattern ……………………………………………………….
62
Figure 5.6: Simulated effect of the silicon wall in front of the antenna (Si_f) on the
H-plane radiation pattern……………………………………………………….
62
Figure 5.7: Effect of thin layer of Si (Si_r), in the cavity under the antenna on
return loss (S11…………………………………………………………………
63
Figure 5.8: Simulated effect of the silicon side-wall thickness (Si_s) on the H- and E-plane
radiation patterns at 143 GHz ………………………………………………….
64
Figure 5.9: Field distribution of on-chip antenna (a) side view, (b) 3D view ……………..
65
Figure 5.10: (a)Variation in the gain by varying the thickness of Si wall in front of the
antenna (Si_f), thickness of side-wall of Si (Si_s), and (b) cavity size (cav_l)
(refer to Fig. 5.1 and 5.2 for parameter identification), (c) variation in the
gain vs frequency by changing the length of the director (dir_l), and
(d) variation in the gain vs frequency by changing the length of the
driver(drv_l) …………………………………………………………………..
66
Figure 5.11: On-package Yagi-Uda antenna HFSS EM-model ……………………………
67
Figure 5.12: (a) On-chip Yagi-Uda antenna, (b) On-chip Yagi-Uda antenna after the
guard-ring is removed ………………………………………………………..
68
Figure 5.13: Yagi-uda fabricated on LCP substrate……………………………………….
69
Figure 5.14: (a) Probed antenna, (b) Setup for E-plane radiation pattern measurements…
70
Figure 5.15: Block Diagram of the radiation pattern measurement setup ………………...
70
Figure 5.16: Measured and simulated return loss and gain of the on-chip antenna with LBE .. 72
Figure 5.17: Measured and simulated E- and H-plane radiation patterns at 143 GHz of on-chip
antenna with LBE (a) E-plane, (b) H-plane …………………………………….
XIV
73
Figure 5.18: Block Diagram of the chip-to-chip link measurement setup…………………….
74
Figure 5.19: Link measurements for two on-chip antennas placed in front of each other…….
74
Figure 5.20: Simulated and Measured on-chip antenna efficiency …………………………… 76
Figure 5.21: Measured and simulated return loss and gain of antenna-in-package on an organic
substrate LCP ……………………………………………………………………. 77
Figure 5.22: Measured and simulated E- and H-plane radiation patterns of on-package (LCP)
antenna on an organic substrate ………………………………………………….. 79
Figure 6.1:
Advanced packaging techniques (a) SoC [94] (b) SiP [95], (c) SoP [97]……….. 83
Figure 6.2: (a) Micro-Coax based Packaging, (b) package using hot vias, and (c) package
using waveguide apertures ……………………………………………………...
85
Figure 6.3: Packaging interconnect technologies (a) embedded wafer level ball grid
array[107], (b) embedded wafer level package [109], (c) flip-chip [111],
and (d) wire-bond [110]………………………………………………………...
86
Figure 7.1: (a)Layout of /2 microstrip resonator coupled with microstrip line and
(b) simulated reflection coefficient of the resonator …………………………..
91
Figure 7.2: Block diagram of 1-port oscillator design …………………………………….
93
Figure 7.3: Complete schematic of the circuit ……………………………………………..
93
Figure 7.4: Micrograph of the fabricated circuit (dimensions in mm)…………………….
94
Figure 7.5: Simulation results for different lengths of short circuit stub and different
diameters of vias ……………………………………………………………..
95
Figure 7.6: Simulated reflection coefficient of the resonator …………………………….
96
Figure 7.7: Measured output power of oscillator …………………………………………
97
Figure 7.8: Measured phase noise ………………………………………………………..
98
Figure 7.9: Simulated phase noise ………………………………………………………..
98
Figure 7.10: 60 GHz 4×1 Yagi-Uda array layout. ………………………………………....
100
Figure 7.11: Block diagram of the Tx/Rx module………………………………………….
102
Figure 7.12: (a) Layout of the proposed package solution for the 60 GHz Tx/Rx module, (b)
Fabricated and assembled Tx/Rx module …………………..……………….
102
Figure 7.13: Fabricated capacitive stub to nullify the effect of ribbon inductance………..
103
Figure 7.14: Simulated return loss results with and without the capacitive stub …………
103
Figure 7.15: Measured S11 of active antenna array ……………………………………….
106
Figure 7.16: (a) Receiver side H-plane Co-polarization at 59 and 61 GHz,transmitter side
H-plane co-polarization at 60 GHz, Hcr polarization at 59 GHz and simulated
H-plane 60 GHz passive antenna, (b) measured Tx/Rx gain vs frequency plot
XV
from 55 to 65 GHz ……………………………………………………………
106
Figure 8.1: Circuit schematic of the designed LNA……………………………………….
108
Figure 8.2: (a) Flip-chip transition model (b) cross section of flip-chip when only substrate
is extended (c) cross section of flip chip when pad size is increased …………
109
Figure 8.3: (a) Cross sectional view of the package (b) Top View of the module for
packaged LNA …………………………………………………………………
110
Figure 8.4: Simulated S-parameters for flip-chip transition with 50 Ω GSG pads on the input
and output of the chip model. The insertion loss includes the loss of the CPW
line on the package ……………………………………………………………
112
Figure 8.5: Sweeping the parameter sub_ext (a) S11 (b) S21 while bump_rad= 25 µm and
bump_h =40 µm and pad_ext= 30 µm are kept constant ……………………
113
Figure 8.6: Sweeping the parameter pad_ext (a) S11 (b) S21 while bump_rad= 25 µm and
bump_h =40 µm and sub_ext =30 µm are kept constant ……………………
114
Figure 8.7: Sweeping the parameter bump_rad (a) S11 (b) S21 while pad_ext= 30 µm,
bump_h =40 µm, and sub_ext =30 µm are kept constant ……………………
115
Figure 8.8: Sweeping the parameter bump_h (a) S11 (b) S21 while bump_rad= 25 µm,
sub_ext =30 µm, and pad_ext= 30 µm are kept constant …………………….
116
Figure 8.9: Smith chart showing inductive and capacitive behavior by varying the parameter
bump_h while bump_rad= 25 µm, sub_ext =30 µm, and pad_ext= 30 µm ….. 116
Figure 8.10: Simulated S-parameters results for optimization of flip-chip parameters: bump
height, bump_rad and pad size. Insertion loss vs dimensions of parameters at 94
GHz and 110 GHz are shown …………………………………………………. 117
Figure 8.11: (a) Simplified HFSS flip-chip model (b) Extracted RLC Equivalent Model …
118
Figure 8.12: S21 and S11 correlation between HFSS and RLC flip-chip equivalent model …. 118
Figure 8.13: S21 and S11 correlation between HFSS and RLC flip-chip equivalent model … 119
Figure 8.14: Yagi-Uda antenna design parameters …………………………………………
121
Figure 8.15: (a) Fabricated Sample and (b) measurement in progress after assembly ……… 122
Figure 8.16: 8.16. (a) Yagi-Uda Antenna (b) SiGe LNA (c) Gold bumped SiGe LNA (d)
Fabricated and assembled Rx module ………………………………………… 123
Figure 8.17: (a) On-chip and Packaged LNA gain and return loss measurement (on- chip
and packaged S12 are omitted and (b) on-chip and packaged measured noisefigure of LNA ……………………………………………………………….
124
Figure 8.18: Measured and simulated reflection coefficient and gain of the passive antenna
and the active receive module ………………………………………………… 125
XVI
Figure 8.19: Block diagram of the measurement setup for radiation pattern measurement ..
126
Figure 8.20: Simulated and measured E- and H-plane radiation patterns of passive antenna .. 127
Figure 8.21: Simulated and Measured H- plane radiation patterns of passive of active
Module………………………………………………………………………….. 128
Figure 8.22: Simulated and measured E-plane radiation patterns of active module ………… 128
Figure 9.1:
Measurement setup for short range channel characterization in (a) LOS
environment and (b) partially obstructed LoS environment ………………….. 132
Figure 9.2:
Measured and theoretical path loss in LoS environment for several different
distances between the Tx and Rx …………………………………………….
Figure 9.3:
133
Measured path loss when LoS path is obstructed by ceramic mug, paper cup,
and a pcb board ……………………………………………………………..
134
Figure 9.4:
Design of via-less CB-CPW …………………………………………………
138
Figure 9.5:
Designed CB-CPW to microstrip transition ………………………………….
138
Figure 9.6:
Fabricated samples: (a) 1 mm long microstrip line, with CPW to microstrip
transition and showing the TRL calibration reference planes, (b) 0.5 mm long
60 ohms CB-CPW line (c) 2 mm long 60 ohms CB-CPW ………………….
141
Figure 9.7:
Fabricated structures using 2 and 9 µm of Cu ………………………………… 142
Figure 9.8:
(a) Step: 1 Cutting sample from the panel …………………………………….
Figure 9.8:
(b) Step: 2 Blue tape attachment ……………………………………………… 143
Figure 9.8:
(c) Step: 3 Etching of Cu for alignment vias …………………………………
143
Figure 9.8:
(d) Step: 4 Alignment, CPW and SIW via drilling ……………………………
144
Figure 9.8:
(e) Step: 5 Sputtering Cu on bottom side to metallize vias …………………… 144
Figure 9.8:
(f) Step: 6 Patterning the top side …………………………………………….
145
Figure 9.8:
(g) Step: 7 Patterning the bottom side ……………………………………….
145
Figure 9.9:
(a) Measurement Setup, (b) sample ready to be probed, (c) measurements
underway ……………………………………………………………………..
142
146
Figure 9.10: 9.10 Measurement of the thru standard after LRRM calibration (a) including
reflection coefficients, (b) Without S11 and S22 to adjust the scale of S21……… 147
Figure 9.11: TRL calibration lines ………………………………………………….………. 148
Figure 9.12: Measurement of the thru standard after TRL calibration ……………………… 148
Figure 9.13: (a) Measured s-parameters of the 0.5mm and 1mm long µstrip line after TRL
calibration (b) measured S21 of 0.5mm, 1 mm long microstrip lines …
150
Figure 9.14: 80 ohms microstrip attenuation vs. frequency (dB/mm) and (dB/𝝀g)…………
150
Figure 9.15: Via-less 60 ohms, CB-CPWs measurements after LRRM calibration ……….
151
XVII
Figure 9.16: Real and imaginary effective dielectric constant vs frequency ……………….
152
Figure 9.17: Comparison between CPW lines fabricated using 2 and 9 µm of Cu ………..
153
Figure 9.18: Fabricated CPW to microstrip transitions and SIWs …………………………
154
Figure 9.19: S-parameters of CPW to microstrip transition ……………………………….
154
Figure 9.20: S-parameters of CPW to microstrip to SIW transition ……………………….
155
Figure 9.21: (a) 3-D flip-chip structure in HFSS, (b) top view, (c) RLC equivalent model … 157
Figure 9.22: EM-simulated results of the flip-chip transition (LCP chip flipped on LCP
package) ……………………………………………………………………….. 159
Figure 9.23: Discontinuity caused due to high force during flip-chip bonding ……………… 160
Figure 9.24: Fabricated (a) LCP chip, (b) LCP with gold bumps, (c) LCP package with
high impedance sections, and (d) LCP chip flipped on LCP package ………… 161
Figure 9.25: Measured and simulated return loss and insertion loss for circuits shown in
Fig. 3…………………………………………………………………………… 162
Figure 9.26: Measured insertion loss of flip-chip transitions with 45 and 85% overlap of
the bump on the landing pad of the package, and insertion loss of the
back-to-back transition in dB/mm ……………………………………………… 163
XVIII
SUMMARY
This Ph.D. dissertation demonstrates the design and development of microwave
and mm-wave on-chip and on-package antennas and organically packaged components
and modules ranging from 20 GHz to 170 GHz.
Because of the tremendous amount of media streaming, video calling and high
definition TV and gaming, the biggest challenge for the wireless industry is the
increasing demand of high data rates. Utilization of mm-wave frequencies is an attractive
option to meet this high demand. In addition to higher data rate requirements for personal
area networks, precision requirements of passive remote sensing and imaging radars have
pushed the need to design radio frequency (RF) front ends in the W-band (75 GHz -110
GHz), D-band (110 GHz -170 GHz) and even at higher frequencies. Recent advances in
low cost semiconductor technologies allow realization of low-cost on-chip RF front-ends
in the high millimeter wave (mm-wave) frequencies, making it possible to realize
compact systems for these application areas. Although integrated circuits (ICs) are one of
the main building blocks of a mm-wave system, in order to realize a fully functional
wireless system, cost-effective antenna design and packaging are two important preconditions. Researchers have investigated and reported low-cost electronics packaging up
to 100 GHz to a great extent on ceramic substrates, but mm-wave packaging above 100
GHz is relatively less explored, particularly on organic substrates.
For packaging of next generation wireless systems, at present, ceramic based
materials are used for advanced package design. Liquid crystal polymer (LCP) is an
organic substrate material that has been demonstrated to be a competitive substrate and
packaging material due to its excellent electrical properties, flexibility and multi-layer
XIX
lamination capability. It has a low dielectric constant (~3.0), a low dielectric loss (0.003),
and temperature stability up to 305 ˚C across a wide frequency range (1-110 GHz). This
material can be processed in large panels with standard printed circuit board (PCB)
manufacturing process. For these reasons, for this work, LCP has been chosen as a
substrate and packaging material to develop organically packaged components and
modules for microwave and mm-wave applications.
The objective of this Ph.D. research was to design and develop mm-wave
components and modules on LCP, to investigate the viability of this organic substrate and
development of fabrication techniques in the K- (18-26.5 GHz), V- (50 to 70 GHz), W(75 to 110 GHz), and D- (110 to 170 GHz) bands. Additionally, a demonstration of a
micro-machined on-chip antenna has also been presented. This dissertation is divided in
three parts: (1) characterization of liquid crystal polymer from 110 to 170 GHz. (2)
development of highly radiation efficient on-chip and AiP antennas, and (3) development
of mm-wave modules with the integration of antennas.
(1)
Since LCP has not been characterized in the D-band, the first part of this
dissertation shows the characterization of LCP using ring resonators from 110 to
170 GHz. The challenge in the characterization at such a high frequency was to
address the issue of radiation loss which may affect the accuracy of extracted
electrical parameters. To analyze the radiation loss resulting from the ring
resonators or feeding structures, a new study has been carried out to address this
issue and extracted electrical parameters from 110 to 170 GHz have been
presented.
(2)
The second part of this dissertation demonstrates the development of on-chip
XX
and on-package antennas. Development of highly radiation efficient antennas and
their integration is an active research area. For potential applications in the E- and
W- band, we have demonstrated the design and development of a wide-band (73
GHz to 91 GHz) single element end-fire tapered slot antenna on LCP with a gain
of 8 dBi. To realize such a wide-band antenna, a new wide-band transition was
optimized for its optimum performance in the W-band. The integration of two
mm-wave antennas, operating at different frequencies, pose challenges (in terms
of coupling and isolation). For the first time we have integrated V-band and Wband antennas using a Hittite chip with optimized spacing showing the excellent
performance in terms of radiation patterns and isolation between two antennas.
Highly efficient on-chip antenna is an ultimate solution towards the
miniaturization of the systems. The development of such antennas is an up-hill
task because of the low-resistivity and high dielectric constant of silicon. In this
work we also demonstrate the development of an end-fire antenna with simulated
and measured radiation efficiency of 82 % and 76%, respectively. This
demonstration paves the way for the development of future chip-to-chip
communication and other potential application at mm-wave and sub-mm wave
frequencies.
(3)
The third part of this dissertation is devoted to the successful demonstrations of
organically developed modules, where antennas are integrated with different
components and wide-band mm-wave interconnects are optimized. We have
developed a 20 GHz low low-cost and low-phase noise oscillator and a 60 GHz
transceiver packaged on LCP using the wire-bond interconnect technology.
XXI
Because of its parasitics, wire-bond interconnect suffers from the issues of high
insertion loss and narrow bandwidth. Therefore, to develop low-loss systems, flipchip interconnects are preferred. Using the flip-chip interconnect, we have
developed mm-wave modules on LCP platforms in the W- and D-band, where the
benefits for this material can be exploited for wireless systems. Since LCP is a
soft and flexible substrate, a process needs to be developed for flip-chip
interconnect otherwise the thermo-compression technique or flipping the chip
using the sliver epoxy technique
may degrade the performance of the
interconnect by creating cracks in the metal and dents in the substrate. For the
first time, we have demonstrated a wide-band flip-chip interconnect from DC to
170 GHz with an insertion loss of as low as 0.2 dB. Moreover, high frequency
operation requires the use of thin substrates to avoid a surface wave issue and
meet the fine-pitch of the high frequency probes. This requires the realization of
fine features as small as 15 to 20 µm. On LCP, whose surface roughness is on the
order of 1-2 µm, a special process needs to be developed and extra care during the
fabrication is required to realize fine features. All these issues are addressed in the
dissertation. We have also investigated the possibility for D-band short-distance
indoor communications. Indoor line-of-sight and obstructed line-of-sight path loss
measurements have been taken and presented.
XXII
CHAPTER I
INTRODUCTION
1.1 Overview and Potential of mm-Wave Applications and Market
In today’s modern world, there has been an increased demand for high
performance wireless systems both in commercial and defense sectors. Some of the
applications include AM and FM radio transmission (153 KHz to 108 MHz), radio
frequency identification (RFID) (120 to 150 KHz 13.56 MHz, 433, 3.1 to 10 GHz),
global positioning system (GPS, 1-2 GHz), cellular communication (800 MHz, 2.4 GHz),
prospective 5G cellular communication (28 and 38 GHz) [1], WiFi (2.4 GHz, 5 GHz, 60
GHz in future) [2], satellite communication (4- 6 GHz) , military radar systems (8-12
GHz), digital satellite television (11-13 GHz), WPAN (60 GHz), automobile collision
avoidance radars (26 GHz, 77 GHz), microwave back haul communication (6, 11, 18, 23
38 GHz, 71 to 77 GHz, 81 to 86 GHz), mm-wave body scanning and imaging (94 GHz),
chip-to-chip communication (80 GHz and above), high resolution medical imaging (122
and 140 GHz and above) [3], radio astronomy(ALMA project) [4-5], short-distance high
speed communication ( 300 GHz and above) and terahertz medical applications. Some of
the above mentioned wireless systems have matured over the years and have been
commercialized, but some systems, especially mm-wave systems, are still in the research
domain. A snapshot of some of the wireless technologies in operation is shown in Fig.
1.1. Some of these products have been developed but the enhancement of the
performance and reducing the cost always demands for more research. Some of the
potential future applications are illustrated in Fig. 1.2.
1
Some of the other active research areas in the wireless domain are wireless power
transfer, wireless gas and electricity metering, energy harvesting, personal area networks
at 60 GHz and above, near field communication, and 5G cellular communication using
disruptive technologies like pico cell and cellular communication at mm-wave
frequencies using large scale MIMO.
Figure 1.1 Wireless technologies and applications in operation
Figure 1.2 Some future potential applications at mm-wave and terahertz frequencies
2
One example of a high speed communications link at 60 GHz or higher include
downloading a Blu-ray movie from a kiosk in a few seconds with mm-wave enabled
devices. Another application is streaming uncompressed high-definition audio/visual
content between a portable device and a graphics display. Most of these links are line-ofsight (LoS) links and indoor shadowing could block the direct communication. Efforts
are being expended to develop switched beam and MIMO techniques, where mm-wave
communication will be enabled using beam forming algorithms. The Internet-of-things is
another huge area, which will interconnect everything around us and according to Cisco’s
report, by year 2020, there will be 50 billion interconnected devices which will require
significant amount of upgrade in our existing wireless and wired infrastructure to enable
real-time flow of information [6-7]. This will create a trillion dollars of new markets and
industry. This internet of things, 5-G cellular communication personal area networks, and
high definition video streaming and imaging will require different specifications based of
the application. Some of these are data rates of 10 Gb/s, 10 years of operations for
machine-to-machine (M2M) sensing devices (10bps, 1Ah), as well as 1 ms real-time
latency to enable the flow of real time information[8].
To realize the aforementioned potential applications, a multitude of technologies
need to be developed. An important area that poses challenge to meet the demand of
higher data rates, low latency, and precision imaging is the development of radiation
efficient mm-wave antennas and the development and integration of antennas with other
low-cost mm-wave front-end components and modules. In this Ph.D. dissertation,
packaging and integration challenges towards the development of low-cost and highly
efficient mm-wave components and modules have been addressed and low-cost solutions
3
have been developed for potential mm-wave applications ranging from 20 GHz to 170
GHz.
1.2 Organization of the Dissertation
This dissertation is divided in three parts: (1) characterization of liquid crystal
polymer from 110 to 170 GHz, (2) development of highly radiation efficient on-chip and
AiP antennas, and (3) development of mm-wave modules with the integration of
antennas.
Chapter 2 reviews mm-wave substrates for advanced mm-wave packaging and
available techniques to characterize mm-wave substrates. It also identifies the challenges
and limitations of mm-wave substrate characterization using different techniques. In
Chapter 3 of this dissertation, the characterization of liquid crystal polymer from 110 to
170 GHz will be presented and a new study/technique to address the issue of radiation
loss, which may cause inaccuracies in the extraction of electrical parameters, is
presented. Chapter 4, in the beginning, reviews the existing antenna-in-package (AiP)
solutions and then describes the development of AiP solutions on organic substrate. Two
unique designs are presented. The first design is the demonstration of an ultra-wide-band
(73 to 91 GHz) tapered slot antenna with a new optimized wide-band mm-wave
microstrip-to-slot-line transition. The focus of the Chapter 5 is the development of highly
radiation-efficient end-fire on-chip antennas for future chip-to-chip and other
applications. This chapter starts with the challenges associated with on-chip antennas and
existing on-chip antenna solutions, and then explains our proposed highly radiationefficient (with measured state-of-the-art radiation efficiency of 76 %) on-chip antenna
solution. Chapter 6 reviews the advanced available packaging technologies. In Chapter 7
4
of this dissertation, the development of a K-Band low phase noise oscillator and a V-band
60 GHz transceiver using wire-bond interconnect technology are described. In Chapter 8,
we present the design and development of organically packaged flip-chip based W-band
receive module. A flip-chip transition for W-band is optimized and state-of-the-art
performance of a W-band module is presented. Chapter 9 pushes the frequency limits
towards 170 GHz and describes the development of D-band transmission lines, flip-chip
based modules and measurements of indoor obstructed and non-obstructed line-of-sight
measurements. It also presents the guidelines (for assembly and fabrication) to develop
mm-wave components on LCP.
5
PART I
Characterization of Liquid Crystal Polymer
from 110 GHz to 170 GHz
6
CHAPTER II
Background/Review of RF Substrates and their Characterization
Methods
Since LCP has not been characterized in the D-band, and one of the objectives of
this dissertation is to develop components and modules in the D-band. Therefore, it’s
very important to characterize LCP and extract its electrical parameters (dielectric
constant and loss tangent) so that the extracted electrical parameters are used in the
development of D-band components and modules. This chapter reviews the RF substrates
and their characterization method. In chapter 3, the characterization of LCP will be
presented.
2.1
RF Substrates for Mm-Wave Modules
In addition to the excellent electrical properties, packaging substrates should be
cost effective and compatible with different package integration technologies. To enable
the packaging of next generation wireless systems, many new materials are explored for
advanced package design. The desired characteristics for mm-wave packaging materials
are low dielectric loss (loss tangent), low and stable dielectric constant, hermeticity, low
coefficient of thermal expansion and multi-layer capability. Mainly, two kinds of
substrates meet the desired properties: ceramic substrates and organic substrates. Until
recently, packaging materials used for mm-wave packaging are advanced microwave
composites and ceramics. Some of these include alumina, high temperature co-fired
ceramics (HTCC) and low temperature co-fired ceramics (LTCC).
Prior to 1990s, multi-layer structures were realized using HTCC materials, which
7
are derivatives of alumina (alumina oxide). Multi-layer lamination was performed by
stacking layers of alumina plates and firing at approximately 1500 ºC to bond and harden
the plates. Unfortunately, this high temperature requirement prohibited the use of highly
conductive metals like silver, copper or gold (which all melt between 962 – 1085 ºC) [9].
Instead of high conductance metals, lower conductance metals like tungsten and
molybdenum were used. Since high conductance metals are necessary for high frequency
devices, HTCC were limited in their frequency range [10].
In the late 1990s, the customer driven wireless market pushed the developers of
RF hardware towards higher RF frequencies and greater circuit integration. HTCCs were
limited to lower frequencies because of their higher co-firing temperature and their
expensive manufacturability and assembly. As a solution to these problems, a ceramicorganic hybrid, known as low temperature co-fired ceramic (LTCC) was created. LTCCs
could be fired at 850-900 ºC, which permitted the use of high conductance metals. This in
turn extended the possible frequency range to much higher frequencies [10]. LTCC is the
current preferred packaging material, but there is a trade-off that after firing, the ceramic
shrinks in all three directions by 15-20%. This introduces an additional level of
complexity [11]. Moreover, LTCC has a higher dielectric constant (𝜺r = 5.9-9.1) that is
detrimental for antenna radiation efficiency [12]. Another limitation of ceramic based
substrate is that these are processed in a smaller tile size (5 inch x 5 inch or 8 inch x 8
inch in a very few foundries) [13], which makes the process expensive. Therefore, efforts
were made to find and develop a new low-cost and low-loss mm-wave substrate material
that can be processed in large panels and also have a low laminate temperature for multilayer packaging solutions.
8
In the past two decades, alternative organic substrate materials have been
developed. Polytetrafluroethylene (PTFE or Teflon), FR-4 and LCP are three examples.
PTFE and FR-4 are both used as printed circuit board (PCB) materials. PTFE offers
excellent RF performance but the cost is higher than other alternatives. FR-4, whose
name is an abbreviation of “flame resistant 4” is a good substrate material only at
frequencies up to 10 GHz [14]. Another limitation of FR-4, HTCC, and LTCC materials
is that multi-layer structures are usually monolithic (made of the same material). In the
case of FR-4, layers are bonded together using a laminating material such as Vialux (by
Dupont). And because of the poor adhesion property of PTFE, packaging with PTFE can
be difficult. But LCP has the advantage that it can bond to itself or to almost any other
material. Because of this and other excellent properties of LCP, which are listed below, in
early 2000, researchers started investigating LCP as a potential high frequency substrate
[15]:

Excellent electrical properties i.e., a low dielectric constant (~3.0), a low
dielectric loss (0.003), and temperature stability up to 305 ˚C across a wide
frequency range (1-110 GHz).

Low lamination temperature, 285 ºC

Low coefficient of thermal expansion compatible with Ag, Cu, Au

3-D multi-layer lamination capability

Flexibility for application in conformal flex circuits

Near hermetic

Flame retardant

Compatible with sequential buildup process in a printed circuit board foundry
9
LCP combines most of the strengths and almost none of the weaknesses of other
materials i.e.; it is low cost, easily packaged and has excellent RF performance. For
these reasons, LCP is chosen as a substrate and packaging material for this research.
LCP has been characterized up to 110 GHz. Since, we plan to develop mm-wave
modules up to 170 GHz, therefore it is important to characterize it up to 170 GHz to
extract its electrical parameters (dielectric constant and lost tangent or dissipation
factor).
2.2
Characterization of Electrical Parameters of Dielectric Materials:
As discussed earlier, the two electromagnetic properties, which define microwave
materials, are permittivity ɛ and permeability µ. ɛ indicates how the medium reacts
when an electric filed is applied, whereas µ indicates how the material reacts if a
magnetic field is applied. To take into account the losses of the material, permittivity and
permeability are both expressed in complex values:
ɛ = ɛ´ - j ɛ´´
µ = µ´ -j µ´´
= ɛo .ɛr (1 – j tan δɛ)
= µo . µr (1 – j tan δµ)
(1.1),
(1.2)
A material is classified as “dielectric” if it has the ability to store energy when an external
electric field is applied. By applying a DC voltage source across a parallel plate capacitor,
we can store an electric charge. Capacitance is defined as the charge “q” per applied
voltage “V” that is Co = q/V. Therefore, Co is also defined as
Co= ɛo (A/d),
(1.3)
10
where A is the area, d is the distance between the two plates, and ɛo = 8.85x10-12 (F/m)
is a universal constant. If a material is inserted between two plates, the capacitance is
increased by a factor ɛr =C/Co , which leads to
C= ɛrɛo (A/d),
(1.4)
In the above expression ɛ is the added storage capability and called the dielectric constant
or relative permittivity. For complex representation
ɛr = ɛr´ - j ɛr´´
(1.5)
The real part is called the dielectric constant and represents the amount of energy stored
and the imaginary part represents the loss factor. The imaginary part is always greater
than zero and is usually much smaller than loss tangent. Loss is also denoted by the loss
tangent tan δ which is defined as the ratio of the imaginary part of the dielectric constant
to the real part. The loss tangent is called tan delta or the dissipation factor.
Dielectric material, that is, insulators, possess a number of important electrical
parameters which make them useful in the electronics industry. Ferroelectric materials
such as barium titanate exhibit spontaneous polarization without the presence of an
external electric field. Their dielectric constants are orders of magnitude larger than those
of normal dielectrics. Thus, they are quite suitable for the manufacturing of small-sized,
highly efficient capacitors. They can also be utilized for memory devices in computers.
Other materials such as ceramics and organics are used as microwave substrates
and accurate measurements of these properties (dielectric constant and loss tangent) can
provide valuable information to properly incorporate the material into its intended
11
application. All materials of interest to the millimeter-wave package are assumed to be
isotropic and nonmagnetic (µr = µo ).
2.3
Material Characterization Methods:
In the following, a brief overview of material characterization methods is given.
Over the years there has been an abundance of methods developed for measuring
permeability and permittivity. These techniques include:
1- Capacitive or parallel plate Method (DC to 30 MHz)
2- Free space method
3- Cavity resonators
4- Transmission-line techniques
a. Open-ended coaxial probe techniques
b. Transmission and Reflection Method using Coaxial T.L and waveguide
c. CPWs and microstrip lines
d. Ring Resonators and T resonators
5- Fourier transform infrared spectroscopy ( 1 to 100 THz)
6- THz time domain spectroscopy (TDS)
Fig. 2.1 illustrates some of the characterization methods enumerated above.
To select a characterization method, one should consider:
1- The exploited frequency range
12
2- The physical properties of the material of concern: is it magnetic or not, low loss
or lossy, isotropic or anisotripic, homogeneous or heterogeneous, dispersive or
not and
3- The shape and nature of the available samples, i.e plate or thin films, liquid or
solid, elastomeric or granular.
Fig. 2.1 (a) Free space measurement setup [16] (b) open resonator method measurement
setup, (c) cavity resonator [17], (d) ring resonator, (e) Terahertz Time domain spectroscopy
(TDS) method, (f) filled waveguide method.
At microwave frequencies, generally higher than 1 GHz, transmission line, resonant
cavity, ring resonator and free-space techniques are commonly used. Each method has its
range of applicability and its limitations. For example, techniques based on cavities are
accurate, but not broad band. The resonant techniques have the ability to measure high
13
quality factor low loss materials but in a narrow frequency band. Resonant methods are
used to extract the permittivity of low loss materials. A material is normally classified as
a low-loss material if tan δ is less than 0.005. Medium loss refers to materials with 0.005
≤ tan δ ≤ 0.1. In general low-loss materials experience very little change in permittivity;
therefore, resonant techniques are well suited for low-loss materials. The broad band
techniques are well suited for high loss low Q materials. Nondestructive techniques,
although not most accurate, allow the maintenance of material integrity. Transmission
line techniques are the simplest of the relatively accurate ways of measuring the electrical
parameters of the materials. Transmission line measurements are made in waveguide,
coaxial line and planar transmission lines (CPWs or microstrip lines). The three major
problems encountered in transmission line measurements are air-gaps, half-wavelength
resonances, and over-moding.
In the following, we will briefly touch upon some characterization techniques
which are used to extract electrical parameters of the substrates.
2.3.1 Capacitance or Parallel Plate Method (DC to 30 MHz) [18]
The parallel plate method is used for frequencies below 30 MHz. LCR meter,
impedance bridges or impedance analyzer measurements are used to measure the parallel
plate capacitance of an electrode dielectric. [19-20]. The permittivity is then obtained
from the capacitance measurement and the material dimensions. Instead of a parallel
plate capacitor, inter-digital capacitors can also been used in certain circumstances, e.g
biosensors to determine remote complex permittivity [21]. The complex capacitance and
the permittivity can be calculated using the non-destructive method from 10 Hz up to 100
MHz. The capacitive method works well if the wavelength is much longer than the
14
conductor separation. In the lower megahertz range, the classical approach treats the
sample as a lossy capacitance measured in a bridge circuit or resonated with an inductor.
Above 1 MHz, the effectiveness of screening electrodes diminishes rapidly with
frequency. Therefore, the established two terminal resonance substitution method,
proposed by Hartshorn and Ward [22], is used. This method has poor uncertainties but is
used because of its ability to measure low losses.
2.3.2 Free Space Method
In this method, as shown in Fig. 2.1 (a), a sample is placed in between the two
horn antennas and measured S-parameters are used to extract electrical parameters. There
are some experimental difficulties such as theoretically the sample should of infinite size
and the propagating wave should be a planar wave. In reality, we can only go closer to
these ideal cases. A dielectric lens is used to focus the beam on a sample area of at least a
wavelength squared. This method is useful at mm-wave frequencies. But at very high
frequencies, the antenna size becomes very small and traditional microwave sources do
not work.
2.3.3 Cavity Resonators
Resonant cavities, illustrated in Fig. 2.1 (c), have very high Q and resonant modes
can be determined as functions of dimensions and relative permittivity. In the split cavity
resonator demonstrated by Kent [23] and further developed by Janezic and Baker-Jarvis
[24], the sample is inserted between the two halves of a cylindrical cavity excited in the
TE01,2q+1
mode. The permittivity is extracted by measuring the resonant frequency and the
dimensions. The material’s loss tangent is extracted by calculating the bandwidth of the
measured peak. Other geometries that can be used for cavity resonant methods are
15
dielectric cylinders, as demonstrated by Hakki and Coleman [25] and Courtney [26], and
non-radiative dielectric waveguides (NRD) [27]. The Fabry-Petro open resonator
technique has been shown to be suitable for characterization up to 300 GHz [28-29].
2.3.4 Transmission Line Techniques
Transmission line techniques generally fall into the following categories:

Off-resonance waveguide and coaxial line, full scattering parameter, 2-port
measurements.

Off-resonance short-circuit line, 1-port measurements.

Open-circuit techniques.

Resonant transmission-line techniques.
The off-resonance techniques can be broadly grouped into two categories:

Point-by-point or uncorrelated-point techniques.

Multi-point or correlated-point techniques.
A detailed discussion of transmission line (Coaxial line and Rectangular Waveguide)
techniques employing off-resonance techniques is given in [30].
Coaxial lines are broadband in the TEM mode and therefore are attractive for
permittivity and permeability measurements. The problem with coaxial lines, however, is
that due to the discontinuity of the radial electric field, any air gap around the center
conductor degrades the measurements by introducing large measurement uncertainty.
16
2.3.5 Fourier Transform Infrared Spectroscopy (1 to 100 THz) [18]
At infra-red frequencies, Fourier transform infra-red spectroscopy can be used to
extract complex permittivity. Further details can be found in [18].
2.3.6 THz Time Domain Spectroscopy (TDS) (0.1 THz to 10 THz)[18]
Terahertz time domain spectroscopy is another technique which is used to
characterize materials at THz frequencies. Further details can be found in [18]
2.4
Challenge in the Characterization of LCP in the D-band and Proposed
Method
A suitable characterization method needs to be chosen to characterize LCP at the
D-band. The parallel plate method is used for lower frequencies. The free-space method
requires extra components. Fourier Transform infrared spectroscopy and THz time
domain spectroscopy methods are used to characterize materials in THz domain and
require special equipment. Since LCP is a low-loss material, we need a technique which
can help us characterize LCP with enough precision. Therefore, resonant methods are a
better choice in this case. The cavity resonator method has limitations in terms of
extraction of the electrical parameters only at one frequency whereas ring-resonator
method gives us resonances at multiple harmonics.
The main challenge, using the ring resonator method, to extract dielectric
parameters at the D-band is to find accurate radiation loss expressions or to find out a
way where we can de-embed the radiation loss from the total loss. We carried out a new
study and a set of simulations to investigate the main source of radiation. The objective is
to find out if the ring is the primary source of radiation or the main cause of radiation is
17
the open-ended feeding microstrip line. This approach/method is discussed in the next
chapter.
18
CHAPTER III
Characterization of LCP from 110 to 170 GHz
In this chapter we present the characterization of LCP from 110 to 170 GHz. We
used the microstrip ring resonator (MRR) method for the extraction of the dielectric
constant (𝜺r) and the loss tangent. The MRR was designed on 2-mil LCP. The copper
surface roughness was first examined using a Tencor profilometer and its rms value
varied between 0.1 µm and 0.2µm. With these values, the surface roughness would not
approach the skin depth until 170 GHz (0.174 µm @ 170 GHz). The ring resonator
designs produce an S21 with periodic resonant peaks. The extraction of 𝜺r is dependent on
the location of the resonant frequencies for a resonator of a given radius, while the
extraction of the tan δ is a function of the unloaded quality factor (Q) of the peaks [31].
The desired resonant peaks and corresponding ring radii were devised according to (3.1):
𝑓0 =
𝑛𝑐
(3.1)
2𝜋𝑟𝑚 √𝜀𝑒𝑓𝑓
In the above equation, fo, rm, 𝜺eff and c correspond to the nth resonant frequency of the
ring, mean radius of the ring, effective dielectric constant of the substrate, and speed of
light in vacuum respectively. We also designed the conductor-backed CPW to microstrip
transition so that the samples could be probed. For the microstrip line and the MRR, a 70
Ω impedance was chosen for two reasons: (1) to reduce the frequency dispersion effect of
the microstrip line, (2) to ensure that the ratio of the microstrip width and the mean radius
of the ring is << 0.2 so that the radiation from the ring structure can be minimized [32].
19
3.1
Extraction of the Relative Permittivity
The effective permittivity can be calculated using equation (3.1). In equation (3.1),
values of n, c, r m are already known and through measurements we measure the resonant
frequency of the RR structure. Relative permittivity can be extracted using quasi-static
[33-36] or frequency dispersive [37-38] models of effective permittivity. For this work,
we have used quasi-static model used in [36]. We have used this model because it
includes the effect of conductor thickness.
We can obtain the quasi-static effective permittivity using the following equation
(3.2)
ɛ𝑒𝑓𝑓(0)
1
−
2
ɛ𝑟𝑒𝑙(𝑓)+1 ɛ𝑟𝑒𝑙(𝑓)−1
12
(1 +
)
+
𝑊
2
2
ℎ
[
=
−
ɛ𝑟𝑒𝑙(𝑓)+1 ɛ𝑟𝑒𝑙(𝑓)−1
12
(1 +
)
+
𝑊
2
2
{
ℎ
𝑊 2
W
+ 0.04 (1 − ) – C for ≤ 1
ℎ
h
]
(3.2)
1
2
–C
for W/h ≥ 1
where
𝐶=
ɛ𝑟𝑒𝑙(𝑓)−1 𝑡/ℎ
2
(3.3)
√𝑊⁄ℎ
If we solve equation (3.2) for ɛ𝑟𝑒𝑙(𝑓) then we get the following equation (3.4)
ɛ𝑟𝑒𝑙(𝑓)=
2ɛ𝑒𝑓𝑓(0) +𝑀𝑡 −1
(3.4)
𝑀𝑡 +1
20
In equation (3.4), Mt is the term, which represents the effect of thickness of metallization.
Mt is defined in [39] as:
𝑊
2.𝑡/ℎ
ℎ
4.6√𝑊/ℎ
𝑀𝑡 = 𝐹 ( ) −
(3.5)
where
1
(1 +
𝑊
𝐹 (ℎ) =
(1 +
{
12ℎ −2
𝑊
12ℎ
𝑊
)
)
𝑊 2
+ 0.04 (1 − ℎ ) , 𝑓𝑜𝑟
𝑊
, 𝑓𝑜𝑟
𝑊
1
−
2
ℎ
ℎ
≤1
(3.6)
≥1
If we substitute ɛ𝑒𝑓𝑓(0) in equation (3.4) with the value of effective permittivity
obtained from equation (3.1), it would give us a fair estimate of relative permittivity
ɛ𝑟𝑒𝑙(𝑓). However, microstrip does not support a pure TEM mode; a phenomena called
frequency dispersion occurs when the fundamental TEM mode starts coupling to the TM o
and TE1 surface-wave modes. TM0 has a zero-frequency cut-off, the TE1 starts
propagating at the frequency given by [40]:
𝑓𝑇𝐸1 =
𝑐𝑜
(3.7)
4𝐻√ɛ𝑟𝑒𝑙(𝑓)−1
One should make sure that TE1 mode is not excited over the characterization range.
Another way to calculate the frequency above which the dispersion of microstrip line
should be taken into account is given by the following equation:
𝑓𝑑 =
𝑍0𝑚
√
𝐻 √ɛ𝑟𝑒𝑙(𝑓)−1
(3.8)
21
where fd is in GHz and H is in cm.
Several models of frequency-dependent effective permittivity have been proposed and a
review and comparative study has been carried out in [41]. We have used the method
presented by Kirschning and Jansen described in [41] because of its demonstrated
accuracy [41] at mm-wave frequencies. In this method,
ɛ𝑒𝑓𝑓(𝑓) =
ɛ𝑟𝑒𝑙(𝑓)− ɛ𝑒𝑓𝑓(0)
(3.9)
1+𝑃(𝑓)
where
𝑃𝑓 = 𝑃1 𝑃2 [(0.1844 + 𝑃3 𝑃4 )10𝑓ℎ)]1.5763
𝑃1 = 0.27488 + [0.6315 + 0.525/(1 + 0.157𝑓ℎ)20 ]𝑢 − 0.065683exp(−8.7513𝑢)
𝑃2 = 0.33622{ 1 − 𝑒𝑥𝑝[−0.03442. ɛ𝑟𝑒𝑙 (𝑓)]}
𝑃3 = 0.0363𝑒𝑥𝑝(−4.6𝑢) × {1 − exp[−(
20
𝑓ℎ 4.97
) ]}
3.87
𝑃4 = 1 + 2.751 {1 − exp[−ɛ𝑟𝑒𝑙 (𝑓)/15.916)8 ]}
By using numerical techniques such as the secant method [42], which was implemented
for the work presented in Chapter 2 of [43], equations 3.2 and 3.9 are coupled to find the
value of ɛ𝑟𝑒𝑙 (𝑓).
3.2
Extraction of the Loss Tangent and Investigation of the Radiation Loss
The extraction of the loss tangent was done by using equation (3.10) in which the
extracted effective permittivity from the dispersive model of [37] was used.
tan 𝛿 =
𝛼𝑑 𝜆0 √𝜀𝑒𝑓𝑓 (𝜀𝑟 − 1)
(3.10)
𝜋𝜀𝑟 (𝜀𝑒𝑓𝑓 − 1)
22
In equation (3.10), λ0, 𝜺eff, and 𝜺r represent the free space wavelength, the effective
permittivity, and the relative permittivity respectively.
The dielectric loss can be calculated using equation (3.10) introduced in [44]. This
equation gives the result in [Np/unit length]. The ring resonator method gives the total
loss at the frequency locations of each resonant peak and by subtracting the theoretical
values for the conductor loss we obtain the dielectric loss as shown in equation (3.11).
𝛼𝑑 = 𝛼𝑡𝑜𝑡𝑎𝑙 − 𝛼𝑐
[
𝑁𝑒𝑝𝑒𝑟𝑠
]
𝑢𝑛𝑖𝑡 𝑙𝑒𝑛𝑔𝑡ℎ
(3.11)
𝛼𝑡𝑜𝑡𝑎𝑙 is the total loss in the microstrip ring resonator, and 𝛼𝑐 is the microstrip conductor
loss. Then dielectric loss is inserted into equation (3.10) to obtain the loss tangent. The
radiation loss has been neglected in this expression for following reasons:

The ring resonator is designed with careful selection of microstrip widths and
mean radius. The radiation properties of ring resonators are explained in [45]
where it is shown that the radiation loss from the ring is extremely low for
the transverse TM11 mode. This is because the field from the inner and outer
edges of the ring interferes with each other destructively at resonance.

By making W/r m << 0.2, the excitation of the TM11 mode is ensured [46]

We know that oan pen-ended microstrip line radiates. This effect has been
neglected because this effect is de-embedded out because the TRL calibration
was used for measurements. This effect is verified by running a set of
simulations in a 3D simulator HFSS. The results will be presented later in
this chapter.
23
3.2.1 Total Loss Calculation
Total loss 𝛼𝑡𝑜𝑡𝑎𝑙 is calculated from each peak resonance found in the measured
S21 response of the ring resonator by computing the loaded (QL) and unloaded Quality
factor (Qu) [47]. QL and QU are calculated using the following expressions:
𝑄𝐿 =
𝑓𝑛𝑡ℎ
𝐵𝑊3𝑑𝐵
(3.12)
𝑄𝑈 = 𝑄𝐿 /(1 − 10
𝑆21,𝑑𝐵 (𝑓𝑛𝑡ℎ )
20
)
(3.13)
where BW3dB is 3 dB bandwidth of the S21 resonance peak and S21,dB(fnth) is the measured
value of S21 in dB at fnth. Finally the total attenuation is calculated by the following
expression:
𝛼𝑡𝑜𝑡𝑎𝑙 =
𝜋
𝑄𝑢 𝜆𝑔
(3.14)
where
𝑐
𝜆𝑔 = 𝑓
(3.15)
𝑛𝑡ℎ √ɛ𝑒𝑓𝑓 (𝑓𝑛𝑡ℎ )
3.2.2 Conductor Loss Calculation
The conductor loss is calculated by using the following expression, originally proposed
by Schneider in [48]:
𝛼𝑐 =
𝑊 2
ℎ
2
𝜋 ln(10) ℎ.𝑍𝑜𝑚 32+(𝑊)
ℎ
10
{
𝑅𝑠
32−( )
20
𝑅𝑠 𝑍𝑜𝑚 .ɛ𝑒𝑓𝑓 (𝑓)
ln(10)
ℎ.ɳ2
{1 +
{1 +
ℎ
𝑊
(1 +
𝜕𝑊
𝜕𝑡
)} , [dB/unit length]
𝑓𝑜𝑟
𝑊
ℎ
≤1
(3.16)
ℎ
𝑊
(1 +
𝜕𝑊
𝜕𝑡
𝑊
6ℎ
ℎ
𝑊
)} . { +
ℎ 5
𝑊
𝑊
ℎ
[(1 − ) + 0.08]}, [dB/unit length], 𝑓𝑜𝑟
24
≥1
where
𝜕𝑊
1
2𝐵
= ln( )
𝜕𝑡
𝜋
𝑡
and
ℎ,
𝐵={
2𝜋𝑊,
𝑊
ℎ
≥ 2𝜋
𝑊
ℎ
(3.17)
≤ 2𝜋
In equation (3.16) Zom can be found using the following expression:
ɳ
8
ln [
+ 0.25𝑊𝑒𝑓𝑓 ]
𝑊𝑒𝑓𝑓
2𝜋√ɛ𝑒𝑓𝑓
𝑍𝑜𝑚 =
{
ɳ
[𝑊𝑒𝑓𝑓 + 1.393 + 0.667 ln(𝑊𝑒𝑓𝑓 + 1.444)]−1
√ɛ𝑒𝑓𝑓
,
𝑊
≤1
ℎ
(3.18)
𝑊
, ≥1
ℎ
where ɳ = 120 𝜋 ,the free space impedance.
In equation (3.16) Rs can be calculated using the following expression. Rs includes a
correction factor originally introduced by Morgan in [49]
2
𝑅𝑠 = 𝑅𝑠 , {1 + 𝜋 𝑡𝑎𝑛−1 [1.4 (
𝛥𝑟𝑚𝑠 2
𝛿𝑠
) ]}
(3.19)
where
𝑅𝑠 , = √𝜋𝑓µ𝑜 𝜌𝑐
(3.20)
In expression (3.19), 𝛿𝑠 is given by
𝛿𝑠 =
25
𝜌𝑐
𝑅𝑠
where 1/𝜌𝑐 =σc=5.8x107 S/m( the conductivity of the copper), µ𝑜 is the permeability of
the vacuum , and 𝛿𝑠 is the frequency-dependent skin depth.
𝑊𝑒𝑓𝑓 in equation (3.18) can be calculated using the following expression:
𝑡
𝑊𝑒𝑓𝑓
4𝜋𝑊
𝑊 + 𝜋 (1 + 𝑙𝑛 𝑡 ),
={
𝑡
2ℎ
𝑊 + 𝜋 (1 + 𝑙𝑛 𝑡 ),
𝑊
ℎ
𝑊
ℎ
≤ 1/2𝜋
(3.21)
≥ 2𝜋
The radiation loss has been neglected based on the arguments presented earlier and the
proof that the ring does not radiate is presented in this work through simulations of 3D
electromagnetic models, with results presented in Fig. 3.2.
The radiation analysis was carried out at each resonant frequency of the MRR,
using a full-wave electromagnetic solver, for open-gap-MRR-gap-open, open-gap-open
and simple microstip line structures as shown in Fig. 3.1(a-c).
Figure. 3.1. (a) open-gap-MRR-gap-open structure, (b) open-gap-open, (c) simple
microstrip (d) CBCPW cross-section
26
The radiation loss curves for cases 3.1(a) and 3.1(b) closely overlap as shown in Fig. 3.2.
Therefore, it is evident that the main cause of the radiation loss is the feeding microstrip
discontinuities and not the ring itself. Moreover, we designed the ring resonator ensuring
that mrr_w/rm << 0.2 so that only the TM11 mode is excited. r m and mrr_w represent the
radius and the width of the ring resonator respectively.
Figure 3.2. Radiation loss simulation results for microstrip, open-gap-open and open-gapMRR-gap-open structures
3.3
Fabrication and Measurements
To fabricate the designed ring resonator, a 2 mil double copper (9 µm) cladded LCP
substrate was used. The patterning of the designs was carried out using standard
lithography and wet etching processes. The fabricated sample is shown in Fig. 3.3 (b).
The measured dimensions of the various features of the MRR and TRL standard lines are
tabulated in Table 3.1.
27
Table 3.1
Dimensions (mm)
mrr_w
0.0625
strip_w
0.0625
c_g
0.035
d_out
6.0303
s
0.041
d_in
5.9053
w
0.037
thru_TRL
0
w_g
0.235
TRL_L1
500
TRL_L2
850
The measurements were taken using Cascade MicroTech Infinity D-band probes.
The pitch of the probes was 75 µm. To calibrate out the cable, probe and test head losses,
we performed LRRM calibration on Cascade 138-356 ISS. After the LRRM calibration,
the TRL calibration was carried out using the designed TRL standard lines shown in Fig.
3.3 (a). After the TRL calibration, the reference plane moved to aa - and bb- as shown in
Fig. 3.3 (a) and (b).
Measured S21 response of the ring resonator is shown in Fig. 3.4. The
measured/extracted dielectric constant and the loss tangent are shown in Fig. 3.5 and Fig.
3.6 respectively.
Using the frequency dispersive model, the LCP dielectric constant is extracted to
be about 3.17 at 155 GHz and the loss tangent is estimated to be 0.0057. The uncertainty
bars represent the 95% confidence interval calculated using the Monte Carlo uncertainty
analysis as implemented in [43], using a population of 1E6 samples for all measured
quantities.
28
Figure 3.3. (a) TRL line standards, (b) ring resonator, (c) coupling gap between the feed line
and MRR
Figure 3.4. Measured S21 of Ring Resonator
29
Figure 3.5. Measured/extracted relative permittivity using ring resonator dielectric
characterization method
Figure 3.6. Measured/extracted loss tangent using ring resonator dielectric characterization
method
30
SUMMARY OF PART 1
In the first part of the dissertation, we first reviewed advanced packaging
substrates and discussed advantages and disadvantages of organic and ceramic substrates.
We also briefly reviewed various substrate characterization methods. Since LCP was not
characterized in the D-band, for the first time, we presented the characterization of the
dielectric properties of LCP from 110-170 GHz using the ring resonator method. We
carried out a study to show that the main source of radiation is the open-ended microstrip
feeding line and not the ring resonator itself. Therefore, if TRL calibration is used,
radiation loss can be eliminated from the total loss. The ring resonator characterization
results show 𝜺r = 3.17 and tan δ varies from 0.005 to 0.009. These results present the
excellent RF performance of LCP across the entire D-band which paves the way for
system-on-package solutions in the D-band using LCP.
31
PART II
Design and Development of on-chip and Antennain-Package Solutions for mm-wave Applications
32
CHAPTER IV
Development of Antenna-in-Package Solutions on Organic Substrates
In the previous two chapters (Ch 2 and Ch 3), we presented the review of
methods to characterize microwave substrates/materials and the characterization of LCP
from 110 to 170 GHz. The development of D-band modules will be presented in the Ch 8
of this dissertation. But since the characterization of LCP up to 110 GHz has been
reported in the literature [17], but the development of W-band end-fire antennas on LCP
and integration of V- and W-band antennas with excellent isolation and radiation patterns
has not been explored and reported before, this chapter focuses on the development of
novel ultra-wideband W-band tapered slot antenna and integration of V-band and Wband antennas on an organic platform. The work presented in this chapter is the first to
demonstrate the design and suitability of organic substrates for mm-wave antenna
development for applications in the V- and W-band, where end-fire antennas are required
and integration of two mm-wave antennas need to be integrated on the same platform.
Section 4.1 reviews the prior art of AiP solutions and in the later sections of the
chapter, design, development and measurements of AiP solutions on organic substrates
will be presented.
4.1 Background and Prior Art of AiP Solutions
Antennas are an integral part of wireless communication systems. To find
optimum and low cost antenna solutions for mm-wave systems, researchers are
investigating the performance and viability of on-chip and on-package antennas. On-chip
antennas are a very attractive option for complete system-on-chip (SoC) realization as
this could lead to a simple package design while the lossy chip-to-package interconnects
33
could be avoided. However, the area on the chip is typically limited, and the radiation
efficiency and directivity of on-chip antennas are quite poor. For this reason, antenna-inpackage (AiP) design and its optimal integration with radio frequency integrated circuits
(RFICs) is very important. With in-package antennas, there is also greater flexibility,
since different antennas can be developed for different applications using the same chip.
For AiP solutions, interconnects are required to connect the chip to the antenna port.
Different
Chip-to-package
transitions/interconnects
are
flip-chip,
wire-bond,
electromagnetically coupled strip lines, and short-via transitions. The design and the
optimization of these interconnects will be discussed in detail in chapter 7 to chapter 9 of
this dissertation, where the development of organically packaged mm-wave modules are
presented. In the following, we will briefly review the development of antennas on
different substrates, which have already been reported in the literature.
Although FR-4(ɛr =4.4 and tanδ =0.02), which is a very low-cost substrate, has
been used as an antenna substrate at lower frequencies, its dissipation losses increase
prohibitively at mm-wave frequencies. Therefore, others solutions have been investigated
to develop in-package mm-wave antennas. Fused Silica (Quartz), high resistive Si,
LTCC, LCP, Teflon (PTFE) are common packaging materials for AiP solutions. An
integrated 60 GHz antenna was developed by IBM and reported in [50]. In this work, a
flip-chip antenna element was printed on a fused silica substrate (ɛ r =3.8 and tanδ
=0.0003) and the bottom metal frame cavity was used as a reflector to increase the
directivity. Gain of 8 dBi and 13% of impedance bandwidth were reported. Because of
complex assembly techniques and higher costs associated with this technique, airsuspended superstrate antennas presented in [50] could not penetrate into the market.
34
Another cavity-backed antenna solution was demonstrated in [51], where high resistive Si
was used as the superstrate and the cavity material. The Si cavity was fabricated using
deep reactive ion etching (DRIE) and metalized afterwards. This antenna exhibits 6 to 8
dBi of gain and 10% bandwidth. Because of its complex processing steps such as DRIE
and critical alignment of the superstrate to cavity, this type of AiP solution couldn’t
flourish.
Another good packaging material is FerroA6-S LTCC (ɛr =3.8 and tanδ =0.0003).
LTCC is a good microwave substrate because of its multilayer capability and good
thermal conductivity. A considerable amount of work has been reported on LTCC (52,
53, 54, 55, and 56]. However, as discussed earlier in chapter 2, chips cannot be embedded
in LTCC because of its high (850 C) Co-firing temperature. It also has a high dielectric
constant, which limits the antenna efficiency considerably. Moreover, it is a brittle
material and can easily break and will not be able to absorb shocks. This becomes a
serious concern for packages greater than 4 cm2.
LCP and PTFE have relatively lower dielectric constants and are also very lowloss materials. A good deal of discussion has already been done in Chapter 2 about the
benefits and limitation of these two packaging materials. Because of low loss and low
dielectric constant of LCP, it is a very good choice for antenna implementation. A fair
amount of work has been reported in the literature using LCP as an antenna substrate [5761]. But the focus of the prior work was mainly on broad-side and end-fire antennas at 60
GHz and integration of two antennas (broad-side and end-fire) in the same band and not
on the ultra-wide band W-band end-fire radiation antenna and integration of multiple
antennas of different bands on the same platform. High-speed and high resolution
35
imaging applications have pushed researchers to explore mm-wave frequencies to fulfill
the ever increasing demand. Highly efficient and low loss antenna solutions at higher
frequencies and integration of multiple antennas in two different bands thus are desirable.
In this chapter of the dissertation, two antenna designs at W-band and V-band are
developed and discussed. For the first time, a low-cost ultra-wide band tapered slot
antenna and integration of V-band and W-band antennas on the same package with an
SPDT switch has been developed on an organic platform.
4.2 An Ultra-Wide-band W-band End-fire Antenna
E-Band and W-band are very attractive for higher data rates. E-band back-haul
communications is an attractive application in this band, which requires a wide band
antenna. High data-rate back-haul systems (71-76 GHz and 81-86 GHz) are commercially
available and deployed. E-band is (70-90 GHz) attractive for back-haul communication
especially because of good wireless propagation, as a clear atmospheric window can be
seen from 70 to 100 GHz with an attenuation as low as 0.5 dB/Km. A wide variety of
wide band antennas have been reported in the literature but very few have been reported
on flexible organic LCP in the E-band and W-band [62]. Tapered slot antennas (TSA) are
known for good directivity which is required at such a high frequency in order to
overcome path loss. Therefore, in this work, for the first time a 16.8 GHz wide band
(75.5-92.3 GHz), end-fire tapered slot antenna has been investigated which showed a
measured gain of around 8 dBi using a novel microstrip-to-slot transition [63] over a
wide bandwidth.
4.2.1 Tapered Slot Antenna (TSA) Design Theory
36
Tapered slot antennas (TSA) are travelling wave antennas (non-resonant
antennas). Unlike standing wave (resonant) antennas, the phase distribution along a
traveling wave antenna cannot be assumed to be constant as mentioned in [64]. The
reflected waves in resonant antennas are minimized by proper termination. For example,
the long wire antenna which is actually a resonant dipole antenna is terminated by a
matched load.
There are two types of traveling wave antennas: slow wave (surface waves)
antennas and fast wave (leaky wave) antennas. Slow wave antennas are those antennas
whose phase velocities are equal or less than the speed of light. These kind of travelling
wave antennas are called end-fire antennas. Fast-wave antennas on the other hand have
phase velocities greater than the speed of light. Such antennas are called leaky wave
antennas. TSA falls into the category of slow-wave antennas. A TSA uses a slot line
etched on a dielectric material, which widens its opening through its length to produce
end-fire radiation. An electromagnetic wave propagates through the surface of the
antenna substrate. The EM wave moves along the increasingly separated metallization
tapers until the separation is such that the wave detaches from the antenna structure and
radiates into the free space from the substrate end. The E-plane of the antenna is parallel
to the substrate since the electric field is established between two conductors that are
separated by the tapered slot. The H-plane, containing the magnetic component of the
EM wave, runs perpendicular to the substrate. TSAs exhibit broad band operation, low
side-lobes, planar footprints and ease of fabrication.
Tapered slot antennas have been first developed by Gibson et al. [65] and
Yngvesson et al [66-67] for phased-array and focal imaging systems. The performance of
37
a TSA is sensitive to the thickness and dielectric constant of the antenna substrate. An
effective thickness (𝑡𝑒𝑓𝑓 ), which represents the electrical thickness of the substrates, has
been defined as:
𝑡𝑒𝑓𝑓 = 𝑡(√ɛ𝑟 -1)
(4.1)
The accepted range of the effective thickness is 0.005λo ≤ teff ≤0.03λo [66]. Here
λo is the free space wavelength. For substrate thicknesses above the upper bound of
effective thickness, unwanted substrate modes develop that degrade the performance of
the TSA, while antennas on thinner substrates suffer from decreased directivity. In our
case, the teff is calculated to be 76 µm ( with ɛr=3.1 for LCP for a thickness of 100 µm).
The free space wavelength at 93 GHz is calculated to be 3.2 mm which defines the upper
and lower bounds of the effective thickness to be 94 µm and 15.7 µm respectively.
Effective thickness of 74 µm, calculated using the chosen parameters of the substrate for
this work, lies between the upper and lower bounds. Yngvesson in [67] presents a
detailed analysis of the effect of of different parameters such as length, dielectric
thickness, width of the aperture, and shape of the antenna.
4.2.2 TSA Design on LCP
The antenna was designed using a novel microstrip-to- slot transition introduced
in [68]. Figure 4.1 shows the structure of this transition, which is a slow wave slot-line
structure along with the tapered slot profile in the ground plane.
38
Figure 4.1. HFSS model with dimensions
Figure 4.4 shows this transition in much more detail. This transition was designed
as the conventional microstrip-to-slot transition, illustrated in Fig. 4.2, requires that the
width of the through 60 ohm slot-line on a 4 mil substrate is about 5 µm, which is below
the limitation of the minimum feature realization on LCP.
Figure 4.2. Conventional microstrip-to-slot transition
The results of the parametric sweep are presented in Fig. 4.3. It can be noticed that as 60
ohm line (with the width of 10 µm) has better matching and as the slot width is increased,
39
the impedance goes up resulting in a mismatch between the microstrip line and slot-line.
Therefore, a new transition is required which can support the wide-band operation of the
tapered slot antenna.
Figure 4.3. Simulated S11 showing difficulty to realize slot width of (10um) for 50 ohms
This transition was optimized in Ansys HFSS to have a good insertion loss and
reflection coefficient up to 100 GHz. Eleven loading stubs (1 mil line width and 1 mil
capacitive gap) were required in a 3.5 mil wide slot line. The feeding structure was
optimized to match the TSA input impedance from Zair =377 ohms down to 110 ohms
where the TSA is further connected to the microstirp-to-slot transition. This transition
transforms the 110 ohms TSA input impedance into 50 ohm in W-Band. The current flow
of this transition is shown in Fig. 4.4 and the equivalent circuit model of the transition is
presented in Fig. 4.5.
40
Figure 4.4. Current flow on the transition [68]
Figure 4.5. Equivalent circuit model of the microstrip-to-slot transition [68]
A snapshot of fabricated back-to-back to microstrip-to-slot transition is shown in Fig. 4.6
and its measured results are presented in Fig. 4.7. It can be observed that the back-to-back
transition loss is around 3.5 dB and for one transition, it is 1.25 dB.
41
Figure 4.6. Fabricated back-to-back transition
Figure 4.7. Measured S-Parameters of the new transition
4.2.3 Fabrication and Measurements of TSA
A double copper cladded 100μm 3850 LCP sheet is used for antenna fabrication.
Precise alignment holes along with ground vias (200μm diameter) were drilled using a
KrF 248 nm excimer laser. The vias were then filled by sputtering 1 μm of copper on
both sides of the sample. Next, the slow wave structure and the TSA profile were
42
patterned using a standard lithography process (photoresist developing followed by
etching of the metal), and at the end, the top side was patterned. The smallest feature size
on this sample was 1 mil and we were able to get that feature with 10 µm of over etching.
The fabricated antenna is shown in Fig. 4.8 (b-d).
Figure 4.8. Fabricated antenna and measurement setup: (a) measurement setup; (b)
backside of substrate (ground having TSA profile; (c) µstrip-to-slot transition with slow
wave structure (d) top side of substrate with CPW line
Measurements were performed using a standard SOLT calibration with 250 µm
GSG probes in a millimeter-wave anechoic chamber. The measurement setup is shown in
Fig. 4.8 (a). A standard horn antenna of 16 dBi was used as a reference transmit antenna.
An Agilent 8510C VNA was used to take the reflection coefficient and Agilent E8361C
was used for gain and radiation pattern measurements. E8361C PNA has frequency range
up to 67 GHz; therefore, N5260A (Head Controller) and V10VAA2 (millimeter-wave
VNA extender) were used to extend the range of PNA in the W-band (75-110 GHz). Fig.
4.9 shows the simulated and measured results.
43
Figure 4.9. (a) Measured and simulated gain and S 11 and (b) H plane co and cross
polarization measured and simulated results.
Due to the limitation of length of the 110 GHz cables (6 inch long), we were only
able to take measurements for 40 degrees each side of H-plane. The measured radiation
pattern and S11 match reasonably well with simulations. The deviation from the
simulation results is attributed to the variation in the gain of the standard horn antenna
and the over etching of metals by around 10 µm. The measured radiation patterns are
skewed a little bit; it may be because of the CPW probe sitting right next to the antenna.
4.3 Integration of V-Band and W-Band Antennas with SPDT Switch on an Organic
Substrate
In the V-Band and W-Band, because of shorter wavelengths, the antenna size is
small. Therefore, with good mm-wave multi-layer packaging materials, multiple antennas
can be integrated in the same package to further increase the data rate. Integration of two
antennas requires careful design. Two frequencies, 57 GHz and 80 GHz, were chosen so
that the frequency spacing of two antennas is sufficient to minimize the interference
between the two antennas. LCP and RO3003™ were chosen for integration of antennas
with the switch. It is for the first time that V-Band and W-Band antennas have been
44
integrated with a Hittite SDD112 switch enabling transmission of data both at 57 GHz
and 80 GHz by controlling the switch control voltages.
4.3.1 Dipole Antenna Design Theory
Dipole antennas radiate at boresight that is normal to the antenna substrate and
ground plane. Standing wave antennas and image theory are important concepts to
understand broadside antenna radiation. A dipole antenna, which is a standing wave
antenna because of the standing wave nature of currents flowing on each open ended
wire, is formed by bending two wires away from each other orthogonally to the feeding
transmission line. The currents on both wires are equal in magnitude but opposite in
phase. To reinforce the fields radiated from each wire and to increase the radiation
efficiency, the phase of the current on each wire should be the same throughout its length.
This condition is only met when the length of the dipole is less than a wavelength at the
frequency of operation. In other words, it means that the length of each wire is less than
half of a wavelength. Beyond that value, the standing wave currents on each wire have
alternate phase (0o or 180o), and the fields radiated from each section cancel each other
thus causing nulls in the radiation pattern. On the other hand, if the dipole is too small
compared to wavelength, the aperture of the antenna will be too small to intercept fields.
When the dipole antenna is placed on a ground plane, the energy is reflected from
the ground plane. The amount of reflected energy depends on the constitutive parameters
of the ground and medium separating the dipole from the ground plane. The most
appropriate technique to analyze this case is image theory. Using image theory, an
equivalent model is found in which the dipole and its virtual image combined together
have same radiation properties as the dipole above the ground plane. In image theory, a
45
couple of assumptions are made: 1) the ground plane is perfect conductor, 2) the size of
the ground plane is infinite. The second assumption requires more in-depth analysis of
the ground plane surface current distribution. In general, when the magnitude of surface
currents ebb off, the ground plane can be truncated with minor effect on the radiation
pattern. A typical rule of thumb is to truncate the ground plane at about five guided
wavelengths from the antenna edges. But his value can be further optimized using some
CAD tools. According to Maxwell’s equations, the tangential components of the electric
fields are null at the ground interface (h=0). Therefore, at the ground interface, the sum of
the direct and virtual tangential electric field is zero. Continuity at the limit of h=0
requires that the electric fields above the ground plane are out-of-phase with the electric
fields below the ground plane. Combining the fields radiated from both sources in the farfield result in the total electrical field EΨ magnitude proportional to
| sin(𝑘𝑜 √ɛ𝑟 ℎ cos(𝜃))|
𝑟
(4.2)
Where the argument of the sin function is half of the phase delay between the direct and
image plane waves paths. 𝑘𝑜 is the propagation constant in free space. From (a), the
radiation intensity is derived as
|EΨ|2
1
𝑈 (ℎ, 𝜃) 𝛼 𝑟
=
| sin(𝑘𝑜 √ɛ𝑟 ℎ cos(𝜃))|2
2ɳ
2ɳ
2
(4.3)
where ɳ = 120 π is the free space impedance. The condition for maximum radiation at
boresight (𝜃 = 0) is
𝑘𝑜 √ɛ𝑟 ℎ =
π
2
𝜆0
ℎ=4
(4.4)
(4.5)
√ɛ𝑟
46
where 𝜆0 is the free space wavelength. This is an important result. At 60 and 80 GHz, the
antenna substrate thickness may range from 500 to 800 µm for a relative permittivity
between 2 and 6. These values are very appropriate for antenna package at 60 GHz. This
is the attractive reason to take advantage of image theory to design high directivity dipole
antenna at 60 and 80 GHz. Moreover, the quarter-wave thick antenna substrate
contributes to a high enough frequency bandwidth. The efficiency of such antennas is
very high as the dipoles are far enough from the ground plane such that return currents do
not cancel direct currents. In this section, the design of integration of 60 GHz and 80 GHz
antennas will be presented and a compromise in terms of substrate height is made.
4.3.2 Integration of V- and W- Band Antenna Arrays on Organic Substrate
The design and stack-up of antennas are inspired from [69-70]. One important
design parameter is the stack-up of the whole package to allow easy integration of the
switch with two antennas. The antenna arrays are arranged orthogonal to each other to
reduce interference from the other antenna. The stack-up shown in Figure 4.10 (e) was
chosen. The ground in the middle of the stack up was required as the Hittite GaAs
SDD112 single pole double thru switch (SPDT) has ground on the back. Another
important design feature of this work is the design of wide-band (which covers both VBand and W-Band) wire-bond chip to package transition. At mm-wave frequencies, the
wire-bond adds inductance, which deteriorates the return and insertion loss. The problem
was solved by using a capacitive stub as shown in Figure 4.10(c). The optimized values
for width and length of the stub were found and the results are shown in Figure 4.11 (a).
One can see that without the capacitive stub the reflection coefficient exceeds -10 dB and
the insertion loss is greater than 1 dB from 80-90 GHz, while with the compensation stub,
47
the insertion loss remains below 1 dB and reflection coefficient is below -10 dB over the
entire desired band.
For fabrication, 9 µm copper cladded LCP and RO3003™ were used. First, the
backside of 15mil RO3003™ (ground plane) was patterned and the 2 mil LCP and
RO3003™ were laminated together with 1mil RO3908 bond ply. Thru vias were drilled
first and then grounding vias were laser drilled from bottom to the middle layer (leaving
the copper on the top and bottom intact).
Figure 4.10: (a) HFSS model of integration of switch with antenna, (b)snapshot of
fabricated module, (c) wide-band wire-bond transition with compensation stub, (d)
measurements underway, and (e) cross-sectional view of integrated module
Thereafter, the vias were plated, which added some copper to the surface of the board.
Next, the cavity was created by laser ablation of the material exposing the metal on the
middle layer to house the switch. Then, the outer images (antennas and feed network)
were created and plated on the final finish. Finally, the switch was mounted in the cavity
and wire bonded to the package as shown in Figure 4.10 (b)
Measurements were performed using a standard SOLT calibration with 250 µm
GSG probes in a millimeter wave anechoic chamber as shown in Figure 4.10(d). Two 25
dBi gain standard horn antennas were initially used to calibrate the system. For
48
measurements, an Agilent PNA was used with a QuinStar LNA and a 25 dBi gain horn
antenna.
Figure 4.11. (a) Measured and simulated gain and S-parameters and (b) H plane Co and
Cross polarization measured and simulated results.
The measured peak gain of the antenna was found by scanning the H-plane with
control voltages of the SPDT switch set such that there is an RF path from RFin to RFout1
where the 57 GHz antenna is wire bonded with the switch. Peak gain of the 57 GHz array
was measured to be 10.08 dBi as shown in Figure 4.11 (a). Peak gain of the 80 GHz array
was measured to be 9 dBi. Figure 4.11 (b) shows the simulated and measured results for
H-plane Co-pol, Cross-pol, and isolation between the two antennas. The isolation
between antennas was measured to be around 25 dB. The measured radiation patterns
and S11 match reasonably well with the simulation results. The slight deviation from the
simulation results is attributed to the variation in the gain of the standard horn antenna
and the over etching of metals.
49
CHAPTER V
Development of an on-Chip Antenna
5.1
Background and Prior Art
Development of highly integrated systems in the millimeter-wave (mm-wave)
frequencies is an attractive research area with potential impact on many significant
applications. While low-cost and high-performance silicon-based technologies pave the
way towards the realization of such systems, antenna integration strategy plays a major
role on the overall cost and performance and requires in-depth consideration.
System-on-package (SoP) solutions allow the choice of the best technology for
the antenna implementation such as low-loss microwave substrates like Liquid Crystal
Polymer (LCP), or Duroid [57]. But this approach requires mm-wave interconnects (flipchip or wire-bond), which affect the performance of the system due to the unavoidable
transition loss and also increases the overall cost of the system because of the additional
precision assembly step.
Another approach for antenna integration is to design an
antenna in an embedded wafer level package, as reported in [71]. Yet again, in [72] an
insertion loss of 0.65 dB was reported for single-ended and differential transitions in
embedded wafer-level ball-grid array (emWLB) technology. Because of these reasons,
namely the extra interconnect loss and the increased assembly cost, SoP solutions may
not be preferred for certain applications.
A System-on-Chip (SoC) solution, on the other hand, is a desirable alternative
that aims to integrate the antenna on the same chip with the front-end components. This
eliminates the mm-wave interconnects and the associated loss that is required for the
chip-to-antenna transition. Furthermore, a SoC solution reduces the overall form-factor of
50
the system, and facilitates assembly as high precision mm-wave interconnects are
eliminated. This would potentially lead to a reduction in the overall system cost keeping
in mind that typically the assembly cost constitutes a major portion of the total cost in
such systems.
Integrated Circuit (IC) space is a critical issue for on-chip antenna realization;
therefore, only high frequency antennas are suitable to be realized on-chip to avoid
prohibitive costs. In the D-band (110 to 170 GHz), the wavelength is around 2 mm,
making it possible to realize an antenna within a 1x1 mm2 area. However, for siliconbased technologies, because of the low-resistivity (~10 Ω-cm), and the high dielectric
constant (11.7) of the silicon substrate, the radiation efficiency and directivity of the onchip antennas are significantly worse than the off-chip variants. While an on-chip
ground-shield can be used to isolate the lossy substrate, because the distance between the
top and bottom metal layers in silicon technologies is typically in the range of 9 to 15
µm, the close proximity generates image currents in the ground plane, resulting in poor
radiation efficiency and drastically reduced antenna bandwidth.
Due to these reasons, it is challenging to design on-chip antennas in commercially
available silicon-based technologies and some of these challenges and existing on-chip
and AiP antenna solutions are explained in [73]. In the following, we will first briefly
touch upon some of the state-of-the-art on-chip antenna solutions, which have been
reported in the literature and then describe our proposed micro-machined on-chip antenna
solution and contribution of this work.
A significant amount of effort has been spent to improve the performance of onchip antennas. By employing a proton implantation technique, the resistivity of Si can be
51
increased, which reduces the loss [74], but does not solve the problem of substrate modes
due to the high dielectric constant of the silicon. Whereas, superstrate antennas can
increase radiation efficiency, however with the cost of increased complexity because of
their non-planar structure and cost due to the extra assembly step [75], they may not be
an attractive and optimal solution. Another technique to improve antenna performance is
to develop high impedance surface (HIS) or artificial magnetic conductor (AMC) based
broad-side on-chip antennas, which have also been reported in the literature [76-77]. But
the reported measured gain is around 1 dBi or less. Moreover, AMC antennas provide
some gain enhancement only over a narrow bandwidth. In [78] Mahanfar
et al.,
presented a new 60 GHz self-assembled monopole antenna for SoC and SiP packages,
using a MEMS fabrication process with estimated efficiency of 25% and derived gain of
-6.25 dBi. These gain values are still low and need to be improved. In [79] Marnat et al.,
presented a non-planar movable plate vertical on-chip antenna with reported gains of -3
and 3.5 dBi at 60 GHz for H and V polarization respectively. Neither simulated nor
measured efficiency were reported to get an estimate about the improvement in
efficiency. Only the gain at two frequencies was reported and gain vs frequency or
measured S21 plots to be used in the Friis equation to calculate gain were also not
provided to estimate the performance of the antenna over a certain bandwidth. Moreover,
non-planarity and the movable plate may also cause some reliability and stability issues.
Therefore more data is needed to evaluate the performance of such antennas for a fair
comparison.
Another promising solution for highly radiation efficient antennas is the removal
of the silicon substrate using localized back-side Etching (LBE) technology. This
52
technology can alleviate the aforementioned problems (low efficiency, high gain, and
non-planar structures) and enable the realization of on-chip antennas in an efficient way.
Recently this technology has gotten much attention as a few foundries like IHP
Microelectronics have integrated this LBE option into their commercially available
standard BiCMOS SiGe process. In the past, Papapolymerou et al. in [80], demonstrated
significantly improved antenna performance by removing the Si beneath using
micromachining technique. Recently, Wang et al. [81] have reported a D-band doubledipole antenna again using micromachining techniques, with a simulated efficiency of as
high as 60%. The aforementioned examples have investigated the integration of on-chip
broad-side antennas; however, for applications such as chip-to-chip communications,
short range communication using consumer electronics, and mm-wave imaging, antennas
with end-fire radiation are also required. Zhang et al. [82] reported on-chip inverted F
and quasi-Yagi antennas using post BEOL CMOS process for 60 GHz radio, but these
antennas provided only low gain (-12.5 dBi and -19 dBi) and low efficiency (3.5% and
5.6%).
In this work, we present a high-performance micro-machined on-chip D-band
planar end-fire antenna for SoC solutions using commercially available LBE technology.
For comparison and performance evaluation, a SoP solution realized in LCP technology
is presented as well. To the best of the author’s knowledge, this is the first time that an
on-chip D-band end-fire antenna has been realized using commercially available SiGe
technology with state-of-the-art performance having 82% simulated radiation efficiency
(and 73 to 76 % maximum measured efficiency), more than 30 GHz of 3-dB bandwidth,
and 4.7 dBi gain for a single element antenna at 143 GHz. Furthermore, the effects of
53
critical design parameters such as thickness of front and side walls of Si and size of the
Si-cavity has been investigated and reported. The effects of guard ring and metal fillers
that are required for process compatibility have also been investigated, and measured
results of on-chip antenna with and without the presence of guard ring and metal fillers
are reported. Performance of both on-chip and on-package antennas are compared and it
has been demonstrated that utilizing a technology-standard micromachining process, a
high-performance and low-form factor on-chip end-fire antenna can be realized with
performance comparable to the off-chip version. This is the first prototype and successful
demonstration of micro-machined end-fire antenna, which showed good enough
reliability, and endured post-processing of LBE for cavity ablation, removal of metal
fillers using infra-red (IR) laser and many measurement iterations. In future, the design
can be modified and optimized to further enhance the reliability.
5.2
Antenna Design
Because of the limited available on-chip space, selection of the antenna type is
critical. Tapered slot and quasi Yagi-Uda antennas are two popular end-fire antennas
reported in the literature. For optimal performance, a tapered slot antenna needs to be 3 to
4 𝝀o long, whereas a quasi Yagi-antenna can be realized within an area of 𝝀0/2 x 𝝀0/2.
Therefore, to minimize the footprint of the on-chip antenna, a quasi-Yagi antenna
topology has been selected for this work.
An X-band uniplanar quasi-Yagi antenna that has the compactness of resonanttype antennas was first demonstrated and reported in [83-84]. The antenna is mainly
composed of the driven element that is fed by a feed network, as illustrated in Fig. 5.1.
54
Figure 5.1. Schematic view of a Yagi-Uda antenna including measurement pads
The director is used to increase the gain and directivity. The driven element and director
are printed on top of the substrate. There is no reflector on the bottom side; instead, a
truncated ground plane is used. The driven element is fed with a coplanar stripline (CPS)
that excites the zero cut-off TE0 dielectric surface-wave modes. The radiation from this
structure is a combination of free space and substrate radiation. The substrate radiation
consists of the combination of a transverse electric (TE) and transverse magnetic (TM)
polarized wave travelling through the medium. The Yagi-Uda antenna structure has two
guided dielectric mediums: a) non-grounded guided dielectric medium, and b) grounded
dielectric medium. According to the wave propagation theory, a wave travelling through
a non-grounded guided dielectric presents TE0 and TM0 as dominant modes, while for a
grounded dielectric medium, TM0 is dominant and TE0 is cut-off. The driven printed
dipole generates TE0 surface wave with very little TM0 mode. The driver and the director
are strongly coupled by the TE0 surface wave. The truncated ground acts as a reflector
55
because the TE0 mode is cut-off by the grounded dielectric slab. For the grounded
dielectric slab cut-off frequencies can be calculated using the following equation.
𝑓𝑐 =
3 ∗ 108 ∗ 𝑛
,
4 ∗ 𝑡 ∗ √𝜀𝑟
(5.1)
where t is the thickness of the substrate in meters, 𝜺r is the dielectric constant of the
medium and n is the mode.The cut-off frequency for this TE mode for LCP with a
dielectric thickness of 50 µm and dielectric constant of 3.2 is 838.5 GHz, which is much
higher than the frequency of operation (140 GHz) for this design. For an on-chip antenna
in SiO2 substrate with a thickness of 9.8 µm and dielectric constant of 4.1, the cut off
frequency equals 3.77 THz [85].
For the CPS fed antenna, the characteristic impedance and length of the CPS line
are two important parameters. CPS spacing (S_CPS) has a significant impact on the
characteristic impedance and should be reduced to minimize the impedance. The length
should be adjusted to be around 𝝀/4 from the edge of the truncated ground plane. As a
design standard, the driven element resonates with a length less than 𝝀/2 (0.45 to 0.49 𝝀),
whereas the length of the directors ranges from (0.4 to 0.45 𝝀). The separation between
directors ranges from 0.3 to 0.4 𝝀. The separation between the driven element and
truncated ground plane should be less than the spacing between driven element and the
driver, usually around 0.25 𝝀. For correct feeding of the driven dipole element, both strips
should carry current of equal magnitude but with opposite polarity. Additionally, for the
measurements of the antenna using RF-probes, ground-signal-ground (GSG) pads are
required, as shown in Fig. 5.1 at the bottom side. Therefore, a balun is designed to
convert a CPS line to a microstrip line. A 180º phase shift, introduced between the two
56
balanced ports of a microstrip balun, ensures that only the coupled microstrip odd mode
is excited at the output of the balun (or at the input of the CPS line). A quarter-wave
transformer was employed to transform the impedance seen at the input of the balun to a
50 Ω microstrip transmission line (MTL). Finally, in order to probe the sample, a
microstrip-to-CPW transition was designed by including ground pads.
5.2.1 On-chip Antenna Design Using Localized Back-side Etching
The quasi-Yagi antenna for on-chip implementation was designed according to
the design guidelines discussed in the previous section. The process technology used is
the 130 nm SiGe BiCMOS platform from IHP microelectronics. This technology features
seven metallization layers and an embedded RF-MEMS module with LBE option. The
design, as will be outlined below, is optimized for maximum gain while maintaining
process compatibility. The EM-simulation model of the designed antenna is shown in
Fig. 5.2. The arrows in Fig. 5.2 also show the direction in which the standard horn gain
antenna should be rotated to measure E- and H-plane radiation patterns. All the design
parameters of the on-chip antenna are reported in Table 5.1. Fig. 5.3 illustrates the crosssectional view of the on-chip end-fire Yagi-Uda antenna, displaying all important parts of
the antenna structure with labels. Since this antenna is designed on commercially
available silicon technology, there are few design considerations that cannot be
overlooked such as the dimension of the silicon cavity, thickness of the silicon walls
around the antenna or guard rings and metal fillers around the antenna. Metal fillers, a
guard ring, and Si around the antenna can affect the antenna performance in an undesired
fashion. Therefore, a comprehensive design analysis needs to be performed to determine
the effect of these parameters, and optimize the antenna design accordingly.
57
Figure 5.2. On-chip Yagi-Uda antenna HFSS EM-model
Figure 5.3. Cross-sectional view of on-chip end-fire Yagi-Uda antenna with LBE
58
Table 5.1
On-Chip Antenna Design Parameters
Dimensions (mm)
dir_l
0.6
Si_s
0.1
drv_l
0.35
Si_f
0.1
qw_w
0.026
bal_l
0.242
50_w
0.015
bal_g
0.1
s
0.74
cav_l
1.4
cav_h
0.3
Si_h
0.3
SiO2_h
0.0098
Si_r
0
50_g
0.02
d
0.2
Since the fundamental operation of a quasi-Yagi antenna relies on surface-wave effects,
for optimum performance a certain height and dielectric constant of the substrate is
required. But for on-chip antenna scenarios, the height of SiO2 within the back-end of the
line (BEOL) is dictated by the technology the antenna is being realized in. For the SiGe
BiCMOS process used in this design, the height of the SiO2 between the lowest and
highest metal layer is 9.8 µm. Assuming that the silicon substrate underneath the antenna
will be etched out by the LBE process, the initial dimensions of the antenna are obtained
from tables given in [64] for maximum directivity in air using one director, one reflector,
and cylindrical-wire elements with a diameter, “d” with 𝑑⁄𝜆 of 0.0085. The equivalent
width of each director and driven element is obtained using w = 2d, which maps the
diameter of a cylindrical dipole to a flat strip with near-zero thickness. This results in an
element width of 0.04 mm at 140 GHz. The dimensions are then scaled to compensate for
59
the 9.8 µm-thick SiO2 substrate. For the final structure shown in Fig. 5.2, the wide
conductive elements are slotted due to the limitation of the maximum metal width
requirements. The simulations show that these slots have a negligible effect on the
performance of the antenna.
The input impedance of the Yagi-Uda antenna is mainly affected by the distance
“s” from the meander line of the balun to the pseudo-reflector, and the spacing of the
meander line gap “bal_g.”. The impedance at the input of the balun is simulated to be 34
Ω and a quarter-wavelength transformer with a characteristic impedance of 41 Ω is used
to transform this impedance to 50 Ω. To extract the insertion loss of the balun, a back-toback balun structure is simulated as illustrated in Fig.5.4 The insertion loss of one
balun(which transforms microstrip line to coplanar strip line (CPS)) is 0.6 dB at 140
GHz.
Fig. 5.4. Simulated insertion loss of back-to-back balun structure
60
Through simulations, it was observed, that the thickness of the front-wall (Si_f) is one of
the most important parameters, which affect the radiation pattern of the antenna.
Simulation results showing the effects of “Si_f” on the E- and H-plane radiation patterns
are presented in Fig. 5.5 and Fig. 5.6. For all simulations a bulk conductivity of 10
Siemens/m was used for silicon.
It is seen from Fig. 5.5 and 5.6 that “Si_f” has a substantial effect on the radiation
pattern and gain of the end-fire antenna. As “Si_f” is increased up to 300 µm, the gain of
the antenna drops by 4 dB compared to a “Si_f” thickness of 25 µm. While the shape of
the E-plane radiation pattern is preserved up to a “Si_f” value of 175 µm, it starts
contracting when “Si_f” equals 300 µm. On the other hand, the contours of the H-plane
radiation pattern are more dependent on the values of “Si_f”. Fig. 5.6 illustrates that for
increasing “Si_f”, the H-plane pattern starts to contract, resulting in a narrower beam
width, lower gain in the end-fire direction, and slightly higher gain in the broadside
direction. Similarly, a gain reduction of 4 dB is observed when “Si_f” equals 300 µm, as
compared to a “Si_f” of 25 µm. Because silicon absorbs most of the energy, if “Si_f” is
further increased, the gain of the antenna is significantly reduced. Therefore, an optimum
front silicon wall thickness should be chosen that does not drastically degrade the antenna
gain while maintaining sufficient support for a physically intact structure that can be
safely handled. Following the design guidelines provided by the technology foundry, a
value of 100 µm is chosen for the “Si_f” parameter with a predicted a gain of 4.7 dBi via
simulations.
61
Figure 5.5. Simulated effect of the silicon wall in front of the antenna (Si_f) on the E-plane
radiation pattern.
Figure 5.6. Simulated effect of the silicon wall in front of the antenna (Si_f) on the H-plane
radiation pattern
62
The thickness of the silicon remaining beneath the antenna “Si_res” is another
important parameter and needs to be well controlled during the fabrication process. Fig.
5.7 demonstrates that if “Si_res” varies during the fabrication process, the frequency of
operation will shift. Even a variation of 10 µm will result into a shift of more than 14
GHz (10%). Consequently, the return loss at the desired frequency will be degraded and
radiation patterns will be distorted. For the technology utilized in this design the value of
“Si_res” by default equals zero. The results presented in Fig. 5.7 serve as a guideline if a
custom back-side silicon etching process is intended to be developed. The back-side
silicon etching used for this process ablates the silicon completely all the way to silicon
dioxide layer with excellent precision.
Figure 5.7. Effect of thin layer of Si (Si_r), in the cavity under the antenna on return loss
(S11)
A set of simulations was also carried out to investigate the effects of the thickness of the
silicon side-wall, “Si_s”. During this set of simulations, “Si_f” was fixed at 100 µm. The
63
simulation results of E- and H-plane radiation patterns are presented in Fig. 5.8. These
results indicate that the silicon side-wall thickness, “Si_s”, has a relatively modest effect
on the antenna performance as compared to the front-wall thickness. A 1.5 dB of gain
variation is observed if “Si_s” is increased up to 300 µm. Almost no distortion was
observed in the shape of E- and H-plane radiation patterns. The field distribution of the
antenna illustrated in Fig. 5.9 also confirms that the effect of the front wall is more
significant as compared to side-walls as front wall directly obstructs and absorbs the
radiation.
Figure 5.8. Simulated effect of the silicon side-wall thickness (Si_s) on the H- and E-plane
radiation patterns at 143 GHz.
The actual dimension of the silicon cavity is also a critical design parameter and needs to
be properly chosen. The cavity needs to be placed directly underneath the antenna and
sufficiently extend below the truncated ground plane as shown in Fig. 5.2 and 5.3.
64
Figure 5.9 Field distribution of on-chip antenna (a) side view, (b) 3D view
In Fig. 5.10 (b), the effect of the cavity size on the antenna gain is displayed. As the
dimensions of the cavity are increased above 1 mm, the gain increases only slightly. For
this design, a cavity size of 1.4 x 1.4 mm2 was chosen as a compromise between the gain
and the overall size of the antenna. In Fig. 5.10 (a), the effects of both side walls are
shown when “Si_s” and “Si_f” are varied one at a time.
To optimize the antenna performance, a parametric simulation of length of the
director and driven dipole was performed and the simulated results are shown in Fig. 5.10
(c) and (d). It can be seen (solid purple line) that the dir_l =0.6mm and drv_l = 0.325mm
gives the optimum performance. The effect of the guard ring and the metal fillers on the
performance of antenna was investigated as well. The guard-ring is a metal ring from top
to bottom metal around the antenna (shown in Fig. 5.2) that is required as a boundary for
the chip fabrication. It was found that the gain reduces by 0.3 to 0.5 dB across the desired
65
band of operation due to the fillers and the guard ring. Simulated and measured radiation
patterns with and without guard-ring are presented in Section IV.
Figure 5.10. (a)Variation in the gain by varying the thickness of Si wall in front of the
antenna (Si_f), thickness of side-wall of Si (Si_s), and (b) cavity size (cav_l) (refer to Fig. 5.1
and 5.2 for parameter identification), (c) variation in the gain vs frequency by changing the
length of the director (dir_l), and (d) variation in the gain vs frequency by changing the
length of the driver(drv_l)
66
5.2.2 Antenna Design on LCP
The on-package antenna was designed on a flexible 50 µm thick LCP substrate. This
substrate material has recently been characterized up to 170 GHz, demonstrating
excellent electrical properties such as a constant dielectric constant of 3.1 and low loss
tangent of 0.006 at 165 GHz [86]. The HFSS EM-model of the on-package antenna is
shown in Fig 5.11. The thickness of the substrate was chosen to be 50 µm considering the
high frequency of operation. The antenna was designed using the design guidelines
discussed in Section II and all dimensions of the on-package antenna are reported in
Table 5.2.
Figure 5.11. On-package Yagi-Uda antenna HFSS EM-model
The simulations of the complete on-package antenna predict 6.3 dBi gain and a 3-dB gain
bandwidth of more than 15 GHz and10-dB impedance bandwidth of around 10 GHz.
67
Table 5.2
On-Package Antenna Design Parameters
Dimensions (mm)
5.3
pdrv_l
0.4
g
0.015
pqw_l
0.4
sub_h
0.05
pqw_w
0.12
cpw_w
0.4
p50_w
0.12
pbal_l
0.28
ps_w
0.08
pbal_g
0.1
pdir_l
0.7
p_d
0.35
Fabrication
The fabrication of the on-chip antenna was performed in IHP Microelectronics
130 nm SiGe BiCMOS process. In Fig. 5.12, the fabricated on-chip antenna with and
without the guard-ring can be seen. The guard-ring was removed from the antenna by
post-processing using an IR laser.
Figure 5.12. (a) On-chip Yagi-Uda antenna, (b) On-chip Yagi-Uda antenna after the guardring is removed,
For the in-package antenna, the fabrication was performed in a clean room environment.
The fabricated on-package antenna is shown in Fig. 5.13.
68
Figure 5.13. Yagi-uda antenna fabricated on LCP substrate
For the fabrication, copper was removed from both sides of the 50 μm LCP for
alignment-via drilling. The LCP was cleaned using a Plasma Therm RIE and then a Karl
Suss MA-6 mask aligner was used to pattern the top and bottom sides of the substrate. An
important consideration here is the realization of the minimum feature size. The smallest
feature size of the on-package antenna in this work is 15 µm. Realization of this feature
size is at the fabrication limits. Additionally, since LCP is an organic substrate and has
1.0 to 1.5 µm surface roughness associated with it, at least 4 to 5 µm of metal needs to be
deposited. Therefore, for such thick metal layers (5 to 9 µm), appropriate measures such
as compensation in the masks for metal over-etching needs to be taken and wet etching
should be performed with extreme care to successfully realize the minimum feature size.
5.4
Measurement Results And Discussion
The fabricated antennas were characterized in D-band (110-170 GHz) using an
E8361C vector network analyzer extended with N5260A (mm-Wave Controller), and
V06VNA2 (mm-Wave Test Heads). Cascade MicroTech Infinity D-band probes, with a
pitch of 75 µm, were used for these measurements. The E-plane radiation pattern
69
measurement setup is shown in Fig. 5.14 (b). The arrows in Fig. 5.15 show the direction
of the movement in which the standard horn gain antenna should be rotated to measure
the radiation pattern. The zero degree for E and H plane is always the center of the
antenna. The horn antenna is moved in a semicircle as shown in Fig. 5.14 (b) to the AUT
structure. A block diagram of the measurement setup is presented in Fig. 5.15 as well.
Figure 5.14 (a) Probed antenna, (b) Setup for E-plane radiation pattern measurements
Figure 5.15 Block Diagram of the radiation pattern measurement setup
70
For radiation pattern measurements, antennas were mounted on a foam material
with a dielectric constant that is close to one. Mm-wave absorbers were used to absorb
any reflection from the surrounding objects. To calibrate the system for taking radiation
pattern measurements, two D-band 24 dBi standard-gain horn antennas were used as a
reference and the gain-comparison method was employed to acquire the gain of the
antenna under test (AUT). The measurements were calibrated to the wave-guide ports of
the mm-wave test heads by using WR-6 wave-guide calibration standards. During data
processing, a measured probe loss of around 2 dB, was taken into account for the gain
estimation of the AUT. Finally, in order to ensure that the radiation pattern measurements
are taken in the far-field, both antennas were spaced at a distance of 150 mm.
5.4.1 On-chip Antenna Measurements
The return loss, gain, and the radiation patterns of the on-chip antenna are
presented in Fig. 5.16 and 5.17 respectively. It is seen from the results presented in Fig.
5.16 that the measured gain is in good agreement with the simulated results and varies
minimally by less than 1.5 dB. The 3-dB bandwidth of this antenna extends beyond 30
GHz in terms of gain; and the 10-dB impedance bandwidth is larger than 20 GHz(14%
bandwidth).
The antenna resonates at 143 GHz and the gain value is 4.7 dBi at this frequency
when the guard ring and the metal fillers in the front side of the antenna are removed by
post-processing. A gain value of 4.3 dBi was measured when the metal fillers and the
guard ring was present; a degradation of only 0.4 dB. The difference in gain with and
without guard ring and metal fillers can be seen in the radiation pattern measurements
71
performed at 143 GHz in Fig. 5.17. The cross-pol pattern is 15 dB below the E-plane Copol pattern, which indicates a good linear polarization of the antenna.
Figure 5.16. Measured and simulated return loss and gain of the on-chip antenna with LBE.
Another set of measurements was performed where two on-chip antennas were
placed in front of each other at a distance of 10 mm, 30 mm and 50 mm, representing a
chip-to-chip communication scenario. The measurement setup for these measurements is
illustrated in Fig. 5.18.
A mm-wave absorber was used to avoid reflections from the metal chuck.
Measurements were performed at three different distances to validate the Friis free space
path loss (FSPL).
72
Figure 5.17. Measured and simulated E- and H-plane radiation patterns at 143 GHz of onchip antenna with LBE (a) E-plane, (b) H-plane.
Fig. 5.19 presents the estimated and measured path loss. The estimated path loss
was calculated by adding the theoretical value of Friis FSPL to the measured gain of the
on-chip antenna. It is seen from the results presented in Fig. 5.19 that the estimated pathloss values correlate well with the measured ones.
73
Figure 5.18. Block Diagram of the chip-to-chip link measurement setup
Figure 5.19. Link measurements for two on-chip antennas placed in front of each other
Because of the non-availability of setup required to do the hot-cold
measurements, to estimate the measured efficiency, we measured the radiation efficiency
of on-chip antenna using Gain/Directivity and Wheeler-Cap method as explained in [87].
Accurate measurement of the radiation efficiency is a challenge especially at mm-wave
frequencies and measurement uncertainties are caused because of many assumptions used
74
in the radiation efficiency methods. The measured efficiency of the on-chip antenna is
calculated to be 76% and 72% using Gain/Directivity and Wheeler-Cap method
respectively as depicted in Fig.20. As explained in [87], to avoid measurement errors, for
G/D method, the sampling interval of 5 degrees was chosen for E and H plane radiation
patterns. Using this method the radiation efficiency was calculated to be 76%, which
correlates well with the simulated efficiency of 82%.
The Wheeler cap, shown in Fig. 5.20, that was used to encapsulate the end-fire
antenna had one side open (2.5 mm x 0.7 mm) in order to be able to slide the cap over the
antenna. As the dimension of the antenna chip is 2 mm x 2 mm, the dimensions of the cap
were chosen to be 2.5 mm x 2 mm x 0.7 mm (W x Lx H). It was ensured that the two cutoff frequencies of the cap lie outside the frequency range (130 to 160 GHz) of interest.
With the chosen dimensions, the first cut off frequency of the cap is 60 GHz, the second
is 120 and the third is 170 GHz. Because of the chosen large dimensions (dictated by the
size of the antenna chip), and one open side (2.5 mm x 0.7 mm), some of the radiation
may not have been completely contained within the cap hence resulting into less
measured efficiency (72%). To compare the accuracy and reliability of the radiation
efficiency methods, radiation efficiency of the antenna on LCP was also measured. The
on-package antenna efficiency was measured to be 89% and 86% using Gain/Directivity
and Wheeler-cap methods respectively. Most of the time, only simulated efficiency is
reported in the literature for mm-wave antennas but this measurement was carried out just
to get a coarse estimate of the measured efficiency to validate the simulated efficiency. In
order to get accurate results, more rigorous methods, complex setups and analyzing
techniques may be utilized.
75
Figure 5.20 Simulated and Measured on-chip antenna efficiency
5.4.2 On-Package Antenna Measurements
Fig. 5.21 shows the simulated and measured gain and return loss of the onpackage antenna. A passive antenna gain of 6 dBi is measured at 143 GHz while the gain
varies by less than 1.5 dB from 135 GHz to 147GHz. Simulated and measured E- and Hplane and cross-pol radiation patterns antenna are shown in Fig. 5.22. When on-chip and
on-package radiation patterns are compared from Fig. 5.22 and Fig. 5.17, it is seen that
the H-plane contour of the on-chip antenna is narrower because of the presence of the
silicon wall around it. Except for this effect, the on-chip antenna performance is
comparable with the antenna developed on LCP, while it should be kept in mind that an
on-package antenna requires an additional mm-wave interconnect (0.5 dB loss per
interconnect at 140 GHz [88]) which further degrades the overall performance.
76
Figure 5.21. Measured and simulated return loss and gain of antenna-in-package on an
organic substrate LCP
Table 5.3 presents the comparison of this work with other on-chip antennas
reported in the literature. All efficiencies, except for the on-chip antenna radiation
efficiency presented in this work, in Table 5.3 are simulated values. This work presents
state-of-the-art performance for an end-fire D-band on-chip antenna in terms of simulated
and measured efficiency and bandwidth. Furthermore, this work demonstrates that an onchip antenna implementation using a standard LBE process is possible with high
performance that is comparable to an on-package version developed on LCP substrate.
77
Table 5.3
Comparison Between State-of the On-Chip Antennas
Ref.
Process
Topology
Freq
(GHz)
Area
2
(mm )
Peak Gain
(dBi)
Radiation
Efficiency
82 % Simulated
efficiency and
76% measured
efficiency at 143
GHz
This
work
0.13 µm
SiGe
BiCMOS
Quasi-Yagi
135 –165
2x2
3.5-5.1
This
work
LCP
Quasi-Yagi
135 - 155
0.8 x 0.8
4-6
92 % Simulated
efficiency
Dual Dipole
125 - 145
1.63 x
0.52
4-7
60% simulated
efficiency
-19, -12
3.5% and 5.6%
Simulated
efficiency
2 and 8
50% simulated
efficiency
[81]
SiGe
BiCMOS
0.2 x 2
[82]
Post BEOL
Inverted–F and
quasi-Yagi
55 - 65.5
[89]
Quartz
Superstrate
Slot and Horn
90 - 99
[90]
0.13 µm
CMOS
Taper slot
140
N/A
-25
N/A
[91]
CMOS
Slot
137 - 142
1.2 x 0.6
-2
18 % simulated
efficiency
[92]
MEMS
Dipole
57-63
2.43 x
2.43
2.18
35 % Efficiency
on low resistivity
silicon
[93]
SiGe
Dipole
83 (12 GHz
of BW)
1.8 x 1
4.1
N/A
78
0.4 x 1.3
Figure 5.22. Measured and simulated E- and H-plane radiation patterns of on-package
(LCP) antenna on an organic substrate
SUMMARY OF PART II
The second part of this dissertation was devoted to demonstrate the design and
development of AiP and on-chip antennas at mm-wave frequencies.
An end-fire travelling wave tapered slot antenna with a wide band novel
microstrip-to-slot transition is presented with good results over a range of 19.2%
bandwidth in the W-band. The antenna has a measured gain of 8 dBi with a slight
variation of 2.5 dB from 75.5 - 92.3 GHz.
We also demonstrated for the very first time, the integration of V-Band and WBand antennas with SPDT switch on multi-layer organic substrates. The measured results
showed 10.08 dBi peak gain for a 57 GHz antenna which matched well with the
simulation results. A minimal variation of 1.2 dB is seen in the measured gain from 54 to
61 GHz. The isolation between two antennas is around 25 dB. This work paves the way
79
for low cost integration of mm-Wave multi band antennas on organic substrates that are
flexible and can be mounted on conformal surfaces.
In another chapter, for the very first time a low form-factor D-band end-fire onchip antenna was presented with high radiation efficiency. Design guidelines for the
development of the on-chip end-fire antenna were presented. The on-chip antenna
showed a 3-dB bandwidth (in terms of gain) of greater than 30 GHz with a gain of 4.7
dBi at 143 GHz and a simulated efficiency of 82% and measured efficiency of 72-76%.
The impedance bandwidth of the on-chip antenna is greater than 20 GHz (14%
bandwidth). E- and H-plane Co- and Cross-pol radiation patterns were measured at 143
GHz. All patterns are in good agreement with results predicted by simulations. The
results of the on-chip D-band end-fire antenna are compared with an on-package version.
It was shown that using a technology standard LBE process, an on-chip antenna with a
comparable performance to an on-package version can be developed.
80
PART III
Design and Development of K-, V-, W, and Dband Front-end Components and Modules for
Microwave and Mm-wave Applications
81
CHAPTER VI
BACKGROUND/LITERATURE SURVEY
6.1
Advanced Packaging Solutions for the Development of Mm-Wave Modules
Size miniaturization, component integration, cost reduction, and performance
enhancement are the primary focus of today’s wireless systems. To achieve these
objectives, low-loss packaging of ICs that have wide-band performance is of crucial
importance. Therefore, advanced packaging techniques have been developed that replace
traditional bulky configurations. These advanced packages include system-on-chip (SoC)
[94], stacked ICs in package (SiP) [95] and system-on-package technologies (SoP) [96]
as shown in Fig. 6.1.
SoC is the most desirable solution as it integrates the whole system on one chip,
but this technology limits the system to one substrate, which raises issues like noise
coupling, complex integration and increased footprint if all passive circuit is also
implemented on the chip. Moreover, on-chip antennas, which have relatively poor
radiation efficiency, also consume a lot of real estate at lower frequencies. SiP and SoP
technologies address many of these issues through multi-functional integration at the
package level with relatively lower cost.
SiP technology allows multiple chips to be stacked up and inter-connected
together using wire-bond, flip-chip, and TSV technologies. This approach allows us to
integrate chips fabricated using multiple semiconductor technologies. SiP is used only for
inter-chip connection; however SoP technology extends this concept and allows us to
integrate high-density hybrid interconnects, compact passive structures, including
inductors and capacitors into the substrate in a multi-layer fashion.
82
Figure 6.1: Advanced packaging techniques (a) SoC [94] (b) SiP [95], (c) SoP [97]
Moreover, it also allows us to embed chips into the substrate. Thus a high
performance module can be implemented while simultaneously achieving cost and size
reduction [98]. SoP modules solve the major shortfalls of SoC by providing a low loss
substrate material for the RF passives and a unique space saving capability for chip
integration in or on the substrate. Connecting these passives and active components on
the board and encapsulating the assembly inside of a robust package are two steps critical
to reliable operation of an RF system. There are several technologies available for the
integration of passives and ICs into the system platform.
The lowest-loss interconnects and transmission lines are made using metal
waveguides (0.04 dB/mm at GHz). Silicon micro-machined metal waveguides with a loss
of 0.05 dB/mm have been fabricated at JPL[99]. These waveguides are manufactured
using silicon micromachining technologies (such as end mill with 80,000rpm speed) and
then metallizing them. In such modules, width and depth are very important and metal
83
waveguides with a thickness of 20 to 200 µm are used at THz[99]. Moreover the metal
surface roughness is also very important and 20 nm of metal surface roughness has been
achieved at Jet Propulsion Laboratory (JPL). The cost of building such modules is
prohibitively high and is greater than $25 K.
Since these are bulky and expensive
solutions, these are avoided at mm-wave frequencies and these solutions are used for
niche terahertz space or defense applications. In the following we will review a few
technologies which are used at mm-wave frequencies.
An elegant approach of interconnects was presented by Bridgewave in [100 ], as
shown in Fig. 6.2 (a) with 0.7 dB of insertion loss at 115 GHz for a 2.2 mm long
structure. Still there is uncertainty how low-cost this solution will be at mm-wave
frequencies. Another approach for packaging is using hot vias[101] as illustrated in Fig.
6.2 (b). This interconnect provides a low-inductance (20pH) interconnect from the front
to the back side of the chip and a loss of 0.5 dB per interconnect at 45 GHz has been
reported by Avago technologies. Yet, no product is available beyond 12 GHz and it has
yet to prove its viability at mm-wave frequencies. Another type of packaging is packages
with waveguide apertures [102] as illustrated in Fig. 6.2 (c). This technology has been
developed for low-cost plastic packaging where chips are embedded in plastic Quad-flat
no-lead (QFN) packages. A loss of 1.2 dB for a single transition has been reported at 77
GHz. It is still higher loss compared to the loss of other surface mount (SMT) and flipchip technologies.
84
Figure 6.2 (a) Micro-Coax based Packaging, (b) package using hot vias, and (c) package
using waveguide apertures
Embedded-wafer-level packaging (emWLP) and embedded-wafer-level ball-grid
array (emWLB), as illustrated in Figure 6.2, are attractive packaging technologies and are
gaining attention of researchers. emWLP solutions for semiconductor devices are used
where large I/O pins and high level of integration are desired [71-72,103-105].
The higher level of integration is achieved by thin film redistribution layers
(RDLs) and sometimes by thru silicon vias (TSVs). Bock et al. [106] demonstrated
emWLB packaging of 77 GHz automotive radar. Bock et al., [106] reports 0.4 dB/mm
insertion loss for transmission lines in emWLB package and 2 dB insertion loss for chipto-package-to-board transition, which is relatively higher than the loss of transmission
lines on organic substrates reported in [3]. Fisher et al. and Agethen et al. [107, 108],
demonstrated a 77 GHz antenna and 60 GHz industrial radar system in emWLP
technology, but they did not mention and model the loss of interconnection of antenna
with the chip pad.
85
Figure 6.3. Packaging interconnect technologies (a) embedded wafer level ball grid
array[107], (b) embedded wafer level package [109], (c) flip-chip [111], and (d) wire-bond
[110].
This kind of interconnection would also add some loss. For example, Li et al. [109]
presented a 77 GHz automotive radar using emWLP and TSV technology and reported a
loss of 1.6 dB for back to back test structure for the transferring channel. This technology
may be used in cases where mm-wave transitions from chip to printed wiring board
(PWB) are intended to be avoided, so that low frequency substrates like FR-4 can be
used. In such cases, the on-chip down conversion mixer should be included and the
antenna must be designed using RDLs. But, there may be some applications where offthe-shelf mm-wave ICs are used to build a mm-wave system. In such cases, the low cost
solution would be to use a direct-chip-attach (DCA) technology or wire-bond technology.
Additionally, because all off-the-shelf chips do not have up/down converters on the chip,
the package designers will have to use high frequency substrates. Therefore, the need to
use high frequency substrates in such cases cannot be avoided, and the design of chip-to86
package mm-wave transitions becomes critical and should be dealt with carefully for
optimal performance. Therefore, none of these technologies would replace the other in
the near future. emWLB along with wire-bond and direct chip attach (DCA)
technologies, both of which require mm-wave interconnects to the board, will be used
together depending upon the application.
As discussed above, when mm-wave interconnection are required, normally we
make use of wire-bonds and flip-chip, which are proven to be easy and effective with
relatively low loss [112-114]. Since wire-bonding is low cost and re-workable, therefore
it is the most commonly used technology. The integration of W-band transceivers with an
optimal arrangement of aluminum nitride, quartz, alumina and LTCC has been reported
in the past [115-116]. These integrations employed wire-bonding techniques, which tend
to be relatively narrow band and quite lossy, compared to flip-chip interconnects, at mmwave frequencies due to its large parasitics. Flip-chip technology addresses these issues
because of short interconnect length. Moreover, to achieve very fine-pitch traces down to
30 µm, using micro-vias and flip-chip technology, high density interconnects can be
realized on the package [111, 117]. Therefore, flip-chip is a preferable choice for highfrequency applications. Researchers have investigated flip-chip technology and reported
their findings in the literature.
Characterization of flip-chip interconnects has been presented in [118] on a
ceramic substrate and Beer et al. [119] have integrated a 122 GHz antenna with flip chip
interconnect. but this interconnect was made using a dummy chip made of LTCC on an
alumina substrate. On the foundations laid by [119], Sun et al. [120] presented a 120 GHz
frequency-modulated continuous-wave (FMCW) radar sensor that was flip-chip packaged
87
into a surface mountable package, where Tx/Rx antennas are situated on a thin polyimide
substrate.
The focus of the research work [103-109] and [119-120] was not the optimization
and modeling of flip-chip interconnects. However, Heinrich et al. in [118] discusses the
characterization of flip-chip interconnects with dummy CPW chips flipped on a ceramic
substrate up to 100 GHz only. Most of the aforementioned work has been carried out on
ceramic substrates. As discussed earlier, ceramic substrates like LTCC and HTCC
technologies have some limitations, and LCP has been identified as an excellent
microwave substrate, but LCP is less explored above 60 GHz. Therefore, we have chosen
LCP as a microwave substrate material to develop organically packaged modules and
components not only in K-, and W-band but to also explore the potential of using LCP up
to 170 GHz. Since emWLB technology requires special facilities, we will use wire-bond
and flip-chip interconnects for the integration of modules and characterized flip-chip
interconnect on an organic substrate for the first time up to 170 GHz.
The focus of the prior work, related to mm-wave packaging on LCP, was on the
development of LCP surface-mount package,[121] W-band compensated 90º bends for
CPW and microstrip lines [122], successful demonstration of W-Band antennas [123] and
60 GHz packaging solutions based on wire-bond technologies [61,124]. Only Patterson et
al. [125] presented a W-band flip-chip packaged power amplifier (PA) reporting 0.75 dB
per interconnect loss, but didn’t characterize the flip-chip interconnect and flip-chip
bonding process on organic substrates. Since LCP is a soft material, special care should
be taken during flip-chip bonding process.
88
The objective of this part of the Ph.D. dissertation was to design and develop mmwave modules from 20 GHz to 170 GHz on an organic LCP substrate and characterize
flip-chip interconnects to achieve high performance at higher frequencies. In this work,
we will demonstrate the integration of K-, and V-band modules on LCP using wire-bond
interconnects and the development of W-band modules using optimized flip-chip
interconnect technology. To optimize the wire-bond interconnect, a compensation
network has been used to reduce the interconnect loss. Since the high demand of data
rates, precision requirements of passive remote sensing and imaging radars, has pushed
the need to develop wireless systems at higher frequencies, the development and
characterization of high performance microwave substrate and mm-wave interconnect is
of utmost importance. As discussed before, at mm-wave frequencies, performance of
wire-bond is narrow band and relatively more lossy, flip-chip interconnect technology
has been used to develop D- band modules as the flip-chip has proven itself as the most
promising interconnect at higher frequencies and it also ensures a compact, low-loss, and
wide-band interconnect. Before using a microwave substrate in a certain frequency range,
it is important to characterize it first so that we get to know of its electrical properties. As
LCP has only been characterized up to 110 GHz, in this work LCP and transmission lines
have been characterized from 110 to 170 GHz. Characterization of a wide-band flip-chip
interconnect from DC to 170 GHz has not been reported before, especially on an organic
substrate. Therefore, we have also characterized a wide-band flip-chip interconnect (DC
to 170 GHz) on LCP, extracted RLC equivalent circuit model of the interconnect and
presented guidelines for the development of high-performance mm-wave modules on
organic LCP substrate.
89
CHAPTER VII
Development of K- and V-Band Modules on LCP
7.1 Low Phase Noise K-Band Oscillator on Organic LCP Substrate
Some work in the area of RF/microwave circuits related to antennas [126], RF
MEMS switches [127], and 3- D integration of RF and mm-wave modules for SOP
solutions [128] have been reported on LCP but work on oscillators and VCOs on organic
substrates has been reported only up to 10 GHz. A fully packaged 1.9 GHz negative
resistance VCO on LCP has been presented in [129]. In [130], the development of 9 GHz
VCO on Duroid was presented. To the best of our knowledge, 9 GHz [130] is the highest
frequency VCO or fixed frequency oscillator demonstration that has been explored on
organic materials. In this work, for the first time, we investigate the performance of a Kband oscillator on organic LCP substrate. This work paves the way for the development
of low cost oscillators and VCOs on organic materials for frequencies above 20 GHz.
The oscillator was designed using a /2 open circuited microstrip resonator
coupled with a microstrip line on LCP. The idea is to get a high Q resonator by avoiding
lossy passive components. From [131], it is known that the phase noise of oscillator
decreases with the increase in the Q of the resonator and power consumption of the
oscillator. Power consumption is limited by the system requirement so the physical
approach is to increase the Q of resonator. Fig. 7.1 (a) shows the layout of the resonator
coupled with microstrip line.The design has been performed in Agilent Momentum on 8
mil thick LCP. The length of the /2 microstrip resonator at 20 GHz is 189 mil and the
width of the coupled microstrip line is 20 mil. The gap between resonator and 50 ohm
microstrip line is 2 mil.
90
Simulation results show that the unloaded and loaded quality factors of the
resonator are 269 and 251, respectively. Because of loose coupling Q l and Qu are very
close to each other. Loaded and unloaded quality factors are defined in equations (1) and
(2). 𝑠21 (𝑓0 ) is the magnitude of s21 at the resonance frequency.
Figure 7.1: (a)Layout of /2 microstrip resonator coupled with microstrip line and (b)
simulated reflection coefficient of the resonator.
Fig. 7.1 (b) shows the simulated reflection coefficient of the loaded resonator
𝑄𝑙 =
𝑓0
(7.1)
∆𝑓3𝑑𝐵
𝑄𝑙
𝑄𝑢 = 1−𝑠
(7.2)
21 (𝑓0)
The S-parameters of a commercially available low noise pHEMT transistor
VMMK-1225 from Avago Technologies were calculated by using its ADS transistor
model available at the vendor’s website. The transistor is used in common source
configuration. A short circuit stub, having length and width of 79 mil and 20 mil,
respectively, is added at the source to provide feedback in order to make the transistor
unstable. The stub is connected to the ground through a via of 6 mil diameter and with a
pad width of 20 mil. The transistor was biased at Vds= 2 V and Ids= 20 mA.
91
The design method given in [132] was used to design the oscillator. The reflection
coefficient of the resonator, G, was calculated. Then the matching network was designed
to optimize the negative resistance at 20 GHz and make S 11.G = 1, which satisfies the
oscillation conditions; closed loop gain greater than or equal to 1 and a phase difference
equal to zero. Here S11 is the reflection coefficient looking into the transistor with the
output port terminated with L. Fig. 7.2 shows the block diagram of the one port
oscillator design. Fig. 7.3 shows the complete schematic of the circuit where the
matching circuit, microstrip line-to-CPW transition, /4 RF chokes, and resonator
coupled with microstrip line were simulated in Agilent Momentum and imported as
components in ADS schematic to simulate the complete oscillator. Figure 7.4 shows a
micrograph of the actual fabricated circuit.
When the conditions given in [131] needed to design the oscillator were met, a
harmonic balance (HB) simulation was run in Agilent ADS to confirm the oscillation
conditions and determine phase noise and output power.
An 8 mil LCP (Ultralam 3850 from Rogers Corporation) with 18 micron copper
on both sides was used as the starting substrate material. The laminated copper was
removed from both sides by etching with a dilute nitric acid. The sample was ablated
with a CO2 laser to form 10 and 20 mil diameter vias. The residual debris around the
inner walls of the vias was removed with acetone and isopropyl alcohol using an
ultrasonicator. The sample was then placed in a DC sputter chamber for copper
metallization with a 100 Angstrom Ti adhesion layer in between LCP and copper.
92
Figure 7.2. Block diagram of 1-port oscillator design.
Figure 7.3. Complete schematic of the circuit.
93
Figure 7.4. Micrograph of the fabricated circuit (dimensions in mm)
The sputtered copper thickness was about 5 micron on both sides of the LCP.
After sputtering, vias were examined under a microscope to ensure adequate
metallization thickness built up for front to back contact. The front side of the sample was
then patterned using a positive working photoresist. Upon completion of Cu and Ti
etching, vias were again tested for continuity. Transistor and the surface mount
components were manually assembled using a highly conductive and low temperature
curable (120oC) silver epoxy paste.
The total current consumption was 32 mA from a 5 V power supply with total dc
power consumption 160 mW. The oscillation frequency was measured to be 25.6 GHz.
As the feedback at the source of the transistor was provided by a short circuited stub with
a via to ground, this large offset in frequency is caused due to some additional inductance
of the via because of different fabricated via size and variation in the stub length. During
simulations, it was also observed that due to a slight change in the stub length the
oscillation frequency shifts. The designed stub length is 79 mil and the simulated
frequency was 20.1 GHz. Actual measurements of the stub length showed a 78 mil value
94
and 10.5 mil diameter of the via. Simulated results that account for different stub lengths
and via size are shown in Fig. 7.5. The red line corresponds to a length of 79 mil and 6mil
diameter of via and the blue to a length of 79 mil and 10.5 mil diameter of via. These
simulations indicate that the via diameters need to be better controlled for higher
accuracy in oscillator frequency. If not, the stub length can be adjusted to achieve the
original oscillation frequency.
20.1GHz
Figure 7.5. Simulation results for different lengths of short circuit stub and different
diameters of vias.
Fig. 7.6 also shows that the resonator reflection coefficient is low and has a very
sharp dip at its resonance frequency. For this reason, very accurate dimensions are
needed for getting exactly a 20 GHz oscillation frequency.
95
Figure 7.6. Simulated reflection coefficient of the resonator
The output power of the oscillator was measured to be -10 dBm which is 0.11
mW resulting in a conversion efficiency of 0.0625%.When the losses due to the cable and
the connectors of about 4 dB are taken into account then the output power is calculated to
be around -6 dBm (0.25 mW) and the conversion efficiency was calculated to be 0.15%.
This low conversion efficiency is due to the fact that the output matching network was
designed and optimized for 20 GHz operation but due to the offset in frequency, (the
causes of which are explained above), the maximum power was not transferred.
Figure 7.7 shows the measured output power of the oscillator. The measurements
were done using an Agilent spectrum analyzer E4446A.The phase noise of the oscillator
was measured to be -104 dBc/Hz and -108 dBc/Hz at 600 kHz and 1 MHz offset,
respectively. Fig. 7.8 shows the measured phase noise measurements of the oscillator
while Fig. 7.9 shows the simulated results using ADS. This phase noise is to the best of
96
our knowledge a state-of-the art result for organic-based oscillators operating above 20
GHz. Table 7.1 lists and compares the phase noise of other organic-based oscillators. The
difference between simulated and measured results of phase noise is because the actual
resistors may be noisier and the simulated output power reported is 3.48 dBm as
compared to -6 dBm for the measured output power. Lower output power also degrades
noise performance and that is what is observed in the measured results. The transistor
was also bonded using silver epoxy, not solder paste, and this may also have introduced
some additional noise and degraded the performance.
The phase noise can be reduced further by having a much higher bypass
capacitance to suppress power supply noise, using solder paste in proper quantity, and
flip-chip bonder for accurately placing the transistors and other components on pads.
Figure 7.7. Measured output power of oscillator.
97
Figure 7.8. Measured phase noise
Figure 7.9. Simulated phase noise.
98
Table-7.1
Comparison of Oscillators’ Phase Noise and Output Power
Technology & Reference
Frequency(GHz)
Phase Noise @offset
Oscillator Duroid [130]
9
-126@1 MHz
2.5
VCO LCP[129]
1.85-1.92
-118@600KHz
-
Oscillator LCP(This work)
25.6
-108@1MHz
0.25
7.2
Pout(mW)
Low Cost 60 GHz RF Front End Transceiver Integrated on Organic Substrate
Research and development for V–band (60-GHz) wireless personal area networks
(WPANs) for broadband and high-data-speed multimedia applications is an active
research area because of the 7 GHz of unlicensed spectrum that exists in many countries.
Significant progress has been made in the development of individual circuits and passive
components. However, very few papers have been reported regarding the integration and
packaging of a whole transceiver front-end, especially on organic substrate like LCP.
Previous efforts have been made towards developing antenna-in-package solutions [133].
In [134], authors reported the design of a modulator and demodulator at 60 GHz on LCP
and in [135] authors present a phased array transmitter at 60 GHz with a chip, packaged
in an organic BGA package. In this work, for the first time, we demonstrate the
integration of a 60 GHz RF front end Tx/Rx array on organic Liquid Crystal Polymer
substrate with GaAs RF chips.
7.2.1 Antenna Design
The 60 GHz Yagi-Uda 1X4 antenna is designed on liquid crystal polymer (LCP)
substrate. The topology of a single-element of the array is designed keeping in view all
99
design guidelines for Yagi-Uda antenna explained in Chapter 5. A driven dipole and three
directors are patterned on the top side of a 200 µm thick LCP substrate. As it is shown in
Figure 7.10, a truncated microstrip ground plane is patterned on the bottom side, and this
acts as a pseudo-reflector for the quasi-Yagi antenna. The driven dipole is fed with a
coplanar strip (CPS) line, which carries a TE0 surface wave mode. A 180º phase shift,
introduced between the two balanced ports of a microstrip balun, ensures that only the
coupled microstrip odd mode is excited at the output of the balun (or input of the CPS
line). An array is formed using a corporate feed network as shown in Fig. 7.10. The
simulated gain of the antenna at 60 GHz is 12.1 dBi.
Fig. 7.11 shows the block diagram of the Tx/Rx module implemented in this
paper. The receiver is implemented by connecting the Yagi-Uda array to a Hittite low
noise amplifier (LNA) HMC ALH-382 through a Hittite single pole double throw
(SPDT) switch HMC SDD-112. The transmitter is implemented by connecting the YagiUda array to a Hittite power amplifier HMC ABH-209 through the Hittite single pole
double throw (SPDT) switch HMC SDD-112.
Figure 7.10. 60 GHz 4×1 Yagi-Uda array layout
100
The chips are wire-bondable and require a backside ground connection.
Therefore, the embedded cavity was ablated all the way to the backside metallization so
that there would be a common RF and DC ground. The dimensions of the cavity were
minimized to reduce wire-bond lengths and, thus, the inductive packaging effects which
degrade the return loss. The packaged solution is shown in Fig. 7.12 (b).
The antenna, the feed network and wire-bond transitions to and from the MMIC
were designed and optimized in Ansoft HFSS, taking into account any parasitic
packaging effects. These were simulated by mimicking a 50 Ω microstrip line on a GaAs
substrate, which was integrated to the array. To minimize the effects of the bond-wire
inductance, a 12.5 x 50 µm ribbon was used to make the chip-to-chip and chip-tosubstrate connections. The longest ribbon length was measured to be 575 µm. During
simulations, it was found that even using a 12.5 x 50 µm ribbon degrades S11
significantly. To minimize the inductive effect of the wire-bonds, a 20 µm wide and 250
µm long capacitive stubs, as shown in Fig. 7.13, were used. These stubs improved the
reflection coefficient by 18 dB at 60 GHz as is evident from Fig. 7.14.
7.2.2 Fabrication
A double copper cladded, 200 µm, 3850 LCP sheet from Rogers Corporation is
used for the transceiver integration. Precise alignment holes along with ground vias were
drilled using a KrF 248 nm excimer laser. Vias were filled by sputtering 9 µm of copper.
A mask specifically developed to protect the filled vias was used, and copper was etched
off elsewhere. Since there are wire-bond adhesion issues to the copper, the samples were
gold electroplated for 7 µm to ensure that gold ribbons will stick on to the gold.
101
Figure 7.11. Block diagram of the Tx/Rx module.
Figure 7.12. (a) Layout of the proposed package solution for the 60 GHz Tx/Rx module, (b)
Fabricated and assembled Tx/Rx module.
102
Capacitive
Stub
Figure 7.13. Fabricated capacitive stub to nullify the effect of ribbon inductance
Before gold plating, a seed layer of 150Ao Ti/0.25 µm Au was created by
evaporating Titanium to ensure good gold adhesion on LCP. Next, the feeding
transmission lines were patterned on the top of the substrate using standard
photolithography. Afterwards, gold and titanium etchants were used to etch the gold and
titanium. After patterning was completed, a KrFl 248-nm excimer laser was used to
ablate the cavity for the chip.
Figure 7.14. Simulated return loss results with and without the capacitive stub.
103
A 200 µm deep cavity was created in the polymer all the way down to the 18 µm
Cu back-side metallization, which works as the excimer laser stop layer. The laser cutting
leaves behind some carbonized LCP residue in a small region around the cavity. This was
first removed using acetone and isopropyl alcohol, and then oxygen plasma was used to
remove this thin residue. Next, chip capacitors and resistors were manually placed with a
special high temperature inorganic conductive silver paste. Since the chip height was 100
µm and a 200 µm cavity had to be drilled to ensure that we have common RF and DC
ground, a 100 µm thick, low temperature curable epoxy film adhesive ESP8660-WL
from AI Technology Inc. was used to raise the chip up to 100 µm so that the top of the
chip is coplanar with the surface of the substrate. The fabricated and assembled Tx/Rx
module is shown in Fig.7.12 (b).
The wire bonds were performed with a West.Bond wedge wire-bonder with 12.5
x 50 µm wide ribbon. The maximum length of the RF wire-bond was measured to be 575
µm and the rest were less than 250 µm. A wedge bonder was ideal for this application
since it is capable of creating a nearly flat wire from pad to pad. In addition, the wedge
bonder creates a “cool bond” by using ultrasonic energy to fuse the contact points.
7.2.3 Measurements and Results
The reflection coefficient of the active antenna array was measured and is shown
in Fig. 7.15. The radiation pattern and gain of the Tx/Rx module were measured at 60
GHz in an anechoic chamber. Two 25 dBi gain horn antennas were initially used to
calibrate the system. For the tests, an Agilent PNA was used with a QuinStar LNA and a
25 dBi gain horn. The LNA was biased at 5 V drawing 64 mA, and the PA was biased at
5 V drawing 40 mA with Vg = + 0.23 V.
104
The measured peak gain of the receiver was found by scanning the H-plane by
turning the LNA ON, and the control voltages “CNTRA” and “CNTRB” of the SPDT
switch were set such that there is an RF path from RFin to RFout1, where the LNA is wirebonded with the SPDT switch. To measure the peak gain of transmitter, the SPDT switch
was set such that there is an RF path from RFout2 to RFin.. The PA is turned ON and the
radiation pattern of transmitter is measured. The angle theta is perpendicular to the plane
where the antenna elements are printed as shown in Fig. 7.10. The peak gain of receiver
and transmitter were measured to be 31.8 dB and 21.6 dB, respectively, and are shown in
Fig. 7.16 (a) and (b). The LNA was consuming 160 mW of DC power. The simulated
gain of the passive antenna is 12.1 dBi and the typical gain of Hittite LNA is 21 dB,
which by adding both gives a total gain of 33.1 dB. The measured gain of 31.8 dB is very
close to the theoretical gain value. A total gain of 21.6 dB is measured for the transmitter,
which is 3.5 dB less than the theoretical gain, assuming a typical gain for the PA of 13 dB
from the manufacturer data sheet. The 1.3 dB loss in the Rx gain and 3.4 dB loss in Tx
gain can be attributed to lossy bond-wire transitions and the difference between the actual
gain and the typical gain specified. Table 7.2 summarizes the results. The transmitter has
a greater loss because of the longer bond-wire transitions (575 µm). The gain vs
frequency plot of transmitter and receiver is shown in Fig. 7.16 (b) where an almost
constant gain can be seen from 55-63 GHz.
105
Figure 7.15. Measured S11 of active antenna array
Table.7.2
Tx/Rx Total Gain Calculation
Tx/Rx
SPDT Loss
Wirebond
Loss
Act.
Gain
Pass
Gain
Est.
Gain
Meas. Tot.
Gain
Tx
1
3.5
13
12.1
25.1
21.6
Rx
1
1.3
21
12.1
33.1
31.8
Figure 7.16. (a) Receiver side H-plane Co-polarization at 59 and 61 GHz,transmitter side Hplane co-polarization at 60 GHz, Hcr polarization at 59 GHz and simulated H-plane 60 GHz
passive antenna, (b) measured Tx/Rx gain vs frequency plot from 55 to 65 GHz.
106
CHAPTER VIII
Development of W-Band Modules on LCP
Recent examples from the literature have demonstrated low-cost integrated ICs in
silicon technologies (SiGe HBTs and CMOS) operational up to D-band frequencies [3].
While these results are very important for the cost reduction of these systems, packaging
of these ICs is equally important. A light-weight, miniaturized packaging solution for
low-cost millimeter-wave ICs is therefore highly desired. The focus of the prior work,
related to mm-wave packaging on LCP, was on W-band compensated 90º bends for CPW
and microstrip lines [122], successful demonstration of W-Band antennas [123,136] and
packaging solutions based on flip-chip and wire-bond technologies [125,137]. Patterson
et al. [125] presented an encapsulated package in [125] but because of via interconnects,
this encapsulation adds 0.15 dB of loss per flip-chip-interconnect. Moreover, an RLC
equivalent circuit model of the interconnect and parameters that affect the performance of
the interconnect were also not discussed. The focus of this work is to investigate,
characterize and model a W-band flip-chip transition on a low-loss organic LCP substrate
and present guidelines to optimally design the flip-chip transition. To the best of the
authors’ knowledge, characterization and RLC modeling of a W-band flip-chip transition
on organic substrate have not been reported before. First we present the packaging of a
W-band SiGe LNA, then we present the measured return loss, radiation patterns and gain
of a W-Band module in which an antenna is integrated with the packaged LNA. The
measurements are in excellent agreement with the simulated results, which confirms the
validity of the interconnect model and characterization of the flip-chip interconnect.
107
8.1 LNA Design:
In this section, we describe a custom designed 0.13 μm SiGe BiCMOS LNA. The
LNA consists of four stages of single-ended common-emitter amplifiers, and provides
17.2 dB gain and less than 7 dB noise figure (NF) at 94 GHz by on-wafer measurements.
Second, we present low-cost, simple, and low-loss flip-chip packaging technique realized
on a flexible, light-weight LCP substrate material.
Figure 8.1 Circuit schematic of the designed LNA
The SiGe BiCMOS LNA is realized in IHP’s 0.13µm SG13S technology. The
technology features HBTs with fT / fmas of 250 / 300 GHz, and seven metallization layers
with two thick top metals (2 and 3 µm thick). The circuit schematic of the designed LNA
is displayed in Fig. 8.1. The LNA consists of four single-ended common-emitter
amplifiers. The input, output and inter-stage networks are realized using thin-filmmicrostrip lines (TFMSLs). The transmission lines have a dielectric (SiO 2) height of 9.83
μm. The device dimensions and the bias currents are optimized for simultaneous noise
and power matching at the input. Consequently, devices with three emitter fingers are
chosen that provide an optimum noise source reflection coefficient close to 50 Ω. For this
108
multiple stage design, RC low-pass networks are included in the bias network to prevent
inter-stage leakage. The design is unconditionally stable, and provides broadband
performance, simultaneous power and noise matching, and consequently low noise
figure.
8.2
Flip-chip Package Design
The flip chip package design was simulated in Ansys high frequency structure
simulator (HFSS) The HFSS model is shown in Figure 8.2 (a). Chip to Package transition
was designed by putting gold bumps on chip and flipping the chip on the substrate as
seen in Figure 8.2 (a) and 8.3 (a). In Fig. 8.2 (a), the bottom and top structures are the
models of a package substrate and a SiGe chip respectively. The chip was modeled by a
50Ω microstrip line on a SiO2/Si substrate stack-up with a thickness of 9.83 μm and 300
μm, respectively. This configuration was chosen to resemble the technology parameters
of the SiGe integrated circuit. The microstrip line is terminated with a GSG pad. The
dimensions of the microstrip line and the GSG pads for chip-model are tabulated in
Table. 8.1.
Fig. 8.2. (a) Flip-chip transition model (b) cross section of flip-chip when only substrate is
extended (c) cross section of flip chip when pad size is increased.
109
Figure 8.3: (a) Cross sectional view of the package (b) Top View of the module for
packaged LNA
Table 8.1
Antenna Design and Chip-Model Parameters
Dimensions (mm)
dir_l
1.1
s
0.1
qw_l
0.5
strip_w
0.02
qw_w
0.1
c_sig_w
0.070
50_w
0.12
c_sig_l
0.070
drv_l
0.74
c_sig_gap
0.020
bal_l
0.5
p_sig_w
0.1
bal_g
0.1
p_sig_g
0.025
The thickness of the package substrate should be selected after careful
consideration. There are three main factors that dictate the selection of the thickness of
the package substrate: First, appropriate size of the width of a signal line; second, the
smallest feature that can be reliably manufactured with the standard printed circuit board
(PCB) manufacturing process; and third, the pitch of GSG pads and GSG-pad dimensions
110
on a chip. As depicted in Fig. 8.2(a) and tabulated in Table I, the RF-signal-pad width
and the ground-signal gap of GSG pads on the chip are70 μm and 20 μm respectively. In
order for the gold bumps to land easily and accurately on the package-GSG pads, the
CPW-GSG pitch on the package was chosen to be 75 μm. For a 50 Ω CB-CPW
(conductor-backed co-planar waveguide) line, if a 100 μm thick substrate is chosen, the
width and the signal-ground spacing of a 50 Ω CB-CPW-signal line will be 150 μm and
25 μm, respectively. With these dimensions, it would be difficult for the bumps on the
ground pads of the chip to land at correct spots on the package. Therefore a 50μm thick
LCP was chosen. This results in a CB-CPW line with a width and gap of 100 μm and
25μm, respectively. Moreover, as explained in [96], the metal below the chip affects the
electrical characteristics of on-chip elements, especially the characteristics of
transmission lines. Thus, in order to avoid any detuning effects, the metal trace
immediately below the chip was removed from the top and back side of the LCP
substrate.
As seen from Figure 8.3 (b), vias were required for the conductor backed CPW
lines and to tie the RF and DC grounds. A via diameter of 50μm was used to
accommodate a 1:1 aspect ratio for laser drilling. The chip-to-package transitions that
include Au bumps and via- interconnects were modeled in HFSS as illustrated in Figure
8.2 (a). As shown in Figure 8.2 (a), the transition was designed from the on-chip
microstrip line to the CPW line on the package, using gold bumps. The optimized
transition has 0.47dB of loss per interconnect and reflections less than 15 dB throughout
W-band as illustrated in Fig. 8.4.
111
Figure 8.4. Simulated S-parameters for flip-chip transition with 50 Ω GSG pads on the
input and output of the chip model. The insertion loss includes the loss of the CPW line on
the package
To accurately estimate the flip-chip transition loss, the SiGe chip should be
modeled carefully. The signal-pad size (c_sig_w and c_sig_l) on the chip is 70 μm x70
μm and the gap between signal and ground pad (c_sig_gap) is 20 μm. The chip is
modeled with actual GSG pad dimensions at the input and output. The model was
optimized such that the input and output impedance is 50 Ω. For this investigation,
strip_w = 20 μm with 70 μm x70 μm GSG pads provides 50 Ω impedance. In Fig. 8.4,
the simulations of the complete transition including SiGe chip-model and the CPW line
on the organic substrate is displayed. The estimated transition loss per interconnect is
0.47dB, while 0.2 dB is associated with the flip-chip transition loss and 0.27 dB is
associated with the loss of transmission lines both on the package (0.1 dB) and the chip
model (0.17 dB).
The diameter and height of the gold stud bumps, used in the model, are 50 µm
and 40µm respectively. The reference plane for the measurements presented in Fig. 8.2 is
at the edge of the CPW lines as shown in the simplified model of flip-chip in Fig. 8.2.
112
To investigate the effect of each parameter on the performance of the
interconnect, we ran a set of simulations by varying the parameters—height of the gold
bump (bump_h), radius of the gold bump (bump_rad), substrate extension under the chip
(sub_ext) and bump-pad extension on the substrate (pad_ext) under the chip— which
affect the performance of the flip-chip interconnect. The findings are shown in Fig. 8.5
thru Fig. 8.10. The results show that pad_ext, bump_rad, and bump_h are the three most
important parameters that affect the characteristics of the flip-chip interconnect.
However, the “sub_ext” parameter has negligible effect on the performance. Fig. 8.5 and
Fig. 8.6 demonstrate the dependence of the flip-chip transition performance on sub_ext
and pad_ext parameters respectively.
For simulations, pad length “lp” was assumed to be 70 µm and the “pad_ext”
variable was swept to observe the change in the response.
Figure 8.5. Sweeping the parameter sub_ext (a) S 11 (b) S21 while bump_rad= 25 µm and
bump_h =40 µm and pad_ext= 30 µm are kept constant.
113
Figure 8.6. Sweeping the parameter pad_ext (a) S 11 (b) S21 while bump_rad= 25 µm and
bump_h =40 µm and sub_ext =30 µm are kept constant.
After studying the results in Fig. 8.5 and Fig. 8.6, we conclude that if metal is
removed under the chip and only the substrate is extended, the good interconnect
performance is preserved. If the metal is also extended under the chip, by increasing the
bump-pad size on the package substrate, the return loss and the insertion loss starts
degrading. Therefore, the pad size on the package should be made as small as possible. In
other words, the overlap between the chip and the package pads should be small and this
can be achieved by careful package layout design and making sure that the bump lands
on the pads close to the edge. This will reduce the capacitance that is caused by the stackup of the chip and the package substrate in the bump section. For this reason, the metal
under the chip should be removed for better performance.
The effect of another important parameter, bump_rad, is presented in Fig. 8.7. It is
apparent from the results that the increase in the radius of the bump deteriorates the S11
114
and S21 of the flip-chip interconnect. Therefore, the diameter of the bump should be
made smaller for optimum performance.
Figure 8.7. Sweeping the parameter bump_rad (a) S 11 (b) S21 while pad_ext= 30 µm,
bump_h =40 µm, and sub_ext =30 µm are kept constant.
Fig. 8.8 and Fig. 8.9 present the results for the case when the parameter bump_rad is
swept from 15 µm to 30 µm. After examining the results in Fig. 8.8 and Fig. 8.9, we
determined that the bump height also needs to be optimized to avoid detuning and
capacitive effect caused by very small values and inductive effect with very large values.
The parameter, “bump_h”, was swept from 10 µm to 100 µm. As the capacitance
due to chip-loading decreases when bump_rad increases from 10 µm to 60 µm, we can
observe that the response of S21 and S11 improves until 60 µm. The best performance is
achieved when bump_rad = 60 µm. Beyond 60 µm, the inductive effect takes over and
the performance again starts degrading. One good way to visualize this capacitiveinductive effect is to plot S11 on Smith chart. This effect is presented in Fig. 8.9.
115
Figure 8.8. Sweeping the parameter bump_h (a) S 11 (b) S21 while bump_rad= 25 µm, sub_ext
=30 µm, and pad_ext= 30 µm are kept constant.
Figure 8.9. Smith chart showing inductive and capacitive behavior by varying the
parameter bump_h while bump_rad= 25 µm, sub_ext =30 µm, and pad_ext= 30 µm
Another way to analyze the effect of bump parameters is to plot S21 against the
dimensions of the parameters. Plots of the insertion loss vs dimensions of the parameters
are shown in Fig. 8.10. Red, blue, green and magenta colored curves, in Fig. 8.10,
indicate the effect of increase in the pad-size (pad_ext) from 0 to 60 µm, substrate
extension (sub_ext) from 0 to 0.3mm, height of the bump (bump_h) from 0 to 100 µm,
and radius of the bump (bump_rad) from 15 µm to 30 µm respectively. The solid and
116
dashed lines show response at 94 GHz and 110 GHz respectively. “pad_ext _0 µm = lp=
70µm” is the reference for pad_extension as shown in Fig. 8.2 (b). When only the
substrate is extended, there is no significant change in S 21 and S11 as expected, but an
increase in the size of the pad degrades the response. One can also observe the transition
from capacitive to inductive effect, at around 60 µm, which is shown in green curves.
Figure 8.10. Simulated S-parameters results for optimization of flip-chip parameters: bump
height, bump_rad and pad size. Insertion loss vs dimensions of parameters at 94 GHz and
110 GHz are shown
After, having performed the full-wave EM simulations for flip-chip interconnects
using Ansoft’s HFSS, RLC model of flip-chip transition was extracted. Agilent advanced
design system (ADS) was used to tune the lumped elements to correlate the EM
simulated results with the model simulated results. Fig. 8.11 displays HFSS and
equivalent RLC models for the flip-chip interconnect. In the model, C denotes the
discontinuity at the LCP-CPW line and GSG pads on SiGe chip. L and R in the model are
because of the skin effect and ohmic loss present in the interconnect. The EM-simulated
and model-simulated S-parameter results are shown in Fig. 8.12, which match closely
117
with the EM-simulated results, from 75 to 110 GHz.
Figure 8.11. (a) Simplified HFSS flip-chip model (b) Extracted RLC Equivalent Model
Figure 8.12. S21 and S11 correlation between HFSS and RLC flip-chip equivalent model
A set of simulations were run to see the effect of “bump_h” parameter on RLC equivalent
model. Values of R, L, and C are tabulated in Table 8.2 and against different values of
height of the bump. The data are plotted in Fig. 8.13. The results presented in Fig. 8.8,
8.9 and Fig. 8.13 confirm that with small values of “bump_h”, the capacitive dielectric
loading effect is more pronounced and the inductive behavior takes over as the bump
height increases.
118
Figure 8.13. S21 and S11 correlation between HFSS and RLC flip-chip equivalent model
Table 8.2
RLC values vs bump_h for interconnect eq. model
8.3
bump_h
(µm)
R
L
C
(Ω)
(pH)
(fF)
10
0.7
20
12.2
30
0.9
30
10.6
50
1.09
36
9.9
60
1.19
38
9.6
90
1.6
48
9
100
1.8
52
8.6
Antenna Design
End-fire antennas, such as the tapered slot antennas (TSA) and quasi-Yagi planar
antennas, are considered to address the need for highly directional radiation patterns.
Although significant effort has been expended to reduce the size of the TSA, the overall
length of the antenna is still about 4 λ0. Therefore, it occupies a lot of space on the
119
substrate. Large antennas are not appropriate for W-Band systems, which take advantage
of the small wavelength (~ 3 mm in free space) to maintain an overall small form factor.
Recently, Khan et al. [136] presented a W-Band end-fire TSA antenna with an overall
size of 5.9 mm x 4 mm, which is almost 2 λ0 long. However, a single element Yagi-Uda
antenna can be realized within a space of λ0/2 x λ0/2. In the past, Deal et al. [138] and
Grajek et al. [139] demonstrated Yagi-Uda antennas at X-Band and Ku-Band
frequencies. Amadjikpe et al. [140] and Khan et al. [141] successfully presented 60 GHz
transceiver module using 1x4 element Yagi-Uda array. The size of the complete module
we present in this paper is smaller than the TSA antenna presented in [136]. For the
afore-mentioned reasons, the quasi-Yagi planar antenna shown in Fig. 8.14 has been
chosen for this paper to reduce the overall size of complete module (3 mm x 1.9 mm).
For this work, we designed a 94 GHz Yagi-Uda 1x1 antenna on LCP substrate.
The complete design guidelines can be found in the antenna design section of chapter 5
of this dissertation. However, a few design considerations are briefly discussed below to
keep the discussion cohesive and self-contained.
The initial dimensions of the antenna are obtained from tables for maximum
directivity in air using one director, one reflector, and cylindrical-wire elements with a
diameter d , and 𝑑⁄𝜆 = 0.0065 [64]. The equivalent width of each element is obtained
using w = 2d, which maps the diameter of a cylindrical dipole to a flat strip with nearzero thickness. This results in an element width of 0.04 mm at 94 GHz. The dimensions
are then scaled to compensate for the LCP substrate. LCP has an 𝜺r = 3 and a
transmission line on LCP has an 𝜺eff = 2.4. Therefore, Yagi-Uda elements are scaled by
1
√2.4
= 0.65 to obtain the correct resonance frequency.
120
Fig. 8.14. Yagi-Uda antenna design parameters
The designed antenna consists of a driven dipole and one director, which are on
the top side of a 50 µm thick LCP substrate. As it is shown in Fig. 8.14, a truncated
microstrip ground plane is on the bottom side, which acts as a pseudo-reflector for the
quasi-Yagi antenna. The driven dipole is fed with a coplanar strip (CPS) line, which
carries a TE0 surface wave mode. A 180º phase shift, introduced between the two
balanced ports of a microstrip balun, ensures that only the coupled microstrip odd mode
is excited at the output of the balun (or input of the CPS line). The impedance at the input
of the balun was simulated to be 64 Ω. This input impedance is affected by the spacing of
the meander line gap “bal_g” and the distance “s” from the meander line of the balun to
the pseudo-reflector. A quarter-wavelength transformer of 57 Ω was used to transform
this input impedance to 50 Ω at the un-balanced port of the balun. A microstrip-to-cpw
transition was then designed to integrate the antenna with the LNA. The dimensions of
antenna design parameters are tabulated in Table 8.1.
8.4
Fabrication of Packaged LNA and Receive Module
Fabrication of the flip chip bonded module was performed in a clean room
environment. First of all, copper was removed from both sides of the 50 μm LCP for via
121
drilling. The LCP was cleaned using Plasma Therm RIE and then 1 μm of copper was
sputtered on both sides.The copper thickness was dictated by the minimum feature size of
25μm to avoid over-etching. A Karl Suss MA-6 mask aligner was used to pattern the top
side of the module. The fabricated top metal layer is shown in Fig. 8.15 (a).
Figure 8.15: (a) Fabricated Sample and (b) measurement in progress after assembly
The chips were gold bumped by keeping the chip on wafer chuck at 100C o. The
height and diameter of the gold bumps were 40μm and 50μm respectively. Although the
simulation results from Fig. 8.7 thru Fig. 8.9 suggest using the smallest possible bump
diameter and bump height of 60 µm for optimum performance, due to available
equipment limitations, bumps with 40 µm of height and 50 µm of diameter could be
placed reliably. The reason being the bumps were put by a ball bonder that leaves a tail
after bonding the bump on the pads. In order to make the height of all gold bumps the
same, gold bumps were coined, which makes the bump height 40 µm. The diameter of
the gold-stud bumps was limited by the diameter of the capillary of the ball bonder. In
the end, gold bumped chips as shown in and 8.16 (c) were flip-chipped on the package
and finally measurements were taken as shown in 8.18 and Fig. 8.21-8.23. The chips
were bonded to this layer using a silver epoxy (σc = 2.5x106 S/m) to adhere the Au stud
122
bumps to the pads on package. Silver epoxy was also modeled as part of package
transition to check its compatibility with Au bumps and its effect on RF performance.
Almost no effect on RF performance was observed. FineTech sub-micron flip-chip
bonder was used for flipping the chip on the package. During flip chip bonding, the chip
holding module and sample holder were kept at 120 ºC and 110 ºC respectively. The
packaged LNA is shown in Fig. 8.15 (b) and size of the packaged LNA was 1.5 x 1.45
mm2.
Fig. 8.16. (a) Yagi-Uda Antenna (b) SiGe LNA (c) Gold bumped SiGe LNA (d) Fabricated
and assembled Rx module.
The passive end-fire Yagi-Uda antenna, the SiGe BiCMOS LNA chip with and
without gold bumps and the final receive module are shown in Fig. 8.16 (a), Fig. 8.16 (b),
Fig. 8.16 (c), and Fig. 8.16 (d) respectively.
8.5
Results and Measurements of Packaged LNA
Measurements of packaged LNA were taken using an Agilent 8510XF VNA with
150 µm pitch GSG probe using SOLT calibration. A plot of the measured on-chip and
packaged s-parameters is shown in Fig. 8.17(a). The results show that the package adds
1.3 dB of loss in the peak gain. The packaged gain curve matches well with the on-wafer
gain curve. Measurements show that the packaged LNA achieves 15.9 dB gain at 94 GHz
123
as compared to 17.2dB of on-wafer measured gain with 1.2 V DC supply, drawing 20
mA with a total power consumption of 24 mW. The total loss of 1.3 dB at 94 GHz
translates into a 0.65dB loss per interconnect, which to the best of author’s knowledge is
the lowest loss for standard flip chip package in the W-band. The return loss of the
packaged LNA was slightly shifted at both ports as expected due to the bumping effect.
The on-wafer noise figure was measured to be 7 dB as displayed in Figure 8.17
(b), which is the lowest noise figure reported in similar technologies at room temperature.
Assuming 7 dB on-wafer NF and using the NF formula for a cascaded system as given in
equation (8.1), the packaged noise figure can be estimated to be 7.7 dB. Figure 8.17(b)
also shows measured noise figure of the packaged LNA. The lowest noise figure value
(8.17dB) was measured at 95 GHz. This measured value is very close to the calculated
NF value of 7.7dB.
Figure 8.17: (a) On-chip and Packaged LNA gain and return loss measurement (on- chip
and packaged S12 are omitted and (b) on-chip and packaged measured noise figure of LNA
124
8.6
Results and Measurements of W-Band packaged receive module
The chip was biased at 1.2 V drawing 16 mA with total DC- power consumption
of 19.2 mW. Return loss measurements were taken using an Anritsu 37397 D Vector
Network Analyzer. Anritsu 3742A-EW transmission reflection modules and Anritsu
3738A broad band test set were used to extend the frequency to 110 GHz. Simulated and
measured return loss and gain plots are shown in Fig. 8.18. The 10 dB return loss
bandwidth for passive and active antennas is 10 GHz or 11%. The measurements match
well with the simulated results.
Figure 8.18. Measured and simulated reflection coefficient and gain of the passive antenna
and the active receive module
To calibrate the system for taking radiation pattern measurements, two 16 dBi
standard horn antennas were used and the gain-comparison method was employed to take
radiation pattern measurements. A 15 dB gain Quinstar LNA was used to increase the
dynamic range, and an Agilent harmonic mixer was used to down-covert the W-band
signal to IF. Fig. 8.19 illustrates the block diagram of the measurement setup for the
radiation pattern measurements. A 250 µm pitch GSG probe was used to probe the
sample.
125
Figure 8.19. Block diagram of the measurement setup for radiation pattern measurement
The far-field radiation patterns were measured in an anechoic chamber. Using the
largest dimension of the horn, D = 8 mm, the minimum distance for the far-field setup
was calculated to be 38 mm. For measurements, the transmitting horn antenna was placed
at 152 mm from the antenna under test (AUT) to make sure that measurements are taken
in far-field of the antenna.
Simulated and measured gain curves are shown in Fig. 8.18. The estimated active
gain was obtained by adding the measured gain of antenna and the LNA. It is evident
from the results presented in Fig. 8.18 that the measured gain is in good agreement with
the simulated/estimated results from 86 to 96 GHz and varies minimally by less than a 1
dB. The passive and active peak gain values are 5.2dBi at 90 GHz and 21.2 dBi at 93
GHz respectively. The 3 GHz frequency shift in the peak gain is due to a slight difference
in the peak gain of the passive antenna and the LNA. The active receive module
demonstrates 16 dB of added gain at 93 GHz. On-chip LNA gain was measured to be
17.2 dB as was reported in [23]. Therefore, the loss per flip-chip interconnect is estimated
to be 0.6 dB, which includes CPW-line loss as well.
126
Simulated and measured E- and H- plane and cross-pol radiation patterns for the
passive antenna are shown in Fig. 8.20. The cross-pol pattern is below 15 dB from Hplane Co-pol pattern which indicates good linear polarization of the antenna. The H- and
E-plane radiations pattern measurements for the active module at 87 GHz, 90 GHz and
94 GHz are presented in Fig. 8.21 and Fig. 8.22. All of the measured patterns correlate
well with the simulated results.
Figure 8.20. Simulated and measured E- and H-plane radiation patterns of passive
antenna.
To analyze the noise performance of the active antenna, the noise figure of the
system and figure-of-merit “G/T” were calculated. The G/T and system noise figure can
be calculated by using equation (8.2) and (8.3) as explained in [31]. With g = 16 dB, F =7
dB, Lf = 0.5 dB, To = 290 K, Lc = 0.2 dB, D A = 21.4 dB and Ti = 290 K, System Noise
Figure (NF) and Figure-of-Merit G/T were calculated to be 8.2 dB and G/T = -11.8 dB/K
respectively.
127
𝐺
𝐷𝐴
=
𝑇
𝑇𝑖 + 𝑇0 (𝑁𝐹 − 1)
𝑁𝐹 = 𝐿𝑓 𝐹 − 𝐿𝑓 /𝑔 + 𝐿𝑓 𝐿𝑐 /𝑔
(8.2)
(8.3)
Figure 8.21. Simulated and Measured H- plane radiation patterns of passive of active
module.
Figure 8.22. Simulated and measured E-plane radiation patterns of active module.
128
8.7
Recommended Guidelines
Recommended guidelines to properly model a chip and optimize the flip-chip
interconnect are given below.

To estimate the accurate flip-chip-transition loss, the chip should be modeled
carefully; the GSG pad sizes and gap between signal and ground should be chosen
such that the input and output impedance on the chip GSG pads is 50 Ω

The metal under the chip should be removed to avoid any detuning effect.

The simulation results show that pad_ext, bump_rad, and bump_h are the three most
important parameters that affect the performance of flip-chip interconnect in terms of
return loss and insertion loss while sub_ext parameter has negligible effect on the
performance

The overlap between the chip and the package-pads should be small and this can be
achieved by careful package-layout-design and making sure that the bump lands on
the package-pad close to the edge.

The diameter of the bump should be made smaller for optimum performance.

The bump height also needs to be optimized to avoid detuning and capacitive effect
with very small values and inductive effect with very large values.
129
CHAPTER IX
Development of D-Band Modules on LCP
In this chapter of the dissertation, we will first present the D-band indoor path loss
measurements, and then the characterization of coplanar waveguide (CPW), microstrip
and flip-chip transition on LCP. We will also present the fabrication process using which
such high frequency structures were developed.
9.1
D-Band Indoor Path-loss Measurements
Ultra-wideband wireless communication systems are expected to help satisfy the
ever growing need for smaller devices that can offer higher speed wireless
communication anywhere and anytime. In the past years, it has become obvious that
wireless data rates exceeding 10 Gbit/s will be required in several years from now [142].
The 60 GHz of spectrum from 110 to 170 GHz (D-band) offers a promising approach to
provide sufficient bandwidth required for ultra-fast and ultra-wideband data
transmissions [143]. This frequency band is ideally suited for short and medium range
communications [143] with much lower atmospheric attenuation levels than those present
in the now popular 60 GHz band. This large bandwidth paired with higher speed wireless
links has potential applications in precision positioning and velocity sensors [144],
passive mm-wave cameras [145] and can open the door to a large number of novel
applications such as ultra-high-speed pico-cell cellular links, wireless short-range
communications, and on-body communication for health monitoring systems.
To enable future D-band wireless communications, it is imperative to understand
propagation mechanisms that govern communication in D-band frequency range. As a
first step in that direction, this paper presents path loss measurements
130
9.1.1 Measurement Setup
The measurement setup consists of the E8361C PNA vector network analyzer
(VNA) with OML test heads (V06VNA2-T/R-A) capable of measuring 110-170 GHz
frequency range and the transmit and receive horn antennas with gain of 23 dBi at 140
GHz. Both antennas are vertically polarized and mounted about 25cm above the ground.
The theoretical half power beam-widths (HPBW) are about 13º in azimuth and 10º in
elevation at 140 GHz. Figure 9.1(a) shows path loss measurement setup for LoS
environment.
By recording the frequency dependent scattering parameter s21 in the frequency
range 110-170 GHz, the channel transfer function is measured. The full available
bandwidth of 60 GHz is used in all measurements, which provides the spatial and
temporal resolution of 5 mm and 0.0167 ns, respectively. All measurement parameters
are summarized in Table 9.1.
9.1.2 Path loss Measurements
Typical short-range communication between devices can be expected to operate at
distances between 0.1 m and 1 m. Hence, in the first measurement scenario, we have
collected channel transfer functions at 0.4572 m, 0.6096 m, 0.762 m, and 0.9144 m
distances using the measurement setup shown in Fig. 9.11(a). Path loss and shadow
fading are called large-scale fading because they are dominant when the receiver moves
over distances greater than several tens of the carrier wavelength. The theoretical freespace path loss at a reference distance d 0 is given by [146].
 4d 0 
PL(d 0 )  20 log10 

  
131
(9.1)
where λ is the wavelength. To obtain the path loss, the first step is to separate large-scale
and small-scale fading characteristics.
Figure 9.1. Measurement setup for short range channel characterization in (a) LOS
environment and (b) partially obstructed LoS environment
TABLE 9.1. MEASUREMENT PARAMETERS.
Parameter
Measurement points
Intermediate frequency bandwidth
Average noise floor
Input signal power
Start frequency
Stop frequency
Bandwidth
Time domain resolution
Maximum excess delay
Symbol
N
f IF
PN
𝑃𝑖𝑛
f start
f stop
B
t
m
Value
801
100 Hz
-85 dBm
0 dBm
110 GHz
170 GHz
60 GHz
0.0167 ns
13 ns
Since the channel transfer function is collected in the frequency domain, to obtain
the channel impulse response, data needs to be converted to the time domain using an
Inverse Fast Fourier Transform (IFFT). To obtain the large-scale fading, we use the local
sliding window technique [147] where the sliding window length is set to 40λ.
Figure 9.2 compares the measured path loss with the theoretical path loss obtained
using the Friis equation in (9.1). From Fig. 9.2 we can observe that the measured path
132
loss increases with frequency and closely follow the path loss predicted by the Friis
equation. However, at lower frequencies, there is a slight disagreement of around 1 dB
between the theoretical and measured values. The reason for this discrepancy comes
from the frequency dependent gain of the horn antenna used in the measurement.
According to the vendor’s data sheet, the antenna gain varies from 22 dBi at 110 GHz to
23.2 dBi at 170 GHz. Therefore, using a constant gain of 23 dBi across the entire
bandwidth for the calculation of measured path loss gives the extra ~ 1 dB loss at lower
frequencies. Figure 2 also shows the path loss for several distances d = [0.45, 0.6, 0.76,
0.9] m and we can observe that the path loss at different distances follows the same trend.
Figure 9.2. Measured and theoretical path loss in LoS environment for several different
distances between the Tx and Rx
The second measurement scenario tests obstructed-line-of-sight (OLoS) type of
communication. The path between the Tx and the Rx is partially obstructed by a ceramic
mug, a disposable cup, and a printed circuit board (PCB) as shown in Fig. 9.1(b). The
distance between the Tx and Rx was 0.9 m, the different objects were positioned in the
133
middle of the Tx-Rx path, and we have varied the height of the objects obstructing the
LoS path. Fig. 9.3 shows the measured path loss when ceramic mug is placed 0.635 cm
and 4.45 cm above the LoS path, when paper cup is placed 2.54 cm and 6.35 cm above
the LoS path, and when a PCB is placed perpendicular and parallel to the LoS, 2.54 cm
above it. The results show that the signal obstructed by a paper cup experiences very little
loss.
Figure 9.3. Measured path loss when LoS path is obstructed by ceramic mug, paper cup,
and a pcb board.
Compared to the LoS path loss, the loss increases by about 2dB and there is very
little shadowing (fluctuations of the path loss) indicating that the most of the signal
propagates through the paper cup. On the other hand, when the signal is barely obstructed
by a ceramic mug, the path loss increases by about 5 dB and the path loss fluctuations are
significantly larger. Furthermore, when ceramic mug obstructs most of the LoS path, the
path loss increases by about 20 dB and the shadowing is significant. Finally, when the
signal is obstructed by a PCB, the path loss is about 10 dB larger, with more shadowing
134
when the PCB is placed perpendicular to the LoS path compared to when it is parallel.
This is expected since obstruction of the path is more significant when the PCB is placed
perpendicularly.
9.2 D- Band Characterization of Co-planar Wave guide and Microstrip
Transmission Lines and SIW on Liquid Crystal Polymer
The research work in the last ten years has proven that Liquid Crystal Polymer is
a very good organic substrate and packaging material. This is due to the fact that it has
multi-layer lamination capabilities, excellent electrical properties ( i.e. low and stable
dielectric constant that is around 3.1) and low loss tangent (0.003) up to 110 GHz. It has
near hermetic nature and also exhibits a controllable coefficient of thermal expansion
(CTE) which can be engineered to match with Cu and Si. Several emerging systems in
the mm-Wave frequency bands, such as communication systems in the unlicensed 60
GHz band (57-64 GHz), back haul communication in the E-band, automotive radars at
77 GHz or the military and space based radars such as cross track scanning of Aerosol –
Cloud Eco System at 94 GHz could potentially benefit from it. Considerable amount of
work (embedded passives, antennas and integration of transceivers) has been reported on
LCP from a few Mega Hertz up to 90 GHz.
The 100 GHz of spectrum from 70 to 170 GHz is ideally suited for short range
communication and for long range communication (e.g., back haul communications in
the E-Band that is from 71-76 GHz and 81-86 GHz with much lower atmospheric
attenuation levels (0.5 dB /Km) than those encountered in the popular 60 GHz band
(12dB/Km)). Additional possible applications in D-band include: (i) industrial sensors,
(ii) active imagers for biomedical applications, (iii) passive imagers for remote sensing,
135
night vision, security, and (iv) 10-40Gb/s wireless I/Os for chip-to-chip communication
within 3D electronic systems [148]. This is due to the fact that the serial data rate on the
back plane is predicted to saturate at 20-30 Gb/s due to poor quality of the channel that
consists of transmission lines on PCB and low bandwidth connectors. One proposed
solution (among others which involve optics and capacitive or inductive coupling) is to
integrate wide-band radio transceivers and antennas in a System on Package (SoP)
platform making use of simple modulation schemes.
LCP has been well characterized up to 110 GHz [17,149-150]. To investigate the
viability of LCP as a packaging and substrate material in the D-band, microstrip lines
and co-planar waveguides are fabricated and measured from 110 GHz to 170 GHz. For
enhanced measurement accuracy and accurate substrate characterization, a through,
reflect, line (TRL) calibration is performed according to NIST guidelines (multi-line
TRL).
9.2.1 Design of CB-CPWs
Microstrip and conductor-backed coplanar waveguide (CB-CPWs) and CPW are
the most commonly used transmission lines in planar microwave circuit design.
Furthermore, microstrip to coplanar wave guide transitions are commonly utilized for the
measurement and packaging of microstrip designs.
When designing RF circuits,
electromagnetic simulators are used with the assumption that metals are perfect electric
conductors and have no metal loss. Even when a conductivity value is added, simulated
transmission lines do not take the metal and the dielectric surface roughness into account.
At low frequencies, this may be acceptable, but at mm-wave frequencies (W-band and Dband), where metal surface roughness and dielectric surface roughness are comparable
136
with the skin depth of the metal (~ 0.15µm @110GHz-170GHz), these effects become
dominant [3]. Copper skin depth can be calculated by equation 9.2.
𝑆=
2837
(9.2)
√𝑓
Here, S is the copper skin depth in mils, and f is the frequency in Hz. Dielectric and
conductor surface roughness might create significant conductor losses which may not be
detected in simulations. That’s why these three transmission line structures have been
designed and measured to investigate the performance of LCP in D-band. All
transmission line measurements were done using Line-Reflect-Reflect-Match (LRRM)
and Thru-Reflect-Line (TRL) calibration. 60 ohms via-less CB-CPWs and 80 ohms vialess CPW to microstrip transitions were designed and measured. High impedance lines
are preferred to relax the fabrication requirements, and in order to reduce dispersion that
is common for the microstrip lines [151-152].
9.2.1.1 Design of Via-less 60 ohms CB-CPWs and 80 ohms microstrip line
An important consideration in designing via-less CB-CPWs is that the parasitic
parallel plate waveguide mode is excited when the total width of the transmission line (S
+ 2*W + 2*Wg) is greater than 𝝀g /2[150]. In Fig.9.4 and Table 9.2, the design
parameters for the CB-CPW are presented. CPW lines were fabricated using 9µm thick
copper, therefore 9µm of over etching was expected, meaning that the total feature size
could be affected by 18µm over all. This was taken into account during design of the
lines. For instance, for a line width of 50 µm, due to expected over etching, the width was
intentionally made 18 µm wider (68µm). In Table 9.2, designed, expected and measured
feature sizes are given.
137
Figure 9.4 Design of via-less CB-CPW
Table 9.2
Design Parameters of CB-CPW Lines
Via-less CB-CPW (on 2mil LCP)
CHx Zo (Ω)
Wg(µm)
Wgnd(µm)
Wsig(µm)
60(designed)
14
320
87
~60(expected)
32
302
69
62 (measured)
31
300
70
9.2.1.2 Design of CB-CPW to Microstrip Transition
In order to have a smooth transition from CPW to microstrip, the 𝜽trans shown in
Fig. 9.5 should be less than 40 o [153]. The TRL standard thru line was designed to have a
total loss of around 0.5 dB across the whole band. Table 9.3 gives the designed, expected
and the measured dimensions for the microstrip lines.
Fig.9.5 Designed CB-CPW to microstrip transition.
138
Table 9.3
Design Parameters of the Microstrip Lines
microstrip Design (on 2mil LCP)
CHx Zo (Ω)
Wmicrostrip (µm)
80 (designed)
70
80 (expected)
52 (82Ω)
80 (measured)
54
9.2.1.3 Design of TRL Lines for Microstrip Loss Extraction
Multiline TRL lines [154] need to be designed carefully in order to be consistent
with the NIST protocol. A set of Multiline TRL lines was designed to completely deembed CB-CPW-to-microstrip transition.
Starting with the 𝜺eff value given by the
Agilent ADS line calculator tool for the selected transmission line, and taking the actual
physical length of the thru line into account, equations (9.3) - (9.5) were used to ensure
proper overlap of the delay calibration lines. The physical length of the line was
estimated first and then plugged into the equations (in meters) along with the other
pertinent information. The results produce the lower, Flower,ln , and upper, Fupper,ln , cut off
frequencies. Between these frequencies the designated delay line will provide adequate
calibration coverage. An ideally calibrated frequency will be at F90, which is the center of
the valid frequency range for a given delay line. The delay lines selected for the CB-CPW
to microstrip transition provide a certain amount of overlap of the target frequency range
from 110 to 170 GHz.
Flower,ln =
c ∗ 20
(Lengthln − Lengththru ) ∗ 360 ∗ √εeff
139
(9.3)
F90,ln =
c ∗ 90
(Lengthln − Lengththru ) ∗ 360 ∗ √εeff
Fupper,ln =
c ∗ 160
(Lengthln − Lengththru ) ∗ 360 ∗ √εeff
(9.4)
(9.5)
Table 9.4
TRL Line Lengths
Line Type
Line Length (µm)
Thru
0
Delay Line 1
500 w.r.t Thru Line
Delay Line 2
850 w.r.t Thru Line
Measured microstrip Line
2000 w.r.t Thru Line
Two calibration lines were designed to provide a 90o shift at different frequencies
of the measurement bandwidth, while keeping the phase shift of each line above 50 o over
the entire bandwidth. Table 9.4 shows the length of the used TRL standard lines.
9.2.2 Fabrication
A 2 mil double copper (9 µm) cladded LCP substrate was used for the fabrication
of the designed structures. The patterning of the designs was carried out using standard
photolithographic process (Karl-Suss MA-6 Mask Aligner), and wet etching process.
Since it is difficult to achieve fine features with wet etching, extreme care is required
during the etching process. Table 9.2 and 9.3 present the expected and measured feature
sizes. Measured and expected values agree within a maximum 4 µm of error. The three
samples with the measured dimensions are shown in Fig 9.6 (a-c)
140
Figure 9.6 Fabricated samples: (a) 1 mm long microstrip line, with CPW to microstrip
transitions and showing the TRL calibration reference planes, (b) 0.5 mm long 60 ohms CBCPW line (c) 2 mm long 60 ohms CB-CPW
9.2.2.1 Additional Fabrication Considerations
During the development of the fabrication recipe, it was observed that a fine
features size of around 20 µm is very difficult to realize using sputtered Cu. The yield is
not that high (50%-75%). Some structures are over-etched and some are shorted as shown
in Fig 9.7(b). This effect needs to be investigated more, but it may be because of the
thermal stress the LCP goes under for 6 hours of metal deposition. To address the
problem, electroplating may be a good solution. Therefore, in order to develop SIWs and
grounded CB-CPWs, where vias needs to be drilled and metallized and some alignments
marks are also required to accurately align structures, a new robust recipe was developed
as shown in. 9.8 (a-g).
141
Fig. 9.7 Fabricated structures using 2 and 9 µm of Cu
Figure 9.8 (a). Step: 1 Cutting sample from the panel
142
Figure 9.8 (b). Step: 2 Blue tape attachment
Figure 9.8 (c). Step: 3 Etching of Cu for alignment vias
143
Figure 9.8 (d). Step:4 Alignment, CPW and SIW via Drilling
Figure 9.8. (e). Step:5 Sputtering Cu on bottom side to metallize vias
144
Figure 9.8 (f). Step: 6 Patterning the top side
Figure 9.8 (g). Step: 7 Patterning the bottom side
145
9.2.3 Measurements
The measurement setup is shown in Fig. 9.9. An Agilent E8361C vector network
analyzer was used to take all the s-parameter measurements. The E8361C has a frequency
range up to 67 GHz, therefore the N5260A (mm-Wave Controller) and V06VNA2 (mmWave Test Heads) were used to extend the range to the D-band (110-170 GHz).
In order to take out cable, probe and test head losses, LRRM calibration was
performed on Cascade 138-356 ISS. 75 um pitch CascadeMicroTech® Infinity D-band
probes were used for all measurements. As shown in Fig. 9.10, a good calibration was
achieved, with a slight variation of 0.02dB for the S21 measurements of the thru standard.
Figure 9.9 (a) Measurement Setup, (b) sample ready to be probed, (c) measurements
underway
146
Figure 9.10 Measurement of the thru standard after LRRM calibration (a) including
reflection coefficients, (b) Without S11 and S22 to adjust the scale of S21
After LRRM calibration, the TRL standards shown in Fig.9.11 were measured to
see if they exhibit any undesired response that can cause problems during TRL
calibration. In Fig. 9.11, aa- and bb- are the reference planes for both ports. For the thru
standard, the total length after the calibration planes is zero, and for line 1 and 2 the line
lengths are 500 µm and 850 µm respectively (with respect to thru standard). After TRL
calibration, the reference plane will be at the middle of the thru-line as shown in Fig 9.6
(a), therefore the CPW to microstrip transitions are de-embedded, and only microstrip
loss is measured /extracted.
147
Fig. 9.11 TRL calibration lines
The thru standard after TRL calibration was measured and the response is shown in Fig. 9.12.
Figure 9.12 Measurement of the thru standard after TRL calibration
148
9.2.3.1 80 ohms Microstrip Loss Extraction with TRL Calibration
After TRL calibration, the reference plane was moved to the center of the thru-line,
therefore the microstrip line loss could be extracted excluding all measurement fixtures,
and the CPW transitions. Fig. 9.13 shows the s-parameters of the 80 ohms, 0.5 mm and
1mm long microstrip line. The high impedance microstrip line was chosen to avoid
dispersion issue. The loss shown in Fig. 9.13(b) is averaged out and Fig. 9.14 shows the
loss vs. frequency plot in dB/mm. The copper (electrodeposited) used for this
investigation has on average of 0.8µm measured surface roughness. If surface roughness
of the copper would be reduced to 0.1-0.3 µm, 10-15% less loss could be achieved when
calculated by the Morgan Model [49], where the surface roughness correction factor
(from [41]) is applied and then this corrected value is used to calculate the conductor loss
using the equation in [41] (p.108).
𝑅𝑠 = √𝜋𝑓𝑛𝑡ℎ µ𝑜 𝜌𝑐
(9.6)
2
𝛥 2
−1 [1.4
𝑅𝑠 ` = 𝑅𝑠 { 1 + 𝑡𝑎𝑛
( ) ]}
𝜋
𝛿𝑠
(9.7)
It can be observed in Fig.9.14, that at 110 GHz, the microstrip loss is measured to be
0.1755 dB/mm which is close to what Thompson et al. reported in [149] (0.24dB/mm) on
2mil LCP. The highest loss (0.331dB/mm) was observed at 170 GHz. Fig. 9.14 also
shows attenuation in terms of dB/guided wavelength where the maximum attenuation is
0.3773 dB/𝝀g.
149
Figure 9.13 (a) Measured s-parameters of the 0.5mm and 1mm long µstrip line after TRL
calibration (b) measured S21 of 0.5mm, 1 mm long microstrip lines
Figure 9.14 80 ohms microstrip attenuation vs. frequency (dB/mm) and (dB/𝝀g)
9.2.3.2 Via-less 60 ohms CB-CPWs Measurements after LRRM Calibration
60 ohm CB-CPWs were measured with the LRRM calibrated system. Since these
lines are CB-CPWs there is a chance of parasitic waveguide mode excitation. The results
are presented in Fig 9.15 (a) and (b). Fig 9.15 (b) shows that at 150 GHz the slope of S21
150
increases. This may be because of a resonance in the CPW lines. This effect can be
reduced by using grounded CPWs to tie top and bottom grounds together. Accurate
measurement can only be done if these CPWs are measured after TRL calibration [155].
Therefore no line-loss value is reported, whereas the low-loss behavior below 150 GHz
meets expected performance for the CPW lines
Figure 9.15. Via-less 60 ohms, CB-CPWs measurements after LRRM calibration
Finally, Fig. 9.16 shows the effective dielectric constant which was extracted after
TRL calibration for the microstrip lines. The real part has a minimum value of 2.52, and
it remains constant around 2.6. This reveals an almost pure TEM mode up to 170 GHz.
This value is comparable to the results in [149], where 2.474 was reported as the highest
real effective dielectric constant up to 110 GHz. The plot in Fig. 9.16 shows that Rogers
LCP has an almost constant dielectric performance from 110-170 GHz.
151
Figure 9.16 Real and imaginary effective dielectric constant vs frequency
9.2.3.3 Comparative study between CPWs fabricated using 2um and 9um Cu
One important observation during this characterization was that in order to
characterize a transmission line on LCP, more than 5 µm of Cu needs to be deposited.
This is because of the 1-2 µm of surface roughness of LCP. To overcome the additional
loss caused by surface roughness, more than 5 µm needs to be deposited. For this reason,
to characterize these lines, we have used 9 µm of electrodeposited Cu. Fig 9.15 shows
that the CPW line fabricated with 2µm of Cu thickness has more loss as compared to the
CPW line which was fabricated using 9 µm of Cu.
152
Fig. 9.17 Comparison between CPW lines fabricated using 2 and 9 µm of Cu
9.2.3.4 CPW to Microstrip Line Transition and Substrate Integreated Waveguide (SIW)
We also measured a CPW to microstrip line transition and SIWs in the D-band.
The structures for which results were reported in earlier sections of this chapter used CBCPWs. The top co-planar ground of the conductor was not connected to the bottom
ground. For the results presented in this section, the top co-planar ground of the CPW is
tied down to the bottom ground with vias to suppress all other modes. The fabricated
structures are illustrated in Fig. 9.18. As can be seen from Fig. 9.19, that the transition is
low-loss and a maximum loss of 0.58 dB for a 2 mm long structure is measured. The SIW
measurements are illustrated in Fig. 9.20 for a 4 mm long SIW structure with a loss of
0.35 dB/mm. But this loss includes two transition losses; (a) CPW to microstrip loss and
(b) microstrip to SIW loss. Accurate loss of SIW can be extracted after carrying out TRL
calibration.
153
Figure 9.18. Fabricated CPW to microstrip transitions and SIWs
Results of the transition and SIW are presented in Fig. 9.19 and 9.20.
Figure 9.19. S-parameters of CPW to microstrip to SIW transition
154
Figure 9.20. S-parameters of CPW to microstrip to SIW transition
9.3 Characterization of a Low-Loss and Wide-Band (DC to 170 GHz) Flip-Chip
Interconnect on an Organic Substrate
Owing to the advancements in semiconductor technology, realization of
integrated circuits (ICs) in the sub-millimeter-wave range is now possible. Researchers
have successfully reported ICs that can operate at 300 GHz, but packaging of such chips
is limited to the performance of chip-to-package interconnections. Therefore, building a
complete system requires careful design of sub-mm-wave interconnects.
Flip-chip is a promising technology that has low parasitics and has proven itself
as a wide-band and low-loss interconnect solution at mm-wave frequencies. Moreover, it
enables low cost and quickly developed systems to be built using off-the-shelf
components. Very good performance of flip-chip interconnects has been demonstrated
below 100 GHz in [156] where a 94 GHz module reporting 0.25 dB of insertion loss per
interconnect (excluding CPW lines loss) was demonstrated. In [156], no compensation
network was used to optimize the performance. In [157], Beer et al. reports the
performance of a flip-chip interconnect to integrate a Si IC with a thin-film antenna on an
155
alumina substrate. The aforementioned work reports 3.5 dB and 6.5 dB of insertion loss
at 122 GHz and 165 GHz, respectively, for a 7 mm long structure.
In this section, state-of-the-art performance of a very wide-band (DC to 170 GHz)
flip-chip interconnect on a liquid crystal polymer (LCP) substrate is demonstrated. To the
best of the author’s knowledge, this is the first time that such a broad band flip-chip
interconnect performance has been reported. To mitigate the effect of the capacitance
caused by the flip-chip overlap section, high-impedance inductive sections are used.
Compared to the results presented in [157], the insertion loss is improved to 0.23 dB and
1.2 dB for a 1.35 mm long structure (including the insertion loss of on-chip and onpackage CPW lines) at 122 GHz and 165 GHz respectively. The transition was measured
from DC to 170 GHz, demonstrating extremely broadband performance. It shows that the
flip-chip transitions, if optimized properly, can work with excellent performance over a
very wide bandwidth (DC to 170 GHz).
In this work, because of its excellent electrical properties (low dielectric constant
~ 3 and a low loss tangent of 0.006 at 170 GHz) [86], LCP was used as the microwave
substrate. Since LCP is a polymer that is soft and flexible, special care must be taken
during the flip-chip bonding process. This work characterizes the flip-chip interconnect
and provides guidelines to optimize the performance of flip-chip interconnects on a liquid
crystal polymer (LCP) organic substrate.
9.3.1 The Design of a Flip-chip Interconnect
The flip-chip interconnect was designed, from DC to 170 GHz, by modeling the
3-D structure in the Ansys high frequency structure simulator (HFSS). As displayed in
Fig. 9.21, the chip and the package were modeled by designing the conductor-backed
156
coplanar waveguide (CB-CPW) transmission lines on 200 µm and 50 µm LCP substrates,
respectively.
Fig. 9.21. (a) 3-D flip-chip structure in HFSS, (b) top view, (c) RLC equivalent model
The dimensions of CPW lines and the height of the chip and package substrates were
chosen so that (a) the minimum feature size can be easily realized in the clean room
environment, (b) samples can be probed with 75 µm pitch probes, and (c) the bumps on
the chip can be landed on the pads of the package accurately. Additionally, to avoid the
parasitic parallel plate waveguide mode, the width of the CPW structures, both on the
chip and package, were made less than 𝝀g /2. The dimensions of the CPW structures are
shown in Table. 9.5. As explained in [156], in order to avoid any detuning effect, the
copper on the package under the chip was also removed. To compensate for the effect of
parasitics caused by the bumps and flip-chip overlap section, high-impedance inductive
sections were utilized. The length of the high-impedance section was estimated using
equation (9.8) given in [158], and then then it was optimized in HFSS.
157
𝑙=
𝜔ℎ 𝑍ℎ 𝑍𝑜 2 𝐶𝑒𝑓𝑓
( 2 2 )
𝑍ℎ − 𝑍𝑜
𝛽ℎ
(9.8)
Here, Zh is the characteristic impedance of the high impedance section, β h is the
propagation constant, ωh is the operating frequency and C eff is the effective capacitance
defined in Fig. 9.21 (c).
Table 9.5
LCP Package- and Chip-Model Parameters (mm)
p_h
0.05
l
0.02
p_l
1.35
b_d
0.05
c_h
0.2
c_l
0.55
b_h
0.04
p_cpw_w
0.4
c_w
0.5
p_g
0.018
p_gnd_w
0.152
d
0.03
c_g
0.03
c_cpw_w
0.5
w
0.03
c_s_w
0.17
p_s_w
0.075
The transition was optimized for D-band operation. The EM-simulated insertionand return loss of the complete transition is reported in Fig. 9.22. It can be seen from Fig.
9.22 that without utilizing the high-impedance compensation sections, return and
insertion loss starts deteriorating as frequency increases. Although we have a slightly
better insertion loss up to 80 GHz, this comes at the cost of degraded performance in the
D-band. The blue curve (S21 with compensation sections) shows slight dips around 40
and 160 GHz. Using different dimensions of the high-impedance sections and the height
of the bump, the slight dips in insertion loss can be avoided. However, this also leads to
an increase of insertion loss at mid-D-band. The bump height and diameter were set to 50
158
µm and 40 µm, respectively, after optimizing for low insertion loss across the complete
D-band.
Figure 9.22. EM-simulated results of the flip-chip transition (LCP chip flipped on LCP
package)
Despite the slight dips in insertion loss, displayed in Fig. 9.22, the simulated S11
and S21 demonstrate good return and insertion loss, and remain higher than 15 dB and
less than 0.8 dB, respectively, across the whole frequency range (DC to 170 GHz) for the
interconnect and the transmission line 1.35 mm long. Over a wide frequency range, the
interconnect loss is compensated with high-impedance inductive sections. The maximum
interconnect loss, if the loss of both package and chip transmission lines (1.35 mm long)
are removed, is 0.3 dB per interconnect at 165 GHz.
9.3.2 Fabrication and Flip-chip Bonding
The chip and package components were fabricated on double copper (9 µm thick)
cladded 200 µm and 50 µm LCP substrates respectively. For the chips to be flipped on
the package, gold-stud bumps on the CPW pads are required, which necessitates gold
pads on the chip. Since gold doesn’t adhere well to copper, first a thin layer of titanium
159
(250 Ao) is evaporated on top of the 9 µm thick copper, and in the end, a layer of 0.3 µm
gold was evaporated. After the metallization process, both substrates were patterned with
standard lithographic process and the metal was etched out using wet etching process.
During the assembly, the FineTech flip-chip bonder was used to flip the chips on the
package. Silver epoxy (σ c = 2.5x106 S/m) was used to adhere the Au stud bumps to the
pads on the package. Gold-stud bumps were bonded on the chip, and finally the chip was
flipped on to the package.
During the flip-chip bonding process, with less than 1 N force on the chip holding
(CCH) module, CCH module and sample holder were kept at 120 Co and 110 Co ,
respectively, for curing. Since LCP is a soft material, a large force deforms the metal and
the substrate causing additional ohmic loss or even discontinuities in worst cases as
shown in Fig 9.23. Therefore, the process (force and thickness on the metal) is optimized
to acquire low-loss interconnect performance. The fabricated and assembled components
and module are shown in Fig. 9.24(a-d). The overall package size is 1.35 x 0.4 mm2 .
Figure 9.23. EM-simulated results of the flip-chip transition (LCP chip flipped on LCP
package)
160
Figure 9.24. Fabricated (a) LCP chip, (b) LCP with gold bumps, (c) LCP package with high
impedance sections, and (d) LCP chip flipped on LCP package
9.3.3 Measurements and Results
An Anritsu 37397D VNA with 3738A (Test Set) and 3742A-EW (TransmissionReflection Module) was used to perform S-parameter measurements up to 110 GHz with
100 µm pitch picoprobes by GGB Industries Inc. For D-band (110-170 GHz)
measurements, an E8361C vector network analyzer along with N5260A (mm-Wave
Controller), and V06VNA2 (mm-Wave Test Heads) were used. D-band measurements
were taken using 75 µm pitch Cascade MicroTech Infinity D-band probes. The reference
plane for both measurements is at the edge of CPW lines as shown in Fig. 9.24(d). The
measurement plane was set to the probe tips by an LRRM calibration using Cascade 138356 ISS. Measured S-parameters are displayed in Fig. 9.25. The measurements correlate
well with simulated results. The reason for the reduction in S21 (around 40 GHz and 155
161
GHz) and shift in S11 as seen in Fig. 9.25, is associated with the over etching of Cu
during the wet-etching process.
Figure 9.25. Measured and simulated return loss and insertion loss for circuits shown in
Fig. 3.
An additional reason for the increased loss is reduced overlap of the bump on the
pads on the package. This effect is also an indirect consequence of over-etching. For the
first iteration, this overlap was close to 45 %. For the second iteration, without changing
the mask, the over-etching was better controlled, and it was possible to land the pads with
85% overlap. It was observed that by using the unused etching solution and selective
etching of the sample help in controlling the over etching. Moreover, while designing the
mask, feature sizes should be slightly over-compensated to avoid over-etching.
The difference in the performance for both cases is shown in Fig. 9.26. In the first
iteration, because of the bad signal and ground connections, the S21 curve starts declining
earlier and reduces below - 1 dB at 130 GHz. However, with 85% overlap, the S 21 curve
remains above -1 dB up to 162 GHz. This is a significant improvement in the
162
performance. Therefore, if a complete overlap of the bump with the package-pads can be
achieved, the performance can be further improved and the additional loss of 0.3 dB can
be mostly eliminated.
Figure 9.26. Measured insertion loss of flip-chip transitions with 45 and 85% overlap of the
bump on the landing pad of the package, and insertion loss of the back-to-back transition in
dB/mm
The fluctuations are seen in Fig. 9.24 around 60 GHz as the VNA source reaches
its frequency limit, but beyond 60 GHz the fluctuation reduces after the multiplexing
coupler test head switches to the mm-wave source modules. In Fig. 9.26, we also report
state-of-the art insertion loss of back-to-back flip-chip transition in dB/mm. To the best
of author’s knowledge, this is the lowest insertion loss (less than 0.2 dB/mm up till 135
GHz and 0.9 dB/mm at 165 GHz) reported in the literature. This loss also includes the
insertion loss of transmission lines that are 1.35 mm long. The results are summarized in
Table 9.6 and previously reported transitions are included for comparison. As seen, the
reported flip-chip transition achieves the lowest insertion loss and the widest bandwidth.
163
Table 9.6
Comparison between State-of-the-art Flip-chip and Wirebond Interconnect
Freq.
(GH)
Technique
S21(dB/mm)
@60 GHz
S21(dB/mm)
@122 GHz
S21(dB/mm)
@165 GHz
This
work
DC- 170
Flip-chip
0.1
0.18
0.9
[157]
110-170
Flip-chip
n/a
0.42
0.9
[159]
0-100
Flip-chip
0.5
n/a
n/a
[157]
110-170
Wire-bond
n/a
1#
10#
# The interconnect loss is reported after subtracting the transmission line loss.
In Table 9.7, a comparison of this work with other interconnect technologies is presented.
It is clearly evident that this transition outperforms the other transitions.
Table 9.7
This
work
Comparison of Flip-chip with Other Interconnects
S (dB/mm)
S (dB/mm)
Freq.
21
21
S (dB/mm)
Technique
21
(GH)
@122 GHz
@165 GHz
0.1 @ 60
DC- 170
Flip-chip
0.18
0.9
GHz
[100]
110-170
Micro_Coax
[101]
0-100
Hot-Via
[102]
110-170
Wave-Guide
[72]
77
emWLP
[160]
75- 110
Stacked via
n/a
0.5@
45 GHz
1.2 dB @
77GHz
0.65@
77GHz
0.12@75
GHz
.
164
0.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0.2@110 GHz
n/a
SUMMARY PART III
The work presented in the third part of this dissertation, for the first time,
demonstrated the working of low-phase noise K-band oscillator on a low cost organic
LCP substrate. For the first time, an organic based K-band (25.6 GHz) low phase noise
oscillator was developed with a value of -108 dBc/Hz at 1 MHz offset and output power
of -6 dBm using a commercially-available GaAs pHEMT transistor. This work
demonstrates that it is possible to develop very low cost oscillators above 20 GHz using
organic substrates that can be manufactured and processed in very high volumes (PCBtype of fabrication) along with commercially available packaged transistors.
We also showed the design and development of a 60 GHz RF front end Tx/Rx
module on an organic LCP substrate. The receiver module provides a gain of 31.8 dB,
which deviates by only 1 dB from 55 to 63 GHz. To the best of authors’ knowledge, this
is the highest Rx gain reported to date for an organic packaged 60 GHz module. The
transmitter module provides a maximum gain of 21.6 dB which deviates by 3 dB from 55
to 63 GHz. 55 to 62 GHz.
For the first time, a detailed analysis and design guidelines to accurately model a
W-Band chip and design an optimized flip-chip interconnect on an organic LCP substrate
was presented. When the coplanar waveguide (CPW) lines loss is included, an insertion
loss of 0.6 dB per flip-chip-interconnect is measured. If CPW lines are de-embedded to
the edge of the chip, 0.25 dB of insertion loss is observed. To validate the model and
designed transition, (3 mm x 1.9 mm) two compact flip-chip packaged W-band modules
were presented. The packaged LNA showed peak measured gain of 15.9 dB and a noise
figure of 8.3 dB. The measurements of the receive module also matched well with the
165
simulated results showing a 10 dB bandwidth of 10 GHz with a passive and active peak
gain of 5.2 dBi and 21.2 dBi, respectively. It demonstrates 16 dB of added gain at 93
GHz to the passive antenna. This work shows the viability of an LCP substrate for
development of low-cost mm-wave organic SiGe based modules in W-Band. It also
paves the way for the development of low-cost sub-mm-wave organic front-ends which
can be made flexible because of the flexible structure of LCP and hence, if required, can
be mounted on conformal surfaces.
Then the focus of the dissertation shifted to the development of D-band modules
and channel characterization. We also presented the path loss measurements of 110-170
GHz indoor wireless channels. The measurements were performed in line-of-sight and
obstructed-line-of-sight environments. The results show that the measured path loss
closely follows the theoretically predicted path loss. Furthermore, the results show how
the path loss changes when the LoS path is obstructed by different objects.
We also presented the characterization of planar transmission lines on an organic
Liquid Crystal Polymer (LCP) substrate in D-Band. The microstrip line showed a loss of
0.1755dB/mm at 110 GHz, and 0.331dB/mm at 170 GHz. A constant effective dielectric
constant from 110-170 GHz is also reported. These results suggest excellent RF
performance of LCP across the entire D-band, which paves the way for System-onPackage solutions in the D-band using LCP. Additionally, guidelines to fabricate
structures with feature size of as small as 15-20 µm were also presented.
In the end the design and characterization of a low loss and wide-band flip-chip
interconnect on LCP from DC to 170 GHz was presented, demonstrating state-of-the-art
performance. Insertion losses of 0.18 and 0.9 dB/mm were measured at 122 and 165
166
GHz, respectively. The maximum interconnect loss, if the loss of TL both on package
and chip is removed, is 0.3 dB per interconnect at 165 GHz. This study shows that if the
parasitic effects of the flip-chip transition are properly absorbed in to the matching
network, a very broad band interconnect performance can be achieved, and interconnect
loss can almost be eliminated (for a certain frequency range) leaving only the loss of
transmission line. It also demonstrates the low-loss behavior of LCP that shows its
viability to be used in mm-wave multi-layer system-on-package (SoP) solutions.
167
Chapter X
Contributions
Salient contributions of this dissertation are enumerated below:
1- The first ever characterization of LCP from 110 to 170 GHz. A new study was
carried out to show that the main source of radiation is the open-ended feeding
microstrip line and not the ring-resonator itself. Moreover, if measurements are
carried out after TRL calibration then radiation loss can be neglected.
2- Development of an ultra-wideband W-band antenna on LCP using an optimized
low-loss microstrip to slot-via transition. This transition has wide-impedance
matching and it utilized the slow-wave concept to provide unbalanced to balanced
mode conversion.
3- The first ever demonstration of integration of V- and W-band antennas with
excellent clean radiation patterns and isolation between two antennas. The
distance between two antennas was carefully chosen and a low-loss multi-band
wire-bond interconnect was designed using capacitive stubs.
4- The first ever development of an on-chip end-fire antenna with a 72%-76%
measured radiation efficiency. A detailed analysis and design guidelines were
provided.
5- Demonstration of a working low-phase noise K-band oscillator on a low cost
organic LCP substrate. For the first time, an organic based K-band (25.6 GHz)
low phase noise oscillator was developed with a value of -108 dBc/Hz at 1 MHz
offset and output power of -6 dBm using a commercially-available GaAs pHEMT
168
transistor. This work demonstrates that it is possible to develop very low cost
oscillators above 20 GHz using organic substrates that can be manufactured and
processed in very high volumes (PCB-type of fabrication) along with
commercially available packaged transistors
6- First ever demonstration of a 60 GHz Tx/Rx module with state-of-the-art
performance on an organic substrate.
7- A detailed analysis and design guidelines to accurately model a W-Band chip and
design an optimized W-band flip-chip interconnect on an organic LCP substrate.
8- Path loss measurements of 110-170 GHz indoor wireless channels. The
measurements were performed in line-of-sight and obstructed-line-of-sight
environments. This study showed how the path loss changes when the LoS path is
obstructed by different objects.
9- The D-band characterization of planar transmission lines on an organic Liquid
Crystal Polymer (LCP) substrate. Development of a fabrication recipe to realize
fine feature size of 15-20 µm with extremely low-loss performance. This
demonstration showed that on LCP, the deposition of metal should be more than
5-6 µm for to avoid extra ohmic loss in the D-band.
10- First-ever characterization and modelling of a low loss and wide-band flip-chip
interconnect on LCP from DC to 170 GHz. State-of-the-art D-band insertion loss
was reported. To achieve low-loss interconnect, high-impedance sections were
used to mitigate the capacitive effect of chip-loading and it was demonstrated that
the transition loss can be absorbed in the matching network. Guidelines were
presented for a flip-chip assembly process on flexible and soft LCP substrates.
169
Chapter XI
Future Work
1. Utilize and develop rigorous methods to characterize radiation efficiency at mmwave frequencies.
2. Develop complex systems on LCP at higher frequencies with multiple flip-chip
transitions at D-band to investigate the reliability
3. Characterize LCP above 170 GHz and investigate and develop systems above
170 GHz.
4. Integrate on-chip antenna with TRX modules.
5. Design and develop on-chip antennas above 170 GHz.
6. Develop multi-layer structures on LCP with chips embedded at mm-wave
frequencies and investigate the effect of registration error resulting from
lamination.
7. Develop fabrication recipes (electro-deposition) to realize fine feature size of 15
to 20 um for mass production on core substrates.
8. Surface Roughness should be reduced by polishing LCP and fine feature
realization should be explored with lower surface roughness and sputtered Cu.
170
Appendix A
Facilities Used
There are various facilities that were needed to finish the Ph.D. research. In the
design stage, a computer with high processing power and a large amount of memory was
required for simulation analysis. The microwave circuit technology group at Georgia
Tech has a computer with 4 Quad-core 3.2 GHz processors with 16 GB of memory. This
was sufficient for all the necessary simulations.
For fabrication, following equipment were used.
1- CVC DC sputterer - used for depositing metal layers
2- CVC E-beam Evaporator - used for depositing metal layers
3- SG2SC Spinner – used for spinning photoresist
4- Karlsus Mask Aligner – used for lithography
5- Tencor Profilometer – used to measure metal thickness and surface roughness
6- Plasma Therm RIE – used to clean samples
All of the above mentioned equipment is available in Petit and Marcus Cleanroom,
Georgia Tech.
For assembly, following equipment were required:
1- Ball wire-bonder- used for placing gold-stud bump on chips
2- Finetech Submicron flip-chip bonder – used for flip-chip bonding
Test and measurement stage required following equipment:
1- N5260A (mm-Wave Controller)
2- Agilent E8361C vector network analyzer
3- V06VNA2 (mm-Wave Test Heads)
171
4- E4446A Spectrum Analyzer
5- Cascade 138-356 ISS.
6- 75 um pitch CascadeMicroTech® Infinity D-band probes
7- Two D-band horn antennas for taking radiation pattern measurements using gain
comparison method.
8- A D-band sub-harmonic mixer
9- Anechoic Chamber
172
List of Authors Publications
Following is a chronological list of papers that have been submitted or/and accepted by
peer reviewed conference or journal for publication during my Ph.D.
Journal Papers:
1-
Chad E. Patterson, Wasif Tanveer Khan, George E. Ponchak, Gary S. May and
John Papapolymerou,"A 60 GHz Active Receiving Switched-Beam Antenna
Array with Integrated Butler Matrix and GaAs Amplifiers," IEEE Transactions on
Microwave Theory and Techniques vol. 60, No. 4, pp. 3599-3607, Dec 2012.
2-
Wasif T. Khan, Aida L. Vera López, A. Cagri Ulusoy, and John Papapolymerou,
“Packaging a W-band Integrated Module with an Optimized Flip-Chip
Interconnect on an Organic Substrate,” IEEE Transactions on Microwave Theory
and Techniques vol. 62, issue. 1 pp.64-72, January 2014
3-
Aida L. Vera López, Wasif T. Khan, and John Papapolymerou, “Orientation
Study to Minimize Coupling Effects in Radiation Patterns of Dual Packaged
Compact Millimeter-wave Antennas,” accepted for publication in IET
Microwaves, Antennas and Propagation.
4-
A. Cagri Ulusoy, Peter Song, Robert L. Schmidt, Wasif T. Khan, Mehmat
Kaynak, Bernd Tillack, John Papapolymerou, and John D. Cressler, “A Low-Loss
and High Isolation D-band SPDT Switch Utilizing Deep-Saturated SiGe HBTs,”
IEEE Microwave and Wireless Components Letters vol.24, No.6, pp.400-402,
June 2014.
5-
A. Cagri Ulusoy, Peter Song, Wasif T. Khan, Mehmat Kaynak, Bernd Tillack,
John Papapolymerou, and John D. Cressler, “A D-Band SiGe Low-Noise
Amplifier Utilizing a Gain-Boosting Technique,” accepted with minor revisions
in IEEE Microwave and Wireless Components Letters.
6-
O. Lemtiri Chlieh, Wasif T. Khan, J. Papapolymerou, “Thermal Modeling of
Microfluidic Channels for Cooling High Power Resistors on Multilayer Organic
Liquid Crystal Polymer Substrate,” submitted for review to IEEE Transactions on
Components, Packaging and Manufacturing Technology.
173
7-
Wasif T. Khan, A. Cagri Ulusoy, Gaetan Dufour, Mehmet Kayanak, Bernd
Tillack, John D. Cressler and John Papapolymerou, “A D-Band Micromachined
End-fire Antenna in 130 nm SiGe BiCMOS Technology,” accepted with some
revisions in IEEE Transactions on Antennas and Propagation.
8-
Wasif T. Khan, A. Cagri Ulusoy, Nelson Lourenco, and John Papapolymerou,
“Organically Packaged 122 GHz Receiving Switched-Beam Array,” to be
submitted to IEEE Transactions on Microwave Theory and Techniques.
9.
Seunghwan Kim, Wasif T. Khan, Alenka Zajic, and John Papapolymerou,
Fellow, IEEE “D-band Channel Measurements and Characterization for Indoor
Applications,” submitted to IEEE Transactions on Antennas and Propagation
Conference Papers:
1-
Wasif T. Khan, S. Bhattacharya, S. Horst, J. Cressler and J. Papapolymerou,
"Low Phase Noise K-band Oscillator on Organic Liquid Crystal Polymer (LCP)
Substrate," IEEE International Microwave Symposium (IMS), Anaheim, CA, pp.
1186-1189, May 2010.
2-
Wasif T. Khan, S. Bhattacharya, C. E. Patterson, G. E. Ponchak , J.
Papapolymerou, “Low Cost 60 GHz RF Front End Transceiver Implemented on
Organic Substrate,”
IEEE International Microwave Symposium (IMS),
Baltimore, MD, June 2011.
3-
E.A. Juntunen, Wasif T. Khan, C. E. Patterson, S. Bhattacharya, D. Dawn, J.
Laskar,J. Papapolymerou, “An LCP Packaged High-Power, High-Efficiency
CMOS Millimeter-Wave Oscillator,” IEEE International Microwave Symposium
(IMS), Baltimore, MD, June 2011.
4-
Wasif T.Khan, Chad E. Patterson and John Papapolymerou, "An UltraWide
Band W-Band End-Fire Antenna on Flexible Organic Substrate," IEEE Antenna
and Propgation Symposium (APS), Chicago,USA, July 8-14,2012
5-
S. Pavlidis, C. A. Donado Morcillo, P. Song, Wasif. T. Khan, R. Fitch, J.
Gillespie, R. Febo, T. Quach, J. Papapolymerou, “A Hybrid GaN/Organic X-Band
174
Transmitter Module,” IEEE Radio and Wireless Symposium (RWS), Austin,
USA, pp. 241-243, January 2013.
6-
Wasif T. Khan, Cagri Ulusoy and John Papapolymeoru, “D- Band
Characterization of Co-Planar Wave Guide and Microstrip Transmission Lines on
Liquid Crystal Polymer,” IEEE Electronic Components and Technology
Conference (ECTC), Las Vegas, USA, pp. 2304-2309, May 2013.
7-
Wasif T. Khan, Cagri Ulusoy, Mehmet Kaynak, Hermann Schumacher and John
Papapolymerou, “A 94 GHz Flip-Chip Packaged SiGe BiCMOS LNA on an LCP
Substrate,” International Microwave Symposium (IMS), Seattle, Washington,
USA, June 2013.
8-
Aida L. Vera López, Wasif T. Khan, Akira Akiba, Koichi Ikeda, Mitsuo
Hashimoto, and John Papapolymerou, “Dual Frequency Organically Packaged
Antenna Arrays at 57 and 80 GHz,” International Microwave Symposium (IMS),
Seattle, Washington, USA, June 2013.
9-
O. Lemtiri Chlieh, Wasif. T. Khan, S. Pavlidis, C. A. Donado Morcillo, J.
Papapolymerou, “Integrated Microfluidic Cooling for GaN Devices on Multilayer
Organic LCP Substrate,” International Microwave Symposium (IMS), Seattle,
Washington, USA, June 2013
10-
Wasif T. Khan, Aida L. Vera López Akira, George E. Ponchak and John
Papapolymerou, “Integration of V-Band and W-Band Antennas with SPDT
Switch on Organic Substrates,” IEEE Antenna and Propagation Symposium
(APS), Orlando, Florida, USA, July 7-13, 2013.
11-
Aida L. Vera López, David Giles, Wasif T. Khan, Outmane Chlieh and John
Papapolymerou, “Microfluidic Channel on Organic Substrates as Size-Reducing
Technique for 915 MHz Antenna Designs,” to be presented at Asia Pacific
Microwave Conference (APMC), Seoul, South Korea, November 2013.
12-
Wasif T. Khan, Carlos A. Donado, A. Cagri Ulusoy, and John Papapolymerou,
“Characterization of Liquid Crystal Polymer (LCP) from 110- GHz to 170 GHz,”
to be presented at IEEE Radio and Wireless Symposium (RWS), Newport Beach,
CA, USA, January 19-22, 2014.
(Student Paper Competition Finalist)
175
13-
S. Pavlidis, Cagri Ulusoy, Wasif T. Khan, O. Lemtiri Chlieh J. Papapolymerou,
“A Feasibility Study of Flip-Chip Packaged Gallium Nitride HEMTs on Organic
Substrates for Wideband RF Amplifier Applications,” accepted and to be
presented at IEEE Electronic Components and Technology Conference (ECTC),
Orlando, Florida, USA, May 2014
14-
F. Cai, Y. H. Chang, K. Wang, S. Pavlidis, Wasif T. Khan, J.
Papapolymerou,”High Resolution Aerosol Jet Printing of D- Band Printed
Transmission Lines on Flexible LCP Substrate,” accepted and to be presented at
IMS 2014, Tampa, Florida, USA.
15-
O. Lemtiri Chlieh, Wasif T. Khan, J. Papapolymerou, “Integrated Microfluidic
Cooling of High Power Passive and Active Devices on Multilayer Organic
Substrate,” accepted and to be presented at IMS 2014, Tampa, Florida, USA.
16-
S. Pavlidis, C. A. Ulusoy, Wasif T. Khan, J. Papapolymerou, “A Low-Cost,
Encapsulated Flip-Chip Package on Organic Substrate for Wideband Gallium
Nitride (GaN) Hybrid Amplifiers,” accepted and to be presented at IMS 2014,
Tampa, Florida, USA.
17-
O. Lemtiri Chlieh, Wasif T. Khan, J. Papapolymerou, “L-Band Tunable
Microstrip Bandpass Filter on Multilayer Organic Substrate With Integrated
Microfluidic Channel,” accepted and to be presented at IMS 2014, Tampa,
Florida, USA.
18-
Wasif T. Khan, A. C. Ulusoy, R. L. Schmid, J. Papapolymerou,"Characterization
of a Low-Loss and Wide-Band (DC to 170 GHz) Flip-Chip Interconnect on an
Organic Substrate," accepted and to be presented at IMS, June 2014, Tampa,
Florida, USA.
19.
Saeed Zeinolabedinzadeh, Wasif T. Khan, Mehmet Kaynak, Bernd. Tillack, John
Papapolymerou, and John D. Cressler, “A 330 GHz, Fully-Integrated SiGe
Transmitter and Receiver with Integrated Antenna,” accepted and to be presented
at RFIC 2014, Tampa, Florida, USA.
20.
Wasif T. Khan, Seunghwan Kim, Alenka Zajic, and John Papapolymerou, “DBand Indoor Path Loss Measurements,” accepted and to be presented at IEEE
176
International Symposium on Antennas and Propagation Symposium (APS), July
6-12, 2014, Memphis, Tennessee, USA.
21.
Dylan B. McQuaide, Wasif T. Khan, and John Papapolymerou, “Orthogonal
Wideband (DC-12 GHz) Microstrip-to-Microstrip Transition using Flexible LCP
Interconnect,” accepted and to be presented at IEEE European Microwave
Conference, Rome, Italy, October 6-9, 2014.
22.
F. M. Inanlou, Wasif T. Khan, P. Song, S. Zeinolabedinzadeh, R. Schmid, T.
Chi, A. Ulusoy, J. Papapolymerou, H. Wang, J. D. Cressler, “Compact, LowPower, Single-Ended and Differential SiGe W-band LNAs,” accepted and to be
presented at IEEE European Microwave Integrated Circuits Conference, Rome,
Italy, October 6-9, 2014.
23.
C. A. Ulusoy, C. Barisich, S. Pavlidis, Wasif T. Khan, J. Papapolymerou, “An
Ultra-Wideband, Hybrid, Distributed Power Amplifier Using Flip-Chip Bonded
GaN Devices on AlN Substrate,” accepted and to be presented at European
Microwave Symposium, Rome, Italy, October 6-9, 2014.
24.
A. Cagri Ulusoy, Robert L. Schmid, Wasif T. Khan, Mehmet Kaynak, Bernd
Tillack, and John D. Cressler, “An Investigation of fT and fmax Degradation Due
to Device Interconnects in 0.5 THz SiGe HBT Technology,” accepted and to be
presented at IEEE Bipolar/BiCMOS citcuits and Technology Meeting, Coronado
California, USA, September 28 to October 1, 2014.
177
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199
VITA
Wasif Tanveer Khan
Wasif Tanveer Khan received the B.Sc. in Electrical Engineering from the University of
Engineering and Technology at Lahore, Pakistan in 2005. From January 2006 to
December 2008, he was a Lecturer at the National University of Computer and Emerging
Sciences-FAST at Lahore, Pakistan. He was awarded an M.S. leading to a
Ph.D. Fulbright scholarship, in 2008. He started his graduate studies at the Georgia
Institute of Technology in 2009 and finished his Master’s degree in Electrical
Engineering, in 2010. At present, he is a Ph.D. student working in the microwave circuit
technology group with Dr. John Papapolymerou. His research interests include RF and
microwave system design, millimeter wave circuit and package design, on-chip and offchip antenna design, and phased array systems. He has authored or co-authored more
than 30 publications in peer-reviewed conferences and journals. Since 2010, he has been
member of the steering committee (Publications Chair) and Technical Program
Committee of the IEEE Radio Wireless Symposium. He has also been an active reviewer
for the IEEE Transactions on Microwave Theory and Techniques, IEEE Transactions on
Antennas and Propagations, and IEEE Microwave and Wireless Components and Letters.
200